JPH05175407A - Semiconductor mounting board - Google Patents
Semiconductor mounting boardInfo
- Publication number
- JPH05175407A JPH05175407A JP3342811A JP34281191A JPH05175407A JP H05175407 A JPH05175407 A JP H05175407A JP 3342811 A JP3342811 A JP 3342811A JP 34281191 A JP34281191 A JP 34281191A JP H05175407 A JPH05175407 A JP H05175407A
- Authority
- JP
- Japan
- Prior art keywords
- metal core
- conductor pin
- hole
- substrate
- semiconductor mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000011347 resin Substances 0.000 abstract description 6
- 229920005989 resin Polymers 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011889 copper foil Substances 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 14
- 238000000034 method Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体搭載基板に関する
もので、より詳しくは、熱放散性に優れた半導体搭載基
板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting board, and more particularly to a semiconductor mounting board having excellent heat dissipation.
【0002】[0002]
【従来の技術】従来、半導体を搭載した基板をプリント
配線板に接続する方法として、ピングリットアレイ、リ
ードレスチップキャリア、リーディットチップキャリア
等の半導体搭載用基板を用いる方法がある。しかし近
年、半導体チップは高速化、高集積化、大容量化の方向
にあり、これに伴って半導体チップの発熱量も増大する
傾向にある。このため、チップ自身の温度上昇による処
理速度の低下、チップ周辺の温度上昇に伴う接続信頼性
の低下等の問題を避けるため、基板に半導体チップが発
生する熱を放散する何らかの機能を付加する必要が生じ
てきている。2. Description of the Related Art Conventionally, as a method of connecting a substrate on which a semiconductor is mounted to a printed wiring board, there is a method of using a semiconductor mounting substrate such as a pin grid array, a leadless chip carrier or a lead chip carrier. However, in recent years, semiconductor chips have tended toward higher speed, higher integration, and higher capacity, and along with this, the amount of heat generated by the semiconductor chips has also tended to increase. Therefore, it is necessary to add some function to dissipate the heat generated by the semiconductor chip to the substrate in order to avoid problems such as a decrease in processing speed due to a rise in temperature of the chip itself and a decrease in connection reliability due to a rise in temperature around the chip. Is happening.
【0003】一般の半導体搭載基板は、主に熱硬化性樹
脂、またはセラミック等の絶縁物を材料として図2のよ
うに構成されているが、放熱機能を付加したものとし
て、図3に示すように、半導体チップ31を包む封止樹
脂32の表面に取り付けてある金属性キャップ33にヒ
ートシンク39を接続し放熱する構造、図4に示すよう
に、半導体搭載部分の穴を形成した基板41と、前記穴
より大きな穴を形成した基板42とを貼り合わせ、この
大きな穴の形成部分に金属板43を貼り合わせ、この金
属板より放熱する構造(特開昭64−39093号公
報)、図5に示すように、内層に金属コア51を埋め込
み、側面及び半導体搭載部の下部から金属コアを露出さ
せ、ここより放熱する構造等がある。A general semiconductor mounting substrate is mainly made of an insulating material such as a thermosetting resin or ceramic as shown in FIG. 2, but as shown in FIG. A structure in which a heat sink 39 is connected to a metallic cap 33 attached to the surface of a sealing resin 32 that wraps the semiconductor chip 31 to radiate heat; a substrate 41 having holes for semiconductor mounting portions formed therein, as shown in FIG. A structure in which a substrate 42 having a hole larger than the hole is bonded, a metal plate 43 is bonded to a portion where the hole is formed, and heat is radiated from the metal plate (JP-A-64-39093), FIG. As shown, there is a structure in which the metal core 51 is embedded in the inner layer, the metal core is exposed from the side surface and the lower portion of the semiconductor mounting portion, and heat is radiated from there.
【0004】しかし、図3の構造は半導体チップとヒー
トシンクが直接接触していないために十分に熱を伝達で
きない、図4の構造は熱を伝達し放熱する金属露出部分
が十分に大きくない、図5の構造は熱容量が大きく従来
の放熱機能の中では最も優れているが、図4の構造と同
様に金属露出部分が十分に大きくない等の問題により、
各構造とも放熱効果が十分ではなかった。However, the structure of FIG. 3 cannot transfer heat sufficiently because the semiconductor chip and the heat sink are not in direct contact with each other, and the structure of FIG. 4 does not have a sufficiently large exposed metal portion for transferring heat and releasing heat. The structure of 5 has a large heat capacity and is the most excellent in the conventional heat dissipation function, but due to the problem that the exposed metal part is not large enough as in the structure of FIG.
The heat dissipation effect was not sufficient in each structure.
【0005】[0005]
【発明が解決しようとする課題】本発明は、半導体チッ
プの高速化、高密度化、大容量化に伴い、放熱機能が要
求される半導体搭載基板に関するものであり、熱放散性
に優れた半導体搭載基板を提供することを目的とする。SUMMARY OF THE INVENTION The present invention relates to a semiconductor mounting board which is required to have a heat dissipation function as the speed, density and capacity of semiconductor chips increase, and the semiconductor has excellent heat dissipation. An object is to provide a mounting board.
【0006】[0006]
【課題を解決するための手段】即ち本発明は、内層に金
属コアを有するピン接続型半導体搭載基板において、プ
リント配線板との接続に用いる導体ピンの他に、金属コ
アに絶縁層を介さずに接続され、かつ、基板の表面より
突出した形状でプリント配線板との接続には用いない導
体ピンを有する半導体搭載基板であり、金属コアの露出
部分で放熱しきれずに蓄積される熱をプリント配線板と
の接続には用いない導体ピンに伝達し、この導体ピンの
基板表面より突出した部分で空気中に放熱することを特
徴とするものである。That is, according to the present invention, in a pin connection type semiconductor mounting board having a metal core in an inner layer, in addition to a conductor pin used for connection with a printed wiring board, an insulating layer is not provided in the metal core. It is a semiconductor mounting board that has conductor pins that are not connected to the printed wiring board in a shape protruding from the surface of the board that is connected to the. It is characterized in that it is transmitted to a conductor pin which is not used for connection with a wiring board, and the portion of the conductor pin protruding from the substrate surface radiates heat into the air.
【0007】以下に本発明の一実施例を図面を用いて説
明する。図1は本発明による半導体搭載基板の製造工程
の一例を示す図で、先ず、図1(a)に示すように、金
属コア11に下穴12を形成し、この下穴12に絶縁樹
脂13を埋め込み硬化させた後、金属コア11の両面に
プリプレグ14および銅箔15を配し、加熱加圧により
積層一体化して金属コア入り基板を得る。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of a manufacturing process of a semiconductor mounting substrate according to the present invention. First, as shown in FIG. 1A, a prepared hole 12 is formed in a metal core 11, and an insulating resin 13 is formed in the prepared hole 12. After burying and hardening, the prepreg 14 and the copper foil 15 are arranged on both surfaces of the metal core 11, and they are laminated and integrated by heating and pressing to obtain a substrate with a metal core.
【0008】次に、図1(b)に示すように、プリント
配線板との接続に用いる導体ピン26を挿入するスルー
ホール16、プリント配線板との接続には用いない導体
ピン27を挿入するスルーホール17を形成する。ここ
で、スルーホール16は下穴12と同心円となるように
形成し、絶縁樹脂13を介して金属コア11とは電気的
に絶縁されるようにする。一方のスルーホール17は回
路パターン20とは接続しない位置に金属コア11と接
続するように形成する。ただし、金属コア11をGND
層またはVCC層として用いる場合は回路パターン20
のGNDラインまたはVCCラインと接続しても問題は
ない。続いて、半導体搭載用凹部18、コア露出部1
9、回路パターン20を形成し、さらに、ソルダーレジ
スト21を印刷し、ニッケル・金メッキを施して半導体
搭載用基板22を得る。Next, as shown in FIG. 1 (b), through holes 16 for inserting conductor pins 26 used for connection with the printed wiring board and conductor pins 27 not used for connection with the printed wiring board are inserted. The through hole 17 is formed. Here, the through hole 16 is formed so as to be concentric with the pilot hole 12, and is electrically insulated from the metal core 11 via the insulating resin 13. One of the through holes 17 is formed so as to be connected to the metal core 11 at a position not connected to the circuit pattern 20. However, the metal core 11 is GND
Circuit pattern 20 when used as a layer or a VCC layer
There is no problem even if it is connected to the GND line or the VCC line. Subsequently, the semiconductor mounting recess 18 and the core exposed portion 1
9. A circuit pattern 20 is formed, a solder resist 21 is printed, and nickel / gold plating is performed to obtain a semiconductor mounting substrate 22.
【0009】次に、図1(c)に示すように、半導体搭
載用凹部18に半導体チップ23を導電ペーストにより
接着し搭載する。続いて、半導体チップ23の入出力端
子と基板22のボンディングパッド24とを金ワイヤー
ボンディング法により結線し、さらに、半導体チップ2
3およびこの周辺を封止樹脂25により硬化封止する。Next, as shown in FIG. 1 (c), the semiconductor chip 23 is mounted in the semiconductor mounting recess 18 by bonding with a conductive paste. Subsequently, the input / output terminal of the semiconductor chip 23 and the bonding pad 24 of the substrate 22 are connected by a gold wire bonding method, and further, the semiconductor chip 2
3 and its periphery are hardened and sealed by the sealing resin 25.
【0010】次に、スルーホール16に接続用の導体ピ
ン26を、スルーホール17に放熱用の導体ピン27を
それぞれ挿入する。ここで用いる導体ピン27について
本例では、2つの異なる径からなる円柱状であり、細い
部分はスルーホール17に挿入され、金属コア11と接
続する部分で、太い部分はスルーホール17の径よりも
太く、かつ、隣接する導体ピン26と接触しない程度に
細く、基板表面より突出して放熱に作用する。さらに、
この突出部分の形状、大きさを工夫して表面積を拡げる
ことにより、放熱効果を高めることも可能である。続い
て、ディップソルダリング法により、導体ピン26をス
ルーホール16に、導体ピン27をスルホール17にそ
れぞれ固定する。このとき、スルーホール17の内部に
半田28が隙間なく充填されることにより、金属コア1
1に蓄積される熱は、効率良く導体ピン27に伝達し外
気へ放熱される。上述の工程により、目的とする半導体
搭載基板を得ることができる。Next, the conductor pin 26 for connection is inserted into the through hole 16 and the conductor pin 27 for heat radiation is inserted into the through hole 17, respectively. In this example, the conductor pin 27 used here has a cylindrical shape with two different diameters, the thin portion is a portion inserted into the through hole 17 and connected to the metal core 11, and the thick portion is larger than the diameter of the through hole 17. It is also thick and thin enough not to make contact with the adjacent conductor pin 26, and protrudes from the substrate surface to act for heat dissipation. further,
It is also possible to enhance the heat dissipation effect by devising the shape and size of the protruding portion and expanding the surface area. Subsequently, the conductor pin 26 is fixed to the through hole 16 and the conductor pin 27 is fixed to the through hole 17 by the dip soldering method. At this time, the solder 28 fills the inside of the through hole 17 without any gap, so that the metal core 1
The heat accumulated in 1 is efficiently transmitted to the conductor pin 27 and radiated to the outside air. Through the steps described above, the target semiconductor mounting board can be obtained.
【0011】[0011]
【発明の効果】本発明によれば、従来の放熱機能として
は最も優れた金属コア入り半導体搭載基板における放熱
面積の問題について、金属コアに絶縁層を介さずに放熱
用の導体ピンを接続し、かつ、この導体ピンの基板表面
より突出した部分の形状を工夫して放熱面積を拡大する
ことにより解決することができ、従来にない高い熱放散
性を有したピン接続型半導体搭載基板を得ることができ
る。According to the present invention, regarding the problem of the heat radiation area in the conventional semiconductor mounting board with a metal core having the best heat radiation function, the heat dissipation conductor pin is connected to the metal core without an insulating layer. Moreover, the problem can be solved by devising the shape of the portion of the conductor pin projecting from the substrate surface to expand the heat dissipation area, and a pin connection type semiconductor mounting substrate having a high heat dissipation property that has never been obtained is obtained. be able to.
【図1】本発明によるピン接続型半導体搭載基板の一実
施例の断面図である。FIG. 1 is a sectional view of an embodiment of a pin connection type semiconductor mounting substrate according to the present invention.
【図2】従来の放熱機能を持たないピン接続型半導体搭
載基板の概念を示す断面図である。FIG. 2 is a cross-sectional view showing the concept of a conventional pin connection type semiconductor mounting substrate having no heat dissipation function.
【図3】従来の放熱機能を持ったピン接続型半導体搭載
基板の概念を示す断面図である。FIG. 3 is a cross-sectional view showing the concept of a conventional pin connection type semiconductor mounting substrate having a heat dissipation function.
【図4】従来の放熱機能を持ったピン接続型半導体搭載
基板の概念を示す断面図である。FIG. 4 is a cross-sectional view showing the concept of a conventional pin connection type semiconductor mounting substrate having a heat dissipation function.
【図5】従来の放熱機能を持ったピン接続型半導体搭載
基板の概念を示す断面図である。FIG. 5 is a cross-sectional view showing the concept of a conventional pin connection type semiconductor mounting substrate having a heat dissipation function.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/50 F 9272−4M ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H01L 23/50 F 9272-4M
Claims (2)
体搭載基板において、プリント配線板との接続に用いる
導体ピンの他に、金属コアに絶縁層を介さずに接続さ
れ、かつ、基板の両面または片面より突出した形状でプ
リント配線板との接続には用いない導体ピンを有するこ
とを特徴とする半導体搭載基板。1. A pin connection type semiconductor mounting substrate having a metal core as an inner layer, which is connected to a metal core without an insulating layer and has both surfaces of the substrate in addition to conductor pins used for connection with a printed wiring board. Alternatively, the semiconductor mounting board is characterized in that it has conductor pins that are not used for connection with the printed wiring board and that have a shape protruding from one surface.
ない導体ピンにおいて、基板表面より突出した部分の少
なくとも片方が、該導体ピンが挿入されるスルーホール
の径より大きい形状を有することを特徴とする請求項1
記載の半導体搭載基板。2. In the conductor pin not used for connection with the printed wiring board, at least one of the portions protruding from the substrate surface has a shape larger than the diameter of the through hole into which the conductor pin is inserted. Claim 1 characterized by
The semiconductor mounting substrate described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3342811A JPH05175407A (en) | 1991-12-25 | 1991-12-25 | Semiconductor mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3342811A JPH05175407A (en) | 1991-12-25 | 1991-12-25 | Semiconductor mounting board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05175407A true JPH05175407A (en) | 1993-07-13 |
Family
ID=18356677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3342811A Pending JPH05175407A (en) | 1991-12-25 | 1991-12-25 | Semiconductor mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05175407A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990037873A (en) * | 1999-02-08 | 1999-05-25 | 구자홍 | Manufacturing method of PCB and PCB thereby |
| KR20000055589A (en) * | 1999-02-08 | 2000-09-05 | 구자홍 | Manufacturing method of PCB and PCB thereby |
| KR100401146B1 (en) * | 2000-12-04 | 2003-10-10 | 앰코 테크놀로지 코리아 주식회사 | Manufacturing method of substrate for manufacturing semiconductor package |
| JP2008283154A (en) * | 2007-05-14 | 2008-11-20 | Furukawa Electric Co Ltd:The | Heat dissipation structure |
| US7554039B2 (en) | 2002-11-21 | 2009-06-30 | Hitachi, Ltd. | Electronic device |
| US20120077317A1 (en) * | 2005-10-14 | 2012-03-29 | Ibiden Co., Ltd. | Multilayered printed circuit board and method for manufacturing the same |
| JP2012222200A (en) * | 2011-04-11 | 2012-11-12 | Hitachi Automotive Systems Ltd | Electronic device |
| DE102011083223A1 (en) * | 2011-09-22 | 2013-03-28 | Infineon Technologies Ag | Power semiconductor module with integrated thick-film circuit board |
-
1991
- 1991-12-25 JP JP3342811A patent/JPH05175407A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990037873A (en) * | 1999-02-08 | 1999-05-25 | 구자홍 | Manufacturing method of PCB and PCB thereby |
| KR20000055589A (en) * | 1999-02-08 | 2000-09-05 | 구자홍 | Manufacturing method of PCB and PCB thereby |
| KR100401146B1 (en) * | 2000-12-04 | 2003-10-10 | 앰코 테크놀로지 코리아 주식회사 | Manufacturing method of substrate for manufacturing semiconductor package |
| US7554039B2 (en) | 2002-11-21 | 2009-06-30 | Hitachi, Ltd. | Electronic device |
| EP1571706B1 (en) * | 2002-11-21 | 2018-09-12 | Hitachi, Ltd. | Electronic device |
| US20120077317A1 (en) * | 2005-10-14 | 2012-03-29 | Ibiden Co., Ltd. | Multilayered printed circuit board and method for manufacturing the same |
| US9027238B2 (en) * | 2005-10-14 | 2015-05-12 | Ibiden Co., Ltd. | Multilayered printed circuit board and method for manufacturing the same |
| JP2008283154A (en) * | 2007-05-14 | 2008-11-20 | Furukawa Electric Co Ltd:The | Heat dissipation structure |
| JP2012222200A (en) * | 2011-04-11 | 2012-11-12 | Hitachi Automotive Systems Ltd | Electronic device |
| DE102011083223A1 (en) * | 2011-09-22 | 2013-03-28 | Infineon Technologies Ag | Power semiconductor module with integrated thick-film circuit board |
| DE102011083223A8 (en) * | 2011-09-22 | 2013-04-25 | Infineon Technologies Ag | Power semiconductor module with integrated thick-film circuit board |
| DE102011083223B4 (en) | 2011-09-22 | 2019-08-22 | Infineon Technologies Ag | Power semiconductor module with integrated thick-film circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1374305B1 (en) | Enhanced die-down ball grid array and method for making the same | |
| KR100310398B1 (en) | Pad Array Semiconductor Device with Thermal Conductor and Manufacturing Method Thereof | |
| US5886415A (en) | Anisotropic conductive sheet and printed circuit board | |
| US6023098A (en) | Semiconductor device having terminals for heat radiation | |
| JP2002537655A (en) | Leadless carrier design and construction | |
| CN100375272C (en) | Thermally Enhanced Component Substrates | |
| JPH09199823A (en) | Chip on board printed wiring board | |
| JPH05175407A (en) | Semiconductor mounting board | |
| JPH10313071A (en) | Electronic part and wiring board device | |
| US20020063331A1 (en) | Film carrier semiconductor device | |
| KR100280083B1 (en) | Printed Circuit Board and Manufacturing Method of Printed Circuit Board and Semiconductor Package Using the Same | |
| JP3931696B2 (en) | Electronic equipment | |
| JPH03174749A (en) | semiconductor equipment | |
| JP2620611B2 (en) | Substrate for mounting electronic components | |
| JP2810130B2 (en) | Semiconductor package | |
| JPH1098127A (en) | Semiconductor package for surface mounting | |
| JPS6239032A (en) | Chip carrier for electronic element | |
| JP3033662B2 (en) | Semiconductor element mounting film and semiconductor element mounting structure | |
| JP2809316B2 (en) | Substrate for mounting electronic components | |
| JP2003007914A (en) | Semiconductor device | |
| JP3576228B2 (en) | Surface mount type semiconductor device | |
| JPH09148484A (en) | Semiconductor device and manufacturing method thereof | |
| JPH03120851A (en) | Semiconductor mounting substrate | |
| JPH05152496A (en) | Semiconductor loaded board | |
| JPH10150065A (en) | Chip size package |