JPH0454081A - High-definition television signal reception and processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides high-definition television systems (hereinafter referred to as HDTV) by receiving and processing high-definition television signals.
There are video signals that use the double-speed television system (hereinafter sometimes referred to as EDTV system), and video signals that use the standard-speed scanning television system (hereinafter sometimes referred to as EDTV system).
The present invention relates to a high-definition television signal reception and processing device that allows video signals adopting the NTSC system (sometimes referred to as the NTSC system) to be simultaneously output from separate output terminals in parallel.

[Prior Art] In recent years, as television screens have become larger, there has been a demand for higher quality display images. In response to these demands, various high-definition television systems are being studied. In Japan, MUSE is a high-definition television signal transmission system developed by NHK (Japan Broadcasting Corporation).
(Multiple Sub-NyquistSam
The pling encoding method is typical, and will be explained below using this as an example.

The MUSE method is in the material rNHK Technical Research Journal 1986.
Volume 39, Issue 2, Volume 172, p18-P53”
The feature is that the number of scanning lines is 112.
It has 5 lines, an interlaced signal with a frame frequency of 307, and a screen aspect ratio of 16:9, making it wider than the current system.

In addition, in the case of a moving image, this MUSE method uses one
Using a multiple subsample band compression method that thins out pixels every other pixel, and in the case of still images, thins out every other pixel so that one cycle takes two frames, the still image transmission band is 24M) f
z, a video transmission band signal of 16 MHz is band-compressed to 8 MHz and transmitted.

Therefore, the MtJSE decoder on the receiving side that receives this has two signal processing systems, one for still image/video processing, and a motion detection circuit for determining still images/videos, and a still image/video processing system.
The scale of the signal processing circuit has become extremely large, including a MIX circuit for mixing video processed signals, a frequency conversion circuit, and the like.

Therefore, instead of using such complex, large-scale, and expensive signal processing circuits, the current NT
A television system (HDT) that uses a television receiver based on the SC system or displays images using double-speed scanning
Progress is also being made in the development of signal processing circuits that can receive and inexpensively reproduce images transmitted by high-definition television systems using V) receivers.

For such purposes, high-definition television signals may be converted into standard television signals or double-speed television signals (ED).
Regarding the conversion method to TV signals), see [Kasezawa et al.
“DTV Compatible MUSE/NTSC Converter” Television Society Technical Report.

VOL, 14, No, 8 pp 13-18 (
1990) reported in J.

EDTV compatible MUSE/NT mentioned in this report
The major features of the SC converter are as follows.

One is the output compatible with EDTV, that is, the number of scanning lines is 11.
525 high-definition television signals of 25 lines/frame
It is possible to obtain an output converted to a double-speed scanning signal of the book/field. Second, we are trying to use frame memory to eliminate aliasing interference.

This converter will be explained below using FIG. 2.

In FIG. 2, 201 is a MUSE signal input terminal;
2 is an amplifier circuit, 203 is an A/D conversion circuit that converts an analog signal into a digital signal, 204 is an ALc (automatic level control circuit) circuit that controls the signal level, and 205 is a MUSE that is non-linearly processed on the transmitting encoder side. A de-emphasis circuit that returns the signal to a linear state, 206 a frame memory, 207
is a horizontal low-pass filter (hereinafter referred to as LPF), 20
8 is an aliasing distortion removal circuit, and 209 is a vertical LPF.
, 210 is an edge enhancement circuit, 211 is a time axis conversion circuit that reads out a signal written with a 32.4MHz clock using a 20, 16M7 clock, or a 30.24M7 clock, 212゜213.214 215 and 216 are respectively time axis conversion circuits, D/A conversion circuits that convert digital signals into analog signals, and 217.
Reference numeral 218219 is an output terminal for brightness signals and color difference signals compatible with HDTV, and 220, 221, and 222 are output terminals for brightness signals and color difference signals compatible with NTSC interlaced scanning displays.

Next, the operation of the circuit shown in FIG. 2 will be explained.

The analog MUSE signal input from the input terminal 201 is
According to the control signal from the ALC circuit 204, the signal is converted into a digital signal by the A/D converter 203 while accurately maintaining the signal level. De-emphasis processing unit 205
Now, M that has been non-linearly processed on the transmitting encoder
Processing is performed to return the USE signal to a linear state, and the processed signal is supplied to the horizontal LPF section 207 and frame memory section 206 at the next stage.

The horizontal LPF section 207 performs horizontal LPF processing on both the incoming signal and the signal delayed by one frame by the frame memory section 206.

The aliasing removal circuit 208 has a built-in frame memory, and performs motion detection based on a two-frame difference and mixing processing. The mixing processing section obtains a signal of the current frame in the case of a moving image, and an average value signal of the current frame and the previous frame in the case of a still image, and mixes and outputs them according to the motion detection signal.

The aliasing removal circuit 208 attempts to obtain a signal from which aliasing interference due to frame offset subsampling processing during still image reception has been removed.

In the vertical LPF section 209, the number of scanning lines of the MUSE signal is 11.
From 25 lines, processing is performed to create 525 scanning lines with the center of gravity of the scanning lines aligned in accordance with EDTV.

The edge enhancement processing unit 210 performs edge enhancement processing only on the luminance signal. In the time axis conversion processing section 211, a signal is written using a write clock synchronized with the MUSE signal, and the signal is read out using a read clock corresponding to the synchronization signal of the HDTV. The above EDTV signal is D/A
The signal is input to the converter 215 and converted into an analog signal.

Further, the EDTV signal is converted to the time axis conversion unit 212.21.
3, 214, where the readout frequency for time axis expansion is set to 1/2 of the time axis conversion processing unit 211.
NTS
It creates C-scheme standard television signals. The signal corresponding to the standard television is input to the D/A converter 216 and converted into an analog signal.

[Problem to be solved by the invention]

The MUSE decoder in the conventional example described above has a configuration in which the luminance and color difference signals are switched between moving image processing and still image processing depending on the presence or absence of image movement. For this reason, the scale of the processing circuit has become extremely large.

Furthermore, the display for displaying high-definition television signals had to be a special horizontally long display with an aspect ratio of 16=9 in view of the NTSC system. Therefore, there was a problem that the television receiving system became very expensive.

In addition, in the method of converting the high-definition television signal in the conventional example above to a standard television signal or to a double-speed television signal (sequential scanning signal) compatible with EDTV, all NTSC system receivers are compatible. Although it is possible to do so, vertical LPF processing converts the center of gravity of the scanning line to a standard (NTSC) display that performs interlaced scanning or for EDTV, so it cannot be used for high-definition televisions with an aspect ratio of 16:9. Even if you want to display it on a horizontal display for John,
There was a problem that it could not be dealt with.

Furthermore, since the aliasing removal circuit with the above configuration performs processing between frames after performing horizontal LPF processing, the flickering component in the frame direction (time direction) does not flicker, but the aliasing interference is With a lip on the top (
It stops and remains. There were some problems.

An object of the present invention is to solve the above-mentioned problems, and when receiving high-definition television signals, it can be applied not only to high-definition television receivers but also to television system receivers such as the NTSC system and EDTV system that currently exist in the world. Another object of the present invention is to provide an inexpensive high-definition television signal reception and processing device that enables simultaneous and parallel display of images.

In other words, according to the high-definition television signal reception and processing device that is intended to be provided by the present invention, when a high-definition television signal is received, the video signal that adopts the high-definition television system (HDTV system) is , to create video signals of three systems: a video signal that adopts the double speed television system (EDTV system) and a video signal that adopts the standard speed scan television system (NTSC system), and output them simultaneously in parallel from separate output terminals. Therefore, by connecting a corresponding display to each output terminal, it is possible to enjoy a television screen according to the user's preference (or economy).

(Means for Solving the Problems) In order to achieve the above object, the present invention receives and processes a high-definition television signal, thereby producing a video signal that adopts a high-definition television system (HDTV system) and a double-speed television. As a high-definition television signal receiving and processing device that can simultaneously output a video signal using the EDTV method (EDTV method) and a video signal using the standard speed scan television method (NTSC method) in parallel, demodulating means for demodulating the received analog high-definition television signal; A/D converting means for converting the demodulated output from the demodulating means from an analog signal to a digital signal;
A synchronizing signal reproducing means receives a digital signal from the D converting means and extracts and reproduces a control signal such as a clock signal or a synchronizing signal for signal processing, and the demodulating means uses the control signal from the synchronizing signal reproducing means. In-field signal processing is performed on the digital high-definition television signal, which is the demodulated output of
In-field signal processing means for outputting digital video signals adopting the SC method in parallel, and the HDTV method, ED
A device was constructed comprising first, second, and third D/A conversion means for converting each digital video signal of the TV system and the NTSC system into an analog signal and outputting the analog signal.

[Operation] After receiving, the high-quality television signal demodulated by the demodulation means and converted into a digital signal by the A/D conversion means is supplied to the synchronization signal reproduction means and the in-field signal processing means.

The intra-field signal processing means performs intra-field signal processing on both still image processed signals and moving image processed signals on the transmitting encoder side to reproduce video signals. For this reason, large circuits such as frame memory for interframe interpolation processing, motion detection, field memory for interfield interpolation, frequency conversion circuit, mixer, etc. required for each of the luminance signal processing section and color difference signal processing section are required. There is no need for a signal processing section that requires a 100% signal processing section, and the overall circuit configuration can be simplified and the circuit scale can be reduced.

Further, the in-field signal processing means uses the clock signal reproduced by the synchronization signal reproduction means and the synchronization signal to
A scanning line according to the TSC method, a scanning line according to the EDTV method, and a scanning line according to the HDTV method are simultaneously created in parallel. Each scan line signal created is a high quality signal D/A
The conversion means, the double-speed signal D/A conversion means, and the standard signal D/A conversion means output the signal as a video signal compatible with three television systems.

In other words, as a means of displaying images, standard speed televisions with an aspect ratio of 4:3 (general televisions using the NTSC system) are currently widely used and manufactured at low cost.
It can be used with any display, double-speed television (EDTV, etc.) display, or horizontal high-definition television display with an aspect ratio of 16:9, depending on your preference. Even if it is not compatible, it is a low-cost NTSC, E
Compatible with DTV displays, you can enjoy high-definition television signals.

Therefore, according to the present invention, it is possible to simultaneously obtain reproduced images that are compatible with a display exclusively for receiving high-definition television signals, a standard display of the NTSC system (and a VTR for the NTSC system), a display for EDTV, etc. becomes.

(Example〕 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 101 is a MUSE signal input section;
2 is a demodulation circuit that demodulates the received MUSE signal into an analog signal with a band of approximately 8 MHz; 103 is an A/D converter that converts the analog signal into a digital signal; and 104 is an A/D converter.
Digitized MUS output from D converter 103
A control signal generation circuit extracts a synchronization signal and a control signal from the E signal and also generates a system clock, etc. 105 is a de-emphasis processing section.

106 performs two-dimensional filter processing within the field on the sent MUSE signal, and the number of scanning lines is 1125,
Interlaced scanning with a frame frequency of 307 (hereinafter 11
107 is a color difference signal processing circuit for 1125/30 output, and 108 is an MUS that is 1125/30.
Within the field where a scanning line is created by converting the scanning line centroid position of the E signal to a scanning line centroid position for non-interlaced scanning with a scanning line number of 1125/2 and a frame frequency of 60 Hz, that is, a scanning line centroid position compatible with EDTV. It is an insertion circuit.

109 uses non-increase scanning (hereinafter referred to as 52
110 is a color difference signal processing circuit for 525/60 output, and 111 is a speed conversion processing circuit that converts the number of scanning lines to a 525/60 luminance signal and color difference signal. Interlaced scanning with a scan line count of 525 and a frame frequency of 30 (hereinafter referred to as 525/
30).

124 125 is a blanking insertion circuit, 112.11
3,114 is a 3-channel D/A converter, 1.15,
116, 117 are 1125/30 luminance signal and color difference signal output terminals, 118, 119° 120 are 525/60 luminance signal and color difference signal output terminals, 121, 122, 12
3 is a 525/30 luminance signal and color difference signal output terminal. Further, 1 is an in-field signal processing circuit that generates three types of video signals by simply performing in-field signal processing on the transmitted MUSE signal.

Next, the operation of the circuit shown in FIG. 1 will be explained.

A MUSE signal input from an input terminal 101 is demodulated into an analog signal with a band of approximately 8 MHz by a demodulation circuit 102, and then converted into a digital signal by an A/D converter 103. The MUSE signal converted into a digital signal is supplied to a de-emphasis processing section 105 and a control signal generation circuit 104. The control signal generation circuit 104 extracts a synchronization signal and a control signal from the MUSE signal, and also generates a system clock and the like to operate the entire system (including the signal processing circuit 1).

The de-emphasis processing unit 105 applies inverse non-linearity to the MUSE signal transmitted by FM modulation from the transmitting side and filters the de-emphasis characteristic to reduce triangular noise in the transmission path, and also to reduce the amplitude of the video signal in areas where the amplitude is small. Reduce noticeable noise components.

The MUSE signal subjected to the above processing is sent to the first field interpolation circuit 106 and the second field interpolation circuit 10.
Enter 8. The intra-field interpolation circuit 106 performs intra-field interpolation processing on both luminance and color difference signals regardless of whether they are still images or moving images, and performs intra-field interpolation processing on both the luminance and color difference signals,
Creates an output signal of 0. Here, a blanking period is inserted into the luminance signal by a blanking insertion circuit 124.
A converter 112 is supplied.

As for the color difference signal, at the time it is output from the intra-field interpolation circuit 106, the band is still compressed in the horizontal/vertical directions and in the time axis direction, so it is input to the color difference signal processing unit 107 and subjected to time axis expansion. After aligning the luminance signal with the horizontal time axis, line sequential processing is performed (vertical line interpolation) to create (RY) and (BY) signals for each line.

Furthermore, interpolation processing is performed to perform pixel interpolation in the horizontal direction, and the result is supplied to the blanking insertion circuit 124. After a blanking period is inserted in the blanking insertion circuit 124, the signal is supplied to the D/A converter 112. D/A converter 112
Now, let's look at one that is compatible with high-definition television displays.
Converts 125/30 luminance/color difference signals into analog signals.

The intra-field interpolation circuit 108 creates a scanning line having an EDTV center of gravity position from the scanning line of the MUSE signal, which is an interlaced scanning signal.

In this case, a 16:9 image will be displayed on a 4:3 display, allowing two display modes: zoom mode and wide mode.

The zoom mode cuts the left and right sides of the 16:9 image, and
:Display images on 3 displays at once (hereinafter referred to as Z
OOM) mode, and wide mode is 16:
A blanking period is provided above and below the image of 9, and a 16:9 image is displayed on a 4:3 display. Below C, WIDE
) mode.

The speed conversion processing circuit 109 converts the speed of both the luminance and color difference signals subjected to the above signal processing into 525/60 EDT compatible outputs, and after inserting a blanking period in the blanking insertion circuit 125 for the luminance signal. , the speed conversion circuit 111, and the D/A converter 113.

Here, the color difference signal is subjected to speed conversion processing on a path independent from the luminance signal, and processing that also serves as time axis expansion is performed to align the horizontal time axis with the luminance signal. The color difference signal processing circuit 110 performs vertical line interpolation (line sequential processing).
(R-Y) and (B-Y) signals are created for each line, and then subjected to interpolation processing to perform horizontal pixel interpolation and supplied to the blanking insertion circuit 125.

After inserting a blanking period in the blanking insertion circuit 125, the speed conversion processing circuit 111 and the D/A converter 1
13. The D/A converter 113 converts the luminance/color difference signals converted into HDTV compatible outputs into analog signals. The speed conversion processing circuit 111 thins out the number of scanning lines to 1/2 for the 525/60 luminance signal and color difference signal converted to EDTV compatible output, and converts the 525/30 interlaced scanning line, that is, the standard speed. is converted into an output signal compatible with the NTSC display of the D/A converter 114.
supply to. The D/A converter 114 converts the luminance/color difference signal converted into 525/30 into an analog signal.

According to the configuration shown in Figure 1, an output for a high-definition television (HDTV) display, an output for an EDTV display, and an output for a standard-speed NTSC display can be simultaneously and parallelly generated using only in-field signal processing. Therefore, it is possible to create video signal output compatible with all kinds of displays and packages such as VTRs that currently exist in the world.

Further, in the high-definition television signal reception and processing device having such a configuration, the blanking insertion circuit 124, 1
25, and instead place it immediately before the D/A converter or
If a blanking insertion circuit is arranged in the /A converter, the memory capacity of the speed conversion processing circuit 111 can be reduced by the blanking period.

Next, the control signal generation circuit 104, which is one of the main circuits in the configuration of FIG. 1, will be explained with reference to FIG.

FIG. 3 is a block diagram showing the inside of a control signal generation circuit 104 that extracts a synchronization signal and a control signal from an incoming MUSE signal and generates a system clock and the like.

In FIG. 3, 301 is an input terminal for the MUSE signal converted into a digital signal by the A/D converter 103;
07 is the switching control signal input terminal (mode switching terminal) for the two display formats (ZOOM, WIDE) in the 525/60 and 525/30 series, 303 is the 1125/30
Phase-locked loop circuit (hereinafter referred to as PLL) that regenerates the clock supplied to the system (1), 30
2 is the output signal from the input terminal 301 and P L L (
1) and the control signal of the 1125/30 system, or the P of the 525/60, 525/30 system.
This is a 1125-based timing generation circuit that supplies clocks to the LL.

304.305 are respectively 525/60°525/
PLL (2) that reproduces clocks compatible with the two display formats of the 30 series (ZOOM, WIDE).

PLL(3), 306 is PLL(2), PLL(3)
308 is a 1125 system timing output terminal; 309 is a 525 system timing generation circuit that supplies control signals and clocks for the 525/60, 525/30 system according to the clock from the 1125 system and the mode switching control signal from the control signal input terminal 307; is a 525 system timing output terminal.

The operation of the circuit shown in FIG. 3 will be explained below.

In FIG. 3, M is converted into a digital signal by the A/D converter 103 in FIG.
The USE signal is P L L (1) of 303 and 11
The signal is input to the timing generation circuit 302 of the 25 system. first,
In P L L (1), 32.4 synchronized with the incoming signal
A MHz clock is generated and input to the 1125 system timing generation circuit 302.

In the 1125 system timing generation/return path 302, various synchronization signals and control signals are created.
A/D converter 103, de-emphasis processing unit 105, and intra-field interpolation processing circuits 106 and 10 that operate synchronously
8. Color difference signal processing section 107, blanking insertion circuit 12
4. Output to the 1125 system timing output terminal 308 to be supplied to the D/A converter 112 and speed conversion circuit 109.

Furthermore, a 32.4 MHz clock is supplied to PLL (2) 304 and PLL (3) 305. P L L (
2) In 304, 32 obtained from the above PLL (1) 303
．． Generates a WIDE clock synchronized with a 4MHz clock. However, the WIDE clock referred to here is a clock that can display almost all of the pixels included in one line in the 1125/30 system within the video period in one line in the 525/60 system. frequency.

In P L L (3) 305, the above PLL (1) 3
ZO synchronized with 32.4MHz clock obtained from 03
Generates a clock for OM. However, here the 200
The clock for M is 3/4 of the number of pixels of the video period bone included in one line in the 1125/30 system,
This is the frequency that can be displayed within the video period of one line in the 525/60 system.

That is, the clock generated by PLL (3) 305 is P
The frequency is 3/4 times that of the clock generated by L L (2) 304 (or it may be exactly 3/4 times as high).

The 525-system timing generation circuit 306 is connected to the PLL (2
) 304, the clock generated by the PLL (3) 305, and the various control signals obtained from the control signal input terminal 307 for switching between two display formats (ZOOM, WIDE) are output to the 525 series circuit in FIG. It is output from the 525 system timing output terminal 309.

In FIG. 1, the circuits that operate at the 525 system timing are the speed conversion circuit 109, the color difference signal processing section 110, the blanking insertion circuit 125, the speed conversion processing circuit 111, and the D/A converters 113 and 114.

As shown in FIG. 3 above, the system of the present invention has a 1125/3
The 0 series (■) and the 525/60゜525/30 series have two display formats: ZOOM (■) and WIDE (■), and in order to control a total of three systems, they are compatible with each. A PLL must be provided.

FIG. 4 is a block diagram showing another embodiment of the present invention. In FIG. 4, the same reference numerals as those in FIG. 1 above perform the same operations. 401 is
This is an intra-field interpolation processing circuit.

Next, the operation of the circuit shown in FIG. 4 will be explained. The intra-field interpolation processing circuit 401 includes a de-emphasis processing section 105
inputs the signal from the MUSE signal, performs two-dimensional filter processing within the field,
Output signal of 5/30 and MUSE which is 1125/30
The scanning line barycenter position of the signal is converted to the barycenter position for non-interlaced scanning with the number of scanning lines 1125/2 and the frame frequency 607, that is, the scanning line barycenter position compatible with EDTV, and the scanning line is converted to a line memory, This is a processing circuit created with a circuit configuration in which most of the elements that make up the circuit are common.

According to the configuration shown in FIG. 4, the circuit scale of the field interpolation processing section is halved compared to that in FIG.
Outputs for TV compatible displays and outputs compatible with standard speed NTSC displays can be obtained simultaneously and in parallel.

Next, an example of the internal configuration and operation of the intra-field interpolation processing circuit 401 shown in FIG. 4 will be described using FIGS. 5 and 6.

FIG. 5 shows the field interpolation processing circuit 4 in FIG.
FIG. 2 is a block diagram showing an example of the configuration of 01.

In FIG. 5, the same reference numerals as in FIG. 4 indicate the same operations.

In FIG. 5, 501 is a MUSE signal input terminal input from the de-emphasis processing unit 105 in FIG.
2 is a TRF (transversal filter) processing circuit;
503 and 504 are the storage capacity for one line of the MUSE signal (here, the capacity is for the signal after TRF processing, that is, the capacity for one line after horizontal interpolation processing. 480 * 2
505 is a line memory with a storage capacity of 2 lines of color difference signals (94*2*8 bits), 508 is a Y whose signal level is different between the luminance signal period and the color difference signal period. /CIIJ control signal input terminals 506, 507, and 515 are selectors that select and output the a side for the luminance signal period and the b side for the color difference signal period, respectively.

509, 510, 514, 516 are adders, 5
12,513 switches the selection input for each field 2
A bit control signal input terminal 511 is a selector that switches and outputs the input signal for each field according to the control signal (2 bits) input from the control signal input terminals 512 and 513, 517 is a vertical delay processing section, and 518 is a selector that switches and outputs the input signal for each field. Vertical center of gravity position conversion processing unit, 519 is an output terminal that outputs the scanning line of the scanning line center of gravity position for 525/60, 520 is an output terminal for 1125/60;
This is an output terminal that outputs a scanning line for 30.

FIG. 6 is an explanatory diagram of the principle of operation of the circuit shown in FIG. 5.

In Figure 6, (a) shows the scanning line center of gravity position of the MUSE signal, (b) shows the scanning line center of gravity position for 525/60 in ZOOM mode, and (c) shows the center of gravity position of the scanning line for 5257 in WIDE mode.
FIG. 6 is a diagram of the center of gravity of the scanning line for 60 as viewed from the vertical-time axis direction. However, in order to simplify the explanation, only the luminance signal is shown here.

As shown in (a), in the MUSE signal, the scanning lines between fields are in an interlaced relationship, and in order to make these scanning lines have a 525/60 non-interlaced relationship in the ZOOM mode, -For example, (b)
A possible method is to create scanning lines at the center of gravity as shown in Figure 3. Furthermore, in WIDE mode, if the number of scanning lines is further thinned out to 3/4 compared to ZOOM mode, -
As an example, a method of creating a scanning line at the center of gravity as shown in (c) can be considered.

Therefore, as shown in FIG. 6(a), the scanning lines of the first field of the incoming signal, which is the MUSE signal, are
2, A3, A4, A5..., and the scanning lines of the second field are Bl, B2... B3. In the case of B4゜B5..., in ZOOM mode (b), in the first field, α1- [3(At)+4(A2)+(A3))/8
゜α2 = (3(A2)+4(A3)+(A4)l
/8°α3 = (3(A3)+4(A4)+(A
5)) /8 ..., and in the second field, β1 = ((Bl) + 4 (B2) + 3 (B3)) /
8゜β2= ((B2)+4(B3)+3(B4))
/8°B3 = ((B3)+4(84)+3(B5)
) /s . . . It is sufficient to create a scanning line at the center of gravity position.

Furthermore, in WIDE mode (c), which performs 3/4 compression processing in the vertical direction, in the first field, μm = (3 (AI) + 4 (A2) + (A3)
) / 8.

β2 = (2(A2)+4(A3)+2(A4))
/8°β3 = ((A3)+4(A4)+3(A5)
) /8 ... The scanning line of the center of gravity position expressed as
And in the second field, β1 = ((BO)+4(Bl)+3(B2))/
8゜β2 = (3(B2)+4(B3)+(B4))
/8°β3 = (2(B3)+4(B4)+2(B
5)) /8 It suffices to create a scanning line at the center of gravity position expressed as...

Next, the operation of the circuit shown in FIG. 5 will be explained using FIG. 6.

The input terminal 501 in FIG. 5 receives the MUSE signal from the emphasis processing unit 105 in FIG.
(1 Lance Versal Filter) The processing circuit 502 performs horizontal pixel interpolation and limits the horizontal pass band to 16 MHz or less (in order to minimize aliasing interference during still image playback, the horizontal pass band is limited to 12 MHz). Process.

The signal subjected to the above processing is input to the vertical delay processing section 517.

In the vertical delay processing section 517, the line memory 503.50
4 to obtain a 1-line delayed output and a 2-line delayed output for the input signal, and a line memory 505 to obtain a 4-line delayed output for the color difference signal. The selector 506 includes
A 1-line delayed output and a 2-line delayed output are inputted from the line memories 503 and 504, and a 2-line delayed output and a 4-line delayed output of the color difference signal are inputted to the selector 507 from the line memories 504 and 505.

Furthermore, the selectors 506 and 507 have control signal input terminals 5
Y/C from 08! LJ? 11 signals are input, and when the luminance signal is input, the a side input is selected, and when the color difference signal is input, the b side input is selected and output. Therefore, when the incoming signal from the vertical delay processing unit 517 is A3 shown in FIG. 6, AI is output during the luminance signal period.

A2. This means that A3 has been obtained. Here, in the color difference signal period, A(-1) (Although not shown in the figure, AI
It means the scanning line two lines before. ), AI.

This means that A3 has been obtained.

However, the color difference signal is subjected to vertical band compression processing, and (RY) and (B-Y) are generated for each line.

(RY), (B-Y), etc. are transmitted. Therefore, once the scanning line is obtained as described above, the subsequent color difference signal processing is performed in the same manner as the luminance signal. Therefore, from now on, the operation will be explained focusing on the luminance signal.

Scanning line A input to the vertical center of gravity position conversion processing unit 518
l and A3 are averaged by adder 509 to obtain (AI+A3)/2, which is input to selector 515, 511 and adder 510. Also scan IRAI, A3
C, l selection 1'3511 2 input L, and scanning line A1
is input to the selector 515.

The adder 510 inputs the output signal of the adder 509 and the signal obtained by doubling the scanning line A2, and performs addition ((Al
) +4(A2) + (A3) ) / 2 is obtained and input to adder 514.516.

The selector 511 selects the 1. In the field corresponding to the 3rd field, the scanning line input to the φ side is changed to the 6th field.
Figure 2. In the field corresponding to the fourth field, the scanning line input to the π side is selected and output.

Also, in WIDE mode, the 1st, 3rd and
...Fields corresponding to fields are φ in the order of input.
The scanning lines input to the side, ω side, and π side are shown in 2. in FIG. 6(C). In the field corresponding to the 4th field,
Scanning lines input to the π side, ω side, and φ side are selected and output in the input order.

Further, an adder 514 inputs the output signal of the adder 510 and the output signal from the selector 511 and adds them to 1/1.
The output signal multiplied by 4 is input to the output terminal 519 as the scanning line at the center of gravity of the 525/60 scanning line. That is, the output terminal 519 has the first
．． In the third field, (3(AI) +4(A2) + (A3)) /
8 = αl.

(3(A2) +4(A3) + (A4) ) /
The scanning line at the center of gravity position represented by 8 = α2... and in the 2nd, 4th, and 4th fields is ((Bl)+4(B2)+3(B3))/8 =β1
゜((B2)+4(B3)+3(B4))/8 =β
In the WIDE mode (FIG. 6(c)), the scanning line at the center of gravity position represented by 2... is output, and 3/4 compression processing in the vertical direction is performed (FIG. 6(c)). In the third field, (3(AI) +4(A2) + (A3)) /
8 = μm.

(2(A2) +4(A3) +2(A4) ) /
8 = μ2... The scanning line at the center of gravity position is expressed as ((BO)+4(Bl)+3(B2))/8 = ν1 in the 2nd, 4th, and 4th fields.
゜(3(B2)+4(B3)+3(B4))/8=
The scanning line at the center of gravity position represented by ν2... will be output.

This corresponds to creating a scanning line at the center of gravity of the 525/60 scanning line based on the principle explained with reference to FIG.

On the other hand, the selector 515 includes the above selectors 506 and 507.
Similarly, the Y/C control signal is input from the control signal input terminal 508, and when the luminance signal is input, the a side is selected and the scanning line A3 is input.
output, and when inputting color difference signals, select the b side (A
(-1)+A3)/2 is output and input to the adder 516. The adder 516 adds the input signals to 1/
When inputting the output signal multiplied by 4, that is, the luminance signal, always (
3(Al)+4(A2)+(A3))/8 is obtained, and when inputting color difference signals, always (2A(-1)+4(
AI) +2(A3) ) / 8, 1125 /
It is input to the output terminal 520 as a scanning line for 30.

As described above, constantly creating a scanning line with one center of gravity in each field corresponds to a shift in the center of gravity of the scanning line relative to the input scanning line. Therefore, the scanning lines input to the output terminal 520 have a 1125/30 interlace relationship for each field. Therefore, the above output signal can be used as a 1125/30 scanning line.

According to the circuit configuration shown in FIG. 5, the line memory of the intra-field interpolation processing circuit 401 is shared, and a part of the vertical scanning line centroid position conversion circuit for creating the scanning line centroid position for 525/60 is used. Using the same intra-field interpolation processing circuit 401, it is possible to simultaneously obtain a scanning line output for a display compatible with high-definition television and a scanning line output of the scanning line gravity center position for a display compatible with EDTV in 200M mode and WIDE mode.

FIG. 7 shows the intra-field interpolation processing circuit 4 in FIG.
FIG. 2 is a program diagram showing another example of the configuration of 01. 7th
In the figure, the same reference numerals as in FIGS. 4 and 5 perform the same operations.

In FIG. 7, 7, 01, 702, 703 are TRF processing circuits 70 equivalent to the TRF processing circuit 502 in FIG.
Reference numeral 4 denotes a vertical delay processing section having the same internal configuration as the vertical delay processing section 517 in FIG.

Next, the operation of the circuit shown in FIG. 7 will be explained. Input terminal 50
The output signal of the de-emphasis processing section 105 obtained from 1 is input to the vertical delay processing section 704. The vertical delay processing section 704 has the same internal configuration as the vertical delay processing section 517 shown in FIG. However, if the input signal is 517 in FIG.
Since the signal input to the vertical delay processing unit 517 in FIG. Half the memory capacity you have is sufficient.

In the vertical delay processing section 704, the A3 shown in FIG.
When the scanning line arrives, the output signals are Al, A2 . This means that A3 has been obtained. The scanning lines AI, A2, and A3 are input to TRF processing circuits 703, 702, and 701, respectively, and each of the TRF processing circuits performs horizontal pixel interpolation and horizontal pass band limitation, similar to the TRF processing circuit 502 in FIG. Do this.

Scanning lines AI and A2 are processed as described above.

A3 is input to the vertical center of gravity position conversion processing section 518,
A scanning line at the center of gravity of the 525/60 scanning line is created and outputted to the output terminal 519, and a 1125/30 scanning line is created and output to the output terminal 520.

According to the configuration shown in FIG. 7, compared to the configuration shown in FIG.
Although the logic part of the TRF processing circuit in the intra-field interpolation processing section increases, the memory capacity of the vertical delay processing section is halved, and the scanning line output for display compatible with high-definition television, 200M mode, and WIDE mode are improved. It is possible to simultaneously obtain the scanning line output of the scanning line gravity center position for an HDTV compatible display.

FIG. 8 shows the field interpolation processing circuit 4 in FIG.
FIG. 2 is a block diagram showing another example of the configuration of 01. In FIG. 8, the same reference numerals as in FIGS. 4, 5, and 7 perform the same operations.

In FIG. 8, 801, 804, 805 are adders;
02, 803 is a TRF processing circuit; 806 is a selector that performs an operation equivalent to 506, 507, 508 in FIG. 5;
807 is a vertical center of gravity position conversion processing unit.

Next, the operation of the circuit shown in FIG. 8 will be explained. Input terminal 50
The output signal of the de-emphasis processing section 105 obtained from 1 is input to the vertical delay processing section 704. When the scanning line A3 shown in FIG. 6(A) arrives from the vertical delay processing unit 704, AI, A2 . A3 is obtained.

In this processing system, TRF processing circuits 703, 702.
The signal inputted to the vertical center of gravity position conversion processing unit 807 via 701 and output from the vertical center of gravity position conversion processing unit 807 to the output terminal 519 is the signal 200 as shown in FIG.
M mode and 1125/30 signal output corresponding to the scanning line at the center of gravity of the EDTV compatible scanning line on WIDEID.

The 1125/30 output signals in FIGS. 5 and 7 above are all 1125
/30 interlaced output signal, but vertical filter processing (
Since the output signal is subjected to vertical center-of-gravity position conversion processing, a sufficient vertical passband cannot be obtained, resulting in 1125
It is difficult to obtain sufficient vertical resolution when reproducing a /30 signal. Further, in the color difference signal, when transmitting a still image, a high frequency component in the horizontal direction is folded back into a low frequency component in the horizontal direction and a high frequency component in the vertical direction. For this reason, it is better not to widen the vertical pass band of the color difference signal.

Therefore, in the configuration example of this circuit, a new TRF processing circuit 802.803 is added for creating a 1125/30 luminance signal.
Adders 801 and 804 are provided. The adder 801 is
Add scanning lines A1 and A3 obtained from the vertical delay processing section,
The signal is input to the TRF processing circuit 803. TRF processing circuit 80
2 performs horizontal pixel interpolation and horizontal pass band limitation on the scanning line A2 obtained from the vertical delay processing section, and on the output obtained from the adder 801, the TRF processing circuit 803 respectively.

The adder 804 is connected to the TRF processing circuit 802.
The adder 801, TRF processing circuits 802, 803, and adder 804 constitute a two-dimensional filter within the field. At this time, the tap coefficients of the TRF processing circuits 802 and 803 are selected to widen the vertical passband. On the other hand, the adder 805 adds the output signals of the adders 509 and 510, and outputs an output signal (2A (-1)) with less aliasing components in the vertical direction, which is equivalent to the adder 516 of FIG. 5 in the color difference signal period.
+4 (Al) +2 (A3) ) / 8 was obtained.

The selector 806 selects and outputs the luminance signal obtained from the adder 804 and the color difference signal obtained from the adder 805 in accordance with the control signal obtained from the control signal input terminal 508 and inputs it to the output terminal 520. By performing the above processing, a 1125/30 scanning line with improved vertical resolution is created and outputted to the output terminal 520 for the luminance signal.

According to the configuration shown in FIG. 8, compared to the configuration shown in FIG.
Although the number of logic units such as TRF processing circuits in the intra-field interpolation processing unit increases, the 200M mode and WID
It is possible to simultaneously obtain a scanning line output at the scanning line gravity center position for an EDTV compatible display on the EID and a scanning line output for a high definition television compatible display with improved vertical resolution during luminance signal reproduction.

FIG. 9 shows the field interpolation processing circuit 4 in FIG.
FIG. 2 is a block diagram showing yet another example of the configuration of 01. 9th
In the figures, the same reference numerals as in FIGS. 4, 5, 7, and 8 perform the same operations.

In FIG. 9, 901 is 701°702. in FIG.
The TRF processing circuit has the same configuration as 703, and 902 is a vertical center of gravity position conversion processing section.

Next, the operation of the circuit shown in FIG. 9 will be explained using FIG. 10. FIG. 10 is a diagram explaining the principle of the signal processing operation in FIG. 9.

As mentioned above, from the vertical delay processing unit 704, the
When the scanning line of A3 shown in b) arrives, AI, A2.
A3 is obtained. First, 1125 of the output terminal 520
Let's take a look at the /30 output system. 1 in this processing system
The output for 125/30 is equivalent to that shown in Figure 8 for the luminance signal, but for the color difference signal, it is equivalent to that shown in Figure 8 above.
Since processing equivalent to the luminance signal processing shown in the figure is performed, the vertical passband is widened during still image transmission.

Therefore, with this circuit configuration, when a still image is transmitted,
The reproduced output of the 1125/30 color difference signal contains slightly more aliasing components than in the configuration shown in FIG. However, considering that the color difference signal has less influence on the human eye during image reproduction than the luminance signal, this does not pose a major problem.

Next, let's take a look at the 525/60 EDTV compatible output system. This configuration has a configuration in which the order of the TRF processing circuit and the vertical center of gravity position conversion processing section is changed compared to the configuration shown in FIG. The fact that this process is possible in principle will be explained using FIG. 1O.

Figure 10 shows the output signal and the vertical center of gravity position when the tap coefficients of N TRF (transversal filter) processing circuits are equal, and the vertical center of gravity position conversion processing is performed after TRF processing. FIG. 6 is a principle diagram for explaining that output signals become equal when TRF processing is performed after conversion processing.

In FIG. 10, (a) shows the case where vertical center of gravity position conversion processing is performed after TRF processing, and (
b) is TR after performing vertical center of gravity position conversion processing.
This shows the case where F processing was performed.

Here, to simplify the explanation, it is assumed that the TRF processing unit has five tap coefficients, and they are 1.1, 2,
1.1, and the coefficient in the vertical direction is assumed to be 1.2.1.

In FIG. 10, (c) is the TRF used to explain the principle.
(d) shows the internal structure of the processing circuit, and (d) shows the internal structure of the vertical center of gravity position conversion processing section used for explaining the principle. 1st
In Figure 0 (a), the output signal at time t shown in the figure corresponds to finding the pixel at the position S (☆) in the figure, and when calculated according to the coefficients shown in the figure, S (☆) = (( a+c)+2 b)+(b'+c
')+((a″+C″)+2b″) ・・・・・・
10(b), the output signal at time t shown in the figure corresponds to finding the pixel at the position M(·) in the figure, and when calculated according to the coefficients shown in the figure, M(·) = (a+a")+(2b'+2(b+b")
))+(2c'+c+c") = (a+a")+2(b+b'+b")+ (c+
2c'+c'') ・・・・・・■.

Here, if we transform the above ■2 and combine them into a, b, and c, we get S(☆)=(a+a")+2(b+b'+b")+(
C+2 C'+C''') That is, S(☆)=M(·), and it can be seen that even if the order of the TRF processing and the vertical center of gravity position conversion processing is changed, the output signals match.

This is not limited to the case of the above-mentioned tap coefficients; boat fishing has non-linear components as shown in the TRF processing circuit in Figure 10 (C) and the vertical center of gravity position conversion processing section (d). If not, if the tap coefficients of the TRF processing circuits are equal, the output signal when vertical center of gravity position conversion processing is performed after performing TRF processing, and the output signal when TRF processing is performed after performing vertical center of gravity position conversion processing. The output signals in the case are equal.

From the above explanation, it can be seen that in FIG. 9, the same output signal as that obtained in FIG. 8 can be obtained at the output terminal 519. Here, the tap coefficients of the actual TRF processing section have many digits after the decimal point, and this affects the filter characteristics of the two-dimensional filter, so the data bit width after TRF processing is usually the same as the bit width of the input signal. In comparison, the bit width is nearly double. Therefore, in an actual circuit, the circuit scale of the vertical center of gravity position conversion processing section when using the configuration shown in FIG. It can be much smaller than the scale.

According to the configuration shown in FIG. 9, compared to the configuration shown in FIG.
The circuit size of the TRF processing circuit in the intra-field interpolation processing section has been reduced to 1/3, and in addition, the circuit size of the vertical center of gravity position conversion processing section has been significantly reduced. A scanning line output at the scanning line gravity center position and a scanning line output for a display compatible with high-definition television can be obtained simultaneously.

FIG. 11 is a block diagram showing still another embodiment of the present invention. In FIG. 11, the same reference numerals as in FIGS. 1 and 4 above perform the same operations. 1101 is a color signal processing circuit for 1125/30 output, 1102 is a luminance signal, a color difference signal, and a 525/6 output color signal processing circuit.
The speed conversion processing circuit 1103 converting to 0 is 525/
This is a color difference signal processing circuit for 60 outputs.

Next, the operation of the circuit shown in FIG. 11 will be explained using FIGS. 12 and 13. FIG. 12 is a block diagram showing details of the color difference signal processing circuit 1101 in FIG.
FIG. 3 is a block diagram showing details of the speed conversion processing circuit 1102 in FIG. 11.

In FIG. 11, the 1125/30 scanning line output created by the intra-field interpolation processing circuit 401 is input to the color difference signal processing circuit 1101.

In the intra-field interpolation circuit 401, the color difference signal is still a signal whose band has been compressed in the horizontal/vertical directions and the time axis direction. FIG. 12 shows the internal configuration of the color difference signal processing section that returns this signal to the original signal.

In FIG. 12, 1201 is a scanning line signal input terminal for 1125/30, 1202 is a time axis expansion section, 1203 is a line sequential processing section, 1204 is a color difference interpolation processing section, and 1205.1
206 is (R-Y), (B-Y) signal output terminal, 12
07.1208 is a color difference signal output terminal for 1125/30.

The color difference signal inputted from the intra-field interpolation circuit 401 is inputted from the input terminal 1201, and is inputted to the time axis expansion section 120.
In 2, the color difference signal whose time axis has been compressed to 1/4 of the luminance signal is read out using a memory at a clock rate of 1/4 of the luminance signal, and the time axis is expanded, and the luminance signal and Align the horizontal time axis.

Next, the line sequential processing unit 1203 performs line sequential processing (vertical line interpolation), and for each line (RY),
(B-Y) Create a signal and output terminal 1205.120
6′ and output to the color difference interpolation processing unit 1204. The above (RY) input to output terminals 1205 and 1206, (
The B-Y) signal is supplied to the speed conversion processing circuit 1102. Further, in the color difference interpolation processing unit 1204 in FIG. 12, the above (RY) is performed.

The (B-Y) signal is subjected to pixel interpolation in the horizontal direction and output to output terminals 1207 and 1208.

The color difference signals outputted to the output terminals 1207 and 1208 are supplied to the D/A converter 112 after a blanking period is inserted in the blanking insertion circuit 124 .

Before performing the interpolation process obtained from the color difference signal processing circuit 1101 for 1125/30, and with respect to the luminance signal,
/4 times the data rate (RY).

The (B-Y) signal and the luminance signal obtained from the field interpolation unit 401 are input to the speed conversion processing circuit 1102. The internal configuration of this speed conversion processing circuit 1102 will be explained using FIG. 13.

In FIG. 13, the same reference numerals as in FIGS. 11 and 12 perform the same operations.

1301 is the above luminance signal input terminal, 1302.1305
1303 is the speed conversion memory section, and 525/1303 is the luminance signal.
60 EDTV compatible output terminal, 1304 is a multiplexing unit that multiplexes color difference signals, 1306 is a separation processing unit that separates color difference signals that have been subjected to speed conversion processing while being multiplexed, and 1307 and 1308 are 525/6
This is an output terminal for 0EDTV compatible output.

The luminance signal is speed-converted from 1125/30 to 525/60 EDTV compatible output by a speed conversion memory unit 1302 and is supplied to an output terminal 1303. Also,
As described above, the color difference signal supplied to the speed conversion processing circuit 1102 has a data rate 1/4 times that of the luminance signal.

Therefore, in the multiprocessing unit 1304, the input terminal 121
(RY) and ( after line sequential processing obtained from 6.1217
B-Y) signal, upper bit and lower bit
It selects and outputs a total of four input signals to multiplex color difference signals and quadruple the data rate. As a result, the color difference signal has the same data rate as the luminance signal, and it becomes possible to control the speed conversion memory section of the color difference signal using the same clock and control signal as the luminance signal.

Next, the color difference signal is converted from 1125/30 to 525/60 by the speed conversion memory unit 1305 while being subjected to multiple processing.
Speed conversion to EDTV compatible output. Separation processing unit 130
6, performs the inverse of the above multiprocessing and outputs the output terminal 1.
Supply to 307.1308.

After performing the above signal processing, the luminance signal is
After a blanking period is inserted in the blanking insertion circuit 125 shown in the figure, it is output to the speed conversion circuit 111 and the D/A converter 113. Regarding the color difference signal, the color difference signal processing circuit 1103 performs only color difference interpolation processing, horizontal pixel interpolation, and blanking insertion circuit 1103 performs pixel interpolation in the horizontal direction.
After inserting a blanking period in step 25, the signal is output to the speed conversion circuit 111 and the D/A converter 113.

According to the configuration shown in FIG. 11, compared to the configuration shown in FIG. 4, most of the circuits of the color difference signal processing section are shared, so that the color difference signal processing section, which has a built-in memory capacity of three lines, The memory capacity of the entire system can be reduced to 1/2.

The configuration of the receiving and processing device capable of outputting video signals compatible with the three television systems in parallel has been described above.

In the embodiments shown in FIGS. 1, 4, and 11, the output signals are output in the form of Y, (RY), and (B-Y), but an RGB matrix circuit is provided in the output section. It is also possible to take the form of RGB output by adding . Since the receiving and processing device of the present invention has a wide variety of output signals, it is most suitable for commercialization as an adapter type product with a built-in BS tuner, for example.

〔Effect of the invention〕

According to the present invention, when receiving a high-definition television signal, it is possible to obtain a signal output capable of simultaneously and parallelly displaying images on all television receivers that currently exist in the world. Advantageously, it is possible to provide a television signal reception and processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example of a high-definition television signal reception and processing device, and FIG. 3 is a block diagram of a control signal generation section in FIG. 4 is a block diagram showing another embodiment of the present invention. FIG. 5 is a block diagram showing a specific example of the intra-field interpolation processing section in FIG. 4.
The figure is an explanatory diagram showing the operating principle of the vertical center of gravity position conversion processing unit in the intra-field interpolation processing unit. Figure 7 is a block diagram showing another example of the configuration of the intra-field interpolation processing unit. FIG. 9 is a block diagram showing still another example of the configuration of the interpolation processing section. FIG. 10 is a block diagram showing still another example of the configuration of the intra-field interpolation processing section. FIG. FIG. 11 is a block diagram showing still another embodiment of the present invention, FIG. 12 is a block diagram showing details of the color difference signal processing unit for 1125/30 output in FIG. 11, and FIG. 525/6 in Figure 11
FIG. 3 is a block diagram showing details of a speed conversion processing section for creating a 0 output. Explanation of symbols 1...In-field signal processing circuit, 101...MU
SE signal input terminal, 102... demodulation circuit, 103...
- A/Di conversion section, 104... Control signal generation section, 105... De-emphasis processing section, 106...
Intra-field interpolation processing circuit, 107... Color difference signal processing circuit, 108... Intra-field interpolation processing circuit, 109
. . . Speed conversion processing circuit, 110 . . . Color difference signal processing circuit, 111 . . . Speed conversion processing circuit, 112, 113.
114...D/A conversion section, 115, 116, 117.
・・1125/30 output terminal, 118, 119, 120
...525/60 output terminal, 121, 122.123
...525/30 output terminal, 124,125...Blanking insertion circuit agent Patent attorney Akio Namiki (C) TRF's A3'A10 Figure (b) Filling, Tamari diagram (Part 2) ( Tonao Difficulty-TRF) (C)
Taku d's office Ohribe■Ixo

Claims (1)

[Claims] 1. By receiving and processing a high-definition television signal, a video signal adopting a high-definition television system (hereinafter referred to as an HDTV system) and a double-speed television system (hereinafter referred to as an EDTV system) can be generated. ) and a video signal that uses the standard speed scanning television system (hereinafter referred to as the NTSC system) in a high-definition television signal receiving and processing device that makes it possible to output simultaneously and in parallel, demodulation means (102) for demodulating the received analog high-definition television signal; A/D conversion means (103) for converting the demodulated output from the demodulation means from an analog signal to a digital signal; and the A/D conversion means. Synchronous signal reproducing means (104) for extracting and reproducing control signals such as clock signals and synchronizing signals for signal processing from input digital signals from
Then, using the control signal from the synchronization signal reproducing means, intra-field signal processing is performed on the digital high-definition television signal that is the demodulated output from the demodulating means, and H
an in-field signal processing means (1) for outputting in parallel a digital video signal adopting the DTV system, a digital video signal adopting the EDTV system, and a digital video signal adopting the NTSC system; First, second and third D/A conversion means (112, 113,
114), and a high-definition television signal reception and processing device. 2. By receiving and processing a high-definition television signal, it is possible to create a video signal that uses the high-definition television system (hereinafter referred to as the HDTV system) and a video signal that uses the double-speed television system (hereinafter referred to as the EDTV system). , a standard speed scanning television system (hereinafter referred to as NTSC system) video signal, and a high-definition television signal receiving and processing device that enables simultaneous and parallel output of the received analog high-definition television. demodulating means (102) for demodulating the demodulating signal; A/D converting means (103) for converting the demodulated output from the demodulating means from an analog signal to a digital signal; and inputting the digital signal from the A/D converting means. synchronization signal reproducing means (104) for extracting and reproducing control signals such as clock signals and synchronization signals for signal processing;
Then, using the control signal from the synchronization signal reproducing means, intra-field signal processing is performed on the digital high-definition television signal that is the demodulated output from the demodulating means, and H
A first intra-field interpolation processing means (106) that creates and outputs a digital video signal adopting the DTV system, and a color difference signal as an output from the first intra-field interpolation processing means (106), a first color difference signal processing means (107) that performs time axis expansion processing, line sequential processing, and interpolation processing on the color difference signal compressed and multiplexed in the time axis, and outputs the resultant processing; and the first intra-field interpolation processing means (106) and the first color difference signal processing means (10
a first D/A converting means (112) which receives the color difference signal from 7), converts the digital signal into an analog signal, and outputs it as a video signal adopting the HDTV system; and a control signal from the synchronizing signal reproducing means. is used to perform in-field signal processing on the digital high-definition television signal that is the demodulated output from the demodulating means, and performs ED
a second intra-field interpolation processing means (108) for creating and outputting a digital video signal adopting the TV system;
a first speed conversion processing means (109) which receives an output signal from the intra-field interpolation processing means (108), converts the number of scanning lines and scanning speed of the signal according to the HDTV system to those according to the EDTV system, and outputs the converted signal; Then, the color difference signal output from the first speed conversion processing means (109) is subjected to time axis expansion processing, line sequential processing, and interpolation processing of the color difference signal compressed and multiplexed in the time axis, and is output. a second color difference signal processing means (110), which inputs a luminance signal as an output from the first speed conversion processing means (109) and a color difference signal from the second color difference signal processing means (110); EDTV by converting digital signals to analog signals
a second D/A converting means (113) that outputs a video signal using a method of converting a luminance signal as an output from the first speed conversion processing means (109) and a second color difference signal processing means (110); )
a second speed conversion processing means (111) which receives a color difference signal from the EDTV system, converts the number of scanning lines and scanning speed of the signal into those according to the NTSC system, and outputs the converted signals;
The signal from the second speed conversion processing means (111) is input and converted from a digital signal to an analog signal and converted into an NTS
1. A high-definition television signal reception and processing device comprising: third D/A conversion means (114) for outputting a video signal adopting the C format. 3. By receiving and processing a high-definition television signal, it is possible to create a video signal that uses the high-definition television system (hereinafter referred to as the HDTV system) and a video signal that uses the double-speed television system (hereinafter referred to as the EDTV system). , a standard speed scanning television system (hereinafter referred to as NTSC system) video signal, and a high-definition television signal receiving and processing device that enables simultaneous and parallel output of the received analog high-definition television. demodulating means (102) for demodulating the demodulating signal; A/D converting means (103) for converting the demodulated output from the demodulating means from an analog signal to a digital signal; and inputting the digital signal from the A/D converting means. synchronization signal reproducing means (104) for extracting and reproducing control signals such as clock signals and synchronization signals for signal processing;
A digital high-definition television signal, which is the demodulated output from the demodulation means, is input, and a line memory that delays the television signal is used to generate a digital video signal with the number of scanning lines according to the HDTV system and scanning according to the EDTV system. intra-field interpolation processing means (401) for generating and outputting digital video signals of scanning lines that match the line gravity center positions by intra-field interpolation processing using control signals from the synchronization signal reproduction means; HDT from intra-field interpolation processing means (401)
A first method that performs time-axis expansion processing, line-sequential processing, and interpolation processing on the color-difference signal in the digital video signal with the number of scanning lines according to the V method, which is compressed and multiplexed in the time-axis, and outputs the resultant A color difference signal processing means (107) and a luminance signal in a digital video signal of the number of scanning lines according to the HDTV system from the field interpolation processing means (401) and a luminance signal from the first color difference signal processing means (107). The color difference signal is input and the digital signal is converted to an analog signal and converted to HD.
a first D/A conversion means (112) that outputs a video signal adopting a TV system; and an EDT from the intra-field interpolation processing means (401).
a first speed converting means (109) that receives a digital video signal of a scanning line that matches the scanning line gravity center position according to the V method, converts it into a signal of the number of scanning lines and a scanning speed according to the EDTV method, and outputs the signal; A second color difference signal that is outputted by subjecting the color difference signal as the output of the first speed converting means (109) to time axis expansion processing, line sequential processing, and interpolation processing of the color difference signal compressed and multiplexed in the time axis. A signal processing means (110) receives the luminance signal as the output of the first speed conversion means (109) and the color difference signal from the second color difference signal processing means (110) and converts the digital signal into an analog signal. a second D/A converter (113) that converts and outputs a video signal that adopts the EDTV system; and a luminance signal as an output of the first speed converter (109) and the second color difference signal processor The color difference signal from (110) is input, and the number of scanning lines and scanning speed are
A second speed converting means (111) converts into an SC method and outputs the same; and a second speed converting means (111) receives an NTSC digital signal from the second speed converting means (111) and converts it into an analog signal to use the NTSC method. A high-definition television signal reception and processing device comprising: third D/A conversion means (114) for outputting as a video signal. 4. By receiving and processing a high-definition television signal, it is possible to create a video signal that uses the high-definition television system (hereinafter referred to as the HDTV system) and a video signal that uses the double-speed television system (hereinafter referred to as the EDTV system). , a standard speed scanning television system (hereinafter referred to as NTSC system) video signal, and a high-definition television signal receiving and processing device that enables simultaneous and parallel output of the received analog high-definition television. demodulating means (102) for demodulating the demodulating signal; A/D converting means (103) for converting the demodulated output from the demodulating means from an analog signal to a digital signal; and inputting the digital signal from the A/D converting means. synchronization signal reproducing means (104) for extracting and reproducing control signals such as clock signals and synchronization signals for signal processing;
A digital high-definition television signal, which is the demodulated output from the demodulation means, is input, and a line memory that delays the television signal is used to generate a digital video signal with the number of scanning lines according to the HDTV system and scanning according to the EDTV system. intra-field interpolation processing means (401) for generating and outputting digital video signals of scanning lines that match the line gravity center positions by intra-field interpolation processing using control signals from the synchronization signal reproduction means; HDT from intra-field interpolation processing means (401)
A first method that performs time-axis expansion processing, line-sequential processing, and interpolation processing on the color-difference signal in the digital video signal with the number of scanning lines according to the V method, which is compressed and multiplexed in the time-axis, and outputs the resultant A color difference signal processing means (1101) and a luminance signal in a digital video signal of the number of scanning lines according to the HDTV system from the field interpolation processing means (401) and a luminance signal from the first color difference signal processing means (1101). A first D/D/D converter inputs a color difference signal, converts the digital signal into an analog signal, and outputs the converted signal as a video signal compatible with the HDTV system.
A conversion means (112), and a luminance signal as an output from the field interpolation processing means (401) and the first color difference signal processing means (110).
The color difference signal after line sequential processing (before interpolation processing) from 1) is input, and using separate memories, the number of scanning lines and the scanning speed are converted into EDT using the HDTV system.
a first speed converting means (1102) that converts into a V system and outputs it; and the first speed converting means (1102).
a second color difference signal processing means (1103) that performs interpolation processing on the color difference signal as the output of the first speed converting means (1102), and a luminance signal as the output of the first speed converting means (1102); A second input unit receives the color difference signal from the color difference signal processing means (1103), converts the digital signal into an analog signal, and outputs the converted signal as a video signal using the EDTV system.
A D/A converting means (113) receives the luminance signal as an output of the first speed converting means (1102) and the color difference signal from the second color difference signal processing means (1103), and performs scanning thereof. a second speed converting means (111) for converting the line number and scanning speed into those according to the NTSC system and outputting the converted data;
), a third D/A conversion means (114) receives an input digital signal according to the NTSC system, converts it into an analog signal, and outputs it as a video signal according to the NTSC system. Quality television signal reception and processing equipment. 5. Receiving the high definition television signal according to claim 4;
In the processing device, the first speed conversion means (1102
) is the color difference signal after line sequential processing from the first color difference signal processing means (1101) during speed conversion processing of the color difference signal (
The multiplex circuit (1304 ), a speed conversion circuit (1305) that performs speed conversion on the output from the multiplex circuit (1304) and outputs the result, and the output from the speed conversion circuit (1305) is inputted and converted to the original (R- A separation circuit (1306) that separates and reproduces the Y) signal and the (B-Y) signal, and allows the clock used for speed conversion of the luminance signal to be directly used for speed conversion of the color difference signal during speed conversion processing. This is a high-definition television signal reception and processing device. 6. In the high-definition television signal reception and processing device according to claim 3 or 4, the intra-field interpolation processing means (401) performs a transversal type (hereinafter referred to as TRF) processing on the input signal. TRF processing means (502) that performs horizontal low-pass filter processing;
Vertical delay means (517) delays the color difference signal and luminance signal in the vertical direction with respect to the output signal from the vertical delay means (502); a scanning line center of gravity position conversion means (518) for creating and outputting a digital video signal of a number of digital video signals and a scanning line that matches the center of gravity position of the scanning line according to the EDTV system. Signal reception and processing equipment. 7. The high-definition television signal reception and processing device according to claim 3 or 4, wherein the intra-field interpolation processing means (401) is a vertical interpolation processor that delays the color difference signal and the luminance signal as input signals in the vertical direction. a delay means (704); a TRF processing means (701 to 703) that performs transversal type (hereinafter referred to as TRF) horizontal low-pass filter processing on the output signal from the vertical delay means (704); The output signal from the TRF processing means (701 to 703) is inputted, and then a digital video signal of the number of scanning lines according to the HDTV system and a digital video signal of the scanning line matching the scanning line gravity center position according to the EDTV system are created and output. A high-definition television signal reception and processing device characterized by comprising: scanning line gravity center position conversion means (518). 8. In the high-definition television signal reception and processing device according to claim 3 or 4, the intra-field interpolation processing means (401) comprises TRF processing means for performing TRF processing;
A scanning line gravity center position conversion processing means (807) and a vertical delay unit (807) that delays the color difference signal and the luminance signal in the vertical direction.
704), and the scanning line barycenter position conversion processing means (
807) is equipped with a selector (511) that switches signal processing for each field or according to the display mode, and an arithmetic circuit that performs arithmetic operations between the output signal of the selector and the input signal. All that is required is to create a scanning line for compressed display and a scanning line for left and right cut display of a screen compatible with EDTV, and furthermore, provide a signal processing path that does not pass through the selector (511) in the arithmetic circuit. , a high-definition television signal reception and processing device, characterized in that it also creates displayable scanning lines on a high-definition television display. 9. Receiving a high definition television signal according to claim 7;
In the processing device, the field interpolation processing means (4
The TRF processing means in 01) is the vertical delay means (704) that delays the color difference signal and the luminance signal in the vertical direction.
1. A television receiving device comprising TRF processing means having different configurations (tap coefficients) for EDTV and HDTV for output signals obtained from the television receiver. 10. In the high-definition television signal reception and processing device according to claim 3 or 4, the intra-field interpolation processing means (401) performs vertical compression display (hereinafter referred to as WIDE) of a screen compatible with EDTV. Creation of scanning lines for ED
Left and right cut display of screen compatible with TV (hereinafter referred to as ZOOM
When creating a scanning line for (denoted as ), the apparatus is characterized by comprising a TRF processing means for performing scanning line barycentric position conversion processing on the output signal obtained from the vertical delay means, and then performing TRF processing on the output signal obtained from the vertical delay means. reception of high-definition television signals,
Processing equipment. 11. The high-definition television signal reception and processing device according to claim 1, 2, 3, or 4, wherein a digital HDT
In the luminance signal processing system for V signal output, one
Equipped with a speed conversion processing unit that performs 2/11 times time expansion,
Furthermore, the color difference signal processing system is characterized in that the time axis expansion processing section of the speed conversion processing means is comprised of a speed conversion processing means that realizes time axis expansion processing that also serves as 12/11 times horizontal time expansion. reception of high-definition television signals,
Processing equipment. 12. The high-definition television signal reception and processing device according to claim 1, 2, 3, or 4, wherein the synchronization signal reproducing means generates a first clock signal when generating a high-definition television signal. The first phase-locked loop (
A high-definition television signal characterized by comprising a PLL (hereinafter referred to as PLL), and second and third PLLs that are generated corresponding to two display formats (WIDE, ZOOM) on an EDTV display, respectively. receiving and processing equipment.