JPH04302468A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device.
It is particularly suitable for application to MOS dynamic RAM.

0002

2. Description of the Related Art With the development of integrated circuit technology, MOS dynamic RAMs are becoming increasingly larger in capacity and density, and their characteristics are also significantly improved.

MOS dynamic RAM, which has been mainly used in the past, consists of one MIS transistor (MI
A memory cell is composed of a MISFET (SFET) and one capacitive element (capacitor), and information is written to or read from the memory cell by accumulating or detecting charge in the capacitor by the switching action of the MISFET. Therefore, as the density of devices increases, it becomes necessary to reduce the area occupied by the capacitor to improve area efficiency.

[0004] In recent years, ultra-highly integrated MOS dynamic RAM after 1 Mbit to 4 Mbit MOS dynamic RAM has been developed.
In AM, instead of a planar capacitor in which a plate electrode is formed on the surface of a semiconductor substrate via a gate insulating film, a first layer electrode (
A stacked capacitor has a second layer electrode (upper electrode) formed on top of the lower electrode via a dielectric film.
capacitor) has become widely used.

FIG. 7 shows an example of a conventional MOS dynamic RAM using this stacked capacitor cell.

As shown in the figure, in this conventional MOS dynamic RAM, p-type silicon (Si
) A field insulating film 102 is selectively formed on the surface of the substrate 101, thereby providing isolation between elements. A gate insulating film 103 is formed on the surface of the active region surrounded by this field insulating film 102. WL1
', WL2' indicate word lines. These word lines W
Sidewall spacers 104 are formed on the sidewalls of L1' and WL2'.

In the p-type Si substrate 101, there are word lines WL.
For example, an n+ type diffusion layer 105 used as a source region or a drain region in a self-aligned manner with respect to
106 is formed. These diffusion layers 105, 10
For example, n- type low impurity concentration portions 105a, 10
6a is formed. The word line WL1' and these diffusion layers 105 and 106 form an n-channel MISFET as an access transistor. In this case, this n-channel MISFET has an LDD (lightly doped drai) structure in which the electric field near the drain region is relaxed by the low impurity concentration portion 106a.

In the figure, 107 indicates an interlayer insulating film. Also,
108 indicates a lower electrode (storage node). This lower electrode 108 is connected to the diffusion layer 1 through a contact hole C1' formed in the interlayer insulating film 107 and the gate insulating film 103.
Connected to 06. Furthermore, 109 indicates a dielectric film. Further, 110 indicates an upper electrode (cell plate). These upper electrode 110, dielectric film 109 and lower electrode 10
8 forms a stacked capacitor. A memory cell is constituted by the above-mentioned access transistor and this stacked capacitor.

Furthermore, 111 indicates an interlayer insulating film. Also,
BL' indicates a bit line. This bit line BL' is connected to the diffusion layer 105 through a contact hole C2' formed in the interlayer insulating films 111 and 107 and the gate insulating film 103.

0010

[Problems to be Solved by the Invention] In the conventional MOS dynamic RAM having the structure as shown in FIG. There has been a problem in that it becomes difficult to ensure sufficient characteristics to stably read and write information to and from memory cells due to a decrease in the amount of stored charge due to a reduction in the area of the capacitor.

Therefore, the present invention increases the storage charge amount by improving the stacked capacitor structure, and even when applied to, for example, a MOS dynamic RAM with a storage capacity of 64 Mbit or more, it is possible to read and write information to and from memory cells. An object of the present invention is to provide a semiconductor memory device that can stably perform the following steps.

0012

Means for Solving the Problems In order to solve the above problems, in the present invention, in a semiconductor memory device having a memory cell constituted by an MIS transistor and a stacked capacitor, the upper surface of the lower electrode of the stacked capacitor is , an uneven surface having side surfaces substantially perpendicular to the semiconductor substrate is provided.

[0013]

[Operation] According to the semiconductor memory device of the present invention configured as described above, on the upper surface of the lower electrode of the stacked capacitor,
Since the unevenness is provided with side surfaces substantially perpendicular to the semiconductor substrate, the effective surface area of the lower electrode can be significantly increased compared to conventional structures, and therefore the stacked capacitor can be improved by that amount. The amount of storage charge can be increased. As a result, even when applied to a MOS dynamic RAM with a storage capacity of 64 Mbits or more, for example, information can be stably read from and written to a memory cell.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

FIG. 1 shows a MOS dynamic RAM according to one embodiment of the present invention.

As shown in the figure, the MO according to this embodiment
In the S dynamic RAM, for example, silicon dioxide (
A field insulating film 2 such as a SiO2 film is selectively formed to provide isolation between elements. On the surface of the active region surrounded by this field insulating film 2,
For example, a gate insulating film 3 such as a SiO2 film is formed. WL1 and WL2 indicate word lines. These word lines WL1 and WL2 are made of, for example, a first layer polycrystalline Si film doped with an impurity such as phosphorus (P),
It is formed of a polycide film in which a high melting point metal silicide film such as a tungsten silicide (WSix) film is superimposed on this impurity-doped polycrystalline Si film. Sidewall spacers 4 made of, for example, SiO2 are formed on the sidewalls of these word lines WL1 and WL2.

In the semiconductor substrate 1, for example, n+ type diffusion layers 5 and 6, which are used as a source region or a drain region, are formed in a self-aligned manner with respect to the word line WL1. In portions of these diffusion layers 5 and 6 below the sidewall spacer 4, for example, n-type low impurity concentration portions 5a and 6a are formed. The word line WL1 and these diffusion layers 5 and 6 form an n-channel MISFET as an access transistor. In this case, this n-channel MISFET is
It has an LDD structure in which the electric field near the drain region is relaxed by the low impurity concentration portion 6a.

In the figure, 7 indicates an interlayer insulating film. This interlayer insulating film 7 is made of, for example, a SiO2 film, a phosphosilicate glass (PSG) film, or a boron phosphosilicate glass (BPSG) film.
) film or arsenic silicate glass (AsSG) film.

Reference numeral 8 denotes a lower electrode (formed by a second layer of polycrystalline Si film doped with an impurity such as phosphorus).
storage node). This lower electrode 8 is connected to the interlayer insulating film 7
and a contact hole C1 formed in the gate insulating film 3
It is connected to the diffusion layer 6 through. This lower electrode 8
It is preferable that the film thickness of the polycrystalline Si film forming this is about twice that of the conventional MOS dynamic RAM shown in FIG.

In this embodiment, an uneven surface 8a having a side surface substantially perpendicular to the semiconductor substrate 1 is formed on the upper surface of the lower electrode 8. Here, the aspect ratio of the concave portion of the unevenness 8a is selected so that the effective surface area of the lower electrode 8 can be increased as much as possible. for example,
If this aspect ratio is 2 or more, the effective surface area of the lower electrode 8 can be increased to about twice or more the occupied area. Note that the unevenness 8a does not necessarily have to be arranged regularly.

In the figure, 9 indicates a dielectric film. This dielectric film 9 is made of, for example, a SiO2 film and silicon nitride (Si3N
4) Formed by a three-layer film (ONO film) consisting of a film and a SiO2 film. The thickness of this ONO film is, for example, about 150 Å. Further, 10 indicates an upper electrode (cell plate) formed of a third layer of polycrystalline Si film doped with an impurity such as phosphorus. A stacked capacitor is formed by the upper electrode 10, dielectric film 9, and lower electrode 8. A memory cell is constituted by the above-mentioned access transistor and this stacked capacitor.

Furthermore, 11 represents an interlayer insulating film such as a PSG film, a BPSG film, or an AsSG film. Further, BL indicates a bit line formed of, for example, an aluminum (Al) film. This bit line BL is connected to a contact hole C2 formed in the interlayer insulating films 11 and 7 and the gate insulating film 3.
It is connected to the diffusion layer 5 through.

Next, a method of manufacturing the MOS dynamic RAM according to this embodiment configured as described above will be explained with reference to FIGS. 2 to 6.

First, as shown in FIG. 2, a field insulating film 2 is selectively formed on the surface of a semiconductor substrate 1 by, for example, the LOCOS method to isolate devices. A gate insulating film 3 is formed on the surface of the active region by thermal oxidation.

Next, a first layer of polycrystalline Si film is formed on the entire surface by, for example, the CVD method, and this polycrystalline Si film is doped with an impurity such as phosphorus by ion implantation or thermal diffusion to lower the resistance. After that, this polycrystalline Si film is finely processed by lithography and etching to form a word line WL1.
, WL2 is formed. These word lines WL1, W
When L2 is formed using a polycide film, sputtering or C
After forming, for example, a high melting point metal silicide film by the VD method, these high melting point metal silicide films and polycrystalline Si
Pattern the film.

Next, these word lines WL1 and WL2
Using this as a mask, an n-type impurity such as phosphorus is ion-implanted into the semiconductor substrate 1 at a low concentration. Next, for example, C
For example, a SiO2 film is formed on the entire surface by the VD method, and this SiO2 film is etched by reactive ion etching (RIE).
) method to form sidewall spacers 4 on the side walls of word lines WL1 and WL2 by etching in a direction perpendicular to the substrate surface. Next, using the sidewall spacers 4 and the word lines WL1 and WL2 as masks, n-type impurities such as arsenic (As) are ion-implanted into the semiconductor substrate 1 at a high concentration, and then, if necessary, the implanted impurities are Heat treatment for diffusion and electrical activation is performed. As a result, for example, n+ type diffusion layers 5 and 6 having low impurity concentration portions 5a and 6a below the sidewall spacer 4 are formed in a self-aligned manner with respect to these word lines WL1 and WL2. .

Next, an interlayer insulating film 7 is formed over the entire surface by, for example, the CVD method. Next, predetermined portions of the interlayer insulating film 7 and gate insulating film 3 are removed by etching to form a contact hole C1. Next, for example, a second layer of polycrystalline Si film is formed on the entire surface by, for example, CVD method, and this polycrystalline Si film is doped with an impurity such as phosphorus by thermal diffusion method or ion implantation method to lower the resistance. After that, this polycrystalline S
The i-film is patterned by etching to form the lower electrode 8 of the stacked capacitor.

Next, as shown in FIG. 3, this lower electrode 8
A resist pattern 12 having a predetermined shape and having an opening corresponding to a predetermined portion of the upper surface of the resist pattern 12 is formed by lithography.

Next, using the resist pattern 12 as a mask, the lower electrode 8 is etched to a predetermined depth by, for example, RIE. As a result, as shown in FIG. 4, the upper part of the upper electrode 8 is selectively etched away in the form of a groove, thereby forming unevenness 8a.

Next, after removing the resist pattern 12, a dielectric film 9 is formed on the upper electrode 8, as shown in FIG. When using, for example, an ONO film as this dielectric film 9, its formation method is as follows. That is, first, an SiO2 film is formed on the surface of the polycrystalline Si film forming the upper electrode 8 by thermal oxidation. Next, a Si3 N4 film is formed on this SiO2 film by CVD. Next, a SiO2 film is formed on this Si3 N4 film by thermal oxidation. As a result, the dielectric film 9 made of ONO film
is formed.

Next, for example, a third layer of polycrystalline Si film is formed on the entire surface by, for example, CVD method, and this polycrystalline Si film is doped with an impurity such as phosphorus by thermal oxidation method or ion implantation method to make the polycrystalline silicon film low. After being made into a resistor, this polycrystalline Si film is finely processed by lithography and etching to form an upper electrode (cell plate) 10 of a stacked capacitor, as shown in FIG.

After this, as shown in FIG. 1, for example, CVD
An interlayer insulating film 11 is formed on the entire surface by a method. Next, predetermined portions of the interlayer insulating film 11, the interlayer insulating film 7, and the gate insulating film 3 are removed by etching to form a contact hole C2. Next, for example, an Al film is formed on the entire surface by, for example, sputtering or vacuum evaporation, and then this Al film is patterned into a predetermined shape by etching to form a bit line BL. After that, a passivation film (such as a silicon nitride film) is applied to the entire surface by, for example, a plasma CVD method.
(not shown) to form the desired MOS dynamic R
Complete AM.

As described above, according to this embodiment, the semiconductor substrate 1 is placed on the upper surface of the lower electrode 8 of the stacked capacitor.
Since the unevenness 8a is formed having side surfaces substantially perpendicular to the surface, the effective surface area of the lower electrode 8 can be increased by the area of the side surface of the concave portion of the unevenness 8a compared to the conventional one. Therefore, it is possible to increase the storage charge amount of the stacked capacitor, and as a result, the storage capacity is 64
Even in MOS dynamic RAM with M bits or more,
Information can be stably written to and read from memory cells.

Although one embodiment of the present invention has been specifically described above, the present invention is not limited to the above-described embodiment.

For example, in the above-described embodiment, the MISFET constituting the memory cell has an LDD structure, but the MISFET does not necessarily have to have an LDD structure.

Further, in the above embodiment, the lower electrode 8 and the upper electrode 10 of the stacked capacitor are made of polycrystalline S.
Although the lower electrode 8 and the upper electrode 10 are formed of an i film, they can also be formed of, for example, an amorphous Si film, a single crystal Si film, a high melting point metal film, a high melting point metal silicide film, etc. .

[0037]

[Effects of the Invention] As explained above, according to the present invention,
Since the upper surface of the lower electrode of the stacked capacitor is provided with unevenness having side surfaces substantially perpendicular to the semiconductor substrate, even when applied to a MOS dynamic RAM with a storage capacity of 64 Mbit or more, for example, the memory cell It is possible to stably write and read information to and from the memory.

[Brief explanation of drawings]

FIG. 1: MOS dynamic R according to an embodiment of the present invention.
It is a sectional view showing AM.

FIG. 2 is a diagram for explaining a method of manufacturing the MOS dynamic RAM shown in FIG. 1;

FIG. 3 is a diagram for explaining a method of manufacturing the MOS dynamic RAM shown in FIG. 1;

FIG. 4 is a diagram for explaining a method of manufacturing the MOS dynamic RAM shown in FIG. 1;

FIG. 5 is a diagram for explaining a method of manufacturing the MOS dynamic RAM shown in FIG. 1;

FIG. 6 is a diagram for explaining a method of manufacturing the MOS dynamic RAM shown in FIG. 1;

FIG. 7 is a cross-sectional view showing a conventional MOS dynamic RAM.

[Explanation of symbols]

1 Semiconductor substrate 2 Field insulation film 3 Gate insulating film WL1, WL2 word line 5, 6 Diffusion layer 7, 11 Interlayer insulation film 8 Lower electrode 9 Dielectric film 10 Upper electrode C1, C2 Contact hole BL bit line

Claims (1)

[Claims] 1. A semiconductor memory device having a memory cell constituted by an MIS transistor and a stacked capacitor, wherein an unevenness having a side surface substantially perpendicular to the semiconductor substrate is provided on the upper surface of the lower electrode of the stacked capacitor. A semiconductor memory device characterized by being provided with.