JPH042000A - Semiconductor integrated circuit provided with ram test mode - Google Patents

Abstract

PURPOSE:To conduct a RAM test without use of an external device such as a tester by providing a test circuit testing a RAM and changeover circuit switching an input to the RAM between the test circuit and a logic circuit. CONSTITUTION:The above circuit is provided with a test circuit 4 testing a RAM 1 and outputting the result of discrimination externally, and a changeover circuit 3 inputting selectively the output of a logic circuit 2 or the output of the test circuit 4 to the RAM 1 based on a test mode signal. Then the changeover circuit 3 inputs the output of the test circuit 4 to the RAM 1 based on a test mode signal 5 to conduct the RAM test and the result of decision is outputted externally from the test circuit 4. Thus, the RAM test is executed without an external device such as a tester and the number of external connection terminals is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to RAM (Random Access re
ad writeMemory) and a logic circuit, and can switch to RAM test mode and test the quality of the RAM using a built-in test circuit.
The present invention relates to a semiconductor integrated circuit having an M test mode.

[Prior Art] FIG. 4 is a block diagram showing a semiconductor integrated circuit equipped with a conventional RAM test mode.

The input end of RAMII is connected to the output end Y1 of the switching circuit 13a. An input terminal A of this switching circuit 13a is connected to the logic circuit 12, and an input terminal B is connected to a test signal input terminal 14 to which a test pattern signal is input. The input terminal S of this switching circuit 13a is connected to the test mode terminal 15. When the test mode signal is input to the test mode terminal 15, this switching circuit 13a sends out the test pattern signal input to the input terminal B1 to RAMII via the output terminal Y1, and when the test mode signal is not input to the test mode terminal 15, sometimes,
A signal from the logic circuit 12 inputted to the input terminal A1 is sent to the RAM II via the output terminal Y1.

The output end of RAM II is connected to the input end B2 of the switching circuit 13b. The input terminal A2 of this switching circuit 13b is connected to the output terminal of the logic circuit 12, and the input terminal S
2 is connected to the test mode terminal 15. and,
An output terminal Y2 of the switching circuit 13b is connected to the output terminal 16.

In the semiconductor integrated circuit configured as described above, during normal operation, the switching circuit 13a is in a state to input the output of the logic circuit 12 to the RAM II. Further, the switching circuit 13b also connects the output terminal of the logic circuit 12 and the output terminal 16.
is connected to.

On the other hand, when testing RAMII, a test mode signal is supplied to the test mode terminal 15.

Then, the switching circuit 13a switches and connects the input terminal of RAMII from the output terminal of the logic circuit 12 connected to the input terminal A to the test signal input terminal 14 connected to the input terminal B1. The switching circuit 13b also receives this test mode signal and switches the output terminal 16 from the output terminal of the logic circuit 12 connected to the input terminal A2 to the output terminal of the RAMII connected to the input terminal B2. .

Next, a test pattern signal is supplied to the test signal input terminal 14 from an external tester. When the RAM 11 receives this test pattern signal, it outputs a predetermined signal corresponding to the test pattern signal. This RAM II output signal is sent to an external tester via the output terminal 16.

Then, the external tester uses the RAMI based on this signal.
Determine whether I is good or bad.

[Problems to be Solved by the Invention] However, in the semiconductor integrated circuit equipped with the above-mentioned RAM test mode, since the RAM test is performed using a test pattern signal supplied from an external tester,
A tester is required for the M test, and the RAM test is complicated. Furthermore, in order to connect an external tester, test signal input terminals 14 are required in a number proportional to the bit width of the RAM 11, and there is also a drawback that the number of external connection terminals is large. For example, RAMII! B
If it is a bit width, at least 16 test signal input terminals 14 are required.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a semiconductor integrated circuit equipped with a RAM test mode that allows a RAM test to be performed without an external device such as a tester and that can reduce the number of external connection terminals. .

[Means for Solving the Problems] A semiconductor integrated circuit equipped with a RAM test mode according to the present invention includes a RAM, a logic circuit, a test circuit that tests the RAM and outputs the determination result to the outside, and a test circuit that tests the RAM and outputs the determination result to the outside. The present invention is characterized by comprising a switching circuit that selectively inputs either the output of the logic circuit or the output of the test circuit to the RAM based on a mode signal.

[Operations] In the present invention, a test circuit and a switching circuit are provided in the semiconductor integrated circuit, and the switching circuit inputs the output of the test circuit to the RAM based on a test mode signal. In this way, the RAM test is carried out, and the determination result is output from the test circuit to the outside.

The test circuit includes, for example, a test pattern generation section that generates a test pattern signal for RAM testing, and a comparison section that compares the output of the RAM with the test pattern signal and outputs a determination signal. When the test circuit is configured in this way, when a test mode signal is input, the test pattern generating section generates a test pattern signal, and the switching circuit inputs this test pattern signal to the RAM. Then, the RAM outputs a signal according to the test pattern signal. The comparison section compares the output signal of this RAM with the test pattern signal and outputs a determination signal to the outside.

In the present invention, since the quality of the RAM is determined in this way, an external device such as a tester is not required, and
There is also no need for an external connection terminal for connecting to a tester or the like.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a semiconductor integrated circuit equipped with a RAM test mode according to a first embodiment of the present invention.

The input end of the RAM 1 is connected to the output end Yt of the switching circuit 3. This switching circuit 3 transfers either the output of the logic circuit 2 connected to the input terminal A or the output of the test circuit 4 connected to the input terminal B1 to the RAM 1 based on the signal input to the input terminal S1. Send.

The test circuit 4 has its input terminal A connected to the test mode terminal 5. Further, the input end B is connected to the output end of the RAM1. Furthermore, the output terminals X and Y of the test circuit 4
are connected to the input terminals B and S of the switching circuit 3, respectively, and the output terminal Z is connected to the output terminal 6.

FIG. 2 is a block diagram showing a specific configuration of the test circuit 4. As shown in FIG.

The test mode setting section 41 is connected to the input terminal A.

This test mode setting section 41 has two output terminals, one output terminal of the test mode setting section 41 is connected to the test circuit control section 42, and the other output terminal is used as the output terminal of the test circuit 4. Connected to end Y. When the test mode signal is input to the input terminal A, the test mode setting section 41 sends this test mode signal to the test circuit control section 42 and the output terminal Y.

Further, the test circuit control section 42 also has two output terminals, one output terminal is connected to the test pattern generation section 43 and the other output terminal is connected to the comparison section 45. This test circuit control section 42 is connected to the test mode setting section 4.
When a test mode signal is input from 1, a test pattern generation signal is sent to a test pattern generation section 43 and a comparison section 45.

Further, the test pattern generation section 43 generates a predetermined test pattern signal when receiving the test pattern generation signal from the test circuit control section 42 and sends this test pattern signal to the output terminal X and the comparison section 45.

The RAM output holding register 44 has R input to the input terminal B.
The output signal of the AMI is input and temporarily held, and this signal is sent to the comparison section 45. The comparison unit 45 compares the test pattern signal input from the test pattern generation unit 43 and the RAM output signal input from the RAM output holding register 44 while the test pattern generation signal is input from the test circuit control unit 42. , when both are the same, a normal signal is output to the output terminal Z, and when both are different from each other, an abnormal signal is output to the output terminal Z.

Next, the operation of this embodiment will be explained. When a test mode signal is input to the test mode terminal 5, the test mode setting section 41 outputs this test mode signal to the input terminal SI of the switching circuit 3 via the output terminal Y. This results in
The switching circuit 3 switches the signal sent to the RAMI from the output of the logic circuit 2 connected to the input terminal A to the output of the test circuit 4 connected to the input terminal B.

The test mode setting section 41 also includes a test circuit control section 42.
Outputs the test mode signal to. Test circuit control section 42
generates a test pattern generation signal when this test mode signal is input. Then, the test pattern generation section 43 receives this test pattern generation signal and generates a predetermined test pattern signal. This test pattern signal is input to the comparator 45 and is also input to the RAMI via the output terminal X and the switching circuit 3.

After RAM1 once stores this test pattern signal,
The stored test pattern signal is input to the input terminal B of the test circuit 4.
Send to.

The RAM output holding register 44 inputs and temporarily holds the test pattern signal output from the RAM 1, and sends this signal to the comparison section 45.

The comparison section 45 compares the output of the test pattern generation section 43 and the output of the RAM output holding register 44 based on the test pattern generation signal from the test circuit control section 42 . If the two output signals are the same, a normal signal is output to the output terminal 6 via the output terminal Z, and if they are different, an abnormal signal is output to the output terminal 6. This kind of operation can be implemented in RAMI
Repeat for all addresses. This allows R.A.
It is possible to judge whether M1 is good or bad.

In this embodiment, the above-mentioned RAM test can be carried out simply by inputting a test mode signal from the outside, so an external device such as a tester is not required. Also,
Since a connection terminal for connecting to an external device such as a tester is not required, the number of external connection terminals can be reduced.

FIG. 3 is a block diagram showing a semiconductor integrated circuit equipped with a RAM test mode according to a second embodiment of the present invention.

This embodiment differs from the first embodiment in that it has two RAMs, and the other configurations are basically the same as the first embodiment. Identical parts will be given the same reference numerals and detailed explanations will be omitted.

The semiconductor integrated circuit according to this embodiment has two RAMs 1a and 1
I am having a baby b. Then, these two RAMs 1a and 1
The input terminals of the switching circuit 3 are both connected to the output terminal Y1 of the switching circuit 3. Further, the output terminals of these RAMs 1a and 1b are both connected to the input terminal B of the test circuit 4.

In this embodiment as well, the same effects as in the first embodiment can be obtained. Incidentally, even in a semiconductor integrated circuit having three or more RAMs, the R
AM tests can be performed.

[Effects of the Invention] As explained above, the present invention includes a test circuit for testing the RAM and a switching circuit for switching the input of the RAM between the test circuit and the logic circuit. This can be carried out without using an external device such as a tester. Furthermore, the number of external connection terminals of the semiconductor integrated circuit can be reduced compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a semiconductor integrated circuit equipped with a RAM test mode according to a first embodiment of the present invention, and FIG. 2 is a block diagram showing a specific configuration of the test circuit.
FIG. 3 is a block diagram showing a semiconductor integrated circuit with a RAM test mode according to a second embodiment of the present invention, and FIG. 4 is a block diagram showing a conventional semiconductor integrated circuit with a RAM test mode. 1, las 1b+ 11; RAM12+ 12;
. Thick circuit, 3.13at 13b; switching circuit, 4
;Test circuit, 5, 15;Test mode terminal, e, is
Output terminal, 14; Test signal input terminal, 41; Test mode setting section, 42; Test circuit control section, 43; Test pattern generation section, 44; RAM output holding register, 45
;Comparison part Figure 1

Claims (2)

[Claims] (1) A RAM, a logic circuit, a test circuit that tests the RAM and outputs the determination result to the outside, and an output of the logic circuit and an output of the test circuit to the RAM based on a test mode signal. 1. A semiconductor integrated circuit equipped with a RAM test mode, comprising a switching circuit for selectively inputting one of the two modes. (2) The test circuit includes a test pattern generation section that generates a test pattern signal for testing the RAM based on the test mode signal, and a test pattern generation section that generates a test pattern signal based on the comparison result between the output of the RAM and the output of the test pattern generation section. 2. The semiconductor integrated circuit with a RAM test mode according to claim 1, further comprising a comparison section that outputs a judgment signal for the RAM.