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JPH04196323A - Structure of bump electrode part and formation thereof - Google Patents

Structure of bump electrode part and formation thereof

Info

Publication number
JPH04196323A
JPH04196323A JP2323326A JP32332690A JPH04196323A JP H04196323 A JPH04196323 A JP H04196323A JP 2323326 A JP2323326 A JP 2323326A JP 32332690 A JP32332690 A JP 32332690A JP H04196323 A JPH04196323 A JP H04196323A
Authority
JP
Japan
Prior art keywords
electrode
film
metal film
carbon black
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2323326A
Other languages
Japanese (ja)
Inventor
Yutaka Okuaki
奥秋 裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2323326A priority Critical patent/JPH04196323A/en
Publication of JPH04196323A publication Critical patent/JPH04196323A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Preventing Corrosion Or Incrustation Of Metals (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive improvement in reliability against corrosive ions and the like by a method wherein carbon black is formed by adsorption as the common electrode for plating to be used for application of a current on the electrode formed on the main surface of a semiconductor element. CONSTITUTION:An SiO2 film 12 is formed on a substrate 11, an electrode 13 to be used for lead out of an outer electrode and consisting of an Al film, for example, is formed thereon, and an SiO2 film 14, which is formed by opening a part of the main surface of the electrode 13, is worked into the shape as indicated in the diagram. Then, a metal film 15 is formed on the electrode 13 which is formed by opening the SiO2 film 14 of the electrode 13. A first photosensitive resist 20 is formed on the region excluding a part of the metal film 15 and the SiO2 film 14, and a film is formed on the whole main surface of the semiconductor substrate 11 by adsorption-treating a carbon black 21. Then, a second resist 22, which is formed by opening the prescribed area where a bump will be formed, a current is applied to the carbon black 21 and a bump electrode 23 is formed. As a result, the metal film on the electrode 23 is covered by carbon black, thereby enabling the metal film to prevent corrosion by corrosive ions and the like, and reliability can be enhanced.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体装置の実装技術の一つであるTAB 
(Tape Automated Bonding )
技術に用いられるバンプ電極部の構造およびその形成方
法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to TAB, which is one of semiconductor device mounting techniques.
(Tape Automated Bonding)
The present invention relates to the structure of a bump electrode part used in technology and a method of forming the same.

(従来の技術) この種の従来の技術として特公昭61−7742号公報
に開示されるものがあり、その例を第2図に工程断面図
として示す。半導体基板11上に5102膜12を形成
し、その上に抵抗加熱法または電子ビーム法等により0
.5〜15μmのアルミニウム膜を形成し、半蝕刻法に
より前記半導体基板1ノに形成された回路素子間を接続
して外部電極取出し用の電極13を形成する。さらに低
温で形成した(:’VD 5102膜J4を全面に被着
し、前記電極13近傍のみを光蝕刻法により開口する(
(a)図)。
(Prior Art) This type of conventional technology is disclosed in Japanese Patent Publication No. 61-7742, an example of which is shown in FIG. 2 as a cross-sectional view of the process. A 5102 film 12 is formed on a semiconductor substrate 11, and a 5102 film 12 is formed on it by a resistance heating method, an electron beam method, etc.
.. An aluminum film with a thickness of 5 to 15 μm is formed, and the circuit elements formed on the semiconductor substrate 1 are connected by a half-etching method to form electrodes 13 for taking out external electrodes. Further, a VD 5102 film J4 formed at a low temperature is deposited on the entire surface, and only the vicinity of the electrode 13 is opened by photoetching.
(a) Figure).

つぎに、複数層からなる金属膜15を蒸着法により全面
に形成する((b)図)。この金属膜15はCr−Cu
 。
Next, a metal film 15 consisting of a plurality of layers is formed over the entire surface by a vapor deposition method (see figure (b)). This metal film 15 is made of Cr-Cu
.

Ni −Cu 、 Cr−Ni−CuもしくはCr−C
u−Au、Ni−Cu−Au、Cr−Ni−Cu等の複
数層であって、同一の蒸着時に真空をブレイクすること
なぐ順次蒸着するものである。
Ni-Cu, Cr-Ni-Cu or Cr-C
Multiple layers of u-Au, Ni-Cu-Au, Cr-Ni-Cu, etc. are deposited in sequence without breaking the vacuum during the same deposition.

また、 Cr、NiO替りにT】を用いても良い。Cr
、Ni。
Further, T] may be used instead of Cr or NiO. Cr
, Ni.

Tiはアルミニウムの電極13およびCVD SiO2
M14の密着力を高めるための膜であり、CuまたはC
u−Auはめっき処理によるバンプの形成を容易にする
ための膜であって、Cr、Nj、Tiのそれぞれの厚さ
は約1000X、Cuは1000〜6000Xの膜厚を
有するものである。
Ti is aluminum electrode 13 and CVD SiO2
This is a film to increase the adhesion of M14, and is made of Cu or C.
u-Au is a film for facilitating the formation of bumps by plating, and each of Cr, Nj, and Ti has a thickness of about 1000X, and Cu has a thickness of 1000 to 6000X.

つぎに、めっき用マスクとして感光性樹脂16を塗布し
た後めっきすべき電極13近傍のみを開口しく(C)図
)、前記金属膜15をめっき用の共通電極としてAu 
* Cut半田等の金属バンプ17を5〜20μmの高
さに形成する((d)図)。
Next, after applying a photosensitive resin 16 as a plating mask, only the vicinity of the electrode 13 to be plated is opened (Figure C), and the metal film 15 is used as a common electrode for plating.
* Metal bumps 17 such as cut solder are formed to a height of 5 to 20 μm (Figure (d)).

前記工程が終了すれば、不要となった感光性樹脂16お
よび金属膜15をプラズマエツチング法もしくはイオン
エツチング法によりドライ雰囲気で除去し、(e)図の
構造を得る。ここで感光性樹脂16′が残っても、信頼
性には問題がない。
When the above steps are completed, the unnecessary photosensitive resin 16 and metal film 15 are removed in a dry atmosphere by plasma etching or ion etching to obtain the structure shown in FIG. Even if the photosensitive resin 16' remains here, there is no problem in reliability.

(発明が解決しようとする課題) しかしながら、前述の方法では、金属膜15をバンプめ
っき用の共通電極としてAu、Cu、半田等の金属・ぐ
ンプ17を形成する電極として用いており、めっき終了
後これら金属膜ノ5の断面部がバンプ電極の電極13の
側面に露出して(・るので、外部からの腐食性イオンに
より露出した金属膜が腐食され、バンプ電極が剥れると
〜・う付着強度の劣化が発生しやすいという問題点があ
った。
(Problem to be Solved by the Invention) However, in the method described above, the metal film 15 is used as a common electrode for bump plating and as an electrode for forming metal bumps 17 such as Au, Cu, solder, etc. Afterwards, the cross section of these metal films 5 is exposed on the side surface of the electrode 13 of the bump electrode, so if the exposed metal film is corroded by corrosive ions from the outside and the bump electrode peels off, then... There was a problem in that adhesive strength was likely to deteriorate.

(課題を解決するための手段) この発明は前述の問題点を解決するため、バンプ電極の
形成方法において、ブラックホールプロセスによって、
電極上にパンダを形成する工程で。
(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention uses a black hole process to form a bump electrode.
In the process of forming pandas on the electrode.

金属膜がバンプ電極外部に露出しないようにカーボンブ
ランク層を形成し、金属膜に共通電極としての通電はブ
ラックホールプロセスによって、カービンブラックの薄
い膜を接触形成させて共通電極とし、バンプ電極を形成
するようにしたものである。
A carbon blank layer is formed so that the metal film is not exposed to the outside of the bump electrode, and the metal film is energized as a common electrode using the black hole process.A thin film of carbine black is formed in contact with the metal film as a common electrode to form the bump electrode. It was designed to do so.

(作用) 本発明は前述のように、・ぐンゾ電極の電極上の金属膜
をカーボンブラックによって外部に露出させないように
したので、腐蝕性イオン等に腐蝕されず、付着強度の劣
化が起きな℃・信頼性の高いバンプ電極を形成できる。
(Function) As described above, the present invention uses carbon black to prevent the metal film on the electrode of the Gunzo electrode from being exposed to the outside, so it will not be corroded by corrosive ions and the adhesive strength will deteriorate. It is possible to form highly reliable bump electrodes at temperatures as low as 30°F.

(実施例) 第1図は、この発明の詳細な説明する工程断面概略図で
ある。従来例と同一部は同−附号を付して説明を割愛す
る。
(Example) FIG. 1 is a process cross-sectional schematic diagram explaining the details of the present invention. Parts that are the same as those in the conventional example will be given the same numbers and will not be described further.

まず(a)図のように、従来と同様技術で基板ll上に
8102膜12を形成し、その上に例えばA/膜から成
る外部電極取出し用電極(J:)、下単に電極と称す)
73を形成、該電極13の主表面の一部を開口したS 
IO2膜14を図示した形状に加工する。
First, as shown in the figure (a), the 8102 film 12 is formed on the substrate 11 using the same technique as before, and on top of that is an electrode (J:) for taking out an external electrode made of, for example, A/film (hereinafter simply referred to as an electrode).
73 is formed, and a part of the main surface of the electrode 13 is opened.
The IO2 film 14 is processed into the shape shown.

次に(b)図のように、やはり従来と同様の技術で。Next, as shown in figure (b), the same technique as before is used.

金属膜15を電極13の前記S IO2膜ノ4が開口さ
れた電極13上に形成する。
A metal film 15 is formed on the electrode 13 in which the SIO2 film 4 of the electrode 13 is opened.

このCVD SiO2膜14につ(・ては、これらのほ
かに例えばンリコン窒化膜(Sl、N4) 、 リンガ
ラス膜(PSG )等を用いることもあるし、特に81
02膜1ζ限定するものではない。
For this CVD SiO2 film 14, in addition to these, for example, a silicon nitride film (Sl, N4), a phosphorus glass film (PSG), etc. may be used, and in particular,
02 film 1ζ is not limited.

次いで(c)図のように、感光性を有する第1のレジス
ト2θを前記金属膜15及び5102膜14の一部を除
いてホトリングラフィ技術によって形成し、さらに前記
半導体基板11の主表面全面にカーボンブラック2ノを
吸着処理する。この処理は例え1げブラックホールプロ
セス技術を用いて形成する。
Next, as shown in FIG. 3(c), a photosensitive first resist 2θ is formed by photolithography technique except for a part of the metal film 15 and the 5102 film 14, and is further applied to the entire main surface of the semiconductor substrate 11. Adsorption treatment of carbon black 2 is carried out. This process is performed using, for example, black hole process technology.

この時のカーピンブラックの粒子サイズは150皿〜2
000nmで、また同等の厚さの被膜を形成する。その
後(d)図のように、バンプを形成する所定のエリヤを
開口した第2のレジスト22を形成し、カーボンブラン
ク層21に通電し、バンプ電極23を形成する。バンプ
電極23の形成が完了したら、(e)図に図示するよう
に、第1のレジスト20、及び第2のレジスト22を有
機溶剤例えば、アセトン等によって溶解除去する。それ
と同時にバンプ電極23の形成された部分以外のカーボ
ンブラック21は前記レジストの溶解とともに除去され
る。カーボンブラックは元々被膜の表面に無数に存在し
ている微細な孔が薬液を通しやすいので有機溶剤による
除去処理は容易に行なえる。
The particle size of carpin black at this time was 150 to 2
000 nm, and a film of equivalent thickness is formed. Thereafter, as shown in FIG. 3(d), a second resist 22 with openings in predetermined areas where bumps will be formed is formed, and the carbon blank layer 21 is energized to form bump electrodes 23. After the formation of the bump electrodes 23 is completed, the first resist 20 and the second resist 22 are dissolved and removed using an organic solvent such as acetone, as shown in FIG. At the same time, the carbon black 21 other than the portion where the bump electrode 23 is formed is removed as the resist is dissolved. Since carbon black has countless fine pores that originally exist on the surface of the film, it is easy for chemical solutions to pass through it, so it can be easily removed using an organic solvent.

次にff1図に図示するように、(e)図で図示したバ
ンプ電極23を加熱溶融処理し1円球状化する。
Next, as shown in FIG. ff1, the bump electrode 23 shown in FIG.

加熱溶融によって、カーボンブラック21の微細な孔か
らバンプ電極の金属例えば、ノ・ンダ、金、等の金属が
金属膜の金属、例えばCu等と合金化層を形成して、金
属膜とバンプ電極間に存在するカーボンブラック層の抵
抗を大巾に低下させ回路機能的に不具合は見い出さない
程度となる。以上の工程により(f)図の構造を得る。
By heating and melting, the metal of the bump electrode, such as copper, gold, etc., forms an alloyed layer with the metal of the metal film, such as Cu, through the fine pores of the carbon black 21, and the metal film and the bump electrode are bonded together. The resistance of the carbon black layer existing in between is significantly lowered to the extent that no defects are found in terms of circuit functionality. Through the above steps, the structure shown in Figure (f) is obtained.

(C′)図はカーボンブラック2ノの層がバンプ電極と
金属膜間全部には存在させない方法の実施例であって、
金属膜15にわずかに接触している状態■としたもので
あるが、効果は同じである。
(C') Figure is an example of a method in which a layer of carbon black 2 is not present between the bump electrode and the metal film,
Although the state (3) is that the metal film 15 is slightly in contact with the metal film 15, the effect is the same.

(発明の効果) 以上、説明したようにこの発明によれば、半導体素子の
主表面に形成された電極に通電するめつき用の共通電極
として、カーボンブラックを吸着形成したので、バンプ
形成めっき後の処理として、有機溶剤で所定のエリヤを
マスキングしたレジストを除去する工程で、同時にその
部分のカーボンブラックも除去され、しかもバンプ電極
の電極上に形成された金属膜が外部に露出しないよう形
成できるので、腐食性イオン等に対して、信頼性が向上
し、しかも作業に酸、アルカリ等の薬液による工程が削
減され経済的な効果も期待出来る。
(Effects of the Invention) As described above, according to the present invention, carbon black is adsorbed and formed as a common electrode for plating that conducts current to the electrode formed on the main surface of a semiconductor element, so that it can be used after bump formation plating. The process is to remove the resist masked in a predetermined area with an organic solvent, and at the same time, the carbon black in that area is also removed, and the metal film formed on the bump electrode can be formed without being exposed to the outside. , reliability against corrosive ions, etc. is improved, and the process of using chemicals such as acids and alkalis is reduced, so economical effects can be expected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の工程断面図、第2図は従来例
の工程断面図である。 1ノ・・・半導体基板、12.14・・・S IO2膜
、13°°。 電極、15・・・金属膜%20・・・第1のレジスト、
21・・ウーカンプライク、22・・・第2のレジスト
、23・・バンプ電極。 第1図(1s1) 本発明の実斌仔110)工程1午面図 第1図(第02)
FIG. 1 is a process sectional view of an embodiment of the present invention, and FIG. 2 is a process sectional view of a conventional example. 1no...Semiconductor substrate, 12.14...S IO2 film, 13°°. Electrode, 15... Metal film% 20... First resist,
21...Woukan pike, 22...Second resist, 23...Bump electrode. Fig. 1 (1s1) Practical test 110) process 1 of the present invention Fig. 1 (No. 02)

Claims (2)

【特許請求の範囲】[Claims] (1)半導体装置におけるバンプ電極部の構造として、 半導体基板上に形成された外部電極取出し用電極とバン
プ電極との間に、カーボンブラック層が形成されている
ことを特徴とするバンプ電極部の構造。
(1) As a structure of a bump electrode part in a semiconductor device, a bump electrode part characterized in that a carbon black layer is formed between the bump electrode and an external electrode extraction electrode formed on a semiconductor substrate. structure.
(2)半導体装置のバンプ電極部の形成に当たり、 (a)半導体基板上に外部電極取出し用電極を形成し、
該電極の主表面を開口するよう酸化膜を形成する工程と
、 (b)前記電極の主表面上に金属膜を形成する工程と、 (c)前記電極のほぼ上部を除いた部分に第1のレジス
トを形成した後、全面にカーボンブラックを吸着処理さ
せる工程と、 (d)バンプ電極を形成する部分を除いて第2のレジス
トを形成し、バンプ電極を形成する工程と、 (e)その後、前記第1、第2のレジストを除去すると
ともに、前記バンプ電極の部分以外の前記カーボンブラ
ックを除去する工程 とを含むことを特徴とするバンプ電極部の形成方法。
(2) In forming the bump electrode portion of the semiconductor device, (a) forming an electrode for taking out an external electrode on the semiconductor substrate;
(b) forming a metal film on the main surface of the electrode; (c) forming a first metal film on the main surface of the electrode except for substantially the top; (d) forming a second resist except for the portion where the bump electrode is to be formed to form the bump electrode; (e) after that. . A method for forming a bump electrode portion, comprising the steps of: removing the first and second resists, and removing the carbon black other than the portion of the bump electrode.
JP2323326A 1990-11-28 1990-11-28 Structure of bump electrode part and formation thereof Pending JPH04196323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2323326A JPH04196323A (en) 1990-11-28 1990-11-28 Structure of bump electrode part and formation thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2323326A JPH04196323A (en) 1990-11-28 1990-11-28 Structure of bump electrode part and formation thereof

Publications (1)

Publication Number Publication Date
JPH04196323A true JPH04196323A (en) 1992-07-16

Family

ID=18153544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2323326A Pending JPH04196323A (en) 1990-11-28 1990-11-28 Structure of bump electrode part and formation thereof

Country Status (1)

Country Link
JP (1) JPH04196323A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005513759A (en) * 2001-07-14 2005-05-12 フリースケール セミコンダクター インコーポレイテッド Semiconductor device and method for forming the same
JP2011055033A (en) * 2009-08-31 2011-03-17 Kyocera Kinseki Corp Piezoelectric oscillator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005513759A (en) * 2001-07-14 2005-05-12 フリースケール セミコンダクター インコーポレイテッド Semiconductor device and method for forming the same
JP2011055033A (en) * 2009-08-31 2011-03-17 Kyocera Kinseki Corp Piezoelectric oscillator

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