JPH0417200A - RAM with self-diagnosis function - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a RAM self-diagnosis function.

[Conventional technology]

In recent years, computer systems have been widely applied in various fields. In this computer system, data necessary for processing is stored in the RAM.

Therefore, the RAM needs to have high reliability in order to prevent improper processing, and at the same time, it is necessary to diagnose the RAM in order to detect failures in the RAM.

However, conventional RAM is manufactured by Hitachi, Ltd.
No consideration was given to diagnosis, as in the block diadem described in Memory Data Book (1989), page 199. Therefore, in a computer system, a microcomputer or the like diagnoses the RAM by write-after-reading for all addresses in the RAM.

[Problem to be solved by the invention]

However, in recent years, as the performance of computer systems has increased, the capacity of memory has increased, resulting in an increase in the amount of time it takes to diagnose the memory.

An object of the present invention is to provide a RAM with a self-diagnosis function that can reduce the load on a microcomputer related to RAM diagnosis.

[Means to solve the problem]

In order to achieve the above object, the present invention includes means for receiving a diagnosis request from the outside, means for diagnosing the RAM itself in response to a previously diagnosed request, and means for transmitting the diagnosis result to the outside.
It is built into RAM as a self-diagnosis function.

[Effect]

By incorporating the above-mentioned self-diagnosis function, all addresses of the RAM can be diagnosed by - times of diagnosis request processing and once of diagnosis result determination processing.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, and 4.

FIG. 1 shows a diagram block of a RAM according to an embodiment of the present invention. Lock 1 is a read/write controller, block 2 is an address decoder, block 3 is a data output buffer, and block 4 is a memory matrix. Further, block 5 is a test controller, and block 6 is a system bus selector.

In the figure, a read/write controller 1, an address decoder 2, a data output buffer 3, and a memory matrix 4 have the same configuration as a general RAM. Therefore, the test controller 5 and system bus selector 6 will be explained below.

FIG. 2 shows a diagram block of the test controller 5 in the RAM of one embodiment of the present invention. Block 51 is a clock generator, block 52 is a program memory, block 53 is a program counter, block 54 is an instruction decoder, block 55 is an arithmetic unit, block 7 is a ■/○ interface, and block 58 is a bus interface.

In the figure, a clock generator 51 generates an operating clock for the test controller 5. Further, according to this operation clock, the instruction indicated by the program counter 53 in the program memory 52 is decoded by the instruction decoder 54, and processing is performed using the arithmetic unit 55 and the general-purpose register 56 based on this. Further, the ■/○ interface 57 creates a test signal that is a switching signal for the I10 interface with the outside and the system selector 6, and the bus interface 58 performs a bus interface with the memory during testing.

FIG. 3 shows a diagram block of the system selector 6 in the RAM of one embodiment of the present invention. Block 61 is a chip select switch, block 62 is a read switch, block 63 is a write switch, block 64 is an address switch, and block 65 is a data switch.

In the figure, these changeover switches are switched by a test signal, and when the test signal is ``O'', an external signal is selected, and when the test signal is ``1'', a test signal is selected.

In normal read/write processing for the RAM, the address decoder 2 selects a - memory cell in the memory matrix 4 corresponding to an external address signal. In addition, the read/write controller 1 creates a read control signal and a write control signal from an external chip select signal, an external read signal, and an external write signal. Controls the direction of data flow between 4 and 4. Specifically, at the time of reading, data from the memory matrix 4 is transmitted to an external data signal in order to read data of a selected memory cell in the memory matrix 4 to the outside. - On the other hand, at the time of writing, in order to write external data to a selected memory cell in the memory matrix 4, an external data signal is sent to the memory matrix 4.
tell to.

In this process, the test signal is set to ``0'', so the system bus selector 6 selects the external address signal from the external address signal and the test address signal, passes it through, and selects one memory of the memory matrix 4. Select a cell.

Next, during the memory test, the test signal is
Therefore, the system bus selector 6 switches to the test mode, and the test controller 5 selects one memory cell in the memory matrix 4, regardless of the external signal. Further, the read/write controller 1 performs processing corresponding to the test chip select signal, test read signal, and test write signal output from the test controller 5 on selected memory cells in the memory matrix 4 .

Next, the contents of the RAM self-diagnosis process will be explained with reference to FIG.

FIG. 4 shows a processing flowchart of the RAM according to an embodiment of the present invention.

Step 1: Clear the error signal that is the output signal of the ■/○ interface 41.

Step 2: Clear the test signal that is the output signal of the I10 interface 41 to enable normal read/write processing to the RAM.

Step 3: Check the test request signal, which is the input signal of the I10 interface 41, to determine whether there is a test request. Further, when a test is requested, the process proceeds to step 4, and when no test is requested, step 3 is repeated. That is, in step 3, a test request is waited for, and in this state, normal read/write processing to the RAM can be performed.

Step 4: Clear the error signal that is the output signal of the ■/○ interface 41. Also, a test signal is set to enable read/write processing to the RAM of the test controller 5.

Step 5: A memory test is performed by the control & calculation unit 42 and the bus interface 43.

Step 6: Based on the result of the memory test conducted in Step 5, determine whether there is a memory error.

Further, when a memory error occurs, the process proceeds to step 7, and when no test occurs, the process branches to step 3, clears the test signal, and waits for a test request again.

Step 7: Set an error signal, which is an output signal of the I10 interface 41, to notify the outside that a memory error has occurred.

In this embodiment, the test controller is configured as a generally known CPU, but it may also be configured as a sequential circuit.

Further, in this embodiment, the test request signal may be created by a microcomputer or by power-on reset processing at the time of system startup.

Furthermore, in this embodiment, diagnosis of RAM has been described, but diagnosis of other than RAM, that is, ROM, is also applicable.

8゜ The same applies to any microcomputer peripheral LSI.

Further, in this embodiment, although a single RAM has been described, the present invention can of course be similarly applied to a memory system using a plurality of the above-mentioned RAMs. At this time, diagnose the RAM.
- Whether the test is performed for all RAMs at once or divided into blocks can be controlled by the method of creating the test request signal and error signal.

According to this embodiment, the microcomputer can diagnose all addresses of the RAM by performing - times of diagnosis request processing and once of diagnosis result determination processing.

〔Effect of the invention〕

According to the present invention, the load on the microcomputer related to RAM diagnosis can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram block diagram of a RAM according to an embodiment of the present invention, FIG. 2 is a diagram block diagram of a test controller in a RAM according to an embodiment of the present invention, and FIG. 3 is a diagram block diagram of a RAM according to an embodiment of the present invention. FIG. 4 is a diagram of the system selector in FIG. Explanation of symbols 1... Read/write controller, 2... Address decoder, 3... Data input/output buffer, 4... Memory matrix, 5... Test controller, 6...
... System bus selector, 51 ... Clock generator, 52 ... Program memory, 53 ... Program counter, 54 ... Instruction decoder, 55 ... Arithmetic unit, 56 ... General-purpose register, 57 ... I10 interface, 58... Bus interface, 61... Chip select changeover switch, 62... Read changeover switch, 63... Write changeover switch, 6
4...Address changeover switch, 65...Data changeover switch. 1st Closed Test Words Figure 3 Figure 2 Figure 4

Claims (1)

[Claims] 1. In RAM that can be randomly accessed, there is a means for receiving a diagnosis request from the outside and a means for receiving a diagnosis request from the RA.
A RAM with a self-diagnosis function characterized by including a means for diagnosing M itself and a means for transmitting the diagnosis result to the outside.
.