JPH04166816A - High brightness liquid crystal panel for projection display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a liquid crystal panel used in a projection display, and particularly to a liquid crystal panel with a large aperture ratio and high brightness.

[Prior art] a-8i (amorphous -, 5ilico
n/amorphous silicon) or p-8i (poly-3
Regarding the 1F T6 ('Fhin-Fi1m-Transistor: thin film transistor or pixel transistor) structure whose channel is a semiconductor thin film made of polycrystalline silicon (Il1con: polycrystalline silicon) etc., please refer to "Liquid Crystal Applied Edition" (edited by Okano and Kobayashi: 2oO ~20
1 page, Baifukan, 1985) or "liquid crystal display" (Taietsu Toshu, pp. 157-163, Shokodo, 198
5 years). Both have a structure in which a semiconductor thin film channel whose electric field is controlled by a gate electrode is provided, and a drain electrode and a source electrode are stacked on both ends of the channel.

In these conventional structures, the gate electrode bus (or gate bus) and the signal electrode bus (or drain bus)
The pixel transistor had a structure in which the electrodes of the pixel transistors were formed from gate electrodes or drain electrodes branched from these gate buses or drain buses.

Here, the conventional structure will be explained using figures.

FIGS. 8 and 9 are examples of conventional pixel configurations.
The figure shows TPT (Th
FIG. 9 is a top structural view of the in-Fi Irn-T'transistor (thin film transistor or pixel transistor), and is a sectional view taken along the dashed line AB in FIG.

The pixel shown in FIG. 8 has a gate bus 1.9 and a gate electrode 1.
a, a-3i2, source voltage 43, drain bus 4.8,
It consists of a drain electrode 4a, a pixel electrode 5.7, a BM opening 6, and a holding electrode 9b.

The cross-sectional view shown in FIG. 9 shows the lower substrate 60 and the gate electrode layer 2.
1. Insulating layer 30. a-3i layer 22, source electrode layer 23,
A 'V F T substrate consisting of a drain electrode layer 24, a pixel electrode layer 27, a protective film 31, an upper substrate 50, an 8M layer 40.
An 8M substrate consisting of a counter electrode 32, the TPT substrate and the 8M substrate.
It consists of a liquid crystal layer 70 inserted between the M substrate and the M substrate.

In general, a liquid crystal panel is provided with a storage capacitor that holds charge written to a pixel electrode in order to stabilize pixel display by compensating for current leakage from the liquid crystal or pixel transistor. In the pixels shown in FIGS. 8 and 9, a storage capacitor is formed in the overlapping portion of the storage electrode 9b branched from the gate bus 9 and the pixel electrode 5.

In the above, the pixel transistor has a-6i2 as a channel and a gate electrode 1 branched from the drain bus 1.
a, a drain electrode 4a branched from the drain bus 4, and a source electrode 3 electrically connected to the pixel electrode 5.

As can be seen from FIG. 8, since there is a branch portion from the gate bus 1, the pixel electrode 5 has a shape in which a small area portion 5S indicated by a dashed line frame protrudes. When the pixel pitch is small, rubbing (rubbing the glass substrate in a certain direction with cotton cloth, etc.) performed to control the alignment of the liquid crystal does not work effectively on this portion 5S, and the portion 5S is affected by the non-alignment of the liquid crystal due to poor alignment. There is a risk that it will become a response area (domain).

For this reason, in the pixel shown in FIG. 8, the shape of the BM aperture 5 is narrowed so as to shield the liquid crystal domain indicated by -, thereby significantly reducing the aperture ratio of the liquid crystal panel.

=9- [Problems to be Solved by the Invention] In the above configuration, pixels 1 to 1 to run transistors are provided in a part of the corner of a rectangular pixel, and the shape of the opening of the pixel electrode, which is ideally rectangular, is greatly distorted. There is a problem.

Moreover, a small-area pixel electrode is formed near the part where the pixel transistor is arranged, and in this small-area pixel electrode part, liquid crystal orientation control is required. There is a risk that domains will be generated that lose their properties and do not respond to electric fields.

Furthermore, since the pixel pitch of high-definition 7-compact liquid crystal panels used in projection displays is small, the aperture ratio is significantly reduced by forming pixel electrodes with gate electrodes or drain electrodes branched from the gate bus or drain bus. The problem arises.

The present invention can be used even in liquid crystal panels with a small pixel pitch.
Has a rectangular open [-1 shape, few domains,
The object of the present invention is to provide a pixel structure in which the aperture ratio can be adjusted to 1.

[Means for Solving the Problems] Instead of the above structure, a pixel transistor is formed by disposing a semiconductor thin film at the intersection of a gate bus and a drain bus of a liquid crystal panel.

That is, instead of using the branch portion from the gate bus and drain bus, a portion of the gate bus at the intersection is used as it is as the gate electrode, and a portion of the drain bus is used as it is as the drain electrode.

[Function] In a structure in which a pixel transistor is formed using a branch part from a gate bus or a drain bus as an electrode, the width of the gate bus or drain bus is not affected, but the area of the pixel electrode is reduced by the area of the branch part. become.

On the other hand, in a structure where the pixel transistor is formed at the intersection of the gate bus and the drain bus, the area of the intersection that already exists is effectively used, so the pixel electrode area is wrinkled by the corresponding area. This reduces the opening area and improves the opening area.

Furthermore, since the pixel transistor is formed at the intersection, the protrusion of the pixel electrode portion of the pixel transistor into the display area is reduced, which reduces distortion of the pixel shape and the number of liquid crystal domains.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a top view of a pixel for explaining the present invention in detail.

The pixel shown in FIG. 1 has a gate bus of 1.9 as in FIG.
, a-3i2.10, source electrode 3.11, drain bus 4.8, pixel electrode 5.7, BM opening 6, holding electrode 9
B, lb, except that a-812 is placed above the gate bus 1.

By providing a-3i2 on the gate bus l in this way, in FIG. 1, the gate voltage g11 as shown in FIG.
a or the gate bus 1 like the drain electrode 4a (7)
An electrode made by branching from the drain bus 4 or by branching from the drain bus 4 does not exist.

As can be seen from the above drawings, in the structure shown in FIG. 1, since the pixel electrode 5.7 is constructed on the channel portion of the pixel transistor or on the gate bus 1, the small area portions 5s and 7s shown by the dashed-dotted line frame protrude. It will look like this.

The portions 5s and 7s shown in FIG. 1 may become non-responsive regions (domains) of the liquid crystal due to alignment failure during rubbing due to the same reason as No.
7s is shielded from light by the gate bus 1 and the holding electrode 1b, and is structured so that it cannot be seen from the outside of the liquid crystal panel.

Therefore, most of the pixel electrode 5 can be used for display, and the BM aperture 6 can be made wider than the conventional one.

FIG. 2 is a cross-sectional view of the pixel shown in FIG. 1 taken along dashed-dotted lines C and B. FIG. Similar to the cross-sectional view shown in FIG. 9, the lower substrate 60
, gate bus layer 21, insulating layer 30, a-81 layer 22, source electrode layer 23, drain bus layer 24, pixel electrode layer 27
, a TFT substrate consisting of a protective film 31, and a plate substrate 50.
An 8M substrate consisting of a BM layer 40, a counter electrode 32, and the TP
It consists of a liquid crystal layer 70 inserted between the T substrate and the 8M substrate.

FIG. 2 shows, as an example of the gate bus layer 21, a two-layer gate bus layer 21 formed of a first layer 21a made of Al or Ta metal and a second layer 21b made of an oxide film of the metal. Ta.

This second layer 21b functions as an insulating layer, and forms a double insulating layer together with the insulating layer 30.

Does the configuration shown in FIG. 1 tend to have a larger area at the intersection between the gate bus 1 and the drain bus 4 than the configuration shown in FIG. 8? The increase in the short-circuit phenomenon with the above-mentioned insulation model is reduced by making the insulation j model positive.

The pixel transistor of the embodiment shown in FIGS. 1 and 2 has a structure in which both left and right ends of a-3i2 do not protrude from the source electrode 3 and drain bus 4. Apart from this structure,
As the structure of the pixel transistor, embodiments as shown in FIGS. 3 to 4 below are possible.

That is, as shown in FIG. 3, this is the case of a pixel transistor having a structure in which both ends of a-3i2 protrude from the source electrode 3 and drain bus 4.

Alternatively, as shown in FIG. 4, the pixel transistor has a structure in which the upper end of as+2 on the source electrode 3 side protrudes from the source electrode 3, but its left and right ends do not protrude from the drain bus 4.

Alternatively, as shown in FIG. 5, both the left and right ends of a S + 2 are made to protrude from the source electrode 3 and the drain bus 4, and at the same time, the upper and lower ends on the source electrode 1f23 side are connected to the source electrode 3 and the gate I bus 1, respectively. This is a case of a pixel I run transistor having a structure in which the main end of the drain electrode 4 side and the lower end of the drain electrode 4 protrude from the gate bus 1. However, in order to prevent light leakage from the pixel transistor,
In FIG. 5, the channel portion of a-3i2 sandwiched between the source electrode 3 and the drain bus 4 is made not to protrude from the edge of the gate bus l.

The light leak is a phenomenon in which external light from a light source illuminating a liquid crystal panel or the like enters a channel portion of a pixel transistor, induces charges, and increases the off-state current of the pixel transistor. Due to future leakage, the effective voltage applied to the pixel electrode decreases, and the display quality of the liquid crystal panel significantly deteriorates.

To prevent this light leakage, there is a general method of shielding the channel section of the pixel transistor from light.
The wider the double width or the upper and lower widths of a S + 2, the greater the light shielding effect.

However, as the width of the gate bus 1 increases, the area of intersection with the source electrode 3 and the drain bus 4 increases, which increases the parasitic capacitance of the pixel transistor or short circuit between the electrodes. Therefore, in order to avoid deterioration of the picture accumulation transistor's performance and to prevent a drop in the yield of liquid crystal panels, it is necessary to
Contrary to the countermeasure against light leakage, it is necessary to reduce the area of intersection between the gate bus 1 and the source electrode 3 or drain bus 4.

Figure 6 shows the requirement to shield the channel portion of the pixel transistor from light leakage, and the requirement to reduce the area of the intersection to improve the short circuit between electrodes and improve the performance of the pixel transistor. An example of a pixel structure that satisfies both of the following is shown below.

That is, in FIG. 6, the ends of Goo 1 to Bus 1 are narrowed inward at the intersection with the source electrode 3 and the drain bus 4, and the end Q between the end P of a S + 2 and the gate bus 4 is narrowed. The structure is such that the distance between the point indicated by the arrow I and the line indicated by S is maintained at a distance sufficient to block light. In addition, at the source electrode 3, the gate bus 1
In order to reduce the area of intersection with , a portion of the left corner is removed as shown in Figure 6.

” - Description Figure 6 shows a structure in which direct light entering the channel portion of a-3i2 is blocked by gate bus l. Furthermore, when using a liquid crystal panel for a projection display,
Strong light from the light source is reflected by the 8M layer 40, gate bus 1, source electrode 3, drain bus 4, etc., and reaches the channel 1°.
(Light leakage may also occur due to light entering the IS. As a countermeasure against this, as shown in FIG. A structure in which it is placed further inside is conceivable.

-I- In any of the embodiments of the present invention shown in FIGS. 1 to 7, by using the poorly aligned portion of the liquid crystal as the storage capacitor forming portion, the display area of the pixel electrode can be used widely, and the size can be reduced. , it is possible to improve the aperture ratio of fine liquid crystal panels.

[Effects of the Invention] Second, according to the present invention, by forming the picture accumulation transistor at the intersection of the gate bus and the drain bus, the poorly aligned portion of the liquid crystal can be used as a storage capacitor forming portion. , the display area of the pixel electrode can be used widely, and the size is small.
This has the effect of improving the aperture ratio of fine liquid crystal panels.

[Brief explanation of the drawing]

FIG. 1 is a top view of a pixel for detailed explanation of the present invention;
FIG. 2 is a cross-sectional view of the pixel shown in FIG. 1 taken along dashed lines A and B, and FIGS. 3, 4, and 5 are examples of pixel structures different from those shown in FIGS. 1 and 2. Figure 6 is a structural diagram of a pixel transistor to explain the structure of the pixel shown in Figure 1, and Figure 7 is a pixel structure diagram to explain light leakage measures and performance improvement of the pixel transistor. FIG. 8 is a pixel structure diagram for explaining an example of a conventional pixel structure, and FIG. 9 is a cross-sectional view taken along the dashed-dotted line AB in FIG. 8. .

Claims (1)

[Claims] 1. A pixel having a structure formed by laminating at least a thin film transistor including a gate electrode, a drain electrode, a source electrode, and a channel of a semiconductor thin film, and a pixel electrode driven by the thin film transistor, A storage capacitor is provided at a portion where the pixel electrode overlaps with a drain bus that is a bus line of the drain electrode of the pixel transistor, a gate bus that is a bus line of the gate electrode, and a part of the gate bus of another pixel adjacent to the pixel. a first substrate formed by arranging pixels having a structure to form a first substrate; a counter electrode provided opposite to the pixel electrode; a light shielding layer;
In a liquid crystal panel having a structure in which a second substrate is formed by laminating the counter electrode and a light shielding layer, and a liquid crystal is sealed between the first substrate and the second substrate, the thin film semiconductor is placed on the gate bus. The structure of the pixel transistor is such that the drain electrode is formed at the intersection of the drain bus and the gate bus, and both ends of the thin film semiconductor are parallel to the drain electrode and the drain electrode. A liquid crystal panel characterized in that the structure is such that a source electrode provided on the panel is not exposed. 2. A pixel has a structure in which at least a thin film transistor including a gate electrode, a drain electrode, a source electrode, and a channel of a semiconductor thin film is laminated, and a pixel electrode driven by the thin film transistor, and the drain electrode of the pixel transistor A pixel having a structure in which a storage capacitor is formed in a portion where the pixel electrode overlaps with a drain bus which is a bus line of the pixel, a gate bus which is a bus line of the gate electrode, and a part of the gate bus of another pixel adjacent to the pixel. a first substrate formed by arranging the pixel electrodes, a counter electrode provided opposite to the pixel electrode, and a light shielding layer;
In a liquid crystal panel having a structure in which a second substrate is formed by laminating the counter electrode and a light shielding layer, and a liquid crystal is sealed between the first substrate and the second substrate, the thin film semiconductor is placed on the gate bus. The structure of the pixel transistor is such that the drain electrode is formed at the intersection of the drain bus and the gate bus, and both ends of the thin film semiconductor are located at the drain electrode or parallel to the drain electrode. A liquid crystal panel characterized in that it has a structure in which a source electrode provided in the panel is exposed. 3. A pixel has a structure in which at least a thin film transistor including a gate electrode, a drain electrode, a source electrode, and a channel of a semiconductor thin film is laminated, and a pixel electrode driven by the thin film transistor, and the drain electrode of the pixel transistor A pixel having a structure in which a storage capacitor is formed in a portion where the pixel electrode overlaps with a drain bus which is a bus line of the pixel, a gate bus which is a bus line of the gate electrode, and a part of the gate bus of another pixel adjacent to the pixel. a first substrate formed by arranging the pixel electrodes, a counter electrode provided opposite to the pixel electrode, and a light shielding layer;
In a liquid crystal panel having a structure in which a second substrate is formed by laminating the counter electrode and a light shielding layer, and a liquid crystal is sealed between the first substrate and the second substrate, the thin film semiconductor is placed on the gate bus. The structure of the pixel transistor is such that the drain electrode is formed at the intersection of the drain bus and the gate bus, and both ends of the thin film semiconductor are on the drain electrode side or with the drain electrode. A liquid crystal panel characterized in that a source electrode side provided in parallel is exposed from the gate electrode. 4. A pixel having a structure formed by laminating at least a thin film transistor including a gate electrode, a drain electrode, a source electrode, and a channel of a semiconductor thin film, and a pixel electrode driven by the thin film transistor, and the drain electrode of the pixel transistor. A pixel having a structure in which a storage capacitor is formed in a portion where the pixel electrode overlaps with a drain bus which is a bus line of the pixel, a gate bus which is a bus line of the gate electrode, and a part of the gate bus of another pixel adjacent to the pixel. a first substrate formed by arranging the pixel electrodes, a counter electrode provided opposite to the pixel electrode, and a light shielding layer;
In a liquid crystal panel having a structure in which a second substrate is formed by laminating the counter electrode and a light shielding layer, and a liquid crystal is sealed between the first substrate and the second substrate, the thin film semiconductor is placed on the gate bus. The structure of the pixel transistor is such that the drain electrode is formed at the intersection of the drain bus and the gate bus, and the drain electrode and the source electrode are provided in parallel with the drain electrode. A liquid crystal panel characterized in that a portion of the thin film semiconductor that is sandwiched between the gate buses and the gate bus and forms a channel of the thin film transistor is disposed at least inward from an end of the gate bus. 5. A liquid crystal panel having the structure according to any one of claims 1 to 4, wherein the light-shielding layer of the second substrate forms the gate bus, the drain bus, and the drain electrode and source electrode that form the electrodes of the thin film transistor; A liquid crystal panel characterized by having a structure that blocks light from any or all of the gate electrodes. 6. A projection type liquid crystal display, characterized in that an image is displayed using a liquid crystal panel having the structure according to any one of claims 1 to 5. 7. A method of combining masks to form a liquid crystal panel having the structure according to any one of claims 1 to 5. 8. Manufacturing a liquid crystal panel using the combination of masks according to claim 7, and a method for manufacturing the same.