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JPH04127545A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH04127545A
JPH04127545A JP2249184A JP24918490A JPH04127545A JP H04127545 A JPH04127545 A JP H04127545A JP 2249184 A JP2249184 A JP 2249184A JP 24918490 A JP24918490 A JP 24918490A JP H04127545 A JPH04127545 A JP H04127545A
Authority
JP
Japan
Prior art keywords
pads
integrated circuit
circuit device
positions
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2249184A
Other languages
Japanese (ja)
Other versions
JP2911988B2 (en
Inventor
Hiroshi Nishida
宏 西田
Ryoji Matsumoto
松本　亮治
Naoki Okuyama
直樹 奥山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP2249184A priority Critical patent/JP2911988B2/en
Publication of JPH04127545A publication Critical patent/JPH04127545A/en
Application granted granted Critical
Publication of JP2911988B2 publication Critical patent/JP2911988B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the positions of inner leads from being subjected to constraint and to make it possible to perform easily also a wiring of signal lines on a printed board by a method wherein a semiconductor chip is connected to the inner leads via a connection route conversion plate having a function to convert a connection route. CONSTITUTION:Each input/output pad on a semiconductor chip 1 and the pad on one side of pads for each signal line 2 are connected to each other via each bonding wire 6. The other pads for signal lines 2 are provided for connecting with the outside in a semiconductor integrated circuit device 5. Each of the other pads and each inner lead 7 which is one part of each lead are connected to each other via each bonding wire 8. The positions of the pads at both ends of the line 2, which are provided on a wiring board 3, can be respectively determined conforming to the positions of the input/output pads on the chip 1 and the positions of the inner leads, which correspond to the other pads for the lines 2. The board 3 is formed into a structure, in which the board has two layers or more of wiring routes so as to prevent the signal conductor 2 from being connected electrically with the signal line 2 even if the conductor 2 connecting two pieces of these pads corresponding to each other intersects the line 2. Thereby, arbitrary pads among the pads can be connected to each other in the shortest distance according to the need.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device.

〔従来の技術〕[Conventional technology]

従来の半導体集積回路装置は、内蔵する半導体チップを
インナーリードに接続する構造を取る場合、リード線の
構造上の制約から半導体チップ上のパッドの位置と半導
体集積回路装置のリードとの位置の対応が決っていた。In conventional semiconductor integrated circuit devices, when a built-in semiconductor chip is connected to an inner lead, due to structural constraints on the lead wires, it is difficult to correspond between the positions of pads on the semiconductor chip and the leads of the semiconductor integrated circuit device. was decided.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来の半導体集積回路装置では、半導体チップ上の
パッドの位置に対する半導体集積回路装置のリードの位
置の対応が決っているため、半導体チップ上で最適のレ
イアウトを行うと、半導体集積回路装置の入出力信号の
リードの位置がおのずと決定され、このことが逆にこの
半導体集積回路装置を用いるプリント基板での信号線の
配線を困難にすることがあるという問題点があった。ま
た、半導体集積回路装置のリード線側で入出力信号のビ
ンの位置を決定すると、半導体チップ上でのパッドの位
置がおのずと決定されてしまい、半導体チップ上で最適
なレイアウトを行うことができず、例えば出力バッファ
の同時動作等による誤動作の原因となるという問題点も
あった。In this conventional semiconductor integrated circuit device, the correspondence between the lead positions of the semiconductor integrated circuit device and the pad positions on the semiconductor chip is determined, so if the optimal layout is performed on the semiconductor chip, the input of the semiconductor integrated circuit device There is a problem in that the position of the output signal lead is determined automatically, which may make it difficult to wire signal lines on a printed circuit board using this semiconductor integrated circuit device. Furthermore, if the positions of the input/output signal bins are determined on the lead wire side of the semiconductor integrated circuit device, the positions of the pads on the semiconductor chip are automatically determined, making it impossible to achieve an optimal layout on the semiconductor chip. However, there is also the problem that, for example, simultaneous operation of output buffers may cause malfunctions.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路装置は、内蔵する半導体チップ
をインナーリードに接続する構造の半導体集積回路装置
において、接続経路を変換する機能を持つ接続経路変換
板を介して前記半導体チップを前記インナーリードに接
続する構成である。The semiconductor integrated circuit device of the present invention has a structure in which a built-in semiconductor chip is connected to an inner lead. This is the configuration to connect.

本発明の半導体集積回路装置は、前記半導体チップと前
記接続経路変換板との間および前記接続経路変換板と前
記インナーリードとの間の接続の少くなくとも一部をボ
ンデングワイヤを用いて行ってもよい。In the semiconductor integrated circuit device of the present invention, at least part of the connections between the semiconductor chip and the connection path conversion board and between the connection path conversion board and the inner leads are made using bonding wires. You can.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）は本発明の一実施例のボンデングワイヤの
接続を模式化した平面図、第１図（ｂ）は同じく側面図
である。FIG. 1(a) is a plan view schematically showing the connection of bonding wires according to an embodiment of the present invention, and FIG. 1(b) is a side view of the same.

半導体チップ１は、両端に接続用パッドを持つ複数の信
号線２を配設した配線板３との間に絶縁膜４を挟んで半
導体集積回路装置５に収容されている。半導体チップ１
の入出力パッドと信号線２の一方のパッドとの間は、ボ
ンデングワイヤ６で接続している。信号線２の他方のパ
ッドは、半導体集積回路装置５に外部と接続するため設
けである。リードの一部であるインナーリード７との間
を、ボンデングワイヤ８で接続している。配線板３に配
設する信号線２の両端のパッドは、半導体チップ１の入
出力パッドとこれに対応するインナーリードとの位置に
合せてそれぞれ位置を定めることが可能である。又、配
線板３は、この対応する２個のパッド間を接続する信号
線２が他の信号線２との間で交叉しても電気的に接続し
ないよう、２層以上の配線経路を持つ構造とすることに
より、必要に応じ任意のパッド間を最短距離で接続する
ことができる。The semiconductor chip 1 is housed in a semiconductor integrated circuit device 5 with an insulating film 4 interposed between the wiring board 3 and a wiring board 3 on which a plurality of signal lines 2 having connection pads at both ends are arranged. semiconductor chip 1
The input/output pad and one pad of the signal line 2 are connected by a bonding wire 6. The other pad of the signal line 2 is provided to connect the semiconductor integrated circuit device 5 to the outside. A bonding wire 8 is connected to an inner lead 7 which is a part of the lead. The pads at both ends of the signal line 2 disposed on the wiring board 3 can be positioned in accordance with the positions of the input/output pads of the semiconductor chip 1 and the corresponding inner leads. Further, the wiring board 3 has a wiring path of two or more layers so that the signal line 2 connecting these two corresponding pads does not electrically connect even if it crosses with another signal line 2. With this structure, arbitrary pads can be connected over the shortest distance if necessary.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体チップ上の任意の
パッドと任意のインナーリードとを接続することを可能
としたので、半導体チップ上でのレイアウトから半導体
集積回路装置のインターリードの位置が制約を受けるこ
とがなくなり、プリント基板上での信号線の配線も容易
に行えるようになるという効果がある。また、半導体チ
ップ上でのレイアウトが自由に行えるため、出力バッフ
ァを各地気パッドごとに分散させて配置することが可能
となり、出力バッファの同時動作業による影響を小さく
できるという効果もある。As explained above, the present invention makes it possible to connect any pad on a semiconductor chip to any inner lead, so the position of interleads in a semiconductor integrated circuit device is restricted by the layout on the semiconductor chip. This has the effect that signal lines can be wired easily on the printed circuit board. Furthermore, since the layout on the semiconductor chip can be freely performed, it is possible to arrange the output buffers in a distributed manner for each air pad, which has the effect of reducing the influence of simultaneous operation of the output buffers.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は本発明の一実施例のボンデングワイヤの
接続を模式化した平面図、第１図（ｂ）は同じく側面図
である。 １・・・半導体チップ、２・・・信号線、３・・・配線
板、４・・・絶縁板、５・・・半導体集積回路装置、６
．８・・・ボンデングワイヤ、７・・・インナーリード
。FIG. 1(a) is a plan view schematically showing the connection of bonding wires according to an embodiment of the present invention, and FIG. 1(b) is a side view of the same. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Signal line, 3... Wiring board, 4... Insulating board, 5... Semiconductor integrated circuit device, 6
．． 8... Bonding wire, 7... Inner lead.

Claims (1)

【特許請求の範囲】 １、内蔵する半導体チップをインナーリードに接続する
構造の半導体集積回路装置において、接続経路を変換す
る機能を持つ接続経路変換板を介して前記半導体チップ
を前記インナーリードに接続することを特徴とする半導
体集積回路装置。 ２、前記半導体チップと前記接続経路変換板との間およ
び前記接続経路変換板と前記インナーリードとの間の接
続の少くなくとも一部をボンデングワイヤを用いて行う
ことを特徴とする請求項１記載の半導体集積回路装置。[Scope of Claims] 1. In a semiconductor integrated circuit device having a structure in which a built-in semiconductor chip is connected to an inner lead, the semiconductor chip is connected to the inner lead via a connection path conversion board having a function of converting connection paths. A semiconductor integrated circuit device characterized by: 2. At least a part of the connections between the semiconductor chip and the connection path conversion board and between the connection path conversion board and the inner leads are made using bonding wires. 1. The semiconductor integrated circuit device according to 1.
JP2249184A 1990-09-19 1990-09-19 Semiconductor integrated circuit device Expired - Lifetime JP2911988B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2249184A JP2911988B2 (en) 1990-09-19 1990-09-19 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2249184A JP2911988B2 (en) 1990-09-19 1990-09-19 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH04127545A true JPH04127545A (en) 1992-04-28
JP2911988B2 JP2911988B2 (en) 1999-06-28

Family

ID=17189153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2249184A Expired - Lifetime JP2911988B2 (en) 1990-09-19 1990-09-19 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2911988B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003174111A (en) * 2001-12-06 2003-06-20 Sanyo Electric Co Ltd Semiconductor device
US6812575B2 (en) 2000-08-29 2004-11-02 Nec Corporation Semiconductor device
US8471349B2 (en) 2010-01-29 2013-06-25 Fujitsu Optical Components Limited Photoreceiving device
CN105914194A (en) * 2016-06-20 2016-08-31 东莞市联洲知识产权运营管理有限公司 An optimized integrated circuit package
CN106098672A (en) * 2016-06-20 2016-11-09 东莞市联洲知识产权运营管理有限公司 A kind of integrated antenna package of improvement

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812575B2 (en) 2000-08-29 2004-11-02 Nec Corporation Semiconductor device
JP2003174111A (en) * 2001-12-06 2003-06-20 Sanyo Electric Co Ltd Semiconductor device
US8471349B2 (en) 2010-01-29 2013-06-25 Fujitsu Optical Components Limited Photoreceiving device
CN105914194A (en) * 2016-06-20 2016-08-31 东莞市联洲知识产权运营管理有限公司 An optimized integrated circuit package
CN106098672A (en) * 2016-06-20 2016-11-09 东莞市联洲知识产权运营管理有限公司 A kind of integrated antenna package of improvement

Also Published As

Publication number Publication date
JP2911988B2 (en) 1999-06-28

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