JP7738180B2 - Local Passive Matrix Display - Google Patents

Description

The present invention relates generally to electronic devices, and more particularly to electronic devices having displays.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to U.S. Patent Application No. 17/894,935, filed August 24, 2022, U.S. Patent Application No. 17/894,942, filed August 24, 2022, U.S. Provisional Patent Application No. 63/247,744, filed September 23, 2021, and U.S. Provisional Patent Application No. 63/247,747, filed September 23, 2021, which are incorporated by reference in their entireties.

Electronic devices often include a display. For example, an electronic device may have a liquid crystal display in which liquid crystal display pixels are used to display images for a user. Liquid crystal displays often include a light emitting diode backlight unit to provide backlight illumination. Display efficiency can be adversely affected by inefficiencies in generating the backlight illumination and transmitting the backlight illumination through the liquid crystal display structure. Liquid crystal display structures also exhibit limited contrast ratios. While organic light emitting diode displays have been developed that exhibit high contrast ratios, these devices may consume more power than desired due to inefficiencies in their organic light emitting diodes. Ensuring that organic light emitting diodes exhibit a desired lifetime can also be difficult.

The electronic device may include a display. The display may be formed by an array of light emitting diodes attached to a surface of a display substrate. The light emitting diodes may be inorganic light emitting diodes formed from discrete crystalline semiconductor structures. An array of pixel control circuits may be used to control the emission of light from the light emitting diodes. Each pixel control circuit may be used to provide a drive signal to a separate set of light emitting diodes arranged in a passive matrix.

Each pixel control circuit may be configured to control one or more respective passive matrices. However, some of the passive matrices may be interrupted by the boundaries for the display (e.g., rounded corners of the active area). These interrupted groups of pixels are sometimes referred to as partial pixel cells. Some of the partial pixel cells may still have dedicated pixel control circuits. Some of the partial pixel cells may not have dedicated pixel control circuits due to their pixel control circuits being outside the target boundaries for the display.

Additional pixel control circuits offset relative to the rest of the array of pixel control circuits may be included to control the partial pixel cells. Alternatively, a donor pixel control circuit in a partial pixel cell may control a pixel in a receptor partial pixel cell without a pixel control circuit. Anode contacts in different columns may be electrically connected to allow the donor pixel control circuit to control the receptor partial pixel cell.

To reduce the size of the display's inactive area, fan-out signal lines for the display may be formed within the display's light-emitting active area. The fan-out signal lines may be formed between rows of pixel control circuits and the bottom edge of the light-emitting active area. Additional signal lines may be formed between columns of pixel control circuits and the side edges of the light-emitting active area.

FIG. 1 is a perspective view of an exemplary electronic device having a display according to one embodiment.

1 is a schematic diagram of an exemplary electronic device having a display according to one embodiment.

FIG. 1 is a diagram of an exemplary display according to one embodiment.

FIG. 2 is a schematic diagram of an exemplary passive matrix of light emitting diodes controlled by a pixel control circuit, according to one embodiment.

FIG. 2 is a top view of an exemplary passive matrix of light emitting diodes with a grid of anode and cathode contacts, according to one embodiment.

FIG. 1 is a schematic diagram of an exemplary pixel control circuit for controlling two passive matrices, according to one embodiment.

FIG. 1 is a schematic diagram of an exemplary pixel control circuit for controlling four passive matrices, according to one embodiment.

1 is a top view of an exemplary display having an active area boundary bordering interrupted pixel cells with pixel control circuits, according to one embodiment.

FIG. 1B is a top view of an exemplary display with additional pixel control circuits used to control partial pixel cells, according to one embodiment.

FIG. 2 is a top view of an exemplary display with partial pixel cells controlled by adjacent pixel control circuits, according to one embodiment.

FIG. 1 is a top view of an exemplary display showing how anode contacts in a donor passive matrix can be electrically connected to anode contacts in a receptor passive matrix, according to one embodiment.

FIG. 2 is a schematic diagram of an exemplary display with pixel mapping circuitry, according to one embodiment.

FIG. 1 is a top view of an exemplary display showing how a receptor passive matrix can be controlled by multiple donor pixel control circuits, according to one embodiment.

FIG. 1 is a top view of an exemplary display with rounded corners and cutouts, according to one embodiment.

FIG. 2 is a top view of an exemplary display with an opening in the active area, according to one embodiment.

FIG. 2 is a top view of an exemplary display having fan-out signal lines in an inactive area of the display, according to one embodiment.

FIG. 2 is a top view of an exemplary display having fan-out signal lines within the active area of the display, according to one embodiment.

1 is a cross-sectional side view of an exemplary display having fan-out signal line regions within an active area, according to one embodiment.

FIG. 2 is a top view of an exemplary display with peripheral signal lines within the active area of the display, according to one embodiment.

FIG. 1 is a top view of an exemplary display in which a first row of pixels in the display active area is aligned with the tops of pixel cells controlled by a first row of pixel control circuits, according to one embodiment.

FIG. 1B is a top view of an exemplary display in which the first row of pixels in the display active area is not aligned with the tops of the pixel cells controlled by the first row of pixel control circuits, according to one embodiment.

FIG. 1B is a top view of an exemplary display in which pixel control circuits are formed in different stamps, according to one embodiment.

An exemplary type of electronic device that may include a display is shown in FIG. 1. An electronic device, such as electronic device 10 of FIG. 1, may be a computing device such as a laptop computer, a computer monitor including an embedded computer, a tablet computer, a mobile phone, a media player, or other handheld or portable electronic device; a smaller device such as a watch device, a pendant device, a headphone or earphone device, a device embedded in eyeglasses or other device worn on a user's head, or other wearable or miniature device; a television or other display for a video; a computer display without an embedded computer; a gaming device; a navigation device; an embedded system such as a kiosk or automobile-mounted system with a display; a device that performs the functions of two or more of these devices; or other electronic equipment. The configuration of device 10 shown in FIG. 1 (e.g., a portable device configuration in which device 10 is a mobile phone, media player, wrist device, tablet computer, or other portable computing device) is shown as an example. Other configurations for device 10 may be used if desired.

Device 10 has one or more displays, such as display 14, attached to a housing structure, such as housing 12. Housing 12 of device 10, sometimes referred to as a case, can be formed from materials such as plastic, glass, ceramic, carbon fiber composites and other fiber-based composites, metal (e.g., machined aluminum, stainless steel, or other metals), other materials, or combinations of these materials. Device 10 may be formed using a unitary construction, where most or all of housing 12 is formed from a single structural element (e.g., a machined piece of metal or a molded piece of plastic), or may be formed from multiple housing structures (e.g., an outer housing structure attached to an internal frame element or other internal housing structure).

Display 14 may be a touch-sensitive display that includes a touch sensor, or it may be insensitive to touch. The touch sensor for display 14 may be formed from an array of capacitive touch sensor electrodes, a resistive touch array, a touch sensor structure based on acoustic touch, optical touch, or force-based touch technology, or other suitable touch sensor components. The touch sensor electrodes may be used to capture touch input from a user's finger or stylus and/or may be used to collect fingerprint data.

Display 14 may include an array of light-emitting pixels, such as an array of light-emitting diode pixels. Generally, display 14 may use liquid crystal display technology, light-emitting diode display technology such as organic light-emitting diode display technology, plasma display technology, electrophoretic display technology, electrowetting display technology, or other types of display technology. A configuration in which display 14 is based on an array of light-emitting diodes may be described herein as an example. However, this is merely an example. Other types of display technologies may be incorporated into device 10 as desired.

A schematic diagram of an electronic device such as electronic device 10 of FIG. 1 is shown in FIG. 2. As shown in FIG. 2, electronic device 10 may have control circuitry 16. Control circuitry 16 includes memory and processing circuitry to support operation of device 10. The memory and processing circuitry may include storage devices such as hard disk drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), or volatile memory (e.g., static or dynamic random access memory). Processing circuitry within control circuitry 16 may be used to control operation of device 10. The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio codec chips, application-specific integrated circuits, etc.

Input/output circuitry within device 10, such as input/output device(s) 18, may be used to enable data to be provided to device 10 and to enable data to be provided from device 10 to external devices. Input/output device(s) 18 may include buttons, joysticks, scroll wheels, touchpads, fingerprint sensors, keypads, keyboards, microphones, speakers, tone generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, and the like. A user can control the operation of device 10 by providing commands through input/output device(s) 18 and can receive status information and other output from device 10 using the output resources of input/output device(s) 18. Input/output device(s) 18 may include one or more displays, such as display 14 of FIG. 1.

The control circuitry 16 is used to execute software, such as operating system code and applications, on the device 10. During operation of the device 10, the software executing on the control circuitry 16 can display images on the display 14 within the input/output device 18.

As shown in the exemplary diagram of FIG. 3, the display 14 may include layers such as a substrate layer 24. A layer such as the substrate 24 may be formed from a layer of material such as a glass layer, a polymer layer, a composite film including a polymer and an inorganic material, a metal foil, a semiconductor such as silicon or other semiconductor material, a layer of material such as sapphire (e.g., a crystalline transparent layer, a ceramic, etc.), or other material. The substrate 24 may be planar or may have other shapes (e.g., concave, convex, flat, and shapes with curved surface regions, etc.). The outer shape of the substrate 24 (e.g., when viewed from above along the Z direction) may be circular, elliptical, rectangular, square, have a combination of straight and curved edges, or have other suitable shapes. As shown in the example of a rectangular substrate in FIG. 3, the substrate 24 may have left and right vertical edges and top and bottom horizontal edges.

The display 14 may have an array of pixels 22 for displaying images to a user. Sets of one or more pixels 22 may be controlled using respective pixel control circuits 20 (sometimes referred to as driver circuits 20 or microdrivers 20). The pixel control circuits 20 may be formed using integrated circuits (e.g., silicon integrated circuits) and/or thin-film transistor circuits on a substrate 24. The thin-film transistor circuits may include thin-film transistors formed from silicon (e.g., polysilicon thin-film transistors or amorphous silicon transistors) and/or thin-film transistors based on semiconductor oxides (e.g., indium gallium zinc oxide transistors or other semiconductor oxide thin-film transistors). Semiconductor oxide transistors, such as indium gallium zinc oxide transistors, may exhibit low leakage current and therefore may be advantageous in display 14 configurations where it is desirable to reduce power consumption (e.g., by reducing the refresh rate of the display's pixels). Display 14 configurations in which the pixel control circuits 20 are each formed from a set of silicon integrated circuits and thin-film semiconductor oxide transistors may be used as desired.

The pixels 22 may be organized into arrays (e.g., arrays having rows and columns). The pixel control circuits 20 may be organized into associated arrays (e.g., arrays having rows and columns). As shown in FIG. 3, the pixel control circuits 20 may be interspersed among the array of pixels 22. The pixels 22 and pixel control circuits 20 may be organized into arrays having rectangular outlines or outlines of other suitable shapes. There may be any suitable number of rows and columns in each array (e.g., 10 or more, 100 or more, or 1000 or more).

Each pixel 22 may be formed from a light-emitting component, such as a light-emitting diode. If desired, each pixel may include a pair of light-emitting diodes or any other suitable number of light-emitting diodes for redundancy. In this type of configuration (as an example), the pair of light-emitting diodes in each pixel may be driven in parallel. If one of the light-emitting diodes fails, the other light-emitting diode will still generate light. Alternatively, or in addition, multiple pixel control circuits may be configured to control each pixel. If one of the pixel control circuits fails, the other pixel control circuit will still control the pixel.

Display driver circuits, such as display driver circuit 28, are coupled to conductive paths, such as metal traces, on substrate 24 using solder or a conductive adhesive. Display driver circuit 28 includes communication circuitry for communicating with system control circuitry via paths 26. Paths 26 may be formed from traces on a flexible printed circuit or other cable, or may be formed using other signal routing structures within device 10. The control circuitry may be located on a main circuit logic board within the electronic device in which display 14 is used. In operation, control circuitry on the circuit logic board (e.g., control circuit 16 of FIG. 1) may provide circuitry, such as display driver circuit 28, with information regarding an image to be displayed on display 14. To display an image on display pixels 22, display driver circuit 28 may provide corresponding image data, control signals, and/or power signals to signal lines S, which in turn provide corresponding image data, control signals, and power to pixel control circuitry 20. Based on the received power, image data, and control signals, pixel control circuitry 20 directs individual subsets of pixels 22 to generate light at desired intensity levels.

Signal lines S may carry analog and/or digital control signals (e.g., scan signals, emission transistor control signals, clock signals, digital control data, power signals, etc.). In some cases, signal lines may be coupled to individual columns of pixel control circuits 20. In some cases, signal lines may be coupled to individual rows of pixel control circuits 20. Each pixel control circuit 20 may be coupled to one or more signal lines. Circuits 28 may be formed at the top edge of display 14 (as in FIG. 3), the bottom edge of display 14, the top and left edges of display 14, the top, left, and right edges of the display, or any other desired location within display 14.

Display control circuitry such as circuit 28 may be implemented using one or more integrated circuits (e.g., display driver integrated circuits such as a timing controller integrated circuit and associated source driver circuitry and/or gate driver circuitry), or may be implemented using thin-film transistor circuitry implemented on substrate 24.

Pixel 22 may be an organic light-emitting diode pixel or a liquid crystal display pixel. Alternatively, pixel 22 may be formed from individual inorganic light-emitting diodes (sometimes referred to as micro-LEDs). Pixel 22 may include light-emitting diodes of different colors (e.g., red, green, and blue). Corresponding signal lines may be used to carry red, green, and blue data. Other color pixel arrangements may be used as desired (e.g., a four-color arrangement, an arrangement including a white pixel, a three-pixel configuration having pixels other than red, green, and blue pixels, etc.). To produce different colors, the light-emitting diodes of pixel 22 may be constructed from different material systems (e.g., AlGaAs for the red diode and GaN multi-quantum well diodes with different quantum well configurations for the green and blue diodes, respectively), may be formed using different phosphorescent materials or different quantum dot materials to produce red, blue, and/or green luminescence, or may be formed using other techniques or combinations of these techniques. The light-emitting diodes of the pixels 22 may emit upward (i.e., the pixels 22 may use a top-emission design) or downward through the substrate 24 (i.e., the pixels 22 may use a bottom-emission design). The light-emitting diodes may have a thickness of about 0.5 to 10 microns (for example) and lateral dimensions of about 2 to 100 microns. Light-emitting diodes having other thicknesses (e.g., less than 2 microns, more than 2 microns, etc.) and other lateral dimensions (e.g., less than 10 microns, less than 20 microns, more than 3 microns, more than 15 microns, etc.) may also be used, if desired.

If desired, digital control signals can be provided to circuitry 20 (via signal line S), which can then generate corresponding analog light emission drive signals based on the digital control signals. During operation of display 14, each pixel control circuit 20 can provide output signals to a corresponding set of pixels 22 based on control signals received by that pixel control circuit from display driver circuit 28.

As an example, each pixel control circuit 20 can control an individual local passive matrix 30 of LED pixels 22. Figure 4 is a schematic diagram of a local passive matrix 30 of LED pixels 22. As shown in Figure 4, the anode of each LED 22 is coupled to an individual anode contact wire A (sometimes referred to as an anode contact A or an anode wire A). The LEDs 22 in each column in the passive matrix are connected to a common anode contact A. The cathode of each LED 22 is coupled to an individual cathode contact wire C (sometimes referred to as a cathode contact C or a cathode wire C). The LEDs 22 in each row of the passive matrix are connected to a common cathode contact C.

The pixel control circuit 20 can control the current and voltage supplied to each anode line A. The pixel control circuit 20 can also control the voltage supplied to each cathode contact line C. In this way, the pixel control circuit 20 controls the current through each light-emitting diode 22, which controls the intensity of light emitted by each light-emitting diode. During passive matrix operation, the pixel control circuit 20 can rapidly scan the pixels 22 row by row, causing each LED 22 to emit light at a desired brightness level. In other words, each pixel in the first row is updated to the desired brightness level, then each pixel in the second row is updated to the desired brightness level, and so on.

The pixel control circuit 20 may have a first output terminal 32 coupled to the anode contact line A and a second output terminal 34 coupled to the cathode contact line C. As an example, the pixel control circuit 20 may have one output terminal 32 for each anode contact line and one output terminal 34 for each cathode contact line. Thus, by using a passive matrix such as that shown in Figure 4, the pixel control circuit 20 may control 64 light-emitting diodes (e.g., an 8x8 grid) using only 16 outputs (eight anode output terminals and eight cathode output terminals).

Figure 5 is a plan view of the passive matrix 30, showing how the pixel control circuits 20 are electrically connected to each anode contact A and cathode contact C. In the example of Figure 5, the local passive matrix of LEDs is an 8x8 array. Thus, there are eight anode contacts A and eight cathode contacts C arranged in an overlapping grid. The anode contacts extend perpendicular to the cathode contacts, and each position of overlap between an anode contact and a cathode contact defines an individual LED pixel 22.

As shown in FIG. 5, the display may include routing lines such as routing lines 36 and 38 for electrically connecting the output terminals of the pixel control circuits 20 to the anode and cathode contacts. Specifically, some routing lines 36 are included to connect the output terminals 32 of the pixel control circuits 20 to the respective anode contacts A. Some routing lines 38 are included to connect the output terminals 34 of the pixel control circuits 20 to the respective cathode contacts C. The inclusion of routing lines 36 and 38 allows the footprint and position of the pixel control circuits 20 to be selected independently from the positions of the anode and cathode contacts. The routing lines 36 and 38 may be formed, by way of example, by metal traces (signal lines) on one or more layers of the substrate 24 and/or conductive vias that penetrate one or more layers of the substrate 24.

Each pixel control circuit 20 can control a single passive matrix of LED pixels or multiple passive matrices of LED pixels. FIG. 6A is a schematic diagram illustrating how an exemplary pixel control circuit 20 can control first and second passive matrices 30 of LEDs 22. FIG. 6B is a schematic diagram illustrating how an exemplary pixel control circuit 20 can control first, second, third, and fourth passive matrices 30 of LEDs 22. In general, each pixel control circuit 20 can control any desired number of LED passive matrices 30 (e.g., 1, 2, 3, 4, 5 or more, etc.). Each passive matrix 30 can include any desired number of LED rows and LED columns (e.g., more than 1, more than 3, more than 6, more than 10, more than 20, more than 50, less than 6, less than 10, less than 20, less than 50, etc.).

Finally, each pixel control circuit 20 can be configured to control a distinct subset of LED pixels. The distinct subset of LED pixels controlled by each pixel control circuit may be referred to as a pixel cell, a passive matrix cell, or the like. Each pixel cell may be comprised of one or more distinct passive matrix cells, as shown and described in connection with Figures 4-6.

Figure 7 is a top view of an exemplary display having multiple pixel control circuits 20 and corresponding pixel cells 40. Each pixel cell may include an array of LED pixels (e.g., micro-LEDs) arranged in one or more passive matrices. Each pixel control circuit 20 can apply signals to the anode contact A and cathode contact C of the passive matrix in its individual pixel cell 40 to control the light emitted by the pixel in that pixel cell 40.

This pixel control scheme can be affected by the geometry of the display's light-emitting area. For example, consider an example in which each pixel control circuit is configured to control m×n cells of pixels (having m rows and n columns). When a pixel control circuit has an associated m×n cell of pixels to control, the pixel control circuit can be said to control a full pixel cell. The pixel control circuits may be distributed across the display such that the majority of pixel control circuits have an associated full m×n cell of pixels to control. However, the display geometry may cause some pixel control circuits to have only partial pixel cells. In other words, a pixel control circuit can control fewer pixels than it could. Conversely, some LED pixels may not have an associated pixel control circuit (due to the display geometry causing individual pixel control circuits to be omitted for those LED pixels).

The light-emitting active area of a display may have a footprint with rounded corners, for example. FIG. 7 shows how the active area of the display follows a rounded boundary 42 at the corners of the display. The boundary 42 (sometimes referred to as a spline 42) may be a target boundary for the display. Light-emitting LED pixels 22 are included or omitted to approximate the curvature of the boundary 42 at the rounded corners.

Figure 7 shows how the target boundary 42 intersects a portion of the pixel cell 40, resulting in the partial pixel cell being a partial pixel cell, as described above. For example, a first pixel control circuit 20-1 controls a full pixel cell 40-1, and a second pixel control circuit 20-2 controls a partial pixel cell 40-2. The partial pixel cell 40-2 is interrupted by the target boundary 42. Thus, pixels outside the boundary 42 within the pixel cell 40-2 may be omitted from the display.

In addition, pixel control circuits outside the target boundary may be omitted from the display. In the example of FIG. 7, three pixel control circuits, including pixel control circuit 20-3, are positioned outside the target boundary 42. Including these pixel control circuits may increase the size of the non-emitting inactive area of the display 14. Therefore, to reduce the size of the non-emitting inactive area, these pixel control circuits (as indicated by the dashed lines) may be omitted from the display. This allows the substrate 24 to be cut to have approximately the same shape as the target boundary 42, with only a small non-emitting inactive area between the edge of the emitting active area and the edge of the substrate.

Omitting these pixel control circuits can result in partial pixel cells that do not have dedicated pixel control circuits. Figure 7 shows how partial pixel cell 40-3 does not have a dedicated pixel control circuit (because its corresponding pixel control circuit 20-3 is located outside the target boundary and is therefore omitted). Similarly, partial pixel cell 40-4 does not have a dedicated pixel control circuit (because its corresponding pixel control circuit is positioned outside the target boundary and is therefore omitted).

The display 14 may include additional components to ensure that the sub-pixel cells having the cut-off pixel control circuits are driven to emit the desired amount of light during operation.

The first option for controlling these partial pixel cells is to include additional pixel control circuits, as shown in FIG. 8. Partial pixel cell 40-3 may include an additional pixel control circuit 20-A1 shifted inside target boundary 42. Therefore, there is sufficient space available on display substrate 24 to include the additional pixel control circuit 20-A1. Partial pixel cell 40-4 may include an additional pixel control circuit 20-A2 shifted inside target boundary 42. Therefore, there is sufficient space available on display substrate 24 to include the additional pixel control circuit 20-A2.

In the central portion of the display, the pixel control circuits may have a pitch 44 in the X direction and a pitch 46 in the Y direction. The pitches 44 and 46 may be uniform across the display, such that the pixel control circuits (which may be formed by integrated circuits) are arranged in evenly spaced rows and columns (as shown in Figures 7 and 8). However, the additional pixel control circuits 20-A1 and 20-A2 are misaligned with respect to the surrounding rows and/or columns. That is, multiple pixel control circuits 20 are arranged in rows and columns. The pixel control circuit 20-A1 is shifted in the X direction relative to the pixel control circuit column. The pixel control circuit 20-A1 is shifted in the Y direction relative to the pixel control circuit row.

As shown in FIG. 8, the spacing between pixel control circuit 20-A1 and its adjacent pixel control circuit is less than pitches 44 and 46. Similarly, the spacing between pixel control circuit 20-A2 and its adjacent pixel control circuit is less than pitches 44 and 46. Therefore, the position of the additional pixel control circuit is modified relative to the remaining pattern of pixel control circuits to ensure that all of the sub-pixel cells have a corresponding pixel control circuit.

Figure 9 illustrates an option for controlling a partial pixel cell without an additional pixel control circuit. As shown in Figure 9, the pixel drive circuits of adjacent partial pixel cells can be used to drive the pixels of the partial pixel cell. As an example, each pixel control circuit drives a 16x16 grid of pixels (arranged in one or more passive matrices). Thus, the pixel control circuit has output terminals for the 16x16 grid of pixels and logic and control circuitry for driving the 16x16 grid of pixels. However, partial pixel cells in a display may include less than a full 16x16 grid of pixels.

Consider pixel cell 40-1, which includes pixel control circuit 20-1 (arranged according to a regular pixel control circuit pattern). Pixel cell 40-1 is interrupted by boundary 42 and is therefore a partial pixel cell. A partial pixel cell, for example, may include only 150 pixels (instead of the 256 pixels of a full 16x16 pixel cell). Thus, pixel control circuit 20-1 only has 150 pixels to control, instead of the full 256. Thus, pixel control circuit 20-1 is underutilized by 106 pixels. In other words, pixel control circuit 20-1 has the capacity to control 106 extra pixels due to the omitted pixels in its pixel cell. Pixels outside the target boundary, such as pixel X1, are normally driven by pixel control circuit 20-1. However, the pixels in area X1 are omitted from the display because they are outside boundary 42.

On the other hand, subpixel cell 40-3 includes pixels in area X2 but does not have a dedicated pixel control circuit. Instead of including an additional pixel control circuit as in FIG. 8, the pixels in area X2 may be driven by the underutilized neighboring pixel control circuit 20-1. Subpixel cell 40-3 may include fewer than 106 pixels in area X2 (e.g., fewer pixels than the underutilization of pixel control circuit 20-1). Thus, pixel control circuit 20-1 has the capability to control all pixels in area X2 in addition to the pixels in its own subpixel cell.

Using this type of scheme, in which underutilized pixel control circuits are used to control pixels that would otherwise not have dedicated pixel control circuits, can allow the number of pixel control circuits in a display to be reduced while maintaining a small inactive border area.

As another example of this concept, consider pixel cell 40-2, which includes pixel control circuit 20-2 (arranged per a regular pixel control circuit pattern). Pixel cell 40-2 is interrupted by boundary 42 and is therefore a partial pixel cell. Therefore, pixel control circuit 20-2 is underutilized. In other words, pixel control circuit 20-2 has the ability to control the extra pixels due to the omitted pixels within that pixel cell. Pixels outside the target boundary, such as pixel Y1, are normally driven by pixel control circuit 20-2. However, pixels within area Y1 are omitted from the display because they are outside boundary 42.

On the other hand, subpixel cell 40-4 includes pixels from area Y2 but does not have a dedicated pixel control circuit. Instead of including an additional pixel control circuit as in FIG. 8, the pixels in area Y2 may be driven by the underutilized neighboring pixel control circuit 20-2. Subpixel cell 40-4 may include fewer pixels than the underutilized amount of pixel control circuit 20-2. Thus, pixel control circuit 20-2 has the ability to control all pixels in area Y2 in addition to the pixels in its own subpixel cell.

Figure 10 is a top view of an exemplary display showing how pixels within a pixel cell can be controlled by pixel control circuits in different adjacent pixel cells. In the example of Figure 10, each pixel control circuit is configured to control four passive matrices (similar to those shown in Figure 6B). In this example, each passive matrix is an 8x8 grid (e.g., similar to that shown in Figure 5). In the central portion of the display, each pixel control circuit can control four 8x8 passive matrices.

Along the boundary 42 (see FIG. 9), one or more of the 8×8 passive matrices may be interrupted. The result may be a partial passive matrix containing fewer than eight complete rows and/or fewer than eight complete columns. FIG. 10 shows how a first partial passive matrix 30-1 (containing eight pixels) and a second partial passive matrix 30-2 (containing 31 pixels) exist adjacent to the display boundary. The partial passive matrix 30-1 may be part of a pixel cell 40-1 (see FIG. 9) that contains a dedicated pixel control circuit 20-1. The partial passive matrix 30-2 is part of a pixel cell 40-3 (see FIG. 9) that does not contain a dedicated pixel control circuit. Each partial passive matrix contains an emitting pixel 22. FIG. 10 also shows the footprint of the omitted pixel 22'. The omitted pixel 22' completes the 8×8 passive matrix for each of the passive matrices 30-1 and 30-2. However, the display boundaries cause pixel 22' to be omitted.

Note that the pixel control circuit 20-1 in FIG. 10 may control passive matrices 30-3, 30-4, and 30-5 in addition to the partial passive matrix 30-1. One or both of the passive matrices 30-3 and 30-4 may be partial passive matrices. Passive matrix 30-5 may be a complete passive matrix (having a complete 8x8 grid of emissive pixels).

The pixel control circuit 20-1 may have eight anode outputs 1A to 8A (e.g., output terminal 32 in FIG. 5) and eight cathode outputs 1C to 8C (e.g., output terminal 34 in FIG. 5) configured to drive the passive matrix 30-1. However, the passive matrix 30-1 is a partial passive matrix. Therefore, the output terminals of the pixel control circuit 20-1 may drive the partial passive matrix 30-2 from an adjacent pixel cell in addition to the partial passive matrix 30-1.

As shown in FIG. 10, cathode outputs 1C to 6C of pixel control circuit 20-1 are electrically connected to cathode contact C of partial passive matrix 30-2. Cathode outputs 7C to 8C of pixel control circuit 20-1 are electrically connected to cathode contacts of partial passive matrix 30-1. Each cathode output terminal in pixel control circuit 20-1 may be electrically connected to a corresponding cathode contact by a separate signal routing line 38. The signal routing line 38 may be formed, by way of example, by metal traces (signal lines) on one or more layers of substrate 24 and/or conductive vias passing through one or more layers of substrate 24. To access the cathode contact C in the partial passive matrix 30-2, some of the signal routing lines 38 (e.g., for output terminals 1C to 6C) can be routed from inside pixel cell 40-1 (including passive matrices 30-1, 30-3, 30-4, and 30-5) across the periphery of pixel cell 40-1 to the outside of pixel cell 40-1.

As shown in FIG. 10, anode outputs 1A to 5A of pixel control circuit 20-1 are electrically connected to anode contact A of partial passive matrix 30-1. Anode outputs 6A to 8A of pixel control circuit 20-1 are electrically connected to anode contacts of partial passive matrix 30-2. Each anode output terminal in pixel control circuit 20-1 may be electrically connected to a corresponding anode contact by a separate signal routing line 36. The signal routing line 36 may be formed, for example, by metal traces (signal lines) on one or more layers of substrate 24 and/or conductive vias through one or more layers of substrate 24. To access anode contact A in partial passive matrix 30-2, some of the signal routing lines 36 (e.g., for output terminals 6A to 8A) may be routed from inside pixel cell 40-1 (including passive matrices 30-1, 30-3, 30-4, and 30-5) beyond the periphery of pixel cell 40-1 to the outside of pixel cell 40-1.

10, some of the pixels in partial pixel matrix 30-1 share anode contacts with some of the pixels in partial pixel matrix 30-2. Accordingly, interconnect routing lines 50 may be included to electrically connect the anode contacts in matrix 30-1 to the anode contacts in matrix 30-2. The interconnect routing lines 50 may be formed, by way of example, by metal traces (signal lines) on one or more layers of substrate 24 and/or conductive vias that penetrate one or more layers of substrate 24. Each interconnect routing line electrically connects two separate anode contacts. For example, a first anode contact overlaps first and second pixels in the leftmost column of pixel matrix 30-1. A second anode contact overlaps one pixel in the rightmost column of pixel matrix 30-2. The interconnect routing lines electrically connect these two anode contacts. As another example, the rightmost anode contact in passive matrix 30-1 overlaps one pixel. The fifth anode contact in passive matrix 30-2 (from left to right) overlaps four pixels. An interconnect routing line electrically connects these two anode contacts.

As shown in FIG. 10, pixels in area X2 of passive matrix 30-2 correspond to corresponding omitted pixels in area X1 of passive matrix 30-1. The electrical connection arrangement between pixel control circuit 20-1, passive matrix 30-1, and passive matrix 30-2 may be selected so that each pixel in area X2 has a corresponding omitted pixel in area X1. In this way, the pixel control circuit can provide an output signal as if the pixel in area X1 actually existed. Based on the electrical connection to pixel control circuit 20-1, pixel 1 in area X2 corresponds to pixel 1' in area X1. In other words, pixel 1 in area X2 is driven by the pixel control circuit as if it were located at row 1, column 1 in passive matrix 30-1. However, when pixel control circuit 20-1 outputs a control signal to control the emission of the pixel at row 1, column 1, pixel 1 in area X2 actually emits light. Based on the electrical connection to the pixel control circuit 20-1, pixel 2 in area X2 corresponds to pixel 2' in area X1. In other words, pixel 2 in area X2 is driven by the pixel control circuit as if it were at row 1, column 8 in passive matrix 30-1. However, when pixel control circuit 20-1 outputs a control signal to control the light emitted by the pixel at row 1, column 8, pixel 2 in area X2 actually emits light. Based on the electrical connection to the pixel control circuit 20-1, pixel 3 in area X2 corresponds to pixel 3' in area X1. In other words, pixel 3 in area X2 is driven by the pixel control circuit as if it were at row 6, column 8 in passive matrix 30-1. However, when pixel control circuit 20-1 outputs a control signal to control the light emitted by the pixel at row 6, column 8, pixel 3 in area X2 actually emits light. Based on the electrical connection to pixel control circuit 20-1, pixel 4 in area X2 corresponds to pixel 4' in area X1. In other words, pixel 4 in area X2 is driven by the pixel control circuit as if it were at row 4, column 4 in passive matrix 30-1. However, when pixel control circuit 20-1 outputs a control signal that controls the emission of the pixel at row 4, column 4, pixel 1 in area X2 actually emits light.

Therefore, the drive scheme and logic within pixel control circuit 20-1 do not need to be modified relative to other pixel control circuits in the display. Pixel control circuit 20-1 outputs signals similar to other pixel control circuits in the display. However, due to the modified electrical connections, pixel control circuit 20-1 controls partial passive matrix 30-1 and partial passive matrix 30-2 using a drive scheme.

Typically (e.g., to control a fully passive matrix such as in FIG. 5), each anode contact in the passive matrix overlaps with pixels in one given column of pixels in the overall display. In FIG. 10, by contrast, overlapping anode contacts with pixels in separate columns of pixels in the display may be electrically connected. Because the anode contacts are electrically connected, the passive matrix operates electrically as if the pixels were in the same column (as in FIG. 5). However, because of the interconnections between the anode contacts, pixels that are from the same (electrically) "column" of the passive matrix are physically split between the two columns of the display.

In FIG. 10, the anode contacts (e.g., for output terminals 1A-5A) are divided among multiple physical locations, and each cathode contact is not divided among different locations. However, if desired, the cathode contacts may be divided among different locations (and electrically connected with interconnect routing lines) similar to the anode contacts in FIG. 10.

In FIG. 10, there is horizontal mirroring of the pixels in area X2 with their corresponding pixels in area X1. In other words, omitted pixel 1' on the left edge of passive matrix 30-1 is mapped to the actual pixel on the right edge of passive matrix 30-2, omitted pixel 2' on the right edge of passive matrix 30-1 is mapped to the actual pixel on the left edge of passive matrix 30-2, and so on. Using horizontal mirroring in this manner can be advantageous for minimizing the complexity of interconnect routing between passive matrices 30-1 and 30-2.

The example in Figure 10 of pixel control circuit 20-1 supplying a signal to an anode contact in passive matrix 30-2 via an anode contact in passive matrix 30-1 is merely illustrative. Alternatively, the opposite configuration may be used, in which pixel control circuit 20-1 supplies a signal to an anode contact in passive matrix 30-1 via an anode contact in passive matrix 30-2.

The electronic device may include a pixel mapping circuit configured to map target pixel luminance values to corresponding pixels controlled by pixel control circuits. Figure 11 is a schematic diagram of an exemplary display in which a pixel mapping circuit 52 is included in a display driver circuit 28. The display driver circuit 28 can receive pixel data (e.g., from a graphics processor or other device component) and output corresponding mapped pixel data to pixel control circuits 20 on the display panel for display.

The pixel mapping circuit 52 may receive pixel data corresponding to a target image to be displayed on the display. In other words, the received pixel data may include target luminance values for physical locations across the display. The pixel mapping circuit 52 maps these target luminance values to specific instructions for each pixel control circuit 20.

As an example, consider pixels 1 and 1' in FIG. 10. Pixel mapping circuit 52 can receive a target luminance value for pixel 1. The pixel mapping circuit can map this target luminance value to pixel 1', which is controlled by pixel control circuit 20-1. Then, when the mapped pixel data is used by pixel control circuit 20-1 to operate the pixel, pixel control circuit 20-1 provides an output to operate pixel 1' at the desired luminance. However, due to the electrical layout of passive matrices 30-1 and 30-2, pixel 1 emits light at the desired luminance. This type of mapping can be performed for each pixel in the display, as needed.

The examples in Figures 9 and 10 of a pixel control circuit from one adjacent pixel cell being used to control all of the remaining pixels in a given partial pixel cell are merely illustrative. In general, pixels within a partial pixel cell may be controlled by one or more pixel control circuits from adjacent pixel cells. Figure 12 is a diagram of a partial pixel cell controlled by multiple adjacent pixel control circuits.

Subpixel cell 40-3 includes a first subset of pixels in area X2 and a second subset of pixels in area Y2, but does not have a dedicated pixel control circuit. Pixel cell 40-1 includes pixel control circuit 20-1 (arranged according to a regular pixel control circuit pattern). Pixel cell 40-1 is interrupted by boundary 42 and is therefore a partial pixel cell. Pixels outside the target boundary, such as pixel X1, are normally driven by pixel control circuit 20-1. However, because pixels in area X1 are outside boundary 42, they are omitted from the display. Pixels in area X2 may be driven by the neighboring, underutilized pixel control circuit 20-1.

Pixel cell 40-2 includes pixel control circuits 20-2 (arranged according to a regular pixel control circuit pattern). Pixel cell 40-2 is interrupted by boundary 42 and is therefore a partial pixel cell. Pixels outside the target boundary, such as pixel Y1, are normally driven by pixel control circuits 20-2. However, pixels within area Y1 are outside boundary 42 and are therefore omitted from the display. Pixels in area Y2 may be driven by neighboring, underutilized pixel control circuits 20-2.

Using this type of scheme, multiple underutilized pixel control circuits are used to control pixels within a single partial pixel cell 40-3. This example is merely illustrative. In general, any partial pixel cell (sometimes referred to as a receptor) that does not have a dedicated pixel control circuit can be controlled by pixel control circuits from any desired number of adjacent pixel cells (sometimes referred to as donor pixel cells that have donor pixel control circuits).

So far, examples have been described in which the display target boundary has rounded corners. The rounded corners may result in partial pixel cells using any of the drive techniques described in connection with Figures 8-12. However, other display layouts may also result in partial pixel cells using any of the drive techniques discussed in connection with Figures 8-12.

Figure 13A is a top view of a display having a light-emitting active area (AA) with a footprint having rounded corners 54. The upper right corner of the display (as viewed from above) is shown in Figure 13A. However, if desired, all four corners of the active area may be rounded. The rounded corners 54 may result in a partial pixel cell using any of the drive techniques described in connection with Figures 8-12. Additionally, a notch 56 is formed along the top edge of the active area. The notch 56 may cause the boundary 42 to have a curvature in one or more portions of the region 58 that defines the notch. The presence of the notch 56 may also result in a partial pixel cell (e.g., within region 58) using any of the drive techniques described in connection with Figures 8-12.

Figure 13B is a top view of a display having a light-emitting active area (AA) with an opening 60. The opening can be, by way of example, a physical hole in the display panel. The opening is laterally surrounded by the light-emitting active area AA. The opening 60 can give rise to a partial pixel cell (e.g., adjacent the boundary of the opening 60) that uses any of the drive techniques described in connection with Figures 8-12.

In general, displays with footprints of any shape (e.g., with boundaries having one or more curved portions and/or one or more straight portions) can result in partial pixel cells that do not have dedicated pixel control circuits. When a display design results in partial pixel cells that do not have dedicated pixel control circuits, any of the drive techniques discussed in connection with Figures 8-12 may be used (regardless of the exact shape of the light-emitting active area).

In addition to using the pixel mapping circuit 52 to provide modified pixel data to the pixel control circuit 20, the display driver circuit 28 may also perform black painting on omitted pixels in the display. Consider the example of FIG. 10, in which some omitted pixels 22' in the passive matrix 30-1 are mapped to physical pixels in the passive matrix 30-2. Other omitted pixels 22' in the passive matrix 30-1 (e.g., omitted pixels 22' outside area X1) are not mapped to any physical pixels in the display. Because no pixels exist in these locations, no light can be emitted at these locations. Thus, in some configurations, these omitted pixels may not receive a target luminance level (and may correspondingly have a random target luminance level or a dummy luminance level assigned during control operation). However, the pixel control circuit 20-1 can still be configured to generate control signals for a complete 8x8 passive matrix (even if some of the pixels in the passive matrix are physically omitted). If random and/or non-zero target luminance values are used for the omitted pixels, pixels in the active area may be undesirably turned on when the pixel control circuit 20-1 operates the passive matrix (even if the active area pixels are not intended to be turned on).

To prevent unwanted light emission from occurring, the display driver circuit 28 can assign a zero gray level to each omitted pixel in the display. The zero gray level may correspond to a physical light-emitting diode that is kept off during operation (e.g., no light is emitted by the pixel, and the pixel appears black). This process is sometimes referred to as blacking out. During blacking out, each omitted pixel is assigned a zero gray level. When modified pixel data (with a zero gray level for the omitted pixels) is then provided to the pixel control circuit 20, the unwanted light emission is mitigated. The blacking out process may optionally be performed by the pixel mapping circuit 52.

It should be noted that the footprint of the display's active area can be selected to reduce the number of partial pixel cells in the display and/or the number of partial pixel cells in the display without dedicated pixel control circuits. As an example, slight adjustments to the radius of curvature of the rounded corners of the display can result in a significant reduction in the number of receptor pixel cells that require corresponding donor pixel cells. Similarly, small adjustments to the total number of rows and columns in the active area can significantly reduce the number of receptor pixel cells that require corresponding donor pixel cells. In general, the size and shape of the display's active area can be selected to optimize the number and placement of partial pixel cells in the display, as desired. The position of the grid of pixel control circuits may also be centered (in both the X and Y directions) with respect to the light-emitting active area to optimize the number and placement of partial pixel cells in the display, as desired.

The display may include various signal lines (e.g., data signal lines, global signal lines, and power supply lines) to operate the pixel control circuits 20 and light emitting diodes 22. Figure 14 is a plan view of an exemplary display having fan-out signal lines used to provide the necessary signals from the display driver circuitry to the signal lines for the display. As shown in Figure 14, the display may include a light emitting active area AA that includes pixel control circuits 20 arranged in an array of rows and columns. As previously described, each pixel control circuit controls one or more passive matrices of light emitting diodes.

As shown in FIG. 14 , the display driver circuitry 28 can be formed on the panel tail 24T. The panel tail 24T can be formed by an extension of the substrate 24. The extension of the substrate 24 can optionally be flexible/bendable. The panel tail 24T can be electrically connected to a flexible printed circuit or other component within the electronic device 10. The display driver circuitry 28 can be formed on the panel tail 24T, on a flexible printed circuit electrically connected to the panel tail 24T, or in another desired location within the device 10. In one exemplary configuration, the panel tail 24T can be bent (e.g., bent 180°) to electrically connect to a circuit printed board underlying the display 14.

The display driver circuit 28 can provide various signals to the pixel control circuits 20 that are used to operate the array of light emitting diodes in the display 14. However, the width of the display driver circuit 28 (and tail 24T) is smaller than the width of the active area of the display. Therefore, a fan-out signal line region 62 is included in the display to provide signals to all of the pixel control circuits as needed. The fan-out signal lines in region 62 can be used to spread the signals from the display driver circuit 28 across the entire area of the display 14 (e.g., the full width of the active area).

In the example of FIG. 14, fan-out signal line region 62 is formed on panel 24T outside of light-emitting active area AA. FIG. 14 similarly shows how peripheral signal lines (e.g., power lines) may be formed outside the active area in regions 64, 66, and 68. Region 64 extends along the right edge of the active area (outside the active area), region 66 extends along the top edge of the active area (outside the active area), and region 68 extends along the left edge of the active area (outside the active area). The display may include any desired components, such as power lines, in these regions.

In FIG. 14, regions 62, 64, 66, and 68 are all positioned outside the light-emitting active area AA of the display. Therefore, substrate 24 must have a non-light-emitting inactive area large enough to accommodate regions 62, 64, 66, and 68. Alternatively, regions 62, 64, 66, and/or 68 may be positioned inside the light-emitting active area to reduce the size of the non-light-emitting inactive area.

Figure 15 is a top view of an exemplary display having a fan-out signal line region in the active area of the display. As shown in Figure 15, the fan-out signal line region 62 at least partially overlaps the active area AA. The signal lines in the fan-out region 62 can be formed between and/or underneath the light-emitting diodes in the active area AA, as shown in more detail in Figure 16.

To increase the amount of fan-out signal line region 62 that can be shifted into the active area (thereby reducing the size requirements for the non-active area), pixel control circuits 20 can be positioned within the active area to maximize the gap between the edge of the active area and the pixel control circuits. As shown in FIG. 15, the row of pixel control circuits closest to the bottom edge of the active area (the edge adjacent to the display driver circuitry and therefore the fan-out signal line region) is positioned with a gap 70 between the pixel control circuit and the bottom edge of the active area. The gap 70 can include a full column of light-emitting diodes from the passive matrix controlled by the pixel control circuit. Consider the previous example in which each pixel control circuit controls four 8x8 passive matrices of light-emitting diodes. Thus, the gap 70 may be equal to the pitch of eight light-emitting diodes to ensure that eight rows of light-emitting diodes are located between the pixel control circuit and the bottom edge of the active area. This maximizes the space within the active area that can accommodate the fan-out signal line region 62, while still ensuring that the bottom row of pixel control circuits can fully control all of the light-emitting diodes along the bottom edge of the active area.

In addition to forming fan-out signal line region 62 at least partially within the active area, one or more peripheral signal lines (e.g., power lines) may be formed within regions 64, 66, and 68 within the active area. In FIG. 15, region 64 extends along the right edge of the active area (inside the active area), region 66 extends along the top edge of the active area (inside the active area), and region 68 extends along the left edge of the active area (inside the active area). The display may include any desired components, such as power lines, in these regions.

Additionally, one or more peripheral signal lines (e.g., power lines) may be formed inside the active area within the rounded corners of the display. FIG. 15 shows rounded corner regions 80-1, 80-2, 80-3, and 80-4. In FIG. 15, region 80-1 extends along the lower left corner of the active area (inside the active area) between regions 68 and 62, region 80-2 extends along the lower right corner of the active area (inside the active area) between regions 64 and 62, region 80-3 extends along the upper left corner of the active area (inside the active area) between regions 68 and 66, and region 80-4 extends along the upper right corner of the active area (inside the active area) between regions 66 and 64. The display may include any desired components, such as power lines, in these regions.

Figure 16 is a side cross-sectional view of an exemplary display having a fan-out signal line region 62 that at least partially overlaps the display active area. Figure 16 shows a pixel control circuit 20 implemented on a substrate 24. The pixel control circuit 20 can be attached to the substrate 24 using an adhesive layer, as an example. A common adhesive layer may attach multiple pixel control circuits to the substrate 24. Additional dielectric layers 72-0, 72-1, 72-2, 72-3, 72-4, 72-5, and 72-6 are formed on the substrate 24 and may optionally be referred to as substrate layers. Multiple metal layers, including metal layers M0, M1, M2, M3, and M4, are also formed on the substrate between the dielectric layers. Various vias 74 may be included to electrically connect different metal layers within the display.

Specifically, dielectric layer 72-0 is formed on substrate 24 (on the same plane as pixel control circuit 20). Dielectric layer 72-0 is sometimes referred to as a planarization layer. Metal layer M0 is formed on dielectric layer 72-0. Dielectric layer 72-1 is formed on metal layer M0. Metal layer M1 is formed on dielectric layer 72-1. Dielectric layer 72-2 is formed on metal layer M1. Metal layer M2 is formed on dielectric layer 72-2. Dielectric layer 72-3 is formed on metal layer M2. Metal layer M3 is formed on dielectric layer 72-3. Dielectric layer 72-4 is formed on metal layer M3. Metal layer M4 is formed on dielectric layer 72-4. Dielectric layer 72-5 is formed on metal layer M4.

In the active area AA, metal layer M4 may form anode contacts A for a passive matrix of light-emitting diodes controlled by pixel control circuitry 20. Light-emitting diodes 22 are formed between the anode contacts A and corresponding cathode contacts C. A planarization layer 72-6 may be formed on top of the cathode contacts C.

In the signal fan-out region 62, metal layers M0 and M1 may be patterned to form fan-out signal lines for transmitting power and analog signals. For example, metal layers M0 and M1 may include positive and negative power supply lines. In the signal fan-out region 62, metal layers M2 and M3 may be patterned to form global signal lines for the display. The global signal lines may be used, for example, to transmit clock signals to the pixel control circuits. In the signal fan-out region 62, metal layer M4 may be patterned to form data signal lines for the display. The data signal lines may be used to transmit display data used by the pixel control circuits to operate the light-emitting diodes at target brightness values (and thus display the target image). The signal lines formed using metal layer M4 may also be digital signal lines that transmit digital signals.

Metal layer M4 is used to form anode contact A within the active area. Therefore, metal layer M4 is patterned only to form fan-out lines outside of the light-emitting active area AA. Fan-out signal lines formed using metal layer M4 do not overlap the light-emitting active area. In contrast, metal layers M2 and M3 are patterned to form fan-out lines in both the active and inactive areas of the display. Similarly, metal layers M0 and M1 are patterned to form fan-out lines in both the active and inactive areas of the display.

The fan-out signal lines in region 62 may be electrically connected to additional signal lines in the active area of the display that carry signals throughout the display (e.g., to pixel control circuits). The fan-out signal lines may be electrically connected (and electrically connected using one or more vias) to signal lines patterned using the same metal layer as the fan-out region or to signal lines patterned using a different metal layer than the fan-out region.

17 is a top view of an exemplary display having peripheral signal lines formed inside the active area. As shown in FIG. 17, signal lines such as power supply line 76 may be formed along the edge of the active area inside the active area in region 64 between pixel control circuits 20 (e.g., the rightmost column of pixel control circuits extending in the Y direction) and the right edge of the active area. Additional signal lines such as global signal line 78 may be formed along the edge of the active area inside the active area in region 64. Pixel control circuits 20 (e.g., the rightmost column of pixel control circuits extending in the Y direction) are interposed between global signal line 78 and power supply line 76 in this example. In general, signal lines may be included at the edge of the active area in region 64, region 66, region 68, region 80-1, region 80-2, region 80-3, and/or region 80-4 (as shown in FIG. 17).

To maximize the amount of space along the left and right edges of the active area to accommodate signal lines, such as power lines, the array of pixel control circuits is centered relative to the left and right edges of the active area. This provides an equal amount of space on both the left and right edges of the active area to accommodate signal lines.

14 and 15 of the panel tail 24T (with corresponding fan-out signal line region 62) formed along the bottom edge of the display is merely illustrative. In general, the panel tail and display driver circuitry can be formed along any desired edge of the display. Regardless of the position of the display driver circuitry and panel tail, fan-out signal line regions may be included adjacent to the display driver circuitry and panel tail, and other edges of the display may include peripheral signal lines.

As previously shown in connection with Figures 7-9, the target boundary 42 may intersect some of the pixel cells 40, resulting in some pixel cells being partial pixel cells. Pixels outside the boundary 42 in pixel cell 40-2 may be omitted from the display. Additionally, pixel control circuits outside the target boundary may be omitted from the display. To mitigate these issues, additional pixel control circuits may be included to control the partial pixel cells (as in Figure 8), or the pixel driver circuit of an adjacent partial pixel cell may be used to drive the pixels of the partial pixel cell (as in Figure 9).

8 and/or 9, the first row of pixels may optionally be shifted relative to the first row of pixel control circuits, as desired. FIG. 18A is a top view of an exemplary display in which the first row of pixels in the display active area is aligned with the tops of the pixel cells controlled by the first row of pixel control circuits 20. The number of pixel rows at distance 102 in FIG. 18A is equal to half the total number of pixel rows in each cell 40.

Consider an example in which each pixel control circuit controls four 8x8 passive matrices, for a total of 16 rows and 16 columns of pixels. In this case, distance 102 in Figure 18A is 8 pixel rows. Therefore, the first row of pixel control circuits has no partial pixel cells outside the rounded corner area. The top of the control area of the first (top) row of pixel control circuits is aligned with the top row of pixels in the active area.

In contrast, in FIG. 18B, the first row of pixels in the display active area is not aligned with the top of the pixel cells controlled by the first row of pixel control circuits 20. The number of pixel rows at distance 104 in FIG. 18B is less than half the total number of pixel rows in each cell 40.

Consider an example in which each pixel control circuit controls four 8x8 passive matrices, for a total of 16 rows and 16 columns of pixels. In this case, distance 104 in Figure 18B is six rows (e.g., seven rows or less) of pixels. Thus, the first row of pixel control circuits has partial pixel cells in both the rounded corner area and the entire top edge of the active area (outside the rounded corner area). The top of the control area of the first row of pixel control circuits is shifted relative to the top row of pixels in the active area.

Adjusting the position of the active area relative to the pixel control circuitry (as in Figure 18B) can reduce the overall number of pixels (in the sub-pixel cells in the rounded corner areas) that require mapping (thus reducing the need for the solutions of Figures 8 and/or 9).

During manufacturing, the pixel control circuits may be transferred by mass transfer array (MTA) in multiple separate stamps to form the pixel control circuits for the entire display. Discrete stamps of pixel control circuits may be fabricated separately and then combined to form a single unitary array of pixel control circuits. In the example of FIG. 19, six different stamps (labeled 1, 2, 3, 4, 5, and 6) form the pixel control circuits for display 14. The size and overlap of each stamp may be selected to reduce the overall number of pixels requiring mapping (in partial pixel cells within rounded corner areas).

As shown in FIG. 19, a vertical offset 106 (e.g., for the top stamps 1 and 2) and/or a horizontal offset 108 (e.g., for the rightmost stamps 2, 4, and 6) can be used to optimize the number of pixels requiring mapping. This can result in the horizontal pitch 110 of the majority of pixel control circuits being less than the pitch 112 between pixel control circuits of different adjacent stamps (e.g., between stamps 1 and 2 in FIG. 19). Similarly, the total vertical pitch 114 of the majority of pixel control circuits can be less than the pitch 116 between pixel control circuits of different adjacent stamps (e.g., between stamps 1 and 3 in FIG. 19).

According to one embodiment, an electronic device is provided that includes a display driver circuit, an array of light-emitting diodes arranged in rows and columns, and an array of control circuits, each of the control circuits configured to control at least one passive matrix of the light-emitting diodes based on a signal from the display driver circuit, a first control circuit providing signals to a plurality of anode contacts, each anode contact of the plurality of anode contacts overlying a plurality of light-emitting diodes in a single individual column, a second control circuit providing signals to a first anode contact overlying at least one light-emitting diode in the first column, the first anode contact being electrically connected to a second anode contact overlying at least one light-emitting diode in a second column different from the first column.

In another embodiment, the array of control circuits is interspersed with an array of light-emitting diodes.

According to another embodiment, the first control circuit provides signals to a plurality of cathode contacts, each cathode contact of the plurality of cathode contacts overlapping a plurality of light-emitting diodes in a single individual row, the plurality of anode contacts and the plurality of anode contacts being orthogonal, and each light-emitting diode being positioned at a point of overlap between the plurality of anode contacts and the plurality of anode contacts.

According to another embodiment, a first control circuit controls a first passive matrix of light-emitting diodes arranged in a first number of rows and a second number of columns.

According to another embodiment, the first control circuit controls a second passive matrix of light-emitting diodes arranged in a third number of rows and a fourth number of columns, the third number being different from the first number.

According to another embodiment, the first control circuit controls a second passive matrix of light-emitting diodes arranged in a third number of rows and a fourth number of columns, the fourth number being different from the second number.

According to another embodiment, the second control circuit supplies a signal to a third anode contact overlying at least one light-emitting diode in a third column, the third anode contact being electrically connected to a fourth anode contact in a fourth column distinct from the third column.

According to another embodiment, the first and second anode contacts overlap a different number of light-emitting diodes.

According to another embodiment, the third and fourth anode contacts overlap a different number of light-emitting diodes.

According to another embodiment, the first anode contact is electrically connected to the second anode contact by an interconnect routing line that extends under at least a portion of the light emitting diodes in the array of light emitting diodes.

According to another embodiment, the third control circuit supplies a signal to a third anode contact overlying at least one light-emitting diode in the third column, the third anode contact being electrically connected to a fourth anode contact in a fourth column distinct from the third column, the second column and the fourth column being adjacent.

According to one embodiment, an electronic device is provided that includes a display driver circuit, an array of light-emitting diodes arranged in rows and columns in a light-emitting area, and an array of control circuits, each of the control circuits configured to control at least one passive matrix of the light-emitting diodes based on a signal from the display driver circuit, a first control circuit having a display driver portion configured to control pixel luminance values at a grid of locations including locations outside the light-emitting area, and an output circuit configured to set the pixel luminance values at the locations outside the light-emitting area to a zero gray level.

According to another embodiment, a passive matrix controlled by a first control circuit includes a plurality of anode contacts and a plurality of cathode contacts extending orthogonally to the plurality of cathode contacts, the plurality of anode contacts including first anode contacts overlapping a first number of light-emitting diodes and second anode contacts overlapping a second number of light-emitting diodes that is less than the first number.

According to another embodiment, the array of control circuits has a first row of control circuits, each control circuit in the first row of control circuits having an output configured to control pixel brightness values in a grid of locations that includes locations outside the light-emitting area, and a first of the rows within the light-emitting area is shifted relative to a top edge of the grid of locations for the first row of control circuits.

According to another embodiment, an array of control circuits is formed on a plurality of separate stamps, including first, second, and third stamps, wherein the first and second control circuits on the first stamp are separated by a first horizontal pitch, the third and fourth control circuits on the first and second stamps are each separated by a second horizontal pitch that is smaller than the first horizontal pitch, the fifth and sixth control circuits on the first stamp are separated by a first vertical pitch, and the seventh and eighth control circuits on the first and third stamps are each separated by a second vertical pitch that is smaller than the first vertical pitch.

According to one embodiment, an electronic device is provided that includes a display driver circuit; an array of light-emitting diodes arranged in a light-emitting area; an array of control circuits, each of the control circuits configured to control at least one passive matrix of light-emitting diodes based on a signal from the display driver circuit; and fan-out signal lines coupled to the display driver circuit and receiving signals from the display driver circuit, the fan-out signal lines at least partially overlapping the light-emitting area.

According to another embodiment, a fan-out signal line includes a first patterned metal layer, a second patterned metal layer formed on the first patterned metal layer, a third patterned metal layer formed on the second patterned metal layer, a fourth patterned metal layer formed on the third patterned metal layer, and a fifth patterned metal layer formed on the fourth patterned metal layer, wherein the fan-out signal line formed from the first and second patterned metal layers carries a power signal, and the fan-out signal line formed from the third and fourth patterned metal layers carries a power signal. The out signal lines carry global signals, the fan-out signal lines formed from the fifth patterned metal layer carry data signals, the fifth patterned metal layer has portions that form anode contacts for a passive matrix of light-emitting diodes, the fan-out signal lines formed from the first and second patterned metal layers at least partially overlap the light-emitting area, the fan-out signal lines formed from the third and fourth patterned metal layers at least partially overlap the light-emitting area, and the fan-out signal lines formed from the fifth patterned metal layer do not overlap the light-emitting area.

According to one embodiment, an electronic device is provided that includes a display driver circuit; an array of light emitting diodes having first and second opposing edges connected by third and fourth opposing edges; an array of control circuits arranged in rows and columns, each of the control circuits configured to control at least one passive matrix of light emitting diodes based on a signal from the display driver circuit; and fan-out signal lines coupled to the display driver circuit and receiving signals from the display driver circuit, the fan-out signal lines being formed between the row of control circuits and a first edge of the array of light emitting diodes.

According to another embodiment, each passive matrix includes a given number of rows of light-emitting diodes, the given number of rows of light-emitting diodes being interposed between a row of control circuits and a first edge of the array of light-emitting diodes.

According to one embodiment, an electronic device is provided that includes a display driver circuit; an array of light emitting diodes having first and second opposing edges connected by third and fourth opposing edges; and an array of control circuits arranged in rows and columns, each of the control circuits configured to control at least one passive matrix of the light emitting diodes based on a signal from the display driver circuit; the array of control circuits is centered relative to the third and fourth opposing edges and a power line extending along at least the third edge, the power line being overlaid by the array of light emitting diodes.

The above are merely exemplary, and various modifications may be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The above-described embodiments may be implemented individually or in any combination.

Claims (20)

a display driver circuit;
an array of light emitting diodes arranged in rows and columns;
an array of control circuits, each of the control circuits configured to control at least one passive matrix of the light emitting diodes based on a signal from the display driver circuit, a first control circuit providing signals to a plurality of anode contacts, each anode contact of the plurality of anode contacts overlying a plurality of light emitting diodes in a single individual column, a second control circuit providing signals to a first anode contact overlying at least one light emitting diode in a first column, the first anode contact being electrically connected to a second anode contact overlying at least one light emitting diode in a second column different from the first column;
An electronic device comprising: The electronic device of claim 1, wherein the array of control circuits is interspersed with the array of light-emitting diodes. 2. The electronic device of claim 1, wherein the first control circuit provides signals to a plurality of cathode contacts, each cathode contact of the plurality of cathode contacts overlapping a plurality of light emitting diodes in a single individual row, the plurality of anode contacts and the plurality of cathode contacts being orthogonal, and each light emitting diode being positioned at an overlap point between the plurality of anode contacts and the plurality of cathode contacts. The electronic device of claim 1, wherein the first control circuit controls a first passive matrix of light-emitting diodes arranged in a first number of rows and a second number of columns. The electronic device of claim 4, wherein the first control circuit controls a second passive matrix of light-emitting diodes arranged in a third number of rows and a fourth number of columns, the third number being different from the first number. The electronic device of claim 4, wherein the first control circuit controls a second passive matrix of light-emitting diodes arranged in a third number of rows and a fourth number of columns, the fourth number being different from the second number. The electronic device of claim 1, wherein the second control circuit supplies a signal to a third anode contact overlapping at least one light-emitting diode in a third column, and the third anode contact is electrically connected to a fourth anode contact in a fourth column different from the third column. The electronic device of claim 7, wherein the first and second anode contacts overlap different numbers of light-emitting diodes. The electronic device of claim 7, wherein the third and fourth anode contacts overlap different numbers of light-emitting diodes. The electronic device of claim 1, wherein the first anode contact is electrically connected to the second anode contact by an interconnect routing line that extends under at least some of the light emitting diodes in the array of light emitting diodes. The electronic device of claim 1, wherein a third control circuit supplies a signal to a third anode contact overlapping at least one light-emitting diode in a third column, the third anode contact being electrically connected to a fourth anode contact in a fourth column distinct from the third column, and the second column and the fourth column being adjacent to each other. a display driver circuit;
an array of light emitting diodes arranged in rows and columns within a light emitting area;
an array of control circuits, each of the control circuits configured to control at least one passive matrix of the light emitting diodes based on a signal from the display driver circuit, a first control circuit having an output configured to control pixel luminance values at a grid of locations including locations outside the light emitting area, the display driver circuit configured to set the pixel luminance values at the locations outside the light emitting area to a zero gray level;
An electronic device comprising: The electronic device of claim 12, wherein the passive matrix controlled by the first control circuit includes a plurality of anode contacts and a plurality of cathode contacts extending orthogonally to the plurality of cathode contacts, the plurality of anode contacts including a first anode contact overlapping a first number of light-emitting diodes and a second anode contact overlapping a second number of light-emitting diodes that is less than the first number. The electronic device of claim 12, wherein the array of control circuits includes a first row of control circuits, each control circuit in the first row of control circuits having an output configured to control pixel brightness values in a grid of locations that includes locations outside the light-emitting area, and a first one of the rows within the light-emitting area is shifted relative to a top edge of the grid of locations for the first row of control circuits. The electronic device of claim 12, wherein the array of control circuits is formed on a plurality of separate stamps, including first, second, and third stamps, wherein the first and second control circuits on the first stamp are separated by a first horizontal pitch, the third and fourth control circuits on the first and second stamps are each separated by a second horizontal pitch that is less than the first horizontal pitch, the fifth and sixth control circuits on the first stamp are separated by a first vertical pitch, and the seventh and eighth control circuits on the first and third stamps are each separated by a second vertical pitch that is less than the first vertical pitch. a display driver circuit;
an array of light emitting diodes disposed in a light emitting area;
an array of control circuits, each of the control circuits configured to control at least one passive matrix of the light emitting diodes based on a signal from the display driver circuit;
fan-out signal lines coupled to the display driver circuit and receiving the signals from the display driver circuit, the fan-out signal lines at least partially overlapping the light-emitting areas;
An electronic device comprising: The fan-out signal line includes a first patterned metal layer, a second patterned metal layer formed on the first patterned metal layer, a third patterned metal layer formed on the second patterned metal layer, a fourth patterned metal layer formed on the third patterned metal layer, and a fifth patterned metal layer formed on the fourth patterned metal layer, and the fan-out signal line formed from the first and second patterned metal layers transmits a power supply signal, and the fan-out signal line formed from the third and fourth patterned metal layers transmits a global signal, 17. The electronic device of claim 16, wherein fan-out signal lines formed from the fifth patterned metal layer carry data signals, the fifth patterned metal layer having portions that form anode contacts for the passive matrix of light-emitting diodes, the fan-out signal lines formed from the first and second patterned metal layers at least partially overlap the light-emitting area, the fan-out signal lines formed from the third and fourth patterned metal layers at least partially overlap the light-emitting area, and the fan-out signal lines formed from the fifth patterned metal layer do not overlap the light-emitting area. a display driver circuit;
an array of light emitting diodes having first and second opposing edges connected by third and fourth opposing edges;
an array of control circuits arranged in rows and columns, each of the control circuits configured to control at least one passive matrix of the light emitting diodes based on signals from the display driver circuit;
fan-out signal lines coupled to the display driver circuit and receiving the signals from the display driver circuit, the fan-out signal lines being formed between a row of control circuits and the first edge of the array of light emitting diodes;
An electronic device comprising: The electronic device of claim 18, wherein each passive matrix includes a given number of rows of light-emitting diodes, the given number of rows of light-emitting diodes being interposed between the row of control circuitry and the first edge of the array of light-emitting diodes. a display driver circuit;
an array of light emitting diodes having first and second opposing edges connected by third and fourth opposing edges;
an array of control circuits arranged in rows and columns, each of the control circuits configured to control at least one passive matrix of the light emitting diodes based on signals from the display driver circuit, the array of control circuits being centered relative to the third and fourth opposing edges;
a power line extending along at least the third edge, the power line being overlaid by the array of light emitting diodes;
An electronic device comprising: