JP7724190B2 - Semiconductor Devices - Google Patents

Description

This disclosure relates to semiconductor devices and is a technology that is effective when applied to semiconductor devices that have ESD (Electro-Static-Discharge) protection circuits.

As disclosed in JP 2020-161721 A, there is a semiconductor device in which a signal input to an input/output pad electrode from outside the semiconductor device is transferred to the internal circuitry via an input/output cell including an ESD protection element (also known as an ESD protection circuit) and an input logic circuit, and a level shift circuit. Also, as disclosed in WO 2016/203648 A, there is a semiconductor device in which input/output cells and power supply cells are arranged in an IO region located along the edge of the periphery of the semiconductor chip, and the internal circuitry is located in a central region surrounded by the IO region of the semiconductor chip.

Japanese Patent Application Laid-Open No. 2020-161721 International Publication No. 2016/203648

When testing a semiconductor device by applying an ESD surge, the level shifter circuit may be destroyed before the ESD protection circuit.

The objective of this disclosure is to provide technology that can ensure the desired ESD resistance without causing internal circuits such as level shifter circuits to break down before the ESD protection circuit does.

Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

A brief summary of the most representative aspects of this disclosure is as follows:

According to one embodiment of the present disclosure, a semiconductor device has input/output cells, IO power supply cells, core power supply cells, and a core logic circuit arranged on a chip, and the core power supply cells include an ESD protection circuit. The input/output cells include a level shifter circuit, which is arranged within the input/output cells. The core logic circuit is arranged outside the input/output cells. The core power supply cells are not arranged in the same row as the input/output cells, but are arranged in a third region between a first region in which the input/output cells and IO power supply cells are arranged and a second region in which the core logic circuit is arranged.

The semiconductor device according to the above embodiment can ensure the desired ESD resistance without causing internal circuits such as level shifter circuits to break down before the ESD protection circuit does.

FIG. 1 is a schematic block diagram of a semiconductor device according to a comparative example. FIG. 2 is a schematic layout diagram of the semiconductor device of FIG. FIG. 3 is a schematic block diagram of a semiconductor device according to an embodiment. FIG. 4 is a schematic layout diagram of the semiconductor device of FIG. FIG. 5 is a schematic plan view of a semiconductor chip on which the semiconductor device of FIG. 3 is formed.

The following describes embodiments and examples using the drawings. However, in the following description, identical components are designated by the same reference numerals, and repeated explanations may be omitted. Furthermore, to clarify the description, the drawings may be more schematic than the actual embodiment, but they are merely examples and do not limit the interpretation of the present invention.

(Embodiment)
Before describing embodiments and examples of the present disclosure, in order to facilitate understanding of the present disclosure, a semiconductor device according to a technique (hereinafter referred to as a comparative example) studied by the present inventors will be described with reference to Figures 1 and 2. Figure 1 is a schematic block diagram of the semiconductor device according to the comparative example. Figure 2 is a schematic layout diagram of the semiconductor device of Figure 1.

The semiconductor device 10S includes input/output cells (IOC) 11, first power supply cells (IO power cells IOPC) 12 (IO power cells 12A and 12B), and second power supply cells (core power cells CPC) 13 (core power cells 13A and 13B) on the periphery of a rectangular semiconductor chip such as single-crystal silicon. The area where the input/output cells 11 and power supply cells 12 and 13 are arranged is called the IO area. The IO area is arranged along the four edges of the semiconductor chip in a plan view. The semiconductor device 10S also includes an internal circuit 14 serving as a core logic circuit (CORE-LOG). The core logic area where the internal circuit 14 is arranged is the central part of the semiconductor chip and is surrounded by the IO area.

The input/output cell 11 is a formation region of an input/output circuit connected to one input/output pad. The power supply cells 12 and 13 are formation regions of ESD protection circuits (CESD, ESD) that protect the semiconductor device from ESD (Electro-Static-Discharge) and noise, and wiring that supplies a power supply potential (VDDIO, VDD) or a ground potential (VSSIO, VSS) to the inside of the chip.
Since it is necessary to uniformly reduce the power supply impedance, the power supply cells 12 and 13 are arranged in a dispersed manner for each of the plurality of input/output cells 11, and are arranged adjacent to and between the input/output cells 11.

The power supply potentials (VDDIO, VDD) include a first power supply potential VDDIO of the I/O cells 11 and a second power supply potential VDD of the internal circuit 14. Similarly, the ground potentials (VSSIO, VSS) include a first ground potential VSSIO of the I/O cells 11 and a second ground potential VSS of the internal circuit 14. The first power supply potential VDDIO can be a potential greater than the second power supply potential VDD (VDDIO > VDD). The first power supply potential VDDIO, first ground potential VSSIO, second power supply potential VDD, and second ground potential VSS are supplied to the I/O cells 11 via power supply wiring. The second power supply potential VDD and second ground potential VSS are supplied to the internal circuit 14 via power supply wiring.

The IO power cell 12A includes an ESD protection circuit (ESD) and a bridge circuit 15, and supplies a first power supply potential VDDIO to the power supply wiring. The IO power cell 12B includes an ESD protection circuit (ESD) and a bridge circuit 15, and supplies a first ground potential VSSIO to the power supply wiring (also called ground wiring).

The core power cell 13A includes an ESD protection circuit (CESD) and a bridge circuit 15, and supplies a second power supply potential VDD to the power supply wiring. The core power cell 13B includes an ESD protection circuit (CESD) and a bridge circuit 15, and supplies a second ground potential VSS to the power supply wiring (also called ground wiring).

The ESD protection circuit (ESD) is connected between a power supply wiring supplied with a first power supply potential VDDIO and a power supply wiring supplied with a first ground potential VSSIO. The ESD protection circuit (CESD) is connected between a power supply wiring supplied with a second power supply potential VDD and a power supply wiring supplied with a second ground potential VSS.

The bridge circuit 15 is connected between a power supply wiring supplied with a first ground potential VSSIO and a power supply wiring supplied with a second ground potential VSS, and includes a pair of bidirectional diodes connecting the power supply wiring supplied with the first ground potential VSSIO and the power supply wiring supplied with the second ground potential VSS. The anode of one diode is connected to the power supply wiring supplied with the first ground potential VSSIO, and the cathode is connected to the power supply wiring supplied with the second ground potential VSS. The anode of the other diode is connected to the power supply wiring supplied with the second ground potential VSS, and the cathode is connected to the power supply wiring supplied with the first ground potential VSSIO.

The input/output cell 11 incorporates an input/output circuit that is connected to an input/output terminal (TIO). The input/output terminal TIO, power supply terminals TVDD and TVDDIO, and ground terminals TVSS and TVSSIO are located on the input/output cell 11, IO power supply cell 12, and core power supply cell 13, respectively, but may also be located away from the input/output cell 11, IO power supply cell 12, and core power supply cell 13, respectively. The input/output terminal TIO, power supply terminals TVDD and TVDDIO, and ground terminals TVSS and TVSSIO are connected to bonding wires, etc., and are also referred to as input/output pads, power supply pads, and ground pads, respectively.

The input/output circuit constituting the input/output cell 11 includes diodes D1 and D2 constituting an ESD protection circuit; an output circuit including a P-channel transistor Q1 and an N-channel transistor Q2 that transmits an output signal to the signal wiring connected to the input/output terminal TIO; an input/output logic circuit IOL including a CMOS inverter that receives an input signal input from the input/output terminal TIO via the signal wiring; and a level shifter circuit LSC. The input signal input from the input/output terminal TIO via the signal wiring is input to the level shifter circuit LSC via the input/output logic circuit IOL, where it is level-converted and supplied to the internal circuit 14. Meanwhile, the signal output from the internal circuit 14 is input to the level shifter circuit LSC, where it is level-converted and supplied to the input/output logic circuit IOL, and output as an output signal from the output circuit including the P-channel transistor Q1 and N-channel transistor Q2 to the input/output terminal TIO.

P-channel transistor Q1 is connected between the power supply wiring for the first power supply potential VDDIO and the signal wiring from input/output terminal TIO, and N-channel transistor Q2 is connected between the signal wiring and the ground wiring for the first ground potential VSSIO. Diode D1 has an anode connected to the signal wiring from input/output terminal TIO and a cathode connected to the power supply wiring for the first power supply potential VDDIO. Diode D2 has an anode connected to the ground wiring for the first ground potential VSSIO and a cathode connected to the signal wiring from input/output terminal TIO. Diode D1 conducts surge current from input/output terminal TIO through the signal wiring and the power supply wiring for the first power supply potential VDDIO toward power supply terminal VDDIO, while diode D2 conducts surge current from ground terminal TVDDIO through the ground wiring for the first ground potential VSSIO and the signal wiring toward input/output terminal TIO. The output circuit may be a so-called open-drain type that does not have P-channel transistor Q1. Additionally, the input/output circuit does not necessarily have to include either the output circuit or the input circuit.

Power supply cells 12A and 13A are equipped with ESD protection circuits (CESD, ESD) corresponding to the power supply terminals (TVDDIO, TVDD), and power supply cells 12B and 13B are equipped with ESD protection circuits (CESD, ESD) corresponding to the ground terminals (TVSSIO, TVSS).

The first power supply potential VDDIO is, for example, 1.8 V (or 3.3 V), and the second power supply potential VDD is, for example, 0.8 V.

When the first power supply potential VDDIO is 1.8 V and the second power supply potential VDD is 0.8 V,
1) The transistors Q1 and Q2 of the output circuit and the input/output logic circuit IOL are composed only of MOSFETs having a breakdown voltage of 1.8 V (also called 1.8 V-MOS).
2) The internal circuit 14 is composed only of MOSFETs (also called core MOS) having a breakdown voltage of 0.8V.
3) The level shifter circuit LSC is configured by mixing 1.8V-MOS and core MOS.
4) The core power supply cells 13A and 13B protect the core MOS of the internal circuit 14 and the core MOS of the level shifter circuit LSC.
5) The IO power supply cells 12A and 12B protect the transistors Q1 and Q2 of the output circuit and the 1.8V-MOS of the input/output logic circuit IOL.

Figure 2 shows the layout relationship between IO power supply cells 12A, 12B, two input/output cells 11, and core power supply cells 13A, 13B arranged in the IO region, and internal circuit 14 arranged in the core logic region. In Figure 2, MOS transistors T1 and T2 represent transistors that make up the ESD protection circuit (CESD), and MOS transistors T3 and T4 represent transistors that make up the ESD protection circuit (ESD). As shown in Figure 2, IO power supply cells 12A, 12B, two input/output cells 11, and core power supply cells 13A, 13B are arranged in this order in the IO region, and internal circuit 14 is arranged adjacent to the IO region above the IO region.

In response to an ESD surge between the power supply terminal TVDD and the ground terminal TVSS in Figure 1, an ESD current flows, as indicated by the ESD current Iesd. This makes the level shifter circuit LSC, which is relatively smaller than the core logic circuit (internal circuit 14), more susceptible to damage. This is because the resistance of the wiring in the portion indicated by R within the core power supply cells (13A, 13B) deteriorates.

In the 7 nm generation, due to the effects of reduced core MOS resistance and increased wiring resistance within the core power cells (13A, 13B), the level shifter circuit LSC breaks down before the ESD protection circuit (CESD) when using the cell layout method shown in Figure 2. This posed the challenge of not being able to achieve the ESD resistance level (Human Body Model (HBM): 2 kV) required for automotive products.

The semiconductor device 10 of the present disclosure is a semiconductor device in which input/output cells 11, IO power supply cells 12 (12A, 12B), core power supply cells 13 (13A, 13B), and a core logic circuit 14 are arranged on a semiconductor chip (101). The core power supply cells 13 (13A, 13B) include an ESD protection circuit (CESD).

The input/output cell 11 includes a level shifter circuit LSC, and the level shifter circuit LSC is arranged within the input/output cell 11.

The core logic circuit 14 is located outside the input/output cell 11.

The core power supply cells 13 (13A, 13B)
It is not arranged in the same row as the input/output cell 11,
The input/output cells 11 and the IO power supply cells 12 (12A, 12B) are arranged in a third region (13R) between a first region (IO region IOR) and a second region (central region CER) of the core logic circuit 14.

The core power supply cells 13 (13A, 13B) are
The long side B2 of the external dimensions is formed to be shorter than the long side B1 of the external dimensions of the IO power supply cells 12 (12A, 12B) (B2<B1),
The short side A2 of the external dimension is equal to or greater than the short side A1 of the external dimension of the IO power supply cells 12 (12A, 12B) (A2≧A1).

The core power supply cells 13 (13A, 13B) are
It is not placed between the input/output cell 11 and the core logic circuit 14,
The power supply cells 12A and 12B are arranged in the fourth region (13RR) between the IO power supply cells 12A and 12B and the core logic circuit 14.

As a result, the semiconductor device described above can ensure the desired ESD resistance without causing internal circuits such as the level shifter circuit LSC to break down before the ESD protection circuit (CESD) does.

In cutting-edge 7nm generation CMOS technology, this technology ensures the desired ESD resistance without damaging vulnerable internal circuits (e.g., level shifter circuits LSC) before the protection circuits do. In particular, it reliably achieves the HBM 2kV required for automotive semiconductor products.

Next, a semiconductor device 10 according to an embodiment will be described using Figures 3 to 5. Figure 3 is a schematic block diagram of a semiconductor device according to an embodiment. Figure 4 is a schematic layout diagram of the semiconductor device of Figure 3. Figure 5 is a schematic plan view of a semiconductor chip on which the semiconductor device of Figure 3 is formed. In Figure 5, the layout diagram of the area enclosed by the dotted line indicated by V is shown.

As shown in FIG. 5, the semiconductor device 10 includes input/output cells (IOC) 11, first power supply cells (IO power cells IOPC) 12 (IO power cells 12A and 12B), and second power supply cells (core power cells CPC) 13 (core power cells 13A and 13B) on the periphery of a rectangular semiconductor chip 101 made of, for example, single-crystal silicon. The area in which the input/output cells 11 and power supply cells 12 are arranged is called the IO area IOR. The IO area IOR is arranged along four edges 21, 22, 23, and 24 of the chip edge of the semiconductor chip 101 in a plan view. The four edges 21, 22, 23, and 24 include a first edge 21, a third edge 23 facing the first edge 21, a second edge 22 between the first edge 21 and the third edge 23, and a fourth edge 24 facing the second edge 22.

The semiconductor device 10 also includes an internal circuit 14 serving as a core logic circuit (CORE-LOG). The core logic region (also referred to as the central region or second region) CER in which the internal circuit 14 is arranged is provided in the central portion of the semiconductor chip 101. Second power supply cells (core power supply cells CPC) 13 (core power supply cells 13A and 13B) are arranged in the region (also referred to as the third region) 13R between the core logic region CER and the IO region IOR.

Figure 3 shows a schematic block diagram of a semiconductor device 10 according to an embodiment. The semiconductor device 10 in Figure 3 differs from the semiconductor device 10S in Figure 1 in that the core power supply cells 13A and 13B are not provided within the array of input/output cells (IOC) 11 and first power supply cells (IO power cells IOPC) 12, but are provided on the internal circuit 14 side. Also, in this example, the core power supply cells 13A and 13B do not have a bridge circuit 15.

The other configurations and functions of Figure 3 are the same as those of Figure 1, so duplicate explanations will be omitted. In other words, the explanation of Figure 1 can be used and referred to for explanations of the circuit configuration, operation, and connections of the input/output cell 11, IO power supply cell 12A, IO power supply cell 12B, core power supply cell 13A, and core power supply cell 13B.

As shown in Figures 3 and 4, the semiconductor device 10 is provided with an input/output terminal TIO, a first power supply terminal TVDDIO, a second power supply terminal TVDD, a first ground terminal TVSSIO, and a second ground terminal TVSS. A first power supply potential VDDIO is supplied to the first power supply terminal TVDDIO. A second power supply potential VDD is supplied to the second power supply terminal TVDD. A first ground potential VSSIO is supplied to the first ground terminal TVSSIO. A second ground potential VSS is supplied to the second ground terminal TVSS.

In the IO region IOR, a first power supply wiring 31, a second power supply wiring (also referred to as first ground wiring) 32, a third power supply wiring 33, and a fourth power supply wiring (also referred to as second ground wiring) 34 are arranged along the first direction X. The first power supply wiring 31 is supplied with a first power supply potential VDDIO from a first power supply terminal TVDDIO. The second power supply wiring (first ground wiring) 32 is supplied with a first ground potential VSSIO from a first ground terminal TVSSIO. The third power supply wiring 33 is supplied with a second power supply potential VDD from a second power supply terminal TVDD. The fourth power supply wiring (second ground wiring) 34 is supplied with a second ground potential VSS from a second ground terminal TVSS.

The core logic region CER is provided with fifth power supply wiring 35 and sixth power supply wiring 36 arranged along the first direction X, and seventh power supply wiring 37 and eighth power supply wiring 38 arranged along a second direction Y intersecting the first direction X. The fifth power supply wiring 35 is connected to the second power supply terminal TVDD, and the sixth power supply wiring 36 is connected to the second ground terminal TVSS. The fifth power supply wiring 35 and the seventh power supply wiring 37 are electrically connected, and the second power supply potential VDD is supplied from the second power supply terminal TVDD. The sixth power supply wiring 36 and the eighth power supply wiring 38 are electrically connected, and the second ground potential VSS is supplied from the second ground terminal TVSS.

The seventh power supply wiring 37 and the eighth power supply wiring 38 are also arranged in region 13R and connected to the third power supply wiring 33 and the fourth power supply wiring 34 provided in the IO region IOR. The core power supply cells 13A and 13B are connected between the seventh power supply wiring 37 and the eighth power supply wiring 38 arranged in region 13R.

The input/output cells 11 are supplied with a first power supply potential VDDIO, a first ground potential VSSIO, a second power supply potential VDD, and a second ground potential VSS. The internal circuit 14 is supplied with a second power supply potential VDD and a second ground potential VSS.

IO power cell 12A includes an ESD protection circuit (ESD) with transistor T1 and a bridge circuit 15, and supplies a first power supply potential VDDIO to power supply wiring 31. IO power cell 12B includes an ESD protection circuit (ESD) with transistor T2 and a bridge circuit 15, and supplies a first ground potential VSSIO to power supply wiring 32.

The ESD protection circuit (ESD) is connected between a power supply wiring 31 supplied with a first power supply potential VDDIO and a power supply wiring 32 supplied with a first ground potential VSSIO.

The bridge circuit 15 is connected between the power supply wiring 32 supplied with the first ground potential VSSIO and the power supply wiring 34 supplied with the second ground potential VSS, and includes a pair of bidirectional diodes connecting the power supply wiring 32 supplied with the first ground potential VSSIO to the power supply wiring 34 supplied with the second ground potential VSS. The anode of one diode is connected to the power supply wiring 32 supplied with the first ground potential VSSIO, and the cathode is connected to the power supply wiring 34 supplied with the second ground potential VSS. The anode of the other diode is connected to the power supply wiring 34 supplied with the second ground potential VSS, and the cathode is connected to the power supply wiring 32 supplied with the first ground potential VSSIO.

The core power cell 13A includes an ESD protection circuit (CESD) with transistor T3, and the core power cell 13B includes an ESD protection circuit (CESD) with transistor T4. The core power cell 13A and the core power cell 13B protect the internal circuit 14 from ESD and noise. The source-drain paths of transistors T3 and T4 are connected between the seventh power wiring 37 and the eighth power wiring 38 arranged in region 13R.

The input/output cell 11 incorporates an input/output circuit that is connected to an input/output terminal (TIO). The input/output terminal TIO, power supply terminals TVDD and TVDDIO, and ground terminals TVSS and TVSSIO are located on the input/output cell 11, IO power supply cell 12, and core power supply cell 13, respectively, but may also be located away from the input/output cell 11, IO power supply cell 12, and core power supply cell 13, respectively. The input/output terminal TIO, power supply terminals TVDD and TVDDIO, and ground terminals TVSS and TVSSIO are connected to bonding wires, etc., and are also referred to as input/output pads, power supply pads, and ground pads, respectively.

The input/output circuit constituting the input/output cell 11 includes diodes D1 and D2 constituting an ESD protection circuit; an output circuit including a P-channel transistor Q1 and an N-channel transistor Q2 that transmits an output signal to the signal wiring connected to the input/output terminal TIO; an input/output logic circuit IOL including a CMOS inverter that receives an input signal input from the input/output terminal TIO via the signal wiring; and a level shifter circuit LSC. The input signal input from the input/output terminal TIO via the signal wiring is input to the level shifter circuit LSC via the input/output logic circuit IOL, where it is level-converted and supplied to the internal circuit 14. Meanwhile, the signal output from the internal circuit 14 is input to the level shifter circuit LSC, where it is level-converted and supplied to the input/output logic circuit IOL, and output as an output signal from the output circuit including the P-channel transistor Q1 and N-channel transistor Q2 to the input/output terminal TIO.

P-channel transistor Q1 is connected between power supply wiring 31 of the first power supply potential VDDIO and the signal wiring from input/output terminal TIO, and N-channel transistor Q2 is connected between the signal wiring and ground wiring 32 of the first ground potential VSSIO. The anode of diode D1 is connected to the signal wiring from input/output terminal TIO, and the cathode is connected to power supply wiring 31 of the first power supply potential VDDIO. The anode of diode D2 is connected to ground wiring 32 of the first ground potential VSSIO, and the cathode is connected to the signal wiring from input/output terminal TIO. Diode D1 flows a surge current from input/output terminal TIO through the signal wiring and power supply wiring 31 of the first power supply potential VDDIO toward power supply terminal VDDIO, and diode D2 flows a surge current from ground terminal TVDDIO through ground wiring 32 of the first ground potential VSSIO and the signal wiring toward input/output terminal TIO. The output circuit may be a so-called open-drain type that does not have a P-channel transistor Q1. Also, the input/output circuit may not have either the output circuit or the input circuit.

In FIG. 3, the internal circuit 14, core power supply cell 13A, and core power supply cell 13B are connected between power supply wiring (35, 37, see FIG. 4) to which the second power supply potential VDD is supplied from the power supply terminal TVDD and ground wiring (36, 38, see FIG. 4) to which the second ground potential VSS is supplied from the ground terminal TVSS. As shown in FIG. 3, by not arranging the core power supply cell 13A and the core power supply cell 13B in the same row as the input/output cell 11, an increase in intra-cell wiring resistance can be avoided.

As shown in FIG. 4, input/output cell 11, IO power supply cell 12A, and IO power supply cell 12B are arranged in IO region IOR. In this example, IO power supply cell 12A and IO power supply cell 12B are arranged on both sides of input/output cell 11. Internal circuit 14 is arranged in core logic region CER. Core power supply cell 13A and core power supply cell 13B are arranged in region 13R between core logic region CER and IO region IOR. Core power supply cell 13A and core power supply cell 13B are also arranged in region 13RR (also called the fourth region) between core logic region CER and IO power supply cells 12A and 12B.

The power supply terminal TVDD is connected to a power supply wiring 35 of the second power supply potential VDD arranged in the internal circuit 14. The ground terminal TVSS is configured to be connected to a ground wiring 36 of the second ground potential VSS arranged in the internal circuit 14.

Here, we will explain the features of the example layout configuration shown in Figure 4.

The long side B2 of the outer shape of the core power cell 13 (13A, 13B) can be the side of the core power cell 13 (13A, 13B) that runs along the direction of the source-drain paths (or gate length direction) of transistors T3 and T4 of the core power cell 13 (13A, 13B). The short side A2 of the outer shape of the core power cell 13 (13A, 13B) can be the side of the core power cell 13 (13A, 13B) that runs along the direction (or gate width direction) that is perpendicular to the direction of the source-drain paths of transistors T3 and T4 of the core power cell 13 (13A, 13B).

Furthermore, the long side B1 of the outer shape of the IO power cell 12 (12A, 12B) can be the side of the IO power cell 12 (12A, 12B) that runs along the direction of the source-drain paths (or gate length direction) of the transistors T1, T2 of the IO power cell 12 (12A, 12B). The short side A1 of the outer shape of the IO power cell 12 (12A, 12B) can be the side of the IO power cell 12 (12A, 12B) that runs along the direction (or gate width direction) perpendicular to the direction of the source-drain paths of the transistors T1, T2 of the IO power cell 12 (12A, 12B).

1) To avoid an increase in wiring resistance within the core power cells 13 (13A, 13B), the core power cells 13 (13A, 13B) are not placed in the same row as the input/output cells 11, but are placed in the region (fourth region) 13RR between the formation region of the IO power cells 12 (12A, 12B) and the formation region of the internal circuit 14.

2) The long side B2 of the core power cells 13 (13A, 13B) is smaller than the long side B1 of the IO power cells 12 (12A, 12B) (B2<B1).

3) The short side A2 of the core power cell (13A, 13B) is equal to or greater than the short side A1 of the IO power cell 12 (12A, 12B) (A2 ≧ A1).

4) Core power supply cells 13 (13A, 13B) are not placed between the input/output cells 11 and the internal circuit 14. This improves the layout flexibility of the signal wiring SL between the level shifter circuit LSC and the internal circuit 14.

The semiconductor device of the embodiment can ensure the desired ESD resistance without damaging vulnerable internal circuits (e.g., level shifter circuits LSC) before the ESD protection circuit (CESD) does due to electrostatic stress. In particular, it can reliably achieve the HBM 2kV required for automotive semiconductor products.

The disclosure made by the present inventor has been specifically described above based on embodiments and examples, but it goes without saying that the present disclosure is not limited to the above embodiments and examples and can be modified in various ways.

10: Semiconductor device 11: Input/output cell 12, 12A, 12B: IO power supply cell 13, 13A, 13B: Core power supply cell 14: Internal circuit IOR: IO region (first region)
CER: Core logic region (central region, second region)
13R: Third area 13RR: Fourth area ESD, CESD: ESD protection circuit

Claims (2)

A semiconductor device in which input/output cells, IO power supply cells, core power supply cells, and a core logic circuit are arranged on a chip,
the core power cell includes an ESD protection circuit;
the input/output cell includes a level shifter circuit, the level shifter circuit being disposed within the input/output cell;
the core logic circuit is arranged outside the input/output cell;
The core power cell includes:
are not arranged in the same row as the input/output cells,
the third region is disposed between a first region in which the input/output cells and the IO power supply cells are disposed and a second region in which the core logic circuit is disposed;
The core power cell includes:
not disposed between the input/output cell and the core logic circuit,
and disposing the power supply cells in a fourth region between the IO power supply cells and the core logic circuit.
Semiconductor device. 2. The semiconductor device of claim 1,
The core power cell includes:
The long side of the external dimension of the power supply cell for I/O is shorter than the long side of the external dimension of the power supply cell for I/O,
The short side of the external dimension of the semiconductor device is equal to or greater than the short side of the external dimension of the IO power supply cell.