JP7718491B2 - METHOD FOR MANUFACTURING ELECTRONIC COMPONENT DEVICE AND ELECTRONIC COMPONENT DEVICE - Google Patents

Description

The present disclosure relates to a method for manufacturing an electronic component device and an electronic component device.

In semiconductor packages containing high-frequency electronic components, the provision of a compartment shield surrounding the electronic components is being considered for electromagnetic wave shielding.

Methods proposed for forming compartment shields include a method using photoresist and a method using laser processing. Methods using photoresist typically involve forming a pattern with openings by exposing and developing a resist layer provided on a substrate, forming a conductive layer that fills the openings, peeling off the resist layer, placing electronic components such as chip components on the substrate, and forming an encapsulating resin layer that encapsulates the electronic components and the conductive layer. Laser processing methods involve forming an encapsulating resin layer that encapsulates the chip components, forming via holes by laser processing the encapsulating resin layer, and forming conductive vias that fill the via holes.

US Patent Application Publication No. 2014/0252646 International Publication No. 2020/179874

One aspect of the present disclosure relates to a method for efficiently and easily manufacturing electronic component devices having conductive vias that penetrate an encapsulating resin layer and function as compartment shields using a small number of steps.

One aspect of the present disclosure relates to a method for manufacturing an electronic component device, including: providing, on a substrate, an encapsulating structure having one or more electronic components disposed on a main surface of the substrate and a curable encapsulating resin layer encapsulating the electronic components; forming a plurality of via holes extending in a thickness direction of the encapsulating resin layer by an imprinting method including pressing a mold into the encapsulating resin layer from the side opposite the substrate; curing the encapsulating resin layer; and forming a plurality of conductive vias filling each of the via holes. One or more of the electronic components are disposed within one or more mounting regions on the main surface of the substrate. Some or all of the plurality of via holes are spaced apart from one another to form one or more rows. The mounting region is an area surrounded by the one or more rows.

Another aspect of the present disclosure relates to an electronic component device comprising a wiring structure, one or more electronic components mounted on a main surface of the wiring structure, an encapsulating resin layer that encapsulates the electronic components, and a plurality of conductive vias penetrating the encapsulating resin layer. The one or more electronic components are disposed within one or more mounting regions on the main surface of the wiring structure. Some or all of the plurality of conductive vias are spaced apart to form two or more rows, and the one or more mounting regions are regions surrounded by two or more rows that extend along the periphery of each of the mounting regions and do not intersect with each other. The two or more rows that extend along the periphery of each of the one or more mounting regions and do not intersect with each other may include a plurality of the conductive vias arranged in a staggered arrangement.

According to one aspect of the present disclosure, an electronic component device having conductive vias that penetrate an encapsulating resin layer and function as a compartment shield can be manufactured efficiently and easily with a small number of steps.

1A to 1C are process diagrams illustrating an example of a method for manufacturing an electronic component device. 1A to 1C are process diagrams illustrating an example of a method for manufacturing an electronic component device. 1A to 1C are process diagrams illustrating an example of a method for manufacturing an electronic component device. FIG. 1 is a plan view showing an example of an electronic component device. FIG. 1 is a plan view showing an example of an electronic component device.

The present invention is not limited to the following examples.

1, 2, and 3 are process diagrams illustrating an example of a method for manufacturing an electronic component device. The method illustrated in FIGS. 1 to 3 includes arranging chip components 2 and chip-type passive components 3, which are electronic components, on the main surface 1S of a flat substrate 1; forming a curable encapsulating resin layer 7 that encapsulates the electronic components (chip components 2 and passive components 3), thereby providing an encapsulating structure 20 on the substrate 1, including the electronic components (chip components 2 and passive components 3) and the encapsulating resin layer 7; forming multiple via holes 15 extending in the thickness direction of the encapsulating resin layer 7 using an imprinting method that includes pressing a mold 10 into the encapsulating resin layer 7 from the side opposite the substrate 1; curing the encapsulating resin layer 7; forming multiple conductive vias 5a, 5b that fill each of the multiple via holes 15; and forming a conductive shielding film 8 that covers the encapsulating resin layer 7 and is connected to the tips of the conductive vias 5a, 5b.

Electronic components (chip components 2 and passive components 3) are arranged in one or more mounting areas 1A on the main surface 1S of the substrate 1. Some or all of the multiple via holes 15 are arranged at intervals to form one or more rows. The mounting area 1A is an area surrounded by the rows of via holes 15. The via holes 15 are arranged at positions corresponding to the conductive vias 5a and 5b to be formed.

The sealing resin layer 7 at the stage where the via holes 15 are formed by the imprinting method may be uncured, or may be semi-cured to the extent that it retains the fluidity necessary to form the via holes 15. In other words, the sealing resin layer 7 into which the mold 10 is pressed may be in a B-stage state.

The thickness of the encapsulating resin layer 7 is typically greater than the height of the electronic components (chip components 2 and passive components 3). The thickness of the encapsulating resin layer 7 may be, for example, 30 to 3000 μm, or 300 to 3000 μm. The thickness of the encapsulating resin layer 7 is typically substantially the same as the depth of the via hole 15.

The encapsulating resin layer 7 can be formed using an encapsulating material that is commonly used to encapsulate electronic components. For example, a film-like encapsulating material may be laminated on the substrate 1 as the encapsulating resin layer 7. To reduce the entrapment of air bubbles, the encapsulating material may be laminated using a vacuum laminator. Typically, the electronic components (chip components 2, passive components 3) are placed on the substrate 1 in advance, and the encapsulating resin layer 7 is formed to cover the electronic components on the substrate 1.

In the imprinting method, a mold 10 is used that has multiple columnar protrusions 10A that have a shape corresponding to the via holes 15 (Figure 2(c)). The protrusions 10A of the mold 10 have tip surfaces that are substantially perpendicular to their height direction. The mold 10 is not particularly limited, but can be made of, for example, silicon or metal. A flip-chip bonder may be used to press the mold 10 into the encapsulating resin layer 7. An example of a commercially available flip-chip bonder that can be used for the imprinting method is the FC3000W manufactured by Toray Engineering Co., Ltd.

The protrusions of the mold 10 may be pressed into the sealing resin layer 7 while the mold 10, the sealing resin layer 7, or both are heated to a predetermined temperature (mold temperature). At this time, a predetermined load is applied to the mold 10 being pressed into the sealing resin layer 7 in the thickness direction of the sealing resin layer 7. The mold temperature and load for the imprinting method are set so that a via hole 15 of the desired depth is formed.

The molding temperature may be, for example, 55 to 110°C. If the encapsulating material used to form the encapsulating resin layer 7 exhibits a relatively low melt viscosity at the molding temperature, via holes with a large depth-to-width ratio can be particularly easily formed. Specifically, the encapsulating material may exhibit a melt viscosity of 20,000 Pa·s or less, 15,000 Pa·s or less, 12,000 Pa·s or less, 3,000 Pa·s or less, 2,500 Pa·s or less, 2,000 Pa·s or less, 1,500 Pa·s or less, 1,400 Pa·s or less, 1,300 Pa·s or less, or 1,200 Pa·s or less at some or all of the temperatures in the 55 to 110°C range or at the molding temperature. The minimum melt viscosity of the encapsulating material in the 55 to 110°C range may be, for example, 100 Pa·s. The melt viscosity here means the complex viscosity measured under the conditions of a frequency of 0.5 Hz, a temperature rise rate of 10° C./min, and a shear mode.

It is not necessary for the tip surface of the mold 15 to reach the substrate 1 and for a via hole 15 to be formed that penetrates the sealing resin layer 7; a portion of the sealing resin layer 7 may remain at the bottom of the via hole 15. The sealing resin layer remaining at the bottom of the via hole 15 may be removed by methods such as wet etching, dry etching, or polishing.

The maximum width of the via hole 15 (or the maximum width of the conductive vias 5a, 5b) may be 10 to 2000 μm. The ratio of the depth of the via hole 15 to its maximum width (hereinafter referred to as the "aspect ratio") may be 1 or greater, or 2 or greater, or 10 or less. The imprint method makes it easy to simultaneously form multiple via holes 15 with large aspect ratios. The conductive vias 5a, 5b also typically have an aspect ratio similar to that of the via hole 15.

After the via holes 15 are formed, the encapsulating resin layer 7 may be cured. Curing is typically performed by thermal curing. Then, conductive vias 5a, 5b are formed to fill the via holes 15 (see (e) of Figure 3). The conductive vias 5a, 5b are arranged on the substrate 1 at intervals so as to form rows. A group 50 of conductive vias including the conductive vias 5a, 5b and surrounding the electronic components (chip components 2 and passive components 3) can function as a compartment shield. Further conductive vias that do not form a row surrounding the electronic components may be provided on the substrate 1.

The conductive vias 5a, 5b are formed, for example, by a method that includes filling the via holes 15 with a conductive precursor and heating the conductive precursor filled in the via holes 15 to form the conductive vias 5a, 5b. In this case, the sealing resin layer 7 may be cured after the conductive precursor is filled in the via holes 15. The method for filling the via holes 15 with the conductive precursor may be a printing method such as screen printing. The conductive precursor may be filled into the via holes 15 by multiple printing processes. The conductive precursor may be filled into the via holes 15 under reduced pressure. By heating the conductive precursor in the via holes 15, the conductive vias 5a, 5b, which are cured versions of the conductive precursor, can be formed.

The conductive precursor for forming the conductive vias 5a and 5b may be a conductive paste containing multiple metal particles and an organic binder in which the multiple metal particles are dispersed. The conductive paste used as the conductive precursor is not particularly limited and may be a sintered copper paste, a sintered silver paste, or a solder paste. The conductive paste used as the conductive precursor may be a transient liquid phase sintering (TLPS) metal adhesive containing multiple metal particles capable of transient liquid phase sintering. In this case, sintering of the conductive paste fuses the multiple metal particles together, thereby forming the conductive vias 5a and 5b, which are conductors containing a metal sintered body. "Transient liquid phase sintering," also known as TLPS, generally refers to sintering that proceeds by heating the particle interfaces of a low-melting-point metal to a liquid phase, followed by reactive diffusion of a high-melting-point metal into the resulting liquid phase. Transient liquid phase sintering allows the melting point of the resulting metal sintered body to exceed the heating temperature for sintering.

The plurality of metal particles capable of transient liquid phase sintering may include a combination of a high-melting point metal and a low-melting point metal. The plurality of metal particles may include separate first metal particles including high-melting point metal particles and second metal particles including low-melting point metal particles, or the high-melting point metal and the low-melting point metal may be included in a single metal particle.

When the conductive precursor contains multiple metal particles capable of transition liquid phase sintering, the conductive via 5 can be formed by heating the conductive precursor to a temperature equal to or higher than the liquid phase transition temperature of the multiple metal particles. The liquid phase transition temperature can be measured by DSC (differential scanning calorimetry) under conditions of heating the multiple metal particles from 25°C to 300°C at a heating rate of 10°C/min in a nitrogen gas flow of 50 ml/min. When the metal particles contain multiple metals, the liquid phase transition temperature observed at the lowest temperature is considered to be the liquid phase transition temperature of the metal particles. For example, the liquid phase transition temperature of a Sn-3.0Ag-0.5Cu alloy is 217°C.

When the multiple metal particles capable of transient liquid phase sintering include a combination of first metal particles containing a high-melting point metal and second metal particles containing a low-melting point metal, the mass ratio of the first metal particles to the second metal particles may be 2.0 to 4.0, or 2.2 to 3.5.

Metal particles containing a high-melting point metal and a low-melting point metal can be obtained, for example, by forming a layer containing one metal on the surface of a metal particle containing the other metal by plating, vapor deposition, etc. Metal particles containing one metal and metal particles containing the other metal may also be composited by collision, etc.

The high-melting point metal may be at least one selected from the group consisting of Au, Cu, Ag, Co, and Ni. The low-melting point metal may be In, Sn, or a combination thereof. Examples of combinations of high-melting point metals and low-melting point metals include a combination of Au and In, a combination of Cu and Sn, a combination of Ag and Sn, a combination of Co and Sn, and a combination of Ni and Sn.

The combination of Cu and Sn produces a copper-tin metal compound (Cu6Sn5) upon sintering. This reaction occurs at around 250°C, so a conductor precursor containing a combination of Cu and Sn can be sintered by heating using common equipment such as a reflow oven. Sn can be contained in the metal particles either as simple Sn metal or as an alloy containing Sn. An example of an alloy containing Sn is the Sn-3.0Ag-0.5Cu alloy. The Sn-3.0Ag-0.5Cu alloy contains 3.0% by mass of Ag and 0.5% by mass of Cu, based on the mass of the alloy.

The content of metal particles in the conductor precursor may be 80% by mass or more, 85% by mass or more, or 88% by mass or more, or 98% by mass or less, based on the mass of the conductor precursor. When the conductor precursor contains a solvent as described below, the content here is a percentage based on the total mass of components other than the solvent.

The average particle size of the metal particles may be 0.5 μm to 80 μm, 1 μm to 50 μm, or 1 μm to 30 μm. Here, the average particle size refers to the volume average particle size measured using a laser diffraction particle size distribution analyzer (e.g., Beckman Coulter, Inc., LS 13 320 Laser Scattering and Diffraction Particle Size Distribution Analyzer).

The organic binder in the conductor precursor may contain a thermoplastic resin. The thermoplastic resin may have a softening point lower than the liquid-phase transition temperature of the metal particles. The softening point of the thermoplastic resin is a value measured by thermomechanical analysis. The softening point measured by thermomechanical analysis is the temperature at which a displacement of 80 μm is observed when a 100 μm thick film obtained by forming a thermoplastic resin is compressed in the thickness direction with a stress of 49 mN while being heated at a heating rate of 10°C/min. A thermomechanical analyzer (TMA8320, manufactured by Rigaku Corporation, measurement probe: standard type for compression loading method) is used as the measurement device.

The softening point of the thermoplastic resin may be 5°C or more lower, 10°C or more lower, or 15°C or more lower than the liquid phase transition temperature of the metal particles. The softening point of the thermoplastic resin may be 40°C or more, 50°C or more, or 60°C or more.

The thermoplastic resin may include, for example, at least one selected from the group consisting of polyamide resin, polyamideimide resin, polyimide resin, and polyurethane resin. The thermoplastic resin may include a polyoxyalkylene group or a polysiloxane group. The polyoxyalkylene group may be a polyoxyethylene group, a polyoxypropylene group, or a combination thereof.

The thermoplastic resin may be at least one resin selected from the group consisting of polyamide resins, polyamideimide resins, polyimide resins, and polyurethane resins, each containing a polyoxyalkylene chain or a polysiloxane chain. For example, polyoxyalkylene groups or polysiloxane groups can be introduced into these resins by using a diamine compound containing a polyoxyalkylene group or a polysiloxane group, or a diol compound containing a polyoxyalkylene group or a polysiloxane group, as a monomer.

The content of the thermoplastic resin in the conductor precursor may be 5 to 30 mass%, 6 to 28 mass%, or 8 to 25 mass%, based on the mass of the conductor precursor. When the conductor precursor contains a solvent, as described below, the content here is a percentage based on the total mass of the components other than the solvent.

The organic binder may contain a solvent, or may contain a solvent and a thermoplastic resin. The solvent may be a polar solvent. The boiling point of the solvent may be 200°C or higher or 300°C or lower.

Examples of solvents include alcohols such as terpineol, stearyl alcohol, tripropylene glycol methyl ether, diethylene glycol, diethylene glycol monoethyl ether (ethoxyethoxyethanol), diethylene glycol monohexyl ether, diethylene glycol monomethyl ether, dipropylene glycol-n-propyl ether, dipropylene glycol-n-butyl ether, tripropylene glycol-n-butyl ether, 1,3-butanediol, 1,4-butanediol, propylene glycol phenyl ether, and 2-(2-butoxyethoxy)ethanol; esters such as tributyl citrate, γ-butyrolactone, diethylene glycol monoethyl ether acetate, dipropylene glycol methyl ether acetate, diethylene glycol monobutyl ether acetate, and glycerin triacetate; ketones such as isophorone; lactams such as N-methyl-2-pyrrolidone; nitriles such as phenylacetonitrile; 4-methyl-1,3-dioxolan-2-one; and sulfolane. The solvents may be used alone or in combination of two or more.

The solvent content may be 0.1 to 10 mass%, 2 to 7 mass%, or 3 to 5 mass%, based on the mass of the conductor precursor.

The organic binder in the conductor precursor may further contain other components such as thermosetting resins, rosins, activators, and thixotropic agents.

Examples of thermosetting resins include epoxy resins, oxazine resins, bismaleimide resins, phenolic resins, unsaturated polyester resins, and silicone resins. Examples of epoxy resins include bisphenol A epoxy resins, bisphenol F epoxy resins, bisphenol S epoxy resins, phenol novolac epoxy resins, cresol novolac epoxy resins, naphthalene epoxy resins, biphenol epoxy resins, biphenyl novolac epoxy resins, and cycloaliphatic epoxy resins.

Examples of rosins include dehydroabietic acid, dihydroabietic acid, neoabietic acid, dihydropimaric acid, pimaric acid, isopimaric acid, tetrahydroabietic acid, and palustric acid.

Examples of activators include aminodecanoic acid, pentane-1,5-dicarboxylic acid, triethanolamine, diphenylacetic acid, sebacic acid, phthalic acid, benzoic acid, dibromosalicylic acid, anisic acid, iodosalicylic acid, and picolinic acid.

Examples of thixotropic agents include 12-hydroxystearic acid, 12-hydroxystearic acid triglyceride, ethylene bisstearic acid amide, hexamethylene bisoleic acid amide, and N,N'-distearyl adipamide.

The conductor precursor can be obtained by mixing metal particles with the components that make up the organic binder. The mixing device may be, for example, a three-roll mill, a planetary mixer, a planetary mixer, a rotation-revolution type agitator, a mortar mixer, a twin-screw kneader, or a thin-layer shear disperser.

The electronic components encapsulated by the encapsulating resin layer 7 can be chip components (semiconductor elements), chip-type passive components, or a combination of these. The chip components may be IC chips. The passive components may be, for example, antennas or capacitors. Even if the electronic components emit high-frequency electromagnetic waves, the conductive vias can provide sufficient electromagnetic wave shielding. Therefore, for example, some or all of the multiple electronic components may emit electromagnetic waves with a frequency of 3.6 GHz or higher during operation. The upper limit of electromagnetic waves emitted by electronic components is typically around 300 GHz.

The substrate 1 may be a substrate for temporary fixing having a temporary fixing material layer that is peeled off from the sealing structure 20 after the conductive vias 5a, 5b are formed. The temporary fixing material layer is peeled off from the sealing resin layer 7, for example, by heating, light irradiation, or mechanical peeling. When the substrate 1 is a substrate for temporary fixing, the method for manufacturing an electronic component device may further include peeling the substrate 1 from the sealing structure 20 and forming a planar wiring structure 6 on the sealing structure 20, the planar wiring structure 6 including rewiring connected to the electronic component and an insulating layer. Alternatively, the substrate 1 may include a wiring structure including rewiring, and the sealing structure 20 may be provided on the wiring structure. In this case, after the conductive vias 5a, 5b are formed, the wiring structure portion of the substrate 1 is not peeled off to form the electronic component device 100. A solder ball 9 may be provided on the surface of the wiring structure 6 opposite the sealing structure 20.

Figure 4 is a plan view showing an example of an arrangement of conductive vias in an electronic component device. The encapsulating resin layer 7 and shielding film 8 are omitted from Figure 4. In the electronic component device 100 shown in Figure 4, multiple conductive vias 5a and 5b are arranged on the main surface of the wiring structure 6 to form one or more closed, circular rows. The rows (conductive via groups 50) formed by the conductive vias 5a and 5b divide the main surface of the wiring structure 6 into multiple mounting regions 6A, 6B, and 6C. Electronic components (chip components 2A, 2B, and 2C and passive components 3) are arranged within the mounting regions 6A, 6B, and 6C. For example, chip component 2A and the passive components 3 arranged around it are surrounded by two rows L1 and L2 extending along the periphery of the mounting region 6A in which they are arranged. Row L1 and the outer row L2 are formed by conductive vias 5a and conductive vias 5b arranged outside it, respectively. The row L1 and the outer row L2 surround the chip component 2A and the passive component 3 without intersecting each other. The mounting areas 6B and 6C in which the chip components 2B and 2C are arranged are also surrounded by two rows extending along their peripheries. Parts of the rows L1 and L2 surrounding the chip component 2A and the mounting area 6A also serve as rows extending along the peripheries of the mounting areas 6B and 6C in which the chip components 2B and 2C are arranged. The via holes 15 for forming the conductive vias 5a and 5b are arranged so as to form rows on the main surface of the substrate 1 that correspond to the rows of the conductive vias 5a and 5b.

One or more electronic components are typically placed in each mounting area inside one or more rows formed by multiple conductive vias. The number of annular rows extending along the periphery of the mounting area may be two or more, three or more, or five or less. When an electronic component is surrounded by two or more rows formed by conductive vias, an even greater electromagnetic wave shielding effect is likely to be achieved.

The distance W between two adjacent conductive vias 5a or 5b in any one row may be, for example, 10 mm or less. Even if the conductive vias are arranged with a gap between them, a small distance W makes it easier to achieve a sufficient electromagnetic wave shielding effect. From a similar perspective, the distance W may be 10 mm or less, 1 mm or less, 100 μm or less, 50 μm or less, or 10 μm or less. From the perspective of process stability and reducing the number of required conductive vias, the distance W may be greater than 0 μm. From a similar perspective, the distance W may be 10 μm or more, 50 μm or more, 100 μm or more, 1 mm or more, or 10 mm or more. The distance W may be 1/10 of the wavelength of the electromagnetic waves to be shielded (electromagnetic waves emitted by electronic components).

When two or more rows extend along the periphery of the mounting area where electronic components are placed, the distance between two adjacent rows (e.g., the distance between row L1 and row L2) may be 10 μm or more and 1 mm or less. The distance between two adjacent rows refers to the distance between the lines connecting the center positions of the conductive vias that make up each row.

As another example shown in Figure 5, multiple conductive vias 5a, 5b may be arranged in a staggered pattern in two or more rows (e.g., rows L1, L2) that extend along the periphery of the mounting area where electronic components are placed and do not intersect with each other. "Staggered pattern" refers to an arrangement in which the conductive vias (or via holes) that make up each of two adjacent rows are arranged alternately in the direction in which the two rows extend. When conductive vias 5a, 5b are arranged in a staggered pattern, a high electromagnetic wave shielding effect can be achieved with a smaller number of conductive vias.

Electronic component devices having conductive vias arranged to form one or more rows surrounding the electronic components, as illustrated in Figures 4 and 5, can be efficiently manufactured using the above-described imprinting method. However, instead of the imprinting method, electronic component devices having conductive vias arranged in a similar pattern may also be manufactured using a photolithography method or a laser processing method.

Below, we will explain the results of verifying the effectiveness of electromagnetic wave shielding using conductive vias.

(Verification test 1)
The analytical model used was an electronic component device having an antenna that oscillates electromagnetic waves at frequencies of 4 GHz, 30 GHz, or 70 GHz, conductive vias that form a row surrounding the electronic component, and a sealing resin layer that seals the electronic component and the conductive vias. The diameter of the conductive vias was set to 100 μm, and the pitch of the conductive vias (the distance between the centers of adjacent conductive vias) was set to 200 μm or 400 μm.

The conductive vias were arranged in one or three rows along a 13.4 mm x 15.4 mm rectangular frame surrounding the electronic component. In the case of three rows, the conductive vias were arranged in an aligned arrangement (equally spaced) in adjacent rows, as in the example of Figure 4, or in a staggered arrangement, as in the example of Figure 5.

The electric field strength was determined at a position outside the conductive via, a specified distance from the center of the chip component, using analysis using the FDTD (Finite-Difference Time-Domain Method). The shielding effect shown in Table 1 is the difference between the electric field strength without the conductive via and the electric field strength with the conductive via.

The analysis results shown in Table 1 confirm that the conductive vias function as compartment shields with good electromagnetic wave shielding effects.

(Verification Test 2)
A 300 μm thick semi-cured film of encapsulant was laminated on a silicon substrate. The silicon substrate and encapsulant specimen were placed on the stage of a flip-chip bonder, and 743 via holes (100 μm diameter) were formed in three rows by an imprinting method in which a mold was pressed into the encapsulant (encapsulating resin layer) on the silicon substrate. The spacing between the centers of adjacent via holes was 200 μm. The three rows of via holes were arranged to extend along the sides of a 15.2 mm x 13.2 mm rectangle. In the imprinting method, the flip-chip bonder stage and mold were heated to 60°C, and a load of 100 N was applied to the mold. After the mold was removed from the encapsulant, the specimen was heated at 140°C for two hours to cure the encapsulant.

Next, the via holes were filled with a copper-containing conductor precursor paste that forms conductive vias by transient liquid phase sintering using a vacuum screen printer (LS-100VC, Newlong Precision Industry Co., Ltd.). The conductor precursor was pre-baked by heating at 100°C for 30 minutes, and then placed in a reflow furnace at 260°C to form copper-containing conductive vias with a height of 370 μm. A copper-containing shielding film was formed by sputtering to cover the surface of the encapsulant (encapsulating resin layer) opposite the silicon substrate.

A test specimen with conductive vias was mounted on a wiring structure with an antenna section, and a signal generator was connected to the antenna section via an attenuator. The signal generator generated 4 GHz electromagnetic waves from the antenna section, and the electric field strength was measured in a 50 mm square area centered on the test specimen. For comparison, test specimen 1, which did not have conductive vias or a shielding film, and test specimen 2, which did not have conductive vias, were prepared, and their electric field strengths were measured in the same way.

The measurement results are shown in Table 2. The maximum electric field strength is the maximum electric field strength outside the frame of the conductive via. The shielding effect is the amount of reduction in the maximum electric field strength of test specimen 2 or 3 compared to the maximum electric field strength of test specimen 1. It was confirmed that the provision of conductive vias provides excellent electromagnetic wave shielding effects.

1...substrate, 2, 2A, 2B...chip components (electronic components), 3...passive components (electronic components), 5a, 5b...conductive vias, 6A, 6B, 6C...mounting area, 7...encapsulating resin layer, 8...shielding film, 9...solder balls, 10...mold, 15...via holes, 20...encapsulating structure, 50...group of conductive vias, 100...electronic component device, L1, L2...row of conductive vias.

Claims (12)

providing, on the substrate, an encapsulating structure having one or more electronic components arranged on a main surface of the substrate and a curable encapsulating resin layer encapsulating the electronic components;
forming a plurality of via holes extending in a thickness direction of the sealing resin layer by an imprint method including pressing a mold into the sealing resin layer from an opposite side to the substrate;
curing the sealing resin layer;
forming a plurality of conductive vias filling each of the plurality of via holes;
Including,
one or more of the electronic components are disposed in one or more mounting areas on the main surface of the substrate;
some or all of the plurality of via holes are arranged at intervals from one another to form one or more rows, and the mounting area is an area surrounded by the one or more rows;
the distance between adjacent via holes in one row is 100 μm or more and 10 mm or less;
A method for manufacturing an electronic component device. The method of claim 1, wherein each of the one or more mounting areas is an area surrounded by two or more of the rows that extend along the periphery of the mounting area and do not intersect with each other. The method of claim 2, wherein two or more of the rows extending along the periphery of each of the one or more mounting areas and not intersecting each other include a plurality of the via holes arranged in a staggered arrangement. The method according to claim 1 , wherein each of the one or more mounting areas is an area surrounded by at least three but not more than five of the rows that extend along the periphery of the mounting area and do not intersect with each other . The method according to any one of claims 1 to 4, further comprising forming a conductive shielding film that covers the sealing resin layer and is connected to the tip of the conductive via. the conductive via is formed by a method including filling the via hole with a conductive precursor and heating the conductive precursor filled in the via hole to form the conductive via;
the conductor precursor contains a plurality of metal particles and an organic binder in which the plurality of metal particles are dispersed,
6. The method of claim 1, wherein when the electrical conductor precursor is heated, the plurality of metal particles form a metal sintered body by transient liquid phase sintering, thereby forming the conductive via comprising the metal sintered body. the sealing structure is provided on the substrate by laminating a film-like sealing material on the substrate,
The sealing material exhibits a melt viscosity of 20,000 Pa s or less at some or all of the temperatures in the range of 55 to 110°C.
The method according to any one of claims 1 to 6. The method described in any one of claims 1 to 7, wherein some or all of the one or more electronic components emit electromagnetic waves with a frequency of 3.6 GHz or higher when in operation. a wiring structure including rewiring;
one or more electronic components mounted on a main surface of the wiring structure;
a sealing resin layer that seals the electronic component;
a plurality of conductive vias penetrating the sealing resin layer;
Equipped with
one or more of the electronic components are disposed in one or more mounting regions on the main surface of the wiring structure;
some or all of the plurality of conductive vias are arranged at intervals from one another to form two or more rows, and one or more of the mounting regions are regions surrounded by two or more of the rows that extend along the periphery of each of the mounting regions and do not intersect with one another;
two or more rows extending along the periphery of each of the one or more mounting regions and not intersecting each other include a plurality of the conductive vias arranged in a staggered arrangement;
The electronic component device , wherein the distance between adjacent conductive vias in one row is 100 μm or more and 10 mm or less . The electronic component device of claim 9, further comprising a conductive shielding film covering the sealing resin layer and connected to the tip of the conductive via. The electronic component device described in claim 9 or 10, wherein some or all of the one or more electronic components emit electromagnetic waves with a frequency of 3.6 GHz or higher when in operation. some or all of the plurality of conductive vias are spaced apart from one another to form rows of three or more and five or less;
the rows extending along the periphery of each of the one or more mounting regions and not intersecting each other are three to five rows each, and each row includes a plurality of the conductive vias arranged in a staggered arrangement;
The electronic component device according to any one of claims 9 to 11.