JP7755791B2 - Image display device manufacturing method and image display device - Google Patents

Description

Embodiments of the present invention relate to a method for manufacturing an image display device and an image display device.

There is a demand for thin image display devices that offer high brightness, a wide viewing angle, high contrast, and low power consumption. To meet these market demands, development is underway on display devices that use self-luminous elements.

The emergence of display devices using micro LEDs, which are minute light-emitting elements, is anticipated as a self-emitting element. One method of manufacturing display devices using micro LEDs involves sequentially transferring individually formed micro LEDs onto a driver circuit. However, as image quality increases to full HD, 4K, 8K, and other high resolutions, the number of micro LED elements increases. Therefore, forming a large number of micro LEDs individually and sequentially transferring them onto a substrate with a driver circuit, etc., requires an enormous amount of time for the transfer process. Furthermore, there is a risk of poor connections between the micro LEDs and the driver circuit, etc., resulting in reduced yields.

A technology is known in which a semiconductor layer including an emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board on which a driving circuit is formed (see, for example, Patent Document 1).

Japanese Patent Application Laid-Open No. 2002-141492

One embodiment of the present invention provides a manufacturing method for an image display device and an image display device that shortens the transfer process of light-emitting elements and improves yield.

A method for manufacturing an image display device according to one embodiment of the present invention includes the steps of forming a graphene-containing layer on a first substrate, forming a semiconductor layer including a light-emitting layer on the graphene-containing layer, processing the semiconductor layer to form a light-emitting element having a bottom surface on the graphene-containing layer and including a light-emitting surface on the surface opposite the bottom surface, forming a first insulating film covering the first substrate, the graphene-containing layer, and the light-emitting element, forming a circuit element on the first insulating film, forming a second insulating film covering the first insulating film and the circuit element, removing a portion of the first insulating film and a portion of the second insulating film to expose a surface including the light-emitting surface, forming a via that penetrates the first insulating film and the second insulating film, and forming a wiring layer on the second insulating film. The light-emitting element includes a connection portion formed on the graphene-containing layer. The via is provided between the wiring layer and the connection portion and electrically connects the wiring layer and the connection portion.

An image display device according to one embodiment of the present invention comprises a substrate having a first surface, a graphene-containing layer provided on the first surface, a light-emitting element provided on the graphene-containing layer, having a bottom surface on the graphene-containing layer and including a surface including a light-emitting surface opposite the bottom surface, a first insulating film covering a side surface of the light-emitting element, the first surface, and the graphene-containing layer, a circuit element provided on the first insulating film, a second insulating film covering the first insulating film and the circuit element, a via provided through the first insulating film and the second insulating film, and a wiring layer provided on the second insulating film. The light-emitting element includes a first semiconductor layer, a light-emitting layer provided on the first semiconductor layer, and a second semiconductor layer provided on the light-emitting layer, the first semiconductor layer, the light-emitting layer, and the second semiconductor layer being stacked in this order from the bottom surface toward the light-emitting surface. The via is provided between the wiring layer and a connection portion formed on the graphene-containing layer from the first semiconductor layer, electrically connecting the first semiconductor layer and the wiring layer.

An image display device according to one embodiment of the present invention comprises a substrate having a first surface, a light-reflective second portion provided on the first surface, a graphene-containing layer provided on the second portion, a semiconductor layer provided on the graphene-containing layer, having a bottom surface on the graphene-containing layer and including multiple light-emitting surfaces on a surface opposite the bottom surface, a first insulating film covering the first surface, side surfaces of the graphene-containing layer, and the semiconductor layer, multiple transistors provided on the first insulating film, a second insulating film covering the first insulating film and the multiple transistors, multiple vias provided through the first insulating film and the second insulating film, and a wiring layer provided on the second insulating film and including wiring electrically connected to the multiple transistors, the multiple light-emitting surfaces, and the multiple vias. The periphery of the semiconductor layer is located within the periphery of the second portion in a planar view. The semiconductor layer includes a first semiconductor layer, a light-emitting layer provided on the first semiconductor layer, and a second semiconductor layer provided on the light-emitting layer, and the first semiconductor layer, the light-emitting layer, and the second semiconductor layer are stacked in this order from the bottom surface toward the light-emitting surface. The plurality of vias are provided between the wiring layer and a connection portion formed on the layer including the graphene from the first semiconductor layer, and electrically connect the first semiconductor layer and the wiring layer.

According to one embodiment of the present invention, a method for manufacturing an image display device is realized that shortens the transfer process of light-emitting elements and improves yield.

According to one embodiment of the present invention, an image display device is realized that shortens the transfer process of light-emitting elements and improves yield.

1 is a schematic cross-sectional view illustrating a part of an image display device according to a first embodiment. FIG. 10 is a cross-sectional view schematically showing a part of a modified example of the image display device according to the first embodiment. FIG. 1 is a schematic block diagram illustrating an image display device according to a first embodiment. FIG. 1 is a schematic plan view illustrating a part of an image display device according to a first embodiment. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the first embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the first embodiment. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing the image display device of the first embodiment. 10A to 10C are schematic cross-sectional views illustrating a modified example of the manufacturing method of the image display device of the first embodiment. 10A to 10C are schematic cross-sectional views illustrating a modified example of the manufacturing method of the image display device of the first embodiment. 10A to 10C are schematic cross-sectional views illustrating a modified example of the manufacturing method of the image display device of the first embodiment. 10A to 10C are schematic cross-sectional views illustrating a modified example of the manufacturing method of the image display device of the first embodiment. 1 is a schematic perspective view illustrating an image display device according to a first embodiment. FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a second embodiment. FIG. 10 is a schematic block diagram illustrating an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a second embodiment. FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a third embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a third embodiment. FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a fourth embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fourth embodiment. FIG. 10 is a schematic cross-sectional view illustrating a part of an image display device according to a fifth embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a fifth embodiment. FIG. 13 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the fifth embodiment. 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. 13A to 13C are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the fifth embodiment. 1 is a graph illustrating the characteristics of a pixel LED element. FIG. 13 is a block diagram illustrating an image display device according to a sixth embodiment. FIG. 13 is a block diagram illustrating an image display device according to a modification of the sixth embodiment.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.
In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are given the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating a part of an image display device according to this embodiment.
1 is a schematic diagram showing the configuration of a sub-pixel 20 of an image display device according to this embodiment. A pixel that forms an image displayed on the image display device is made up of a plurality of sub-pixels 20.

In the following, explanations will be given using the three-dimensional coordinate system of XYZ. The subpixels 20 are arranged in a two-dimensional plane. The two-dimensional plane on which the subpixels 20 are arranged is referred to as the XY plane. The subpixels 20 are arranged along the X-axis and Y-axis directions. Figure 1 shows a cross section taken along line AA' in Figure 4 (described below), which is a cross section created by connecting multiple cross sections perpendicular to the XY plane. In other figures, cross sections of multiple cross sections perpendicular to the XY plane, like Figure 1, do not show the X-axis and Y-axis, but show the Z-axis perpendicular to the XY plane. In other words, in these figures, the plane perpendicular to the Z-axis is referred to as the XY plane. For convenience, the positive direction of the Z-axis is sometimes referred to as "up" or "upper," and the negative direction of the Z-axis is sometimes referred to as "down" or "lower." However, the direction along the Z-axis is not necessarily the direction of gravity. The length along the Z-axis is sometimes referred to as height.

The subpixel 20 has a light-emitting surface 153S that is approximately parallel to the XY plane. The light-emitting surface 153S is a surface that emits light primarily in the positive direction of the Z axis, which is perpendicular to the XY plane.

As shown in FIG. 1, the subpixel 20 of the image display device includes a substrate 102, a graphene layer 140, a light-emitting element 150, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, a via 161k, and a wiring layer 110.

In this embodiment, the substrate 102 on which the light-emitting element 150 is formed is a light-transmitting substrate, such as a glass substrate. The substrate 102 has a first surface 102a, and the light-emitting element 150 is formed on the first surface 102a. The light-emitting element 150 is driven by a TFT provided via a first interlayer insulating film 156. The process of forming circuit elements including TFTs on a large glass substrate is established for the manufacture of liquid crystal panels, organic EL panels, etc., and has the advantage of being able to utilize existing plants.

The subpixel 20 further includes a color filter 180. The color filter (wavelength conversion member) 180 is provided on the surface resin layer 170 via a transparent thin-film adhesive layer 188. The surface resin layer 170 is provided on the second interlayer insulating film 108 and the wiring layer 110.

The configuration of the sub-pixel 20 will be described in detail below.
The graphene layer 140 is provided on the first surface 102a. The graphene layer 140 includes a graphene sheet 140a. A graphene sheet (layer including graphene) 140a is provided for each light-emitting element 150, and the light-emitting element 150 is provided on the graphene sheet 140a. The graphene sheet 140a has an outer periphery that roughly coincides with the outer periphery of the light-emitting element 150 in the XY plane view. The graphene layer 140 and the graphene sheet 140a are layered bodies in which, for example, several to about ten layers of single-layer graphene are stacked.

In this example, the light-emitting element 150 is provided on the graphene sheet 140a via a buffer layer 145. The buffer layer 145 has an outer periphery that roughly coincides with the outer periphery of the light-emitting element 150 in an XY plane view. In this example, the buffer layer 145 is formed from an insulating material, such as AlN. The buffer layer 145 is primarily used to promote the growth of the semiconductor layers that form the light-emitting element 150.

Light-emitting element 150 includes light-emitting surface 153S and bottom surface 151B. Light-emitting surface 153S is the surface opposite bottom surface 151B of light-emitting element 150. Light-emitting element 150 is a prismatic or cylindrical element having bottom surface 151B on first surface 102a. In this example, bottom surface 151B of light-emitting element 150 is the surface in contact with buffer layer 145.

Light-emitting element 150 includes an n-type semiconductor layer (first semiconductor layer) 151, a light-emitting layer 152, and a p-type semiconductor layer (second semiconductor layer) 153. N-type semiconductor layer 151, light-emitting layer 152, and p-type semiconductor layer 153 are stacked in this order from bottom surface 151B toward light-emitting surface 153S. Therefore, in this example, n-type semiconductor layer 151 is provided in contact with buffer layer 145.

The n-type semiconductor layer 151 includes a connection portion 151a. For example, the connection portion 151a, together with the buffer layer 145 and the graphene sheet 140a, is provided on the first surface 102a so as to protrude in one direction from the n-type semiconductor layer 151. The protrusion direction is not limited to one direction, but may be two or more directions, or may be provided so as to protrude around the entire circumference of the n-type semiconductor layer 151. The height of the connection portion 151a is the same as or lower than the height of the n-type semiconductor layer 151, and the light-emitting element 150 is formed in a stepped shape. The connection portion 151a is n-type and electrically connected to the n-type semiconductor layer 151. The connection portion 151a is connected to one end of the via 161k, and the n-type semiconductor layer 151 is electrically connected to the via 161k via the connection portion 151a.

If the light-emitting element 150 has a prismatic shape, the shape of the light-emitting element 150 in the XY plane view is, for example, approximately square or rectangular. If the shape of the light-emitting element 150 in the XY plane view is a polygon including a square, the corners may be rounded. If the shape of the light-emitting element 150 in the XY plane view is cylindrical, the shape of the light-emitting element 150 in the XY plane view is not limited to a circle, and may be, for example, an ellipse. By appropriately selecting the shape and arrangement of the light-emitting element in the XY plane view, the degree of freedom in layout is improved.

For the light emitting element ₁₅₀ , for example, a gallium nitride compound semiconductor including a light emitting layer such as _{InXAlYGa1 -X-} YN (0≦X, 0≦Y, X+Y<1) is suitably used. Hereinafter, the above-mentioned gallium nitride compound semiconductor may be simply referred to as gallium nitride (GaN). The light emitting element 150 in one embodiment of the present invention is a so-called light emitting diode. The wavelength of light emitted by the light emitting element 150 is, for example, approximately 467 nm±30 nm. The wavelength of light emitted by the light emitting element 150 may be blue-violet light of approximately 410 nm±30 nm. The wavelength of light emitted by the light emitting element 150 is not limited to the above-mentioned value and may be any appropriate value.

The area of the light-emitting layer 152 in the XY plane is set according to the emitted color of the red, green, and blue subpixels. Hereinafter, the area in the XY plane may be simply referred to as the area. The area of the light-emitting layer 152 is appropriately set based on factors such as luminosity and the conversion efficiency of the color conversion section 182 of the color filter 180. In other words, the area of the light-emitting layer 152 of the subpixels 20 of each emitted color may be the same or may differ for each emitted color. The area of the light-emitting layer 152 is the area of the region surrounded by the periphery of the light-emitting layer 152 projected onto the XY plane.

The first interlayer insulating film (first insulating film) 156 covers the first surface 102a, the graphene layer 140, the buffer layer 145, and the light-emitting element 150. In this example, the first interlayer insulating film 156 covers the side surfaces of the graphene sheet 140a, the side surfaces of the buffer layer 145, and the side surfaces of the light-emitting element 150. The first interlayer insulating film 156 insulates the light-emitting elements 150 from each other. The first interlayer insulating film 156 insulates the light-emitting element 150 from circuit elements such as the transistor 103. The first interlayer insulating film 156 provides a flat surface for forming the circuit 101 including circuit elements such as the transistor 103. By covering the light-emitting element 150, the first interlayer insulating film 156 protects the light-emitting element 150 from thermal stress, etc., that occurs when forming the transistor 103, etc.

The first interlayer insulating film 156 is formed from an organic or inorganic insulating material. The insulating material used for the first interlayer insulating film 156 is preferably a white resin. Because the white resin reflects the lateral emitted light from the light-emitting element 150 and the returned light resulting from the interface of the color filter 180, using a white resin for the first interlayer insulating film 156 contributes to a substantial improvement in the luminous efficiency of the light-emitting element 150.

The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin such as SOG (Spin On Glass) or a novolac-type phenolic resin. The scattering particles are colorless or white, and have a diameter of about 1/10 to several times the wavelength of the light emitted by the light-emitting element 150. Suitable scattering particles have a diameter of about 1/2 _the wavelength of the light. Examples of such scattering particles include _TiO2 , _Al2O3 , and ZnO.

The white resin can also be formed by utilizing a large number of minute pores dispersed in a transparent resin. When the first interlayer insulating film 156 is whitened, for example, a SiO ₂ film formed by atomic layer deposition (ALD) or CVD may be used instead of SOG or the like.

The first interlayer insulating film 156 may be a black resin. By using a black resin for the first interlayer insulating film 156, scattering of light within the subpixel 20 is suppressed, and stray light is more effectively suppressed. An image display device with suppressed stray light is able to display sharper images.

A TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is provided to ensure flatness when forming the transistor 103 and to protect the TFT channel 104 of the transistor 103 from contamination and the like during heat treatment. The TFT lower layer film 106 is an insulating film made of, for example, _SiO2 or the like.

The transistor 103 is formed on the TFT lower layer film 106. In addition to the transistor 103, other transistors, capacitors, and other circuit elements are formed on the TFT lower layer film 106, and the circuit 101 is formed with wiring and other elements. For example, in FIG. 3, which will be described later, the transistor 103 corresponds to the drive transistor 26. Other circuit elements in FIG. 3 include the selection transistor 24 and capacitor 28. The circuit 101 includes the TFT channel 104, the insulating layer 105, the second interlayer insulating film 108, vias 111s and 111d, and the wiring layer 110.

In this example, the transistor 103 is a p-channel thin film transistor (TFT). The transistor 103 includes a TFT channel 104 and a gate 107. The TFT channel 104 is preferably formed by a low temperature polysilicon (LTPS) process. In the LTPS process, the TFT channel 104 is formed by polycrystallizing and activating an amorphous silicon region formed on the TFT underlayer film 106. For example, laser annealing using a laser is used to polycrystallize and activate the amorphous silicon region. TFTs formed by the LTPS process have sufficiently high mobility.

The TFT channel 104 includes regions 104s, 104i, and 104d. Regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106. Region 104i is provided between regions 104s and 104d. Regions 104s and 104d are doped with impurities such as boron (B) by ion implantation or the like to form p-type semiconductor regions, and are ohmically connected to vias 111s and 111d.

Gate 107 is located on TFT channel 104 via insulating layer 105. Insulating layer 105 is provided to insulate TFT channel 104 from gate 107 and to insulate it from other adjacent circuit elements. When a lower potential than region 104s is applied to gate 107, a channel is formed in region 104i, thereby controlling the current flowing between regions 104s and 104d.

The insulating layer 105 is, for example, SiO _2. The insulating layer 105 may also be a multi-layer insulating layer including SiO ₂ , Si ₃ N ₄ , etc. depending on the area being covered.

Gate 107 may be formed, for example, from polycrystalline silicon, or from a high-melting-point metal such as tungsten or molybdenum. The polycrystalline silicon film of gate 107 is generally formed by CVD or the like.

A second interlayer insulating film (second insulating film) 108 is provided on the gate 107 and the insulating layer 105. The second interlayer insulating film 108 is formed of, for example, the same material as the first interlayer insulating film 156. That is, the second interlayer insulating film 108 is formed of a white resin or an inorganic film such as _SiO2 . The second interlayer insulating film 108 also functions as a planarizing film for forming the wiring layer 110.

Since the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108 are configured as described above, they are not provided above the light-emitting surface 153S. In other words, the opening 158 is formed by removing a portion of each of the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. The light-emitting surface 153S is exposed through the opening 158. As described below, the opening 158 is filled with a surface resin layer 170.

Vias 111s and 111d are provided through the second interlayer insulating film 108 and insulating layer 105. The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes multiple wirings that may have different potentials. In this example, the wiring layer 110 includes wirings 110s, 110d, and 110k.

A portion of wiring 110s is provided above region 104s. Another portion of wiring 110s is connected to, for example, the power supply line 3 shown in Figure 3, which will be described later. A portion of wiring 110d is provided above region 104d. Another portion of wiring (second wiring) 110d is connected to the surface including the light-emitting surface 153S. A portion of wiring 110k is provided above connection portion 151a. Another portion of wiring 110k is connected to, for example, the ground line 4 shown in Figure 3, which will be described later.

In the wiring layers of the cross-sectional views in Figures 1 and subsequent figures, unless otherwise specified, the symbol for that wiring layer will be displayed next to one of the wires included in the wiring layer to which the symbol is attached.

Via 111s is provided between wiring 110s and region 104s, electrically connecting wiring 110s and region 104s. Via 111d is provided between wiring 110d and region 104d, electrically connecting wiring 110d and region 104d.

Wiring 110s is connected to region 104s via via 111s. Region 104s is the source region of transistor 103. Therefore, the source region of transistor 103 is electrically connected to power line 3 via via 111s and wiring 110s.

Wiring 110d is connected to region 104d via via 111d. Region 104d is the drain region of transistor 103. Therefore, the drain region of transistor 103 is electrically connected to p-type semiconductor layer 153 via via 111d and wiring 110d.

Via 161k is provided through the second interlayer insulating film 108, insulating layer 105, TFT lower film 106, and first interlayer insulating film 156. Via 161k is provided between wiring (first wiring) 110k and connection portion 151a, and electrically connects wiring 110k and connection portion 151a. Therefore, n-type semiconductor layer 151 is electrically connected to ground line 4 via connection portion 151a, via 161k, and wiring 110k.

The wiring layer 110 and vias 111s, 111d, and 161k are formed, for example, from Al, Cu, or alloys thereof, or laminated films of these with Ti, etc. For example, in an Al and Ti laminated film, Al is laminated on a thin film of Ti, and Ti is further laminated on top of the Al.

The surface resin layer 170 covers the second interlayer insulating film 108 and the wiring layer 110. The surface resin layer 170 also fills the opening 158. The surface resin layer 170 covers the light-emitting surface 153S. The surface resin layer 170 filled in the opening 158 covers part of the side surfaces of the first interlayer insulating film 156, the TFT lower film 106, the insulating layer 105, and the second interlayer insulating film 108. The surface resin layer 170 is a transparent resin that protects the second interlayer insulating film 108 and the wiring layer 110, and also provides a planarized surface for bonding the color filter 180.

The color filter 180 includes a light-shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is provided directly above the light-emitting surface 153S of the light-emitting element 150 in accordance with the shape of the light-emitting surface 153S. In the color filter 180, the portion other than the color conversion portion 182 is the light-shielding portion 181. The light-shielding portion 181 is a so-called black matrix, and reduces blurring caused by color mixing of light emitted from adjacent color conversion portions 182, enabling the display of sharp images.

The color conversion section 182 may have one layer or two or more layers. Figure 1 shows a case where the color conversion section 182 has two layers. Whether the color conversion section 182 has one layer or two layers is determined by the color, i.e., wavelength, of the light emitted by the subpixel 20. If the emitted color of the subpixel 20 is red, the color conversion section 182 preferably has two layers: a color conversion layer 183 and a filter layer 184 that transmits red light. If the emitted color of the subpixel 20 is green, the color conversion section 182 preferably has two layers: a color conversion layer 183 and a filter layer 184 that transmits green light. If the emitted color of the subpixel 20 is blue, the color conversion section 182 preferably has one layer.

When the color conversion section 182 has two layers, the first layer is the color conversion layer 183 and the second layer is the filter layer 184. The first color conversion layer 183 is located closer to the light-emitting element 150. The filter layer 184 is stacked on top of the color conversion layer 183.

The color conversion layer 183 converts the wavelength of light emitted by the light-emitting element 150 to the desired wavelength. In the case of a subpixel 20 that emits red light, the color conversion layer 183 converts light having a wavelength of 467 nm ± 30 nm, which is the wavelength of the light-emitting element 150, to light having a wavelength of, for example, approximately 630 nm ± 20 nm. In the case of a subpixel 20 that emits green light, the color conversion layer 183 converts light having a wavelength of 467 nm ± 30 nm, which is the wavelength of the light-emitting element 150, to light having a wavelength of, for example, approximately 532 nm ± 20 nm.

The filter layer 184 blocks the wavelength components of blue light that remain unconverted by the color conversion layer 183.

If the color of light emitted by subpixel 20 is blue, the light may be output via color conversion layer 183, or directly without passing through color conversion layer 183. If the wavelength of light emitted by light-emitting element 150 is approximately 467 nm ± 30 nm, the light may be output without passing through color conversion layer 183. If the wavelength of light emitted by light-emitting element 150 is 410 nm ± 30 nm, it is preferable to provide one color conversion layer 183 to convert the wavelength of the output light to approximately 467 nm ± 30 nm.

Even in the case of a blue subpixel 20, the subpixel 20 may have a filter layer 184. By providing the blue subpixel 20 with a filter layer 184 that transmits blue light, minute external light reflections other than blue light that occur on the surface of the light-emitting element 150 are suppressed.

FIG. 2 is a cross-sectional view schematically showing a part of a modified example of the image display device according to the present embodiment.
2, to avoid complexity, the surface resin layer 170, the transparent thin film adhesive layer 188, and the color filter 180 are not shown. The structures above the surface resin layer 170 are assumed to be provided on the second interlayer insulating film 108, on the wiring layer 110, and in the opening 158.

In this modified example, the method of connecting the light-emitting element 150a to the wiring 110d1 in the subpixel 20a differs from the method of connecting the light-emitting element 150 to the wiring 110d in the first embodiment described above. This modified example also differs from the first embodiment in that a translucent electrode 159s is provided over the wiring 110s. In other respects, this modified example is the same as the first embodiment, and the same components are designated by the same reference numerals and detailed descriptions thereof are omitted where appropriate.

As shown in FIG. 2, subpixel 20a includes light-emitting element 150a, wiring 110d1, and translucent electrode 159d. A portion of wiring 110d1 is provided above region 104d and via 111d. A portion of wiring 110d1 is connected to region 104d via via 111d. Another portion of wiring 110d1 does not extend to reach light-emitting surface 153S and is not directly connected to light-emitting surface 153S.

The transparent electrode 159d is provided over the wiring 110d1. The transparent electrode 159d is provided over the light-emitting surface 153S. The transparent electrode 159d is also provided between the wiring 110d1 and the light-emitting surface 153S, electrically connecting the wiring 110d1 and the light-emitting surface 153S.

Translucent electrode 159s is provided over wiring 110s. Translucent electrode 159d and translucent electrode 159s are formed from a translucent conductive film. An ITO film, a ZnO film, or the like is preferably used as the translucent conductive film. In this example, a translucent electrode is not provided on wiring 110k, but a translucent electrode may also be provided on wiring 110k.

The light-emitting surface 153S is preferably roughened. When the light-emitting surface 153S of the light-emitting element 150 is roughened, the light extraction efficiency can be improved.

By providing a transparent electrode 159d on the light-emitting surface 153S, the connection area between the transparent electrode 159d and the p-type semiconductor layer 153 can be increased, and the area of the light-emitting surface 153S can be increased, thereby improving the light-emitting efficiency. If the light-emitting surface 153S is roughened, the connection area between the light-emitting surface 153S and the transparent electrode 159d can be increased to reduce contact resistance, thereby further improving the light-emitting efficiency.

This embodiment may include any of the configurations of the subpixels 20 and 20a described above. In other embodiments described below, electrical connection may be made either directly via metal wiring or via a transparent electrode.

FIG. 3 is a schematic block diagram illustrating an image display device according to this embodiment.
3, the image display device 1 of this embodiment includes a display area 2. Subpixels 20 are arranged in the display area 2. The subpixels 20 are arranged, for example, in a lattice pattern. For example, n subpixels 20 are arranged along the X axis, and m subpixels 20 are arranged along the Y axis.

A pixel 10 includes multiple subpixels 20 that emit light of different colors. Subpixel 20R emits red light. Subpixel 20G emits green light. Subpixel 20B emits blue light. The emission color and brightness of a single pixel 10 are determined by the three types of subpixels 20R, 20G, and 20B emitting light at the desired brightness.

One pixel 10 includes three subpixels 20R, 20G, and 20B, which are arranged linearly on the X axis, as shown in Figure 3, for example. Each pixel 10 may have subpixels of the same color arranged in the same column, or, as in this example, subpixels of different colors arranged in each column.

The image display device 1 further includes power supply lines 3 and ground lines 4. The power supply lines 3 and ground lines 4 are laid out in a grid pattern along the arrangement of the subpixels 20. The power supply lines 3 and ground lines 4 are electrically connected to each subpixel 20 and supply power to each subpixel 20 from a DC power supply connected between the power supply terminal 3a and the GND terminal 4a. The power supply terminal 3a and the GND terminal 4a are provided at the ends of the power supply lines 3 and the ground lines 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power supply terminal 3a relative to the GND terminal 4a.

The image display device 1 further includes scanning lines 6 and signal lines 8. The scanning lines 6 are arranged in a direction parallel to the X-axis. That is, the scanning lines 6 are arranged along the row direction of the subpixels 20. The signal lines 8 are arranged in a direction parallel to the Y-axis. That is, the signal lines 8 are arranged along the column direction of the subpixels 20.

The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the subpixels 20 in each column via scanning lines 6, and supplies a selection signal to each subpixel 20.

The signal voltage output circuit 7 is arranged along the X-axis direction on the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the subpixels 20 in each row via signal lines 8 and supplies a signal voltage to each subpixel 20.

The subpixel 20 includes a light-emitting element 22, a selection transistor 24, a drive transistor 26, and a capacitor 28. In Figure 3 and Figure 4 described below, the selection transistor 24 may be labeled T1, the drive transistor 26 may be labeled T2, and the capacitor 28 may be labeled Cm.

The light-emitting element 22 is connected in series with the drive transistor 26. In this embodiment, the drive transistor 26 is a p-channel TFT, and the anode electrode of the light-emitting element 22 is connected to the drain electrode of the drive transistor 26. The main electrodes of the drive transistor 26 and the selection transistor 24 are the drain electrode and source electrode. The anode electrode of the light-emitting element 22 is connected to the p-type semiconductor layer. The cathode electrode of the light-emitting element is connected to the n-type semiconductor layer. The series circuit of the light-emitting element 22 and the drive transistor 26 is connected between the power supply line 3 and the ground line 4. The drive transistor 26 corresponds to transistor 103 in Figure 1, and the light-emitting element 22 corresponds to the light-emitting element 150 in Figure 1. The current flowing through the light-emitting element 22 is determined by the voltage applied between the gate and source of the drive transistor 26, and the light-emitting element 22 emits light with a brightness corresponding to the current flowing.

The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and the signal line 8 via its main electrode. The gate electrode of the selection transistor 24 is connected to the scanning line 6. A capacitor 28 is connected between the gate electrode of the drive transistor 26 and the power supply line 3.

The row selection circuit 5 selects one row from an array of m rows of subpixels 20 and supplies a selection signal to the scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having the required analog voltage value to each subpixel 20 in the selected row. The signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row. The signal voltage is held by the capacitor 28. The drive transistor 26 passes a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light at a brightness corresponding to the current that has passed through it.

The row selection circuit 5 sequentially switches the selected row and supplies a selection signal. In other words, the row selection circuit 5 scans the rows in which the subpixels 20 are arranged. A current corresponding to the signal voltage flows through the light-emitting elements 22 of the sequentially scanned subpixels 20, causing them to emit light. Each pixel 10 emits light with a color and brightness determined by the color and brightness emitted by the RGB subpixels 20, and an image is displayed in the display area 2.

FIG. 4 is a schematic plan view illustrating a part of the image display device of this embodiment.
1, the light-emitting element 150 and the driving transistor 103 are stacked in the Z-axis direction with a first interlayer insulating film 156 interposed therebetween. The light-emitting element 150 corresponds to the light-emitting element 22 in FIG. 3. The driving transistor 103 corresponds to the driving transistor 26 in FIG. 3 and is also denoted as T2.

As shown in FIG. 4, the cathode electrode of the light-emitting element 150 is provided by the connection portion 151a. The connection portion 151a is provided in a layer lower than the transistor 103 and the wiring layer 110. The connection portion 151a is electrically connected to the wiring 110k via the via 161k. More specifically, one end of the via 161k is connected to the connection portion 151a. The other end of the via 161k is connected to the wiring 110k via the contact hole 161k1.

The anode electrode of the light-emitting element 150 is provided by the p-type semiconductor layer 153 shown in Figure 1. The wiring 110d extends through the opening 158 to the surface including the light-emitting surface 153S. The p-type semiconductor layer 153 is connected to one end of the wiring 110d via the surface including the light-emitting surface 153S. The surface including the light-emitting surface 153S is in the same plane as the light-emitting surface 153S. One end of the wiring 110d is connected to the surface including the light-emitting surface 153S, and the remaining surface is the light-emitting surface 153S.

The other end of wiring 110d is connected to the drain electrode of transistor 103 via via 111d. The drain electrode of transistor 103 is region 104d shown in Figure 1. The source electrode of transistor 103 is connected to wiring 110s via via 111s. The source electrode of transistor 103 is region 104s shown in Figure 1. In this example, wiring layer 110 includes power line 3, and wiring 110s is connected to power line 3.

In this example, the ground line 4 is provided in a layer even higher than the wiring layer 110. Although not shown in Figure 1, an interlayer insulating film is further provided on the wiring layer 110. The ground line 4 is provided on the uppermost interlayer insulating film and is insulated from the power line 3.

In this way, the light-emitting element 150 can be electrically connected to the wiring layer 110 provided above the light-emitting element 150 by using the via 161k. Furthermore, the light-emitting element 150 can be electrically connected to the wiring layer 110 provided above the light-emitting element 150 by providing an opening 158 that exposes the light-emitting surface 153S.

A method for manufacturing the image display device 1 of this embodiment will be described.
5A to 7B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment.
As shown in FIG. 5A , in the manufacturing method of the image display device 1 of this embodiment, a substrate (first substrate) 102 is prepared. The substrate 102 is a light-transmitting substrate, for example, a substantially rectangular glass substrate measuring approximately 1500 mm × 1800 mm. A graphene layer 1140 is formed on the first surface 102a. The graphene layer 1140 is a layer containing graphene, and is preferably formed by stacking several to approximately ten monolayer graphene layers. The graphene layer 1140, cut to an appropriate size and shape, is placed at a predetermined position on the first surface 102a and adsorbed to the substrate 102 due to the flatness of the first surface 102a. The graphene layer 1140 may be adhered to the first surface 102a, for example, with an adhesive or the like.

As shown in FIG. 5B, a buffer layer 1145 is formed over the graphene layer 1140 shown in FIG. 5A. The buffer layer 1145 is formed, for example, by a physical vapor deposition method such as sputtering. Providing the buffer layer 1145 can promote GaN crystal growth. The buffer layer 1145 can be made of any material that promotes GaN crystal growth, and can be an insulating material or a conductive material such as a metal. For example, the buffer layer can be a metal layer containing a single crystal of Hf, Cu, or the like. Furthermore, as in other embodiments described below, the formation of the buffer layer can be omitted and the semiconductor layer can be grown directly on the graphene layer.

The semiconductor layer 1150 is formed over the buffer layer 1145. The semiconductor layer 1150 is formed in the following order from the buffer layer 1145 side toward the positive direction of the Z axis: an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153. The semiconductor layer 1150 includes, for example, GaN, and _more specifically, _{InXAlYGa1 -X-YN} (0≦X, 0≦Y, X+Y<1). Crystal defects due to mismatch of crystal lattices are likely to occur in the initial growth stage of the semiconductor layer 1150, and crystals primarily composed of GaN generally exhibit n-type semiconductor characteristics. Therefore, by growing the n-type semiconductor layer 1151 on the buffer layer 1145, it is possible to improve yield.

The semiconductor layer 1150 can be formed using physical vapor deposition techniques such as evaporation, ion beam deposition, molecular beam epitaxy (MBE), and sputtering, with low-temperature sputtering being preferred. Low-temperature sputtering is preferable because it allows for lower temperatures during film formation when assisted by light or plasma. Epitaxial growth by MOCVD can sometimes exceed 1000°C. In contrast, low-temperature sputtering is known to enable epitaxial growth of GaN crystals, including the light-emitting layer, on the graphene layer 1140 at low temperatures of approximately 400°C to 700°C (see Non-Patent Documents 1 and 2, etc.). Such low-temperature sputtering is suitable for forming the semiconductor layer 1150 on a circuit substrate having TFTs and other devices formed using the LTPS process.

By growing a GaN semiconductor layer 1150 on the graphene layer 1140 and buffer layer 1145 using an appropriate deposition technique, a single-crystallized semiconductor layer 1150 including a light-emitting layer 1152 is formed on the buffer layer 1145. The graphene layer 1140 is cut to an appropriate size and shape and provided on the first surface 102a. Therefore, the buffer layer 1145 does not grow in areas where the graphene layer 1140 is not present, but grows over the graphene layer 1140. The semiconductor layer 1150 also does not grow in areas where the buffer layer 1145 is not present, but grows over the buffer layer 1145. Although not shown, during the growth of the buffer layer 1145 and the semiconductor layer 1150, amorphous deposits containing growth seed materials such as Al and Ga may accumulate in areas where the graphene layer 1140 is not present.

As shown in FIG. 6A, the semiconductor layer 1150 shown in FIG. 5B is etched into the desired shape to form the light-emitting element 150. In the process of forming the light-emitting element 150, the connection portion 151a is formed, and then other portions are formed by further etching. This allows the formation of a light-emitting element 150 having the connection portion 151a that protrudes in one direction from the n-type semiconductor layer 151 above the first surface 102a. To form the light-emitting element 150, for example, a dry etching process is used, and preferably anisotropic plasma etching (Reactive Ion Etching, RIE) is used. If deposits are formed in areas where the graphene layer 1140 is not present, the formed deposits are removed in the etching process of forming the light-emitting element 150.

The graphene layer 1140 shown in Figure 5B is shaped into a graphene sheet 140a having an outer periphery that roughly matches the outer periphery of the connection portion 151a by over-etching during the process of forming the connection portion 151a. The buffer layer 1145 shown in Figure 5B is also shaped into a buffer layer 145 having an outer periphery that roughly matches the outer periphery of the connection portion 151a by over-etching during the process of forming the connection portion 151a.

As shown in FIG. 6B, a first interlayer insulating film (first insulating film) 156 is formed to cover the first surface 102a, the graphene layer 140, the buffer layer 145, and the light-emitting element 150. The TFT lower film 106 is formed on the first interlayer insulating film 156, for example, by CVD or the like.

The TFT channel 104 is formed at a predetermined position on the TFT underlayer film 106. For example, in the LTPS process, the transistor 103 is formed as follows. First, amorphous silicon is deposited in the shape of the TFT channel 104. CVD, for example, is used to deposit the amorphous silicon. The deposited amorphous silicon film is then polycrystallized by laser annealing, forming the TFT channel 104.

Then, the source and drain electrodes of the TFT channel 104 are formed as p-type semiconductor regions by introducing impurities such as boron (B) into regions 104s and 104d using, for example, ion implantation techniques.

The insulating layer 105 is formed over the TFT underlayer film 106 and the TFT channel 104. The insulating layer 105 is formed, for example, by CVD. The gate 107 is formed above the TFT channel 104, with the insulating layer 105 interposed between them. An appropriate formation method is used to form the gate 107, depending on the material of the gate 107. For example, if the gate 107 is polycrystalline Si, the gate 107 is formed, like the TFT channel 104, by laser annealing amorphous Si to polycrystallize it. Alternatively, the gate 107 may be formed by etching a high-melting-point metal film, such as W or Mo, formed by sputtering.

The second interlayer insulating film (second insulating film) 108 is formed over the insulating layer 105 and the gate 107. An appropriate manufacturing method is applied to form the second interlayer insulating film 108 depending on the material of the second interlayer insulating film 108. For example, when the second interlayer insulating film 108 is made of _SiO2 , a technique such as ALD or CVD is used.

The flatness of the second interlayer insulating film 108 only needs to be such that the wiring layer 110 can be formed on the second interlayer insulating film 108, and a planarization process does not necessarily have to be performed. If a planarization process is not performed on the second interlayer insulating film 108, the number of processes can be reduced. For example, if there are areas around the light-emitting element 150 where the thickness of the second interlayer insulating film 108 is thin, the depth of the via hole 162k (described below) will be shallower, ensuring a sufficient opening diameter. This makes it easier to ensure electrical connection through the via, and reduces yield reductions due to poor electrical characteristics.

As shown in FIG. 7A, via hole 162k is formed to penetrate the second interlayer insulating film 108, insulating layer 105, TFT lower film 106, and first interlayer insulating film 156, reaching connection portion 151a. Opening 158 is formed to reach light-emitting surface 153S by removing part of second interlayer insulating film 108, part of insulating layer 105, part of TFT lower film 106, and part of first interlayer insulating film 156. Via hole 112d is formed to penetrate the second interlayer insulating film 108 and insulating layer 105, reaching region 104d. Via hole 112s is formed to penetrate the second interlayer insulating film 108 and insulating layer 105, reaching region 104s. The via holes and openings are formed, for example, by RIE or the like.

As shown in FIG. 7B, via 161k is formed by filling via hole 162k shown in FIG. 7A with a conductive material. Vias 111d and 111s are formed by filling via holes 112d and 112s shown in FIG. 7A with a conductive material, respectively. Thereafter, wiring layer 110 including wirings 110k, 110d, and 110s is formed on second interlayer insulating film 108. Wirings 110k, 110d, and 110s are connected to vias 161k, 111d, and 111s, respectively. Wiring layer 110 may be formed simultaneously with the formation of vias 161k, 111d, and 111s.

8A and 8B are schematic cross-sectional views illustrating a method for manufacturing an image display device according to a modified example of the present embodiment.
8A and 8B show steps for forming the subpixel 20a shown in FIG. 2. In this case, the steps from forming the second interlayer insulating film 108 to forming the via holes 162k, 112d, and 112s are the same as those described above. In the following description, it is assumed that the steps of FIG. 8A and 8B are performed after the step of FIG. 7A.

As shown in FIG. 8A, vias 161k, 111d, and 111s are formed by filling via holes 162k, 112d, and 112s shown in FIG. 7A with a conductive material. Then, a wiring layer 110 including wirings 110k, 110d1, and 110s is formed. Here, a portion of wiring 110d1 is connected to via 111d. Meanwhile, another portion of wiring 110d1 is not directly connected to light-emitting surface 153S and is located away from opening 158. As in the first embodiment, vias 161k, 111d, and 111s and wiring layer 110 may be formed simultaneously.

As shown in FIG. 8B, a translucent electrode 159d is formed over the wiring 110d1 and the light-emitting surface 153S. As in this example, the light-emitting surface 153S is preferably roughened by wet etching or the like before the translucent electrode 159d is formed. Note that the roughening process may be performed immediately after the opening 158 is formed. The translucent electrode 159d is also formed between the wiring 110d1 and the light-emitting surface 153S, and electrically connects the wiring 110d1 and the light-emitting surface 153S. The translucent electrode 159s is formed over the wiring 110s. The translucent electrodes 159d and 159s are formed simultaneously. When a translucent electrode is formed on the wiring 110k, it is formed simultaneously with the translucent electrodes 159d and 159s.

After this, upper structures such as color filters are formed to form subpixel 20a, a modified example of the image display device of the first embodiment.

For example, the circuit in Figure 3 is a drive circuit that drives a light-emitting element 150 using a selection transistor 24, a drive transistor 26, and a capacitor 28. Such a drive circuit is formed within the subpixels 20, 20a. Parts of the circuits other than the drive circuit are formed outside the subpixels 20, 20a, for example, on the periphery of the display area 2. For example, the row selection circuit 5 shown in Figure 3 is formed simultaneously with the drive transistors, selection transistors, etc., and is formed on the periphery of the display area 2. In other words, the row selection circuit 5 can be incorporated simultaneously using the manufacturing process described above.

The signal voltage output circuit 7 is preferably incorporated into a semiconductor device manufactured using a manufacturing process that enables high integration through microfabrication. The signal voltage output circuit 7 is mounted on a separate substrate along with a CPU and other circuit elements, and is interconnected with the subpixels 20, 20a via connectors or the like provided on the periphery of the display area, for example, before or after the incorporation of the color filters described below.

In the image display device 1 of this embodiment, each light-emitting element 150 can form an image in the display area 2 by emitting light upward from the light-emitting surface 153S. However, if light is scattered below the light-emitting surface 153S, the light-emitting efficiency is substantially reduced because the substrate 102 is translucent. Therefore, for example, by providing a light-reflecting film or light-reflecting plate on the surface opposite the first surface 102a of the substrate 102, the light scattered toward the substrate 102 can be reflected toward the light-emitting surface 153S. Such a light-reflecting film or light-reflecting plate may be provided on the substrate 102, or may be provided inside a case, frame, or the like that secures the image display device 1.

9A to 9C are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment.
9, the diagram above the arrow shows a configuration including the color filter 180, and the diagram below the arrow shows a structure including the light-emitting element 150 and the like formed in the above-described process. In Fig. 9, the arrows indicate the process of bonding the color filter to the structure including the light-emitting element 150 and the like.
In Fig. 9, to avoid complexity, components other than those on the illustrated substrate 102 are omitted. The omitted components are the circuit 101 including the TFT channel 104, wiring layer 110, etc., shown in Fig. 1, and via 161k. Fig. 9 also shows some color conversion members such as color filter 180. In the explanations related to Figs. 9 to 10D, a structure including the substrate 102, light-emitting element 150, first interlayer insulating film 156, TFT lower layer film 106, insulating layer 105, second interlayer insulating film 108, surface resin layer 170, and the components whose illustrations are omitted will be referred to as structure 1192.

As shown in FIG. 9 , one surface of the color filter (wavelength conversion member) 180 is adhered to the structure 1192. The other surface of the color filter 180 is adhered to a glass substrate 186. A transparent thin-film adhesive layer 188 is provided on one surface of the color filter 180, and the color filter 180 is adhered to the exposed surface of the surface resin layer 170 of the structure 1192 via the transparent thin-film adhesive layer 188.

In this example, the color filter 180 has color conversion sections arranged in the positive direction of the X axis in the order of red, green, and blue. For red, a red color conversion layer 183R is provided as the first layer, and for green, a green color conversion layer 183G is provided as the first layer, with a filter layer 184 provided as the second layer in each case. For blue, a single color conversion layer 183B may be provided, or a filter layer 184 may be provided. A light-shielding section 181 is provided between each color conversion section, but it goes without saying that the frequency characteristics of the filter layer 184 can be changed for each color of the color conversion section.

The color filter 180 is attached to the structure 1192 by aligning the positions of the color conversion layers 183R, 183G, and 183B of each color with the position of the light-emitting element 150.

10A to 10D are schematic cross-sectional views showing a modified example of the method for manufacturing the image display device of this embodiment.
10A to 10D show a method for forming a color filter by an inkjet method.

As shown in Figure 10A, a structure 1192 is prepared in which components such as a light-emitting element 150 are formed on a substrate 102.

As shown in Figure 10B, a light-shielding portion 181 is formed on the structure 1192. The light-shielding portion 181 is formed using, for example, screen printing or photolithography techniques.

As shown in Figure 10C, a phosphor corresponding to the emitted color is ejected from an inkjet nozzle to form a color conversion layer 183. The phosphor colors the areas where the light-shielding portion 181 is not formed. The phosphor is, for example, a fluorescent paint made from a general phosphor material, a perovskite phosphor material, or a quantum dot phosphor material. When using a perovskite phosphor material or a quantum dot phosphor material, it is preferable because it can realize each emitted color, has high monochromaticity, and high color reproducibility. After drawing with the inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film when colored is set to be thinner than the thickness of the light-shielding portion 181.

As already explained, for blue-emitting subpixels, if no color conversion section is formed, the color conversion layer 183 is not formed. Furthermore, when forming a blue color conversion layer for blue-emitting subpixels, if only one layer of color conversion section is required, the thickness of the blue phosphor coating is preferably approximately the same as the thickness of the light-shielding section 181.

As shown in Figure 10D, the paint for the filter layer 184 is sprayed from an inkjet nozzle. The paint is applied over the phosphor coating. The total thickness of the phosphor and paint coatings is approximately the same as the thickness of the light-shielding portion 181.

Whether it is a film-type color filter or an inkjet-type color filter, it is desirable for the color conversion layer 183 to be as thick as possible in order to improve color conversion efficiency. On the other hand, if the color conversion layer 183 is too thick, the emitted light of the color-converted light will approximate Lambertian, while the emission angle of the unconverted blue light will be limited by the light-shielding portion 181. This causes the problem of viewing-angle dependency in the display color of the displayed image. In order to match the light distribution of the unconverted blue light to the light distribution of the subpixels that have the color conversion layer 183, it is desirable for the thickness of the color conversion layer 183 to be approximately half the opening size of the light-shielding portion 181.

For example, in the case of a high-resolution image display device with a resolution of approximately 250 ppi (pitch per inch), the pitch of the subpixels 20 is approximately 30 μm, so the thickness of the color conversion layer 183 is preferably approximately 15 μm. Here, if the color conversion material is made of spherical phosphor particles, it is preferable that they be stacked in a close-packed structure to suppress light leakage from the light-emitting element 150. To achieve this, at least three particle layers are required. Therefore, the particle size of the phosphor material that makes up the color conversion layer 183 is preferably approximately 5 μm or less, and more preferably approximately 3 μm or less.

FIG. 11 is a schematic perspective view illustrating the image display device according to this embodiment.
11 , the image display device of this embodiment has a light-emitting circuit section 172 having a large number of sub-pixels 20 provided on a substrate 102. A color filter 180 is provided on the light-emitting circuit section 172. Other embodiments and modified examples described later also have a configuration similar to that shown in FIG.

The effects of the image display device 1 of this embodiment will be described.
In the manufacturing method of the image display device 1 of this embodiment, the light emitting element 150 is formed by etching the semiconductor layer 1150 that has been crystal-grown on the substrate 102. Thereafter, the light emitting element 150 is covered with a first interlayer insulating film 156, and the circuit 101 including circuit elements such as the transistor 103 that drives the light emitting element 150 is fabricated on the first interlayer insulating film 156. Therefore, the manufacturing process is significantly shortened compared to the case where individual light emitting elements are transferred to the substrate 102.

In the manufacturing method of the image display device 1 of this embodiment, the graphene layer 1140 formed on the substrate 102 can serve as a seed for crystal growth of the buffer layer 1145 and the semiconductor layer 1150. If the first surface 102a of the substrate 102 is sufficiently flat, the first surface 102a can easily adsorb and fix the graphene layer 1140. This simplifies the production means and allows the process to be configured without contaminating the production site, thereby achieving substantially high productivity.

For example, an image display device with 4K resolution has more than 24 million subpixels, and an image display device with 8K resolution has more than 99 million subpixels. Forming such a large number of light-emitting elements individually and mounting them on a circuit board would require an enormous amount of time. Therefore, it is difficult to realize an image display device using micro LEDs at a realistic cost. Furthermore, mounting a large number of light-emitting elements individually reduces yield due to poor connections during mounting, unavoidably increasing costs.

In contrast, in the manufacturing method of the image display device 1 of this embodiment, the light-emitting element 150 is formed after the entire semiconductor layer 1150 is formed on the graphene layer 1140 formed on the substrate 102, so the transfer step of the light-emitting element 150 can be eliminated. Therefore, in the manufacturing method of the image display device 1 of this embodiment, the time for the transfer step can be shortened and the number of steps can be reduced compared to conventional manufacturing methods.

The semiconductor layer 1150, which has a uniform crystal structure, is grown on the buffer layer 1145 formed on the graphene layer 1140. Therefore, by appropriately patterning the graphene layer 1140, the light-emitting element 150 can be positioned in a self-aligned manner. This eliminates the need to align the light-emitting element on the substrate 102, facilitates miniaturization of the light-emitting element 150, and is suitable for high-definition displays.

After the light-emitting element is formed directly on the substrate 102 by etching or the like, the light-emitting element 150 is electrically connected to the circuit element formed on the upper layer of the light-emitting element 150 by forming a via, thereby achieving a uniform connection structure and suppressing a decrease in yield.

In this embodiment, for example, the glass substrate formed as described above can be covered with an interlayer insulating film, and then driving circuits and scanning circuits including TFTs can be formed on the planarized surface using an LTPS process or the like. This has the advantage of allowing the use of existing flat panel display manufacturing processes and plants.

In this embodiment, the light-emitting element 150 formed below the transistor 103, etc., can be electrically connected to the power supply line, ground line, driving transistor, etc. formed above by forming vias that penetrate the first interlayer insulating film 156, the TFT lower layer film 106, the insulating layer 105, and the second interlayer insulating film 108. By using this technologically established multilayer wiring technology, a uniform connection structure can be easily achieved, improving yield. Therefore, yield reduction due to poor connections of the light-emitting element, etc. is suppressed.

Second Embodiment
FIG. 12 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.
This embodiment differs from the other embodiments described above in that a light-reflecting layer 120 including a light-reflecting plate 120a is provided on the first surface 102a, and a light-emitting element 150 is provided on the light-reflecting plate 120a via an insulating layer 114. This embodiment differs from the other embodiments described above in that an n-type semiconductor layer 251 provides a light-emitting surface 251S. This embodiment differs from the other embodiments described above in that the light-emitting element 250 is driven by an n-type transistor 203. The same components as those in the other embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

As shown in FIG. 12, the subpixel 220 of the image display device of this embodiment includes a substrate 102, a light-reflecting layer 120, a graphene layer 140, a light-emitting element 250, a first interlayer insulating film 156, a transistor 203, a second interlayer insulating film 108, a via 261a, and a wiring layer 110.

The light-reflecting layer 120 is provided on the first surface 102a. The light-reflecting layer 120 includes a light-reflecting plate 120a. The light-reflecting plate (first part) 120a is provided on the first surface 102a and is a film-like, layer-like, or plate-like member that has a rectangular or any polygonal, elliptical, circular, or other shape in an XY plane view.

The light-reflecting layer 120 includes multiple light-reflecting plates 120a, and in this example, a light-reflecting plate 120a is provided for each light-emitting element 250. In this example, the multiple light-reflecting plates 120a are separated from each other, but they may also be connected to each other.

The outer periphery of the light-reflecting plate 120a is set to include the outer periphery of the light-emitting element 250 when the light-emitting element 250 is projected in the XY plane. In other words, in the XY plane, the outer periphery of the light-emitting element 250 is disposed within the outer periphery of the light-reflecting plate 120a. One light-reflecting plate 120a may be provided for one light-emitting element 250, or one light-reflecting plate 120a may be provided for multiple light-emitting elements 250. The multiple light-reflecting plates 120a may not be separated one by one, but may be connected in a lattice pattern, for example. The light-reflecting layer 120 may have a single light-reflecting plate 120a. The single light-reflecting plate 120a is provided, for example, over the entire display area 2 shown in Figure 13 described below.

The light-reflecting plate 120a is made of a material that has light-reflecting properties. The light-reflecting plate 120a is made of a metal material such as Ag or an alloy containing Ag. Any suitable material that has light-reflecting properties can be used, not limited to Ag.

An insulating layer 114 is provided over the first surface 102a, the light-reflecting layer 120, and the light-reflecting plate 120a. The insulating layer 114 is formed of an oxide film such as _SiO2 . The insulating layer 114 is provided to insulate the light-reflecting plate 120a from the light-emitting element 250. The insulating layer 114 also provides a planarized surface for forming the graphene sheet 140a.

The graphene layer 140, including the graphene sheet 140a, is provided on the insulating layer 114. The light-reflecting plate 120a is provided between the first surface 102a and the graphene layer 140, and the light-emitting element 250 is provided on the light-reflecting plate 120a via the graphene sheet 140a and the insulating layer 114. The light-emitting element 250 is provided directly above the light-reflecting plate 120a.

By providing the light-reflecting plate 120a in this manner, light scattered downward from the light-emitting element 250 is reflected upward by the light-reflecting plate 120a. Therefore, the luminous efficiency of the light-emitting element 250 is substantially improved.

The light-emitting element 250 includes a light-emitting surface 251S. The light-emitting element 250 is a rectangular or cylindrical element having a bottom surface 253B on the first surface 102a. The light-emitting surface 251S is the surface opposite the bottom surface 253B. The bottom surface 253B is the surface that contacts the graphene sheet 140a.

Light-emitting element 250 includes a p-type semiconductor layer (first semiconductor layer) 253, a light-emitting layer 252, and an n-type semiconductor layer (second semiconductor layer) 251. P-type semiconductor layer 253, light-emitting layer 252, and n-type semiconductor layer 251 are stacked in this order from bottom surface 253B toward light-emitting surface 251S. In this embodiment, light-emitting surface 251S is provided by n-type semiconductor layer 251. Because n-type semiconductor layer 251 can have a lower resistance than p-type semiconductor layer 253, it can be made thicker. This makes it easier to roughen light-emitting surface 251S.

The light-emitting element 250 includes a connection portion 253a. The connection portion 253a is provided on the insulating layer 114, protruding in one direction from the p-type semiconductor layer 253. As in the other embodiments described above, the connection portion 253a may protrude in multiple directions or may protrude around the outer periphery of the p-type semiconductor layer 253. The height of the connection portion 253a is the same as or lower than the p-type semiconductor layer 253, and the light-emitting element 250 is formed in a stepped shape. The connection portion 253a is p-type and electrically connected to the p-type semiconductor layer 253. The connection portion 253a is connected to one end of the via 261a, electrically connecting the p-type semiconductor layer 253 to the via 261a.

The light-emitting element 250 has a shape in the XY plane similar to that of the light-emitting element 150 in the other embodiments described above. An appropriate shape is selected depending on the layout of the circuit elements, etc. The shape of the light-reflecting plate 120a in the XY plane can be any shape as described above, and an appropriate shape is selected depending on the layout of the circuit elements, etc.

Light-emitting element 250 is a light-emitting diode similar to light-emitting element 150 in the other embodiments described above. That is, the wavelength of light emitted by light-emitting element 250 is, for example, blue light of approximately 467 nm ± 30 nm, or blue-violet light of approximately 410 nm ± 30 nm. The wavelength of light emitted by light-emitting element 250 is not limited to the above values and can be any appropriate value.

The transistor 203 is provided on the TFT lower layer film 106. The transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. Preferably, the transistor 203 is formed by an LTPS process or the like, as in the other embodiments described above. In this embodiment, the circuit 101 includes the TFT channel 204, the insulating layer 105, the second interlayer insulating film 108, the vias 111s and 111d, and the wiring layer 110.

The TFT channel 204 includes regions 204s, 204i, and 204d. Regions 204s, 204i, and 204d are provided on the TFT underlayer film 106. Regions 204s and 204d are doped with impurities such as phosphorus (P) by ion implantation or the like to form n-type semiconductor regions. Region 204s is in ohmic contact with via 111s. Region 204d is in ohmic contact with via 111d.

The gate 107 is provided on the TFT channel 204 via an insulating layer 105. The insulating layer 105 insulates the TFT channel 204 from the gate 107.

In transistor 203, when a voltage higher than that of region 204s is applied to gate 107, a channel is formed in region 204i. The current flowing between regions 204s and 204d is controlled by the voltage applied to region 204s by gate 107. The TFT channel 204 and gate 107 are formed using the same materials and manufacturing methods as the TFT channel 104 and gate 107 in the other embodiments described above.

The wiring layer 110 includes wirings 110s, 110d1, and 210a. Wirings 110s and 110d1 are the same as those in the modified example of the first embodiment described above in Figure 2. A portion of wiring 210a is provided above connection portion 253a. Another portion of wiring 210a extends to, for example, power line 3 shown in Figure 13 described below, and is connected to power line 3.

Vias 111s and 111d are provided through the second interlayer insulating film 108. Via 111s is provided between wiring 110s and region 204s. Via 111s electrically connects wiring 110s and region 204s. Via 111d is provided between wiring 110d1 and region 204d. Via 111d electrically connects wiring 110d1 and region 204d. Vias 111s and 111d are formed using the same materials and manufacturing methods as in the other embodiments described above.

The via 261a penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer 106, and the first interlayer insulating film 156. The via 261a is provided between the wiring 210a and the connection portion 253a, and electrically connects the wiring 210a and the connection portion 253a.

The wiring 110s is electrically connected to, for example, the ground line 4 shown in Figure 13 described below. The wiring 110d1 is electrically connected to the n-type semiconductor layer 251 via the transparent electrode 159d.

In this embodiment, the translucent electrode 159d is provided over the light-emitting surface 251S of the roughened n-type semiconductor layer 251. The translucent electrode 159d is provided over the wiring 110d1. The translucent electrode 159d is also provided between the light-emitting surface 251S and the wiring 110d, and electrically connects the n-type semiconductor layer 251 and the wiring 110d.
As in the other embodiments described above, the wiring 110d may be extended and directly connected to the n-type semiconductor layer 251, as in the example shown in FIG.

FIG. 13 is a schematic block diagram illustrating an image display device according to this embodiment.
13, an image display device 201 of this embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. In the display area 2, as in the other embodiments described above, for example, subpixels 220 are arranged in a lattice pattern on the XY plane.

As in the other embodiments described above, pixel 10 includes multiple subpixels 220 that emit light of different colors. Subpixel 220R emits red light. Subpixel 220G emits green light. Subpixel 220B emits blue light. The emission color and brightness of a single pixel 10 are determined by the three types of subpixels 220R, 220G, and 220B emitting light at the desired brightness.

One pixel 10 includes three subpixels 220R, 220G, and 220B, which are arranged linearly on the X axis, as in this example. Each pixel 10 may have subpixels of the same color arranged in the same column, or, as in this example, may have subpixels of different colors arranged in different columns.

The subpixel 220 includes a light-emitting element 222, a selection transistor 224, a drive transistor 226, and a capacitor 228. In FIG. 13, the selection transistor 224 may be labeled T1, the drive transistor 226 may be labeled T2, and the capacitor 228 may be labeled Cm.

In this embodiment, the light-emitting element 222 is provided on the power supply line 3 side, and the drive transistor 226 connected in series to the light-emitting element 222 is provided on the ground line 4 side. In other words, the drive transistor 226 is connected to a lower potential side than the light-emitting element 222. The drive transistor 226 is an n-channel transistor.

A selection transistor 224 is connected between the gate electrode of the drive transistor 226 and the signal line 208. A capacitor 228 is connected between the gate electrode of the drive transistor 226 and the ground line 4.

The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage of a different polarity to the signal line 208 in order to drive the driving transistor 226, which is an n-channel transistor.

In this embodiment, the polarity of the drive transistor 226 is n-channel, and therefore the polarity of the signal voltage, etc., differs from the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select one row from the array of m rows of subpixels 220. The signal voltage output circuit 207 supplies a signal voltage having the required analog voltage value to each subpixel 220 in the selected row. The drive transistor 226 of the subpixel 220 in the selected row passes a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light at a brightness corresponding to the current flowing through the light-emitting element 222.

A method for manufacturing the image display device of this embodiment will be described.
14A to 17B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment.

As shown in FIG. 14A, the light-reflecting layer 120 is formed on the first surface 102a. The light-reflecting layer 120 may be formed by sputtering or the like, or by applying Ag paste or the like to the shape of the light-reflecting plate 120a and then firing it. The light-reflecting plate (first portion) 120a of the light-reflecting layer 120 is provided at a position where the light-emitting element 250 will be formed.

As shown in FIG. 14B, the insulating layer 114 is formed over the first surface 102a and the light-reflecting layer 120. The insulating layer 114 is formed by CVD or the like. The exposed surface of the insulating layer 114 is preferably planarized by CMP (Chemical Mechanical Polishing) or the like in order to adsorb and attach the graphene layer 1140.

As shown in Figure 14C, a graphene layer 1140 is formed on the insulating layer 114. The graphene layer 1140 is then preferably cut to a size sufficiently larger than the area of the light-emitting element 250 to be formed on the graphene layer 1140, and then adsorbed and attached to the insulating layer 114.

As shown in FIG. 15A, the semiconductor layer 1150 is formed over the graphene layer 1140. The semiconductor layer 1150 is formed in the following order from the graphene layer 1140 toward the positive direction of the Z axis: the p-type semiconductor layer 1153, the light-emitting layer 1152, and the n-type semiconductor layer 1151. In this embodiment, the semiconductor layer 1150 differs from the other embodiments described above in that formation begins with the p-type semiconductor layer 1153. However, the semiconductor layer 1150 can be formed using the same techniques as the other embodiments described above. That is, physical vapor deposition is used, and preferably low-temperature sputtering is used. Alternatively, physical vapor deposition methods such as evaporation, ion beam deposition, and MBE may be used to form the semiconductor layer 1150.

As with the other embodiments described above, deposits containing growth seed material may be deposited in areas where graphene layer 1140 is not present.

As shown in Figure 15B, the light-emitting element 250 is formed into the desired shape by dry etching or the like of the semiconductor layer 1150 shown in Figure 15A. In the process of forming the light-emitting element 250, the connection portion 253a is formed, and then other portions are formed by further etching. The graphene layer 1140 shown in Figure 15A is over-etched when the connection portion 253a is formed. Therefore, the periphery of the graphene sheet 140a is shaped so that it roughly matches the periphery of the light-emitting element 250.

As shown in FIG. 16A, a first interlayer insulating film 156 is formed covering the graphene layer 140, the insulating layer 114 and the light-emitting element 250.

As shown in FIG. 16B, the TFT lower layer film 106 is formed over the first interlayer insulating film 156 by CVD or the like. The TFT channel 204 is formed on the planarized TFT lower layer film 106. An insulating layer 105 is formed to cover the TFT lower layer film 106 and the TFT channel 204. A gate 107 is formed on the TFT channel 204 with the insulating layer 105 interposed therebetween. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107.

As shown in FIG. 17A, via hole 162a is formed to penetrate second interlayer insulating film 108, insulating layer 105, TFT lower layer film 106, and first interlayer insulating film 156, reaching the surface of connection portion 253a. Opening 158 is formed to reach light-emitting surface 251S by removing part of second interlayer insulating film 108, part of insulating layer 105, part of TFT lower layer film 106, and part of first interlayer insulating film 156. After forming opening 158, light-emitting surface 251S may be roughened. Via hole 112d is formed to penetrate second interlayer insulating film 108 and insulating layer 105, reaching region 204d. Via hole 112s is formed to penetrate second interlayer insulating film 108 and insulating layer 105, reaching region 204s. The via holes and openings are formed, for example, by RIE or the like.

As shown in FIG. 17B, via 261a is formed by filling via hole 162a shown in FIG. 17A with a conductive material. Vias 111d and 111s are also formed by filling via holes 112d and 112s shown in FIG. 17A with a conductive material, respectively. Thereafter, wiring layer 110 including wirings 210a, 110d1, and 110s is formed. Wirings 210a, 110d1, and 110s are connected to vias 261a, 111d, and 111s, respectively. Wiring layer 110 may be formed simultaneously with the formation of vias 261a, 111d1, and 111s.

A translucent conductive film including translucent electrodes 159d and 159s is formed to cover the second interlayer insulating film 108, the light-emitting surface 251S, and the wiring layer 110. The translucent electrode 159d is formed over the wiring 110d1 and the light-emitting surface 251S, and is also formed between the wiring 110d1 and the light-emitting surface 251S so as to electrically connect the wiring 110d1 and the light-emitting surface 251S. The translucent electrode 159s is formed over the wiring 110s. Although not shown in this embodiment, a translucent electrode may also be formed over the wiring 210a.

Then, the subpixels 220 of the image display device 201 of this embodiment are formed by providing a color filter (wavelength conversion member) 180, etc.

The effects of the image display device of this embodiment will be described.
In the image display device of this embodiment, similarly to the other embodiments described above, the time required for the transfer process for forming the light emitting element 250 can be shortened, and the number of processes can be reduced. In addition, by using the n-type semiconductor layer 251 as the light emitting surface 251S, the light emitting surface 251S can be sufficiently roughened. Therefore, the light emitting efficiency can be improved, and an increase in loss due to contact resistance can be suppressed.

(Third embodiment)
FIG. 18 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.
This embodiment differs from the other embodiments described above in that a light emitting element 250 having an n-type semiconductor layer 251 as a light emitting surface 251S is driven by a p-type transistor 103. The same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

As shown in FIG. 18, the subpixel 320 of the image display device of this embodiment includes a substrate 102, a light-reflecting layer 120, a graphene layer 140, a light-emitting element 250, a first interlayer insulating film 156, a transistor 103, a second interlayer insulating film 108, a via 361a, and a wiring layer 110. The transistor 103 is a p-channel TFT. The light-emitting element 250 provides a light-emitting surface 251S formed by an n-type semiconductor layer 251.

The light-emitting element 250 is provided on the light-reflecting plate 120a via the graphene sheet 140a and the insulating layer 114. The light-reflecting plate 120a is provided in the same configuration as in the other embodiments described above. The light-reflecting plate 120a is provided directly below the light-emitting element 250. The outer periphery of the light-reflecting plate 120a is set to include the outer periphery of the light-emitting element 250 when projected in the XY plane. The light-reflecting plate 120a reflects scattered light downward from the light-emitting element 250 toward the light-emitting surface 251S, thereby substantially improving the light-emitting efficiency.

The light-emitting element 250 is a prismatic or cylindrical element having a bottom surface 253B on the first surface 102a. The light-emitting surface 251S is the surface opposite the bottom surface 253B. The bottom surface 253B is the surface in contact with the graphene sheet 140a.

The light-emitting element 250 includes a p-type semiconductor layer (first semiconductor layer) 253, a light-emitting layer 252, and an n-type semiconductor layer (second semiconductor layer) 251. The p-type semiconductor layer 253, the light-emitting layer 252, and the n-type semiconductor layer 251 are stacked in this order from the bottom surface 253B toward the light-emitting surface 251S. The p-type semiconductor layer 253 includes a connection portion 253a. The connection portion 253a is provided so as to protrude from the p-type semiconductor layer 253 in one direction above the insulating layer 114. The connection portion 253a is connected to one end of the via 361a, and electrically connects the p-type semiconductor layer 253 to the via 361a.

The configuration of transistor 103 is the same as in the first embodiment. Detailed description of the configuration of transistor 103 will be omitted.

The wiring layer 110 is formed on the second interlayer insulating film 108. The wiring layer 110 includes wirings 310k, 310a, 110d1, and 110s. Wirings 310a and 310k are provided above and in close proximity to the light-emitting element 250. Wiring 310a is provided above the connection portion 253a. Wiring 310k is provided in a position that does not intersect with wiring 310a.

The via 361a penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer 106, and the first interlayer insulating film 156. The via 361a is provided between the wiring (third wiring) 310a and the connection portion 253a. The via 361a electrically connects the wiring 310a and the connection portion 253a.

Vias 111d and 111s are provided in the same manner as in the other embodiments described above.

The transparent electrode 359k is provided over the wiring 310k. The transparent electrode 359k is provided over the light-emitting surface 251S. The transparent electrode 359k is also provided between the wiring 310k and the light-emitting surface 251S, electrically connecting the wiring 310k and the light-emitting surface 251S. The wiring 310k and the transparent electrode 359k are connected to, for example, the ground line 4 shown in FIG. 3. Therefore, the n-type semiconductor layer 251 is electrically connected to the ground line 4 via the light-emitting surface 251S, the transparent electrode 359k, and the wiring (fourth wiring) 310k.

A transparent electrode 359d is provided over the wiring 310a. A transparent electrode 359d is provided over the wiring 110d1. A transparent electrode 359k is also provided between the wiring 310a and the wiring 110d1, electrically connecting the wiring 310a and the wiring 110d1. Therefore, the p-type semiconductor layer 253 is electrically connected to the region 104d via the connection portion 253a, the via 361a, the wiring 310a, the transparent electrode 359d, the wiring 110d1, and the via 111d.

The transparent electrode 159s is provided over the wiring 110s. The wiring 110s and the transparent electrode 159s are connected to the power supply line 3 shown in FIG. 3, for example. Therefore, the region 104s of the transistor 103 is electrically connected to the power supply line 3 via the via 111s, the wiring 110s, and the transparent electrode 159s.

The vias 361a, 111d, 111s and the wiring 310k, 310a, 110d1, 110s are formed using the same materials and manufacturing methods as in the other embodiments and their variations described above.

As in the other embodiments described above, a color filter 180 and the like are further provided.

A method for manufacturing the image display device of this embodiment will be described.
19A to 20B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment.
The steps can be the same as those in the second embodiment up to the step of forming the graphene layer 1140 on the substrate 102 on which the light reflecting layer 120 and the insulating layer 114 have been formed, and then forming the semiconductor layer 1150 on the graphene layer 1140. In the following description, it is assumed that the steps in Figures 19A to 20B are performed in addition to the steps in Figure 15A and subsequent steps.

As shown in Figure 19A, the semiconductor layer 1150 shown in Figure 15A is processed into the desired shape to form the light-emitting element 250. After the connection portion 253a is formed, other portions of the light-emitting element 250 are formed. The graphene layer 1140 shown in Figure 15A is over-etched when forming the connection portion 253a, and the graphene sheet 140a is shaped to have an outer periphery that approximately matches the outer periphery of the light-emitting element 250. In this example, the connection portion 253a and the graphene sheet 140a are formed so as to protrude in one direction above the insulating layer 114 when viewed from the light-emitting surface 251S.

As shown in Figure 19B, a first interlayer insulating film 156 is formed to cover the insulating layer 114, the graphene sheet 140a, and the light-emitting element 250. As in the first embodiment, a TFT lower layer film 106 is formed, a TFT channel 104 is formed, an insulating layer 105 is formed, and a gate 107 is formed. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and the gate 107.

As shown in Figure 20A, the via hole 362a is formed so as to penetrate the second interlayer insulating film 108, the insulating layer 105, the TFT lower film 106, and the first interlayer insulating film 156 and reach the connection portion 253a. The opening 158 and the via holes 112d and 112s are formed in the same manner as in the other embodiments described above.

As shown in FIG. 20B, the via holes 362a, 112d, and 112s shown in FIG. 20A are filled with a conductive material to form vias 361a, 111d, and 111s. The wiring layer 110 including wirings 310k, 310a, 110d1, and 110s is formed on the second interlayer insulating film 108. The wirings 310a, 110d1, and 110s are connected to the vias 361a, 111d, and 111s, respectively. A translucent conductive film is formed on the wiring layer 110, and translucent electrodes 359k, 359d, and 159s are formed. The translucent electrode 359k is formed over the wiring 310k and the light-emitting surface 251S, and is also formed between the wiring 310k and the light-emitting surface 251S. The translucent electrode 359d is formed over the wiring 310a and the wiring 110d1, and is also formed between the wiring 310a and the wiring 110d1. The translucent electrode 159s is formed over the wiring 110s.

The image display device of this embodiment allows for a circuit configuration in which the n-type semiconductor layer 251 serves as the light-emitting surface 251S, while the p-channel transistor 103 drives the light-emitting element 250. This improves the degree of freedom in circuit configuration and circuit layout, shortening the design period for the image display device.

(Fourth embodiment)
FIG. 21 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.
The image display device of this embodiment includes a flexible substrate 402 instead of a glass substrate. Light-emitting elements and circuit elements such as transistors are formed on a first surface 402a of the substrate 402. In other respects, the image display device is similar to the other embodiments described above, and the same components are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

As shown in FIG. 21 , the image display device of this embodiment includes a subpixel 420. The subpixel 420 includes a substrate 402. The substrate 402 includes a first surface 402a. When the substrate 402 is made of a resin such as a polyimide resin, a layer 113 containing a silicon compound such as _SiO2 is formed on the first surface 402a. The layer 113 containing a silicon compound is provided between the substrate 402 and the graphene layer 140. The light-reflecting layer 120 and the light-reflecting plate 120a are formed on the layer 113 containing a silicon compound. The layer 113 containing a silicon compound is provided to improve adhesion between the substrate 402 made of a resin and the light-reflecting layer 120 made of a metal material.

An insulating layer 114 is formed on the silicon compound-containing layer 113 and the light-reflecting layer 120. The insulating layer 114 is planarized by CMP or the like.

The light-emitting element 250 is mounted on the light-reflecting plate 120a via the graphene sheet 140a and the insulating layer 114. In this example, the structure and components above the insulating layer 114 are the same as those in the second embodiment described above, and detailed description will be omitted.

The substrate 402 is flexible. The substrate 402 is formed, for example, from a polyimide resin. The first interlayer insulating film 156, the second interlayer insulating film 108, the wiring layer 110, and the like are preferably formed from materials with a certain degree of flexibility, depending on the flexibility of the substrate 402. Note that the wiring layer 110, which has the longest wiring length, is at the highest risk of breakage when bent. When the image display device is bent, the inner surface contracts due to compressive stress, while the outer surface expands due to tensile stress. A neutral plane exists within the image display device where these stresses cancel each other out, and no expansion or contraction due to bending stress occurs at the neutral plane. Therefore, by placing the wiring layer 110 on the neutral plane, the risk of breakage of the wiring layer 110 can be avoided. If necessary, multiple protective films may be provided on the front and back surfaces of the image display device to reduce bending stress. It is also desirable to adjust the film thickness, film quality, material, etc. of these protective films so that the neutral plane overlaps the position of the wiring layer 110 .

In this example, the structure and components above the insulating layer 114 are the same as in the second embodiment, but may be the same as in other embodiments or variations.

A method for manufacturing the image display device of this embodiment will be described.
22A and 22B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment.
As shown in FIG. 22A , in this embodiment, a substrate 1002 different from that in the other embodiments described above is prepared. The substrate (first substrate) 1002 includes two substrate layers 102 and 402. The substrate 102 is a light-transmitting substrate, such as a glass substrate. The substrate (second substrate) 402 is provided on the first surface 102 a of the substrate 102. For example, the substrate 402 is formed by applying a polyimide material to the first surface 102 a of the substrate 102 and baking the applied material. Before forming the substrate 402, an inorganic film such as _SiNx may be formed on the substrate 102. In this case, the substrate 402 is formed by applying a polyimide material to the inorganic film and baking the applied material. A layer 113 containing a silicon compound is formed over the first surface 402 a of the substrate 402. The first surface 402 a of the substrate 402 is the surface opposite to the surface on which the substrate 102 is provided.

The upper structure of the subpixel 420 is formed on such a substrate 1002 by applying the processes described above, for example, in Figures 14A to 17B and Figures 9 to 10D.

As shown in Figure 22B, the substrate 102 is removed from the structure on which the upper structure, including a color filter (not shown), has been formed. The substrate 102 can be removed, for example, by laser lift-off.

The substrate 102 can be removed at any appropriate time, not just at the time mentioned above. If the substrate 402 is made of organic resin and there is a high-temperature process to be performed after removing the substrate 102, the substrate 402 may shrink or otherwise be damaged by the heat of such a process. Therefore, it is preferable to remove the substrate 102 in a process that follows such a high-temperature process. For example, it is preferable to remove the substrate 102 after the process of forming the wiring layer 110 has been completed. Removing the substrate 102 at an appropriate time may reduce defects such as cracks and chips during the manufacturing process.

The effects of the image display device of this embodiment will be described.
As with the other embodiments described above, the image display device of this embodiment has the effect of shortening the time required for the transfer process for forming the light-emitting element 150 and reducing the number of processes, and also has the following effect: Since the substrate 402 is flexible, it can be bent into an image display device, and can be attached to a curved surface or used in a wearable device or the like without any discomfort.

Fifth Embodiment
FIG. 23 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.
In this embodiment, an image display device with higher luminous efficiency is realized by forming multiple light-emitting surfaces 551S1 and 551S2 on a single semiconductor layer 550 including a light-emitting layer. In the following description, the same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

As shown in FIG. 23, the image display device of this embodiment includes a subpixel group 520. The subpixel group 520 includes a substrate 102, a light-reflecting layer 120, a graphene layer 140, a semiconductor layer 550, a first interlayer insulating film 156, a plurality of transistors 103-1 and 103-2, a second interlayer insulating film 108, a plurality of vias 561a1 and 561a2, and a wiring layer 110. In this embodiment and its modified examples, the reference numeral for the light-reflecting layer 120 will be written alongside the reference numeral for the light-reflecting plate 530. The reference numeral for the graphene layer 140 will also be written alongside the reference numeral for the graphene sheet 540.

The semiconductor layer 550 is provided on the first surface 102a side of the substrate 102. In this example, the light-reflecting layer 120 is provided between the substrate 102 and the semiconductor layer 550. The light-reflecting layer 120 is provided on the first surface 102a. The light-reflecting layer 120 includes a light-reflecting plate 530. The insulating layer 114 covers the first surface 102a, the light-reflecting layer 120, and the light-reflecting plate 530. The insulating layer 114 is planarized.

In this embodiment, by turning on p-channel transistors 103-1 and 103-2, holes are injected from one side of semiconductor layer 550 via wiring layer 110 and vias 561a1 and 561a2. By turning on p-channel transistors 103-1 and 103-2, electrons are injected from the other side of semiconductor layer 550 via wiring layer 110. Holes and electrons are injected into semiconductor layer 550, and the recombination of the holes and electrons causes light to be emitted by the light-emitting layer 552. The drive circuit for driving light-emitting layer 552 may have the circuit configuration shown in Figure 3, for example. Using the other embodiments described above, it is also possible to reverse the n-type and p-type semiconductor layers of the semiconductor layer and drive the semiconductor layer with n-channel transistors. In that case, the drive circuit may have the circuit configuration shown in Figure 13.

The configuration of the sub-pixel group 520 will now be described in detail.
The graphene layer 140 includes a graphene sheet 540. The graphene sheet 540 is provided on the insulating layer 114. The graphene sheet 540 has an outer periphery that approximately coincides with the outer periphery of the semiconductor layer 550. The semiconductor layer 550 is provided on the light reflecting plate 530 via the insulating layer 114 and the graphene sheet 540. The outer periphery of the light reflecting plate 530 (second portion) is set so as to include the outer periphery of the semiconductor layer 550 when the semiconductor layer 550 is projected onto the light reflecting plate 530 in the XY plane view.

The semiconductor layer 550 includes multiple light-emitting surfaces 551S1 and 551S2. The semiconductor layer 550 is a rectangular or cylindrical laminate having a bottom surface 553B on the first surface 102a. The light-emitting surfaces 551S1 and 551S2 are the surfaces of the semiconductor layer 550 opposite the bottom surface 553B. In this example, the bottom surface 553B is the surface in contact with the graphene sheet 540. The light-emitting surfaces 551S1 and 551S2 are preferably surfaces in substantially parallel planes. The substantially parallel planes may be the same plane or different planes. The light-emitting surfaces 551S1 and 551S2 are spaced apart.

The semiconductor layer 550 includes a p-type semiconductor layer 553, a light-emitting layer 552, and an n-type semiconductor layer 551. The p-type semiconductor layer 553, the light-emitting layer 552, and the n-type semiconductor layer 551 are stacked in this order from the bottom surface 553B toward the light-emitting surfaces 551S1 and 551S2.

The p-type semiconductor layer 553 includes connection portions 553a1 and 553a2. Connection portion 553a1 is provided on the insulating layer 114 to protrude in one direction from the p-type semiconductor layer 553. Connection portion 553a2 is provided on the insulating layer 114 to protrude from the p-type semiconductor layer 553 in a direction different from that of connection portion 553a1. Connection portions 553a1 and 553a2 are not limited to protruding in one direction, but may be provided to protrude in multiple directions. A portion of the protruding portion around the periphery of the semiconductor layer 550 may serve as connection portions 553a1 and 553a2. The height of connection portions 553a1 and 553a2 is lower than the height of the semiconductor layer 550 and is the same as the height of the p-type semiconductor layer 553, or, as in this example, lower than the height of the p-type semiconductor layer 553. The semiconductor layer 550 is formed in a stepped shape.

Connection portion 553a1 is p-type and electrically connects via 561a1, which is connected at one end to connection portion 553a1, to p-type semiconductor layer 553. Connection portion 553a2 is p-type and electrically connects via 561a2, which is connected at one end to connection portion 553a2, to p-type semiconductor layer 553.

The n-type semiconductor layer 551 has two light-emitting surfaces 551S1 and 551S2 on its upper surface. The two light-emitting surfaces 551S1 and 551S2 are spaced apart from each other. In other words, one subpixel group 520 essentially includes two subpixels. In this embodiment, as in the other embodiments described above, a display area is formed by arranging subpixel groups 520, each including essentially two subpixels, in a grid pattern.

The protruding directions of connecting portions 553a1 and 553a2 are determined, for example, depending on the arrangement of light-emitting surfaces 551S1 and 551S2. Connecting portion 553a1 is provided, for example, so that its distance from light-emitting surface 551S1 is sufficiently shorter than its distance from light-emitting surface 551S2. In other words, connecting portion 553a1 is provided in a position sufficiently closer to light-emitting surface 551S1 than light-emitting surface 551S2. Connecting portion 553a2 is provided, for example, so that its distance from light-emitting surface 551S2 is sufficiently shorter than its distance from light-emitting surface 551S1. In other words, connecting portion 553a2 is provided in a position sufficiently closer to light-emitting surface 551S2 than light-emitting surface 551S1.

The first interlayer insulating film (first insulating film) 156 covers the side surfaces of the p-type semiconductor layer 553, the light-emitting layer 552, and the n-type semiconductor layer 551. The first interlayer insulating film 156 covers a portion of the upper surface of the n-type semiconductor layer 551. The light-emitting surfaces 551S1 and 551S2 of the n-type semiconductor layer 551 are not covered by the first interlayer insulating film 156. The first interlayer insulating film 156 is preferably a white resin, as in the other embodiments described above.

The TFT lower layer film 106 is formed over the first interlayer insulating film 156. The TFT lower layer film 106 is not provided over the light-emitting surfaces 551S1 and 551S2. The TFT lower layer film 106 is planarized, and TFT channels 104-1, 104-2, etc. are formed on the TFT lower layer film 106.

An insulating layer 105 covers the TFT lower layer 106 and the TFT channels 104-1 and 104-2. The gate 107-1 is provided on the TFT channel 104-1 via the insulating layer 105. The gate 107-2 is provided on the TFT channel 104-2 via the insulating layer 105. The transistor 103-1 includes the TFT channel 104-1 and the gate 107-1. The transistor 103-2 includes the TFT channel 104-2 and the gate 107-2.

The second interlayer insulating film (second insulating film) 108 covers the insulating layer 105 and gates 107-1 and 107-2.

TFT channels 104-1 and 104-2 include p-type doped regions, and transistors 103-1 and 103-2 are p-channel TFTs. Transistor 103-1 is located closer to light-emitting surface 551S1 than light-emitting surface 551S2. Transistor 103-2 is located closer to light-emitting surface 551S2 than light-emitting surface 551S1.

An opening 558-1 is provided above the light-emitting surface 551S1. An opening 558-2 is provided above the light-emitting surface 551S2. The second interlayer insulating film 108, insulating layer 105, TFT lower film 106, and first interlayer insulating film 156 are not provided in the openings 558-1 and 558-2, and the light-emitting surfaces 551S1 and 551S2 are exposed through the openings 558-1 and 558-2.

A transparent electrode 559k is provided over the light-emitting surfaces 551S1 and 551S2. Electrons are injected through the transparent electrode 559k and the light-emitting surfaces 551S1 and 551S2. The light-emitting surfaces 551S1 and 551S2 are covered with the transparent electrode 559k, and the openings 558-1 and 558-2 are filled with a surface resin layer 170.

When viewed in the XY plane, the light-emitting surfaces 551S1 and 551S2 are square, rectangular, other polygonal, circular, etc. The shape of the tops of the openings 558-1 and 558-2 can also be square, rectangular, other polygonal, circular, etc. In order to reduce light reflection and loss on the wall surfaces of the openings 558-1 and 558-2, it is preferable that the openings 558-1 and 558-2 be formed in a tapered shape so that the area increases toward the top, as in this example. When viewed in the XY plane, the shape of the light-emitting surfaces 551S1 and 551S2 and the shape of the tops of the openings 558-1 and 558-2 may or may not be similar.

The wiring layer 110 is provided on the second interlayer insulating film 108. The wiring layer 110 includes wirings 510s1, 510d1, 510k, 510d2, and 510s2.

Wiring 510k is provided between light-emitting surface 551S1 and light-emitting surface 551S2. A translucent electrode 559k is provided over wiring 510k. Wiring 510k and translucent electrode 559k are connected to, for example, ground line 4 in Figure 3.

Vias 111d1, 111s1, 111d2, and 111s2 are provided through the second interlayer insulating film 108 and insulating layer 105. Via 111d1 is provided between one p-type doped region of transistor 103-1 and wiring 510d1. Via 111s1 is provided between the other p-type doped region of transistor 103-1 and wiring 510s1. Via 111d2 is provided between one p-type doped region of transistor 103-2 and wiring 510d2. Via 111s2 is provided between the other p-type doped region of transistor 103-2 and wiring 510s2.

Wiring 510d1 is provided above connection portion 553a1. Wiring 510d1 is connected to the p-type region corresponding to the drain electrode of transistor 103-1 via via 111d1. Wiring 510s1 is connected to the p-type region corresponding to the source electrode of transistor 103-1 via via 111s1. Wiring 510d2 is provided above connection portion 553a2. Wiring 510d2 is connected to the region corresponding to the drain electrode of transistor 103-2 via via 111d2. Wiring 510s2 is connected to the region corresponding to the source electrode of transistor 103-2 via via 111s2.

The via 561a1 penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer 106, and the first interlayer insulating film 156. The via 561a1 is provided between the connection portion 553a1 and the wiring 510d1, and electrically connects the connection portion 553a1 and the wiring 110d1.

The via 561a2 penetrates the second interlayer insulating film 108, the insulating layer 105, the TFT lower layer 106, and the first interlayer insulating film 156. The via 561a2 is provided between the connection portion 553a2 and the wiring 510d2, and electrically connects the connection portion 553a2 and the wiring 510d2.

Transistors 103-1 and 103-2 are drive transistors for adjacent subpixels and are driven sequentially. Holes supplied from either of the two transistors 103-1 and 103-2 are injected into the light-emitting layer 552, and electrons supplied from wiring 510k are injected into the light-emitting layer 552, causing the light-emitting layer 552 to emit light.

In this embodiment, the resistance of the n-type semiconductor layer 551 and the p-type semiconductor layer 553 suppresses drift currents that flow in a direction parallel to the XY plane. Therefore, electrons injected from the light-emitting surfaces 551S1 and 551S2 and holes injected from the vias 561a1 and 561a2 both travel along the stacking direction of the semiconductor layer 550. Because light is rarely emitted from the outside of the light-emitting surfaces 551S1 and 551S2, multiple light-emitting surfaces 551S1 and 551S2 provided on one semiconductor layer 550 can be made to emit light by the transistors 103-1 and 103-2, respectively.

As mentioned above, the areas outside the light-emitting surfaces 551S1 and 551S2 do not serve as light sources, so a light-reflecting plate 530 may also be provided for each of the light-emitting surfaces 551S1 and 551S2.

A method for manufacturing the image display device of this embodiment will be described.
24A to 26B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this embodiment.
In this embodiment, the steps up to the formation of the light-reflecting layer 120 and the insulating layer 114 can be the same as in the other embodiments described above. In the following description, it is assumed that the step corresponding to the step in Fig. 14B is performed before the step in Fig. 24A is performed. Note that in this embodiment, the light-reflecting layer 120 includes a light-reflecting plate 530, and the shape of the light-reflecting plate 530 differs from that in the other embodiments described above.
24A , the graphene layer 1140 is provided on the insulating layer 114. The graphene layer 1140 has a sufficient area, and the periphery of the graphene layer 1140 is set to include the periphery of the light reflecting plate 530, for example.

As shown in Figure 24B, the semiconductor layer 1150 is formed on the graphene layer 1140. The semiconductor layer 1150 is formed in the following order from the graphene layer 1140 toward the positive direction of the Z axis: a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151.

As shown in Figure 24C, the semiconductor layer 1150 shown in Figure 24B is shaped into a desired shape by etching or the like to form the semiconductor layer 550 including the connection portions 553a1 and 553a2. The desired shape is, for example, a square or rectangle, or another polygon, circle, etc. in an XY planar view. In this example, the connection portion 553a1 is formed in the negative direction of the X axis, and the connection portion 553a2 is formed in the positive direction of the X axis. The graphene layer 1140 shown in Figure 24B is over-etched during the shaping of the semiconductor layer 1150, and is shaped to have an outer periphery that approximately matches the outer periphery of the semiconductor layer 1150.

As shown in FIG. 25A, a first interlayer insulating film 156 is formed covering the insulating layer 114, the graphene layer 140 and the semiconductor layer 550.

As shown in FIG. 25B, the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and the TFT channels 104-1 and 104-2 are formed on the TFT lower layer film 106. An insulating layer 105 is formed over the TFT lower layer film 106 and the TFT channels 104-1 and 104-2. The gate 107-1 is formed on the TFT channel 104-1 via the insulating layer 105. The gate 107-2 is formed on the TFT channel 104-2 via the insulating layer 105. The second interlayer insulating film 108 is formed over the insulating layer 105 and the gates 107-1 and 107-2. The methods and materials for forming the TFT channels 104-1 and 104-2, the insulating layer 105, and the gates 107-1 and 107-2 can be the same as those in the other embodiments described above.

As shown in FIG. 26A, via holes 112d1 and 112s1 are formed, penetrating the second interlayer insulating film 108 and insulating layer 105 and reaching TFT channel 104-1. Via holes 112d2 and 112s2 are formed, penetrating the second interlayer insulating film 108 and insulating layer 105 and reaching TFT channel 104-2. Via hole 562a1 is formed, penetrating the second interlayer insulating film 108, insulating layer 105, TFT lower film 106, and first interlayer insulating film 156 and reaching connection portion 553a1. Via hole 562a2 is formed, penetrating the second interlayer insulating film 108, insulating layer 105, TFT lower film 106, and first interlayer insulating film 156 and reaching connection portion 553a2. A part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower film 106, and a part of the first interlayer insulating film 156 is removed to form an opening 558-1 that reaches the light-emitting surface 551S1. A part of the second interlayer insulating film 108, a part of the insulating layer 105, a part of the TFT lower film 106, and a part of the first interlayer insulating film 156 is removed to form an opening 558-2 that reaches the light-emitting surface 551S2.

As shown in FIG. 26B, via holes 112d1, 112s1, 112d2, 112s2, 562a1, and 562a2 are filled with a conductive material to form vias 111d1, 111s1, 111d2, 111s2, 561a1, and 561a2. A wiring layer 110 is formed, and wirings 510d1, 510s1, 510d2, 510s2, and 510k are formed.

Emitting surfaces 551S1 and 551S2 are each roughened. A translucent conductive film is then provided to cover wiring layer 110, and translucent electrodes 559d1, 559s1, 559d2, 559s2, and 559k are formed. Translucent electrode 559k is formed to cover light-emitting surfaces 551S1 and 551S2, and electrically connects light-emitting surfaces 551S1 and 551S2 to wiring 510k.

Then, upper structures such as color filters are formed.

In this way, a subpixel group 520 is formed having a semiconductor layer 550 with two light-emitting surfaces 551S1 and 551S2.

In this embodiment, two light-emitting surfaces 551S1 and 551S2 are provided on one semiconductor layer 550, but the number of light-emitting surfaces is not limited to two, and three or more light-emitting surfaces can also be provided on one semiconductor layer 550. As an example, one or two columns of subpixels can be realized with a single semiconductor layer 550. As will be described later, this reduces the recombination current that does not contribute to light emission per light-emitting surface, and increases the effect of realizing finer light-emitting elements.

(Modification)
FIG. 27 is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of this embodiment.
This modification differs from the fifth embodiment in that two n-type semiconductor layers 5551a1 and 5551a2 are provided on the light-emitting layer 552. In other respects, this modification is the same as the fifth embodiment, and the same components are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

As shown in FIG. 27, the image display device of this modified example includes a subpixel group 520a. The subpixel group 520a includes a semiconductor layer 550a. The semiconductor layer 550a includes a p-type semiconductor layer 553, a light-emitting layer 552, and n-type semiconductor layers 5551a1 and 5551a2. The p-type semiconductor layer 553 and the light-emitting layer 552 are stacked in this order from the graphene layer 140. The n-type semiconductor layers 5551a1 and 5551a2 are both stacked on the light-emitting layer 552.

The n-type semiconductor layers 5551a1 and 5551a2 are formed in island shapes on the light-emitting layer 552, and in this example, are spaced apart along the X-axis direction. A first interlayer insulating film 156 is provided between the n-type semiconductor layers 5551a1 and 5551a2, and the n-type semiconductor layers 5551a1 and 5551a2 are separated by the first interlayer insulating film 156.

The n-type semiconductor layers 5551a1 and 5551a2 have approximately the same shape when viewed in the XY plane, and their shape is approximately square or rectangular, but may also be other polygonal shapes, circles, etc.

The n-type semiconductor layer 5551a1 has a light-emitting surface 5551S1. The n-type semiconductor layer 5551a2 has a light-emitting surface 5551S2. The light-emitting surface 5551S1 is exposed through an opening 558-1 formed by removing portions of the first interlayer insulating film 156, the TFT lower layer 106, the insulating layer 105, and the second interlayer insulating film 108. The exposed light-emitting surface 5551S1 is the surface of the n-type semiconductor layer 5551a1. The light-emitting surface 5551S2 is exposed through an opening 558-2 formed by removing portions of the first interlayer insulating film 156, the TFT lower layer 106, the insulating layer 105, and the second interlayer insulating film 108. The exposed light-emitting surface 5551S2 is the surface of the n-type semiconductor layer 5551a2.

The shapes of the light-emitting surfaces 5551S1 and 5551S2 in the XY plane are substantially the same as the shapes of the light-emitting surfaces in the fifth embodiment, and are generally square or similar. The shapes of the light-emitting surfaces 5551S1 and 5551S2 are not limited to a square as in this embodiment, but may be circular, elliptical, or polygonal, such as a hexagon. The shapes of the light-emitting surfaces 5551S1 and 5551S2 may be similar to or different from the shapes of the openings 558-1 and 558-2.

Translucent electrode 559k is provided on each of light-emitting surfaces 5551S1 and 5551S2. Translucent electrode 559k is also provided on wiring 510k. Translucent electrode 559k is provided between wiring 510k and light-emitting surface 5551S1, and between wiring 510k and light-emitting surface 5551S2. Translucent electrode 559k electrically connects wiring 510k and light-emitting surfaces 5551S1 and 5551S2.

A manufacturing method of this modified example will be described.
28A to 29B are schematic cross-sectional views illustrating a method for manufacturing the image display device of this modified example.
24A and 24B in the fifth embodiment are applied up to the step of forming the semiconductor layer 1150 on the graphene layer 1140. In the following description, it is assumed that the step of Fig. 28A is applied after the step described above in Fig. 24B.

As shown in Figure 28A, in this modification, the semiconductor layer 1150 shown in Figure 24B is etched to form a p-type semiconductor layer 553 including a light-emitting layer 552 and connecting portions 553a1 and 553a2. Further etching is performed to form two n-type semiconductor layers 5551a1 and 5551a2.

When forming n-type semiconductor layers 5551a1 and 5551a2, etching may be performed even deeper. For example, etching to form n-type semiconductor layers 5551a1 and 5551a2 may be performed to a depth greater than that which reaches light-emitting layer 552 and p-type semiconductor layer 553. When forming n-type semiconductor layers by deep etching, it is desirable to etch at least 1 μm outside the outer periphery of light-emitting surfaces 5551S1 and 5551S2 shown in FIG. 27. By positioning the etching position outside the outer periphery of light-emitting surfaces 5551S1 and 5551S2, recombination current can be suppressed.

As shown in FIG. 28B, a first interlayer insulating film 156 is formed covering the insulating layer 114, the graphene layer 140 and the semiconductor layer 550a.

As shown in Figure 28C, the TFT lower layer film 106 is formed on the first interlayer insulating film 156, and TFT channels 104-1 and 104-2 are formed on the TFT lower layer film 106. Furthermore, an insulating layer 105 is formed on the TFT channels 104-1 and 104-2, and gates 107-1 and 107-2 are formed on the insulating layer 105. A second interlayer insulating film 108 is formed to cover the insulating layer 105 and gates 107-1 and 107-2.

As shown in FIG. 29A, via holes 112d1, 112s1, 112d2, 112s2, 562a1, and 562a2 are formed in the same manner as in the fifth embodiment. Opening 558-1 is formed by removing part of the second interlayer insulating film 108, part of the insulating layer 105, part of the TFT lower film 106, and part of the first interlayer insulating film 156, so as to reach light-emitting surface 5551S1. Opening 558-2 is formed by removing part of the second interlayer insulating film 108, part of the insulating layer 105, part of the TFT lower film 106, and part of the first interlayer insulating film 156, so as to reach light-emitting surface 5551S2.

As shown in Figure 29B, as in the fifth embodiment, a wiring layer 110 is formed and a translucent conductive film is formed.

In this way, a subpixel group 520a having two light-emitting surfaces 5551S1 and 5551S2 is formed.

In this modified example, as in the fifth embodiment, the number of light-emitting surfaces is not limited to two, and three or more light-emitting surfaces may be provided on one semiconductor layer 550a.

The effects of the image display device of this embodiment will be described.
FIG. 30 is a graph illustrating the characteristics of a pixel LED element.
30, the vertical axis represents the luminous efficiency [%] of the pixel LED element, and the horizontal axis represents the relative value of the current density flowing through the pixel LED element.
30, in the region where the relative value of the current density is less than 1.0, the luminous efficiency of the pixel LED element is almost constant or increases monotonically. In the region where the relative value of the current density is greater than 1.0, the luminous efficiency decreases monotonically. In other words, there exists an appropriate current density for the pixel LED element that maximizes the luminous efficiency.

It is expected that a highly efficient image display device can be realized by suppressing the current density to a level that allows sufficient brightness to be obtained from the light-emitting element. However, Figure 30 shows that at low current densities, the luminous efficiency tends to decrease as the current density decreases.

As explained in the first to fourth embodiments, the light-emitting element is formed by separating all layers of the semiconductor layer 1150, including the light-emitting layer, individually by etching or the like. At this time, the junction surface between the light-emitting layer and the n-type semiconductor layer is exposed at the end. Similarly, the junction surface between the light-emitting layer and the p-type semiconductor layer is exposed at the end.

When such edges exist, electrons and holes recombine at the edges. However, this recombination does not contribute to light emission. Recombination at the edges occurs almost independently of the current flowing through the light-emitting element. It is believed that recombination occurs according to the length of the junction surface that contributes to light emission at the edges.

When two cubic light-emitting elements of the same dimensions are made to emit light, the four side surfaces of each light-emitting element become edges, so the two light-emitting elements have a total of eight edges, and recombination can occur at all eight edges.

In contrast, in this embodiment, the semiconductor layers 550 and 550a have four side surfaces, with two light-emitting surfaces and four ends. However, since the region between the openings 558-1 and 558-2 receives little electron or hole injection and contributes very little to light emission, the number of ends that contribute to light emission can be considered to be six. In this way, in this embodiment, the number of ends of the semiconductor layer is substantially reduced, thereby reducing recombination that does not contribute to light emission. By reducing recombination that does not contribute to light emission, the drive current for each light-emitting surface is reduced.

In cases where the distance between subpixels is shortened for higher resolution or when the current density is relatively high, the distance between light-emitting surface 551S1 and light-emitting surface 551S2 is shortened in subpixel group 520 of the fifth embodiment. In this case, if the n-type semiconductor layer is shared, as in the fifth embodiment, some of the electrons injected into the driven light-emitting surface may be diverted, causing the undriven light-emitting surface to emit weak light. In subpixel group 520a of the modified example, the n-type semiconductor layer is separated into two, and each n-type semiconductor layer has its own light-emitting surface, thereby reducing the occurrence of weak light emission in the light-emitting surface that is not driven.

In this embodiment, the semiconductor layers including the light-emitting layer are stacked in the following order from the side of the first interlayer insulating film 156: p-type semiconductor layer, light-emitting layer, and n-type semiconductor layer. This is preferable from the perspective of roughening the exposed surface of the n-type semiconductor layer to improve light-emitting efficiency. As in the other embodiments, as mentioned above, the stacking order of the p-type and n-type semiconductor layers may be reversed, and the n-type semiconductor layer, light-emitting layer, and p-type semiconductor layer may be stacked in this order.

Specific examples have been described for each of the subpixels and subpixel groups of the image display devices of the above-described embodiments. Each of these specific examples is merely an example, and other configuration examples can be achieved by appropriately combining the configurations and process steps of these embodiments. For example, in the first embodiment, instead of using a p-type semiconductor layer as the light-emitting surface, an n-type semiconductor layer can be used, and in the second to fourth embodiments, instead of using an n-type semiconductor layer as the light-emitting surface, a p-type semiconductor layer can be used as the light-emitting surface.

Sixth Embodiment
The image display device described above can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

FIG. 31 is a block diagram illustrating an image display device according to this embodiment.
FIG. 31 shows the main components of a computer display.
31 , an image display device 601 includes an image display module 602. The image display module 602 is an image display device having the configuration of, for example, the first embodiment described above. The image display module 602 includes a display area 2 in which a plurality of subpixels including the subpixel 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.

The image display device 601 further includes a controller 670. The controller 670 receives control signals separated and generated by an interface circuit (not shown) and controls the row selection circuit 5 and the signal voltage output circuit 7 to drive each subpixel and the driving order.

(Modification)
The image display device described above can be an image display module having an appropriate number of pixels, and can be, for example, a computer display, a television, a portable terminal such as a smartphone, or a car navigation system.

FIG. 32 is a block diagram illustrating an image display device according to a modified example of this embodiment.
FIG. 32 shows the configuration of a high-definition flat-screen television.
As shown in Fig. 32, an image display device 701 includes an image display module 702. The image display module 702 is, for example, the image display device 1 having the configuration of the first embodiment described above. The image display device 701 also includes a controller 770 and a frame memory 780. The controller 770 controls the drive order of each sub-pixel in the display area 2 based on a control signal supplied via a bus 740. The frame memory 780 stores one frame's worth of display data and is used for processing such as smooth video playback.

The image display device 701 has an I/O circuit 710. In Figure 32, the I/O circuit 710 is simply referred to as "I/O." The I/O circuit 710 provides interface circuits, etc. for connecting to external terminals and devices. The I/O circuit 710 includes, for example, a USB interface for connecting an external hard disk drive, etc., and an audio interface, etc.

The image display device 701 has a receiving unit 720 and a signal processing unit 730. An antenna 722 is connected to the receiving unit 720, which separates and generates necessary signals from the radio waves received by the antenna 722. The signal processing unit 730 includes a DSP (Digital Signal Processor) and a CPU (Central Processing Unit), and the signals separated and generated by the receiving unit 720 are separated and generated by the signal processing unit 730 into image data, audio data, etc.

By using the receiving unit 720 and the signal processing unit 730 as high-frequency communication modules for transmitting and receiving signals in a mobile phone, for Wi-Fi, or as a GPS receiver, the device can also be used as another image display device. For example, an image display device equipped with an image display module with an appropriate screen size and resolution can be used as a mobile information terminal such as a smartphone or car navigation system.

The image display module in this embodiment is not limited to the configuration of the image display device in the first embodiment, but may be a modified version thereof or a version of another embodiment. Furthermore, it goes without saying that the image display module in this embodiment and the modified version has a configuration including a large number of subpixels, as shown in Figure 11.

According to the embodiments described above, it is possible to realize a manufacturing method for an image display device and an image display device that shortens the transfer process of light-emitting elements and improves yield.

Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other.

1,201,601,701 Image display device, 2 Display area, 3 Power supply line, 4 Ground line, 5,205 Row selection circuit, 6,206 Scanning line, 7,207 Signal voltage output circuit, 8,208 Signal line, 10 Pixel, 20,20a,220,320,420 Subpixel, 22,222 Light-emitting element, 24,224 Selection transistor, 26,226 Drive transistor, 28,228 Capacitor, 101 Circuit, 102,402 Substrate, 102a,402a First surface, 103,103-1,103-2,203 Transistor, 104,104-1,104-2,204 TFT channel, 105 Insulating layer, 107,107-1,107-2 Gate, 108 Second interlayer insulating film, 110 Wiring layer, 110d, 110k, 310a, 310k Wiring, 120 Light reflecting layer, 120a, 530 Light reflecting plate, 140 Graphene layer, 140a, 540 Graphene sheet, 150, 250 Light emitting element, 151B, 253B, 553B Bottom surface, 153S, 251S, 551S1, 551S2, 5551S1, 5551S2 Light emitting surface, 156 First interlayer insulating film, 159d, 159s, 359d, 359k, 559k Translucent electrode, 161k, 261a, 361a, 561a1, 561a2 Via, 180 Color filter, 520, 520a Subpixel group, 1140 Graphene layer, 1150 Semiconductor layer

Claims (19)

forming a layer including graphene on a first substrate;
forming a semiconductor layer including a light-emitting layer on the graphene-containing layer;
processing the semiconductor layer to form a light-emitting element having a bottom surface on the graphene-containing layer and including a light-emitting surface opposite the bottom surface;
forming a first insulating film covering the first substrate, the graphene-containing layer, and the light-emitting element;
forming a circuit element on the first insulating film;
forming a second insulating film covering the first insulating film and the circuit element;
removing a portion of the first insulating film and a portion of the second insulating film to expose a surface including the light emitting surface;
forming a via that penetrates the first insulating film and the second insulating film;
forming a wiring layer on the second insulating film;
Equipped with
the light-emitting element includes a connection portion formed on the layer including graphene,
The via is provided between the wiring layer and the connection portion, and the wiring layer and the connection portion are electrically connected to each other. The method for manufacturing an image display device according to claim 1, wherein in the step of forming the semiconductor layer, the semiconductor layer is formed by sputtering. forming a first portion having light reflectivity on the first substrate before forming the graphene-containing layer;
The method for manufacturing an image display device according to claim 1 , wherein the outer periphery of the light emitting element is arranged within the outer periphery of the first portion in a plan view. The method for manufacturing an image display device according to claim 1, wherein the first substrate includes a light-transmitting substrate. the first substrate further includes a flexible second substrate provided on the light-transmitting substrate,
5. The method for manufacturing an image display device according to claim 4, further comprising the step of removing the light-transmitting substrate after forming the wiring layer. The method for manufacturing an image display device according to claim 5 , further comprising the step of forming a layer containing a silicon compound on the second substrate before forming the layer containing graphene. The method for manufacturing an image display device according to claim 1, further comprising the step of forming a translucent electrode on the light-emitting surface. The method for manufacturing an image display device according to claim 1, wherein the semiconductor layer includes a gallium nitride compound semiconductor. The method for manufacturing an image display device according to claim 1, further comprising the step of forming a wavelength conversion member on the light-emitting element. a substrate having a first surface;
a layer including graphene provided on the first surface;
a light-emitting element provided on the graphene-containing layer, having a bottom surface on the graphene-containing layer and including a surface including a light-emitting surface that is a surface opposite to the bottom surface;
a first insulating film covering a side surface of the light-emitting element, the first surface, and the graphene-containing layer;
a circuit element provided on the first insulating film;
a second insulating film covering the first insulating film and the circuit element;
a via provided through the first insulating film and the second insulating film;
a wiring layer provided on the second insulating film;
Equipped with
the light-emitting element includes a first semiconductor layer, a light-emitting layer provided on the first semiconductor layer, and a second semiconductor layer provided on the light-emitting layer, and is stacked in this order from the bottom surface toward the light-emitting surface, with the first semiconductor layer, the light-emitting layer, and the second semiconductor layer;
the via is provided between a connection portion formed on the layer including the graphene from the first semiconductor layer and the wiring layer, and electrically connects the first semiconductor layer and the wiring layer ;
the wiring layer includes a first wiring connected to the via and a second wiring connected to a surface including the light emitting surface,
The second semiconductor layer is electrically connected to the circuit element via a surface including the light emitting surface and second wiring . a substrate having a first surface;
a layer including graphene provided on the first surface;
a light-emitting element provided on the graphene-containing layer, having a bottom surface on the graphene-containing layer and including a surface including a light-emitting surface that is a surface opposite to the bottom surface;
a first insulating film covering a side surface of the light-emitting element, the first surface, and the graphene-containing layer;
a circuit element provided on the first insulating film;
a second insulating film covering the first insulating film and the circuit element;
a via provided through the first insulating film and the second insulating film;
a wiring layer provided on the second insulating film;
Equipped with
the light-emitting element includes a first semiconductor layer, a light-emitting layer provided on the first semiconductor layer, and a second semiconductor layer provided on the light-emitting layer, and is stacked in this order from the bottom surface toward the light-emitting surface, with the first semiconductor layer, the light-emitting layer, and the second semiconductor layer;
the via is provided between a connection portion formed on the layer including the graphene from the first semiconductor layer and the wiring layer, and electrically connects the first semiconductor layer and the wiring layer ;
the wiring layer includes a third wiring connected to the via and a fourth wiring connected to a surface including the light emitting surface,
The image display device , wherein the first semiconductor layer is electrically connected to the circuit element through the connection portion, the via, and the third wiring . a first portion having light reflectivity provided between the first surface and the graphene-containing layer,
The image display device according to claim 10 , wherein an outer periphery of the light emitting element is disposed within an outer periphery of the first portion in a plan view. The image display device according to claim 10 , wherein the substrate includes a light-transmitting substrate. The image display device according to claim 10 or 11 , wherein the substrate includes a flexible substrate. The image display device according to claim 14 , further comprising a layer containing a silicon compound between the flexible substrate and the layer containing graphene. The image display device according to claim 10 or 11 , further comprising a light-transmitting electrode provided on the light-emitting surface. 12. The image display device according to claim 10, wherein the first semiconductor layer is a p-type, and the second semiconductor layer is an n-type. 12. The image display device according to claim 10 , wherein the light emitting element includes a gallium nitride compound semiconductor. The image display device according to claim 10 or 11 , further comprising a wavelength conversion member on the light emitting element.