JP7600144B2 - Synchronization device and synchronization method - Google Patents

Description

The present disclosure relates to a synchronization device and a synchronization method.

TWS (True Wireless Stereo) earphones using Bluetooth (registered trademark) are rapidly becoming popular. Due to the demand for smaller size and lower power consumption, the Bluetooth Low Energy (BLE) standard, which is a lower power consumption standard than the conventional Bluetooth standard, is being developed.

When playing stereo audio with TWS earphones, it is extremely important to synchronize the left and right music playback while maintaining the correct positioning, so there is a demand for highly reliable audio playback synchronization technology.

In the conventional Bluetooth standard, when audio is played, time information is transmitted from the playback device, such as a smartphone or music player, and playback synchronization is achieved by synchronizing with this time information. On the other hand, in the BLE standard, this time information is not included in the packet, so audio playback synchronization must be achieved using a method different from the conventional technology.

JP 2018-11204 A

The present disclosure provides a synchronization device and a synchronization method that can achieve precise synchronization between a master and a slave that communicate wirelessly.

In order to solve the above problems, according to one aspect of the present disclosure, there is provided a synchronization device that synchronizes time-series data between a master and a slave via wireless communication, comprising:
The master is
a packet generator for generating a plurality of packets;
a packet transmission unit that transmits an arbitrary packet of the plurality of packets to the slave at a predetermined interval;
The slave is
A packet receiving unit for receiving the arbitrary packet;
a counter that counts the interval between the arbitrary packets based on a reference clock signal;
A synchronization device is provided that adjusts the frequency of the reference clock signal based on the count value of the counter, thereby achieving synchronization between the master and the multiple slaves.

According to another aspect of the present disclosure, there is provided a synchronization device that synchronizes time-series data between a master and a plurality of slaves via wireless communication, comprising:
The master is
a packet generator for generating a plurality of packets;
a packet transmission unit that transmits any one of the plurality of packets to one of the plurality of slaves at a predetermined interval;
One of the plurality of slaves
A packet receiving unit for receiving the arbitrary packet;
a counter that counts the interval between the arbitrary packets based on a reference clock signal;
A synchronization device is provided that adjusts the frequency of the reference clock signal based on the count value of the counter, thereby achieving synchronization between the master and the multiple slaves.

the plurality of packets include information regarding packet intervals and time series data;
a latch unit that latches the count value of the counter every time a new packet is received by the packet receiving unit;
an information extraction unit that extracts information regarding a packet interval included in the packet received by the packet receiving unit;
an ideal count value calculation unit that calculates an ideal count value based on the extracted information about the interval between packets;
a difference calculation unit that calculates a difference between the count value of the counter latched by the latch unit and the ideal count value;
The clock signal generating device may further include a frequency adjusting unit that adjusts a frequency of the reference clock signal based on the difference.

The frequency adjustment unit may lower the frequency of the reference clock signal if the count value of the counter latched by the latch unit is greater than the ideal count value, and may increase the frequency of the reference clock signal if the count value of the counter latched by the latch unit is smaller than the ideal count value.

The slave is
a control value calculation unit that calculates a control value for adjusting the frequency of the reference clock signal based on a change in the difference over time so that the difference becomes equal to or smaller than a predetermined value;
The frequency adjuster may adjust the frequency of the reference clock signal based on the control value.

The slave is
a speed component extracting unit that extracts a speed component indicating a change value per unit time of the difference;
an acceleration component extraction unit that extracts an acceleration component that indicates a change value per unit time of the velocity component,
The control value calculation section may calculate the control value based on the velocity component and the acceleration component.

the slave has a control value adjustment unit that adjusts the control value so that the variation in the control value falls within a predetermined range;
The frequency adjustment unit may adjust the frequency of the reference clock signal based on the control value adjusted by the control value adjustment unit.

the packet transmission unit transmits a packet group including the plurality of packets a plurality of times at a predetermined interval;
the counter in the slave measures an interval between each packet included in the packet group;
The slave is
an interpolation unit that interpolates count values when there is a packet interval whose count value has not been measured among the intervals between packets included in the packet group;
an exclusion unit that excludes count values that are outside a tolerance range from among the count values counted by the counter;
The difference calculation section may calculate a difference between a count value obtained by performing the interpolation by the interpolation section and the exclusion by the exclusion section, and the ideal count value.

The time series data may be data including biometric information or audio data.

The packet receiving unit in each of the plurality of slaves may perform wireless communication with the master at different times to receive the plurality of packets including unique time series data transmitted from the master.

the master is an information providing terminal having a storage unit for storing audio data;
two slaves that wirelessly communicate with the information providing terminal at different times,
One of the two slaves may be an earphone that reproduces audio data for the left ear transmitted from the master, and the other may be an earphone that reproduces audio data for the right ear transmitted from the master.

According to another aspect of the present disclosure, there is provided a synchronization device that synchronizes time series data between a master and a slave via wireless communication, comprising:
The master is
a first counter that performs a counting operation based on a first reference clock signal;
a second counter that counts intervals between a plurality of packets transmitted from the information providing terminal based on a second reference clock signal;
a first packet transmitting unit configured to transmit a packet including the count value of the first counter and the count value of the second counter to the slave;
The slave is
a third counter that performs a counting operation based on a third reference clock signal;
a fourth counter that counts intervals between the plurality of packets transmitted from the information providing terminal based on a fourth reference clock signal;
a second packet transmitting unit configured to transmit a packet including the count value of the third counter and the count value of the fourth counter to the master;
A synchronization device is provided, comprising: a frequency adjustment unit that adjusts a frequency of the fourth reference clock signal based on the count value of the second counter and the count value of the fourth counter transmitted from the master.

a difference calculation unit that calculates a difference between the count value of the second counter transmitted from the master and the count value of the fourth counter,
The frequency adjusting section may adjust the frequency of the fourth reference clock signal based on the difference.

The count value of the first counter and the count value of the third counter may be adjusted so that they are the same or the difference between them is the same each time packet communication is performed between the master and the slave.

The slave is
an end time information acquiring unit that acquires information regarding a transmission end time included in a plurality of packets transmitted from the information providing terminal;
a start time calculation unit that calculates information regarding a start time of reproduction or processing of the time series data based on the information regarding the transmission end time;
The clock signal may include a synchronization unit that synchronizes with the master a time at which time series data is reproduced or processed based on the count value of the third counter, the count value of the fourth counter after the frequency of the fourth reference clock signal has been adjusted by the frequency adjustment unit, the difference calculated by the difference calculation unit after the frequency of the fourth reference clock signal has been adjusted by the frequency adjustment unit, and information regarding the start time.

The slave is
a fifth counter for counting divisions of the reproduced or processed time series data;
a count value acquiring unit that acquires a count value of the third counter and a count value of the fourth counter every time the fifth counter counts up,
The second packet transmitting unit may transmit the count value of the third counter and the count value of the fourth counter acquired by the count value acquiring unit to the master.

the time series data is audio data,
The fifth counter may count the number of frames of the audio data.

the frequency adjusting unit adjusts a frequency of the fourth reference clock signal based on the difference when the master and the slave start packet communication;
The synchronization unit may synchronize with the master a time at which the time series data is reproduced or processed, during an interval between packet communication between the master and the slave and the information providing terminal.

One of the master and the slave may be a first earphone that receives audio data for the left ear from the information providing terminal, and the other may be a second earphone that receives audio data for the right ear from the information providing terminal at a timing separate from that of the first earphone.

Each of the first earphone and the second earphone may have a master/slave determination unit that transmits and receives packets to each other and determines whether the device is the master or the slave based on profile information contained in the packets received by each of the first earphone and the second earphone.

The master and the slave may perform packet communication in accordance with the Bluetooth (registered trademark) Low Energy standard.

According to another aspect of the present disclosure, there is provided a synchronization method for synchronizing time series data between a master and a plurality of slaves via wireless communication, the method comprising:
The master is
Generate multiple packets,
transmitting any packet among the plurality of packets to one of the plurality of slaves at a predetermined interval;
One of the plurality of slaves is
receiving said any packet;
Counting the interval between the arbitrary packets with a counter based on a reference clock signal;
A synchronization method is provided in which the frequency of the reference clock signal is adjusted based on the count value of the counter, thereby achieving synchronization between the master and the multiple slaves.

According to another aspect of the present disclosure, there is provided a synchronization method for synchronizing time series data between a master and a slave via wireless communication, the method comprising:
The master is
A first counter performs a counting operation based on a first reference clock signal;
counting intervals between a plurality of packets transmitted from the information providing terminal with a second counter based on a second reference clock signal;
Transmitting a packet including the count value of the first counter and the count value of the second counter to the slave;
The slave is
A third counter performs a counting operation based on a third reference clock signal;
counting intervals between the plurality of packets transmitted from the information providing terminal by a fourth counter based on a fourth reference clock signal;
Transmitting a packet including the count value of the third counter and the count value of the fourth counter to the master;
There is provided a synchronization method for adjusting a frequency of the fourth reference clock signal based on the count value of the second counter and the count value of the fourth counter transmitted from the master.

FIG. 1 is a diagram showing a schematic configuration of a synchronization device according to an embodiment of the present invention. FIG. 1 is a diagram showing the timing of packet communication conforming to the BLE standard. FIG. 3 is a diagram showing the data structure of one packet transmitted within the subinterval of FIG. 2 . FIG. 2 is a block diagram showing an example of a hardware configuration of a master or a slave constituting a part of the synchronization device according to the present embodiment. FIG. 4 is a functional block diagram of software processing performed by a master and a slave. FIG. 13 is a diagram showing an example of the relationship between a PCD count value and an ideal PCD count value. 11 is a flowchart showing a processing operation when the master M is an information providing terminal such as a smartphone and the slave is an earphone. 11 is a flowchart showing a processing operation when one of the master and slave is the left earphone and the other is the right earphone. 9 is a detailed flowchart of a clock recovery process in the flowcharts of FIGS. 7 and 8 . 11 is a diagram showing the procedure of clock recovery processing performed by a slave using arrows. 11 is a diagram showing the procedure following FIG. 10 with arrows. 12 is a diagram showing the procedure following FIG. 11 with arrows. Conceptual diagram of adjusting the timing of sound output from the left and right earphones. A diagram using arrows showing the steps taken by the slave to adjust the sound output timing of the left and right earphones and check the discrepancy in sound output timing. 15 is a diagram showing the procedure following FIG. 14 with arrows. 16 is a diagram showing the procedure following FIG. 15 with arrows. 17 is a diagram showing the procedure following FIG. 16 with arrows. 18 is a diagram showing the procedure following FIG. 17 with arrows.

The following describes in detail the embodiments of the present disclosure.

(Outline of Synchronizing Device)
The synchronization device according to the present embodiment synchronizes time-series data between a master and a slave via wireless communication. The master transmits a packet including the time-series data to the slave via wireless communication, and the slave synchronizes the time-series data included in the received packet with the time-series data of the master.

There is no restriction on the type of time series data transmitted and received between the master and the slave. As an example, the time series data may be data including biometric information or audio data. Below, an example in which the master and the slave synchronize audio data will be mainly described. In this case, the master may be an information providing terminal that provides audio data, and the slave may be an earphone. Alternatively, the master may be one of the left or right earphones, and the slave may be the other earphone.

Figure 1 is a diagram showing the schematic configuration of a synchronization device 1 according to this embodiment. The synchronization device 1 in Figure 1 includes an information providing terminal 2, such as a smartphone, tablet, mobile phone, or portable music player, and left and right earphones 3a, 3b that receive audio data from the information providing terminal 2 and output audio. The information providing terminal 2 can be the master M, and the left and right earphones 3a, 3b can be the slaves S1, S2. Alternatively, one of the left and right earphones 3a can be the master M, and the other can be the slave S.

In this embodiment, it is assumed that the master M and the slaves S1 and S2 perform wireless communication using the above-mentioned Bluetooth (registered trademark) Low Energy (BLE). BLE consumes less power than normal Bluetooth and can extend the continuous use time of small communication devices such as the earphones 3a and 3b, which have limited battery capacity, so it is expected to become more widespread in the future.

For example, if the master M is the information providing terminal 2 and the slaves S1 and S2 are the left and right earphones 3a and 3b, in the BLE standard, the master M transmits only audio data for each earphone 3a, 3b to that earphone. In other words, audio data for one earphone 3a, 3b is not transmitted to the other earphone 3a, 3b. Since the earphones 3a and 3b communicate wirelessly, a process of synchronizing the audio data received by each earphone 3a, 3b must be performed between the information providing terminal 2 and each earphone 3a, 3b, and the earphones 3a, 3b must also synchronize with each other. This embodiment has a technical feature in the synchronization process performed between the master M and the slaves S1 and S2. First, the BLE standard will be described.

Furthermore, it is stated that the accuracy of the clock for the BLE-PHY counter used in the BLE device has an error of less than ±2 μsec.

In addition, with regard to connection and clock requirements, the BLE standard specifies synchronous connection (ISO: Isochronous connection) and general data frame connection (ACL: Asynchronous Connection Interval).

In this embodiment, the master M and slaves S1 and S2 transmit audio data and perform clock recovery via a synchronous connection (ISO), and exchange counter values between the left and right earphones 3a and 3b via a general data frame connection (ACL) via the GATT (Genetic Attribute) profile to adjust the counter deviation.

Figure 2 is a diagram showing the timing of packet communication conforming to the BLE standard. Figure 2 shows an example in which a master M (information providing terminal 2) transmits packets containing audio data for playback to two slaves S1 and S2 (left and right earphones 3a and 3b). Within the ISO interval, multiple packets are arranged at predetermined intervals. The transmission interval of one packet is called a subinterval. Having received a packet from master M, slaves S1 and S2 transmit a packet containing acknowledgement (ACK) information to master M. The transmission period of a packet group containing multiple packets is called a synchronization delay, and this synchronization delay information is included in the packet and transmitted from master M to slaves S1 and S2.

As can be seen from Figure 2, there is a difference in the packet transmission times between the left and right earphones 3a and 3b. As described above, with BLE, a packet containing left audio data is transmitted to the left earphone 3b, and a packet containing right audio data is transmitted to the right earphone 3a. Furthermore, with BLE, packets cannot be transmitted to the left and right earphones 3a and 3b simultaneously. For this reason, as shown in Figure 2, there is a difference in the packet transmission times between the left earphone 3b and the right earphone 3a. However, by specifying the Synchronization Delay for the left packet and the right packet respectively, the end times of the Synchronization Delay are made to match between the left and right earphones 3a and 3b.

In this embodiment, audio data starts to be played through the left and right earphones 3a and 3b after the end time of the Synchronization Delay and the Presentation Delay period has elapsed.

Figure 3 is a diagram showing the data structure of one packet transmitted within the subinterval of Figure 2. The data structure of the packet in Figure 3 complies with the BLE standard and is called a BLE packet. As shown in Figure 3, a BLE packet has a preamble, an access address, a PDU, and a CRC. The preamble does not contain data related to audio data, but does contain a BLE modulated signal. The access address contains information that identifies the communication partner and information that indicates the type of packet. In addition to containing audio data, the PDU contains the above-mentioned synchronization delay and information related to the packet interval (BLE parameters). The CRC is data for error checking.

Figure 4 is a block diagram showing an example of the hardware configuration of the master M or slaves S1 and S2 that constitute a part of the synchronization device 1 according to this embodiment. More specifically, Figure 4 shows the hardware configuration of the earphones 3a and 3b. As described above, the earphones 3a and 3b in Figure 4 operate as slaves S1 and S2 when receiving audio data from the information providing terminal 2. In addition, they operate as master M or slave S when performing synchronization processing between the earphones 3a and 3b.

The earphones 3a and 3b in Figure 4 have a clock generation unit (CRG) 11, a counter unit 12, an RF (Radio Frequency) unit 13, a baseband unit 14, a CPU 15, an audio processing unit (Audio Processor) 16, a buffer interface unit (BIF) 17, an audio interface unit (AIF: Audio Interface) 18, an audio output unit (Audio Chip) 19, a speaker 20, and a microphone 21.

The RF unit 13 receives and demodulates a wireless signal including the packet shown in Figure 2. Although a description of the internal configuration of the RF unit 13 is omitted, the RF unit 13 receives and demodulates a wireless signal in the 2.4 GHz band in accordance with the BLE standard. In this way, the RF unit 13 functions as a packet receiving unit that receives multiple packets transmitted from the master M.

The baseband unit 14 has a PHY unit 14a and a LINK unit 14b. The PHY unit 14a converts the signal demodulated by the RF unit 13 into a digital signal. The LINK unit 14b extracts a packet having a specific access address and calculates an ideal PCD count value (ideal PCD count value) from the packet interval information contained in the packet. The PCD count value is the count value of a counter (called PCD counter 12a) that counts the interval of packets transmitted from the master M, as described later. In this way, the LINK unit 14b functions as an information extraction unit that extracts information about the packet interval contained in the received packet, and an ideal count value calculation unit that calculates an ideal count value based on the extracted information about the packet interval. In addition, the LINK unit 14b may receive the PCD count value of the communication partner as the ideal PCD count value.

The CPU 15 performs a comparison process (CMP), a PCD control process, a SyncDelay detection process (end time information acquisition section), and a Depacket process. In the comparison process, the ideal PCD count value calculated by the LINK section 14b or the PCD count value of the communication partner is compared with the count value of a PCD counter 12a (described later) in the own device.

In the PCD control process, the difference between the ideal PCD count value and the count value of the PCD counter 12a is detected based on the comparison result of the comparison process, and the frequency of the reference clock signal that operates the PCD counter 12a is controlled based on that difference.

In the Depacket process, the contents of the received packet are extracted. In the Sync Delay detection process, the Synchronization Delay contained in the received packet is detected. Information such as the Synchronization Delay and audio data in the packet is stored in the first RAM 22. The data stored in the first RAM 22 is read out by the audio processing unit 16.

In this way, the CPU 15 functions as a difference calculation unit that calculates the difference between the PCD count value and the ideal count value, and a frequency adjustment unit that adjusts the frequency of the reference clock signal based on the difference.

In addition, when the CPU 15 adjusts the sound output timing and checks the sound delay between the left and right earphones 3a, 3b, it performs a process of generating an LR synchronization packet that synchronizes the left and right earphones 3a, 3b, and a process of generating a playback delay value during LR communication.

The audio processing unit 16 has a DSP 16a, reads packet information stored in the first RAM 22, and calculates the above-mentioned Presentation Delay. The audio processing unit 16 also has a built-in DMAC 16b that performs DMA transfer of the audio data of the packets stored in the first RAM 22. The DMAC 16b stores the audio data in the second RAM 23.

In addition, when the audio processing unit 16 adjusts the sound output timing and checks the sound delay between the left and right earphones 3a, 3b, it performs packet delay processing using the playback delay value generated by the CPU 15, and mixes the audio data taking into account the playback delay value.

The clock generation unit 11 has a crystal oscillator 11a, a 1/2 frequency divider 11b, a PLL circuit (SysPLL) 11c, a 1/N frequency divider 11d, an unequal frequency division PCD clock generation unit 11e, and a 1/4 frequency divider 11f. The crystal oscillator 11a outputs a source oscillation signal of, for example, 32 MHz. The 1/2 frequency divider 11b outputs a frequency-divided signal in which the frequency of the source oscillation signal is reduced by half. The PLL circuit 11c uses the frequency-divided signal to generate a clock signal that is PLL-controlled. The frequency of the clock signal is, for example, a signal with a frequency faster than that of the source oscillation signal. The 1/N frequency divider 11d generates a frequency-divided signal in which the frequency of the clock signal is reduced by 1/N. The unequal frequency division PCD clock generating unit 11e variably controls the frequency of a clock signal that is the source of a reference clock signal that operates the PCD counter 12a, depending on the difference between the ideal PCD count value and the count value of the PCD counter 12a. The frequency of the clock signal output from the unequal frequency division PCD clock generating unit 11e is divided by four by a quarter divider 11f to generate a reference clock signal.

The counter unit 12 has a PCD counter 12a and a frequency division control register 12b. The frequency division control register 12b stores a frequency division control value corresponding to the difference between the ideal PCD count value and the count value of the PCD counter 12a, calculated by the CPU 15 described above. The unequal frequency division PCD clock generation unit 11e described above sets the frequency division ratio of the clock signal based on the frequency division control value stored in the frequency division control register 12b.

The PCD counter 12a is a 32-bit counter that performs counting operations in synchronization with the reference clock signal output from the 1/4 frequency divider 11f. The PCD counter 12a counts the interval between packets transmitted from the master M in synchronization with the reference clock signal. The count value of the PCD counter 12a is sent to the CPU 15 and also to the BIF 17.

The BIF 17 has a BIF section 17a, a comparator (CMP) 17b, a trigger generation section (Kicker) 17c, a FIFO 17d, and an I2S communication section 17e. The comparator 17b compares the count value of the PCD counter 12a with a value corresponding to the playback time determined by the Synchronization Delay included in the packet sent from the master M and the Presentation Delay calculated by the audio processing section 16. When the comparator 17b detects a match, the trigger generation section 17c outputs a trigger signal.

When a trigger signal is output from the trigger generating unit 17c, the FIFO 17d sequentially outputs the audio data stored in the second RAM 23. The audio data output from the FIFO 17d is serially transmitted to the AIF 18 via the I2S communication unit 17e.

The AIF 18 performs a predetermined audio processing on the audio data output from the BIF 17, and then transmits it to the audio output unit 19. The audio output unit 19 performs D/A conversion on the audio data from the AIF 8 and outputs it to the speaker 20. In addition, the surrounding audio signal collected by the microphone 21 is A/D converted and sent to the AIF 18.

Figure 5 is a functional block diagram of the software processing performed by master M and slaves S1 and S2. More specifically, the area above the dashed line in Figure 5 shows the functional blocks of the software processing, and the area below the dashed line shows the hardware configuration blocks related to the software processing.

The hardware configuration blocks shown in FIG. 5 correspond to some of the blocks in the block diagram of FIG. 4. For example, the BLE-PHY counter 14c in FIG. 5 is provided inside the LINK unit 14b in FIG. 4. The PCD counter 12a in FIG. 5 corresponds to the PCD counter 12a inside the counter unit 12 in FIG. 4. The BIF 17 in FIG. 5 corresponds to the BIF 17 in FIG. 4. Although omitted in FIG. 5, in reality, the AIF 18 and the audio output unit 19 are present between the BIF 17 and the speaker 20 as shown in FIG. 4. The PCD latch unit 17f in FIG. 5 is provided, for example, in the comparator 17b in FIG. 4. The PCD control unit 11g in FIG. 5 is provided in the unequal frequency division PCD clock generation unit 11e in FIG. 4.

The software functional block diagram shown in FIG. 5 includes a BLE-PCD counter pair acquisition unit 31, a left/right PCD deviation calculation unit 32, an output PCD calculation unit (synchronization unit) 33, a Presentation Delay calculation unit (start time calculation unit) 34, an audio decoder 35, an audio frame counter (fifth counter) 36, an audio PCD counter pair acquisition unit (count value acquisition unit) 37, a dropout/wrap-around detection unit 38, an outside allowable error data removal unit 39, a BLE parameter extraction unit 40, an ideal PCD value calculation unit 41, a PCD difference extraction unit 42, a speed component extraction unit 43, an acceleration component extraction unit 44, an ideal PCD control value calculation unit 45, and a possible PCD control value calculation unit 46. These software functional blocks are mainly executed by the CPU 15 in FIG. 4.

The BLE-PCD counter pair acquisition unit 31 acquires a pair of the count value of the BLE-PHY counter 14c and the count value of the PCD counter 12a of the communication partner (e.g., master M), and also acquires a pair of the count value of the BLE-PHY counter 14c and the count value of the PCD counter 12a of its own device (e.g., slaves S1 and S2). The count value of the BLE-PHY counter 14c is periodically calibrated so that it becomes the same value between master M and slaves S1 and S2, or so that the difference between the count values becomes the same. For this reason, in the following explanation, it is assumed that the count values of the BLE-PHY counters 14c on the master side and slave side are the same, or that the difference between them is the same.

The left/right PCD deviation calculation unit 32 calculates the difference between the count value of the PCD counter 12a of the master M and the count values of the PCD counters 12a of the slaves S1 and S2. The Presentation Delay calculation unit 34 calculates the Presentation Delay from the Synchronous Delay included in the packet transmitted from the communication partner (e.g., master M). The output PCD calculation unit 33 calculates the count value of the PCD counter 12a corresponding to the playback time of the audio data based on the Presentation Delay and the difference between the count values of the PCD counter 12a calculated by the left/right PCD deviation calculation unit 32.

The audio frame counter 36 counts the number of audio frames output. The audio PCD counter pair acquisition unit 37 acquires the count value of the PCD counter 12a and the count value of the BLE-PHY counter 14c of its own device (e.g., slaves S1 and S2) when the audio frame counter 36 counts up. The count values of the PCD counter 12a and the BLE-PHY counter 14c acquired by the audio PCD counter pair acquisition unit 37 are transmitted to the communication partner (e.g., master M).

The dropout/wrap-around detection unit 38 interpolates the count value when the PCD counter 12a fails to count the interval between packets. In addition, since the PCD counter 12a restarts counting from 0 when it reaches its maximum count value, the dropout/wrap-around detection unit 38 detects that the PCD counter 12a has restarted counting from 0 in the middle of counting and calculates the count value corresponding to the interval between packets.

The outside error tolerance data removal unit 39 improves the reliability of the count value by removing the count value of the PCD counter 12a if the count value is not within the expected range.

The BLE parameter extraction unit 40 extracts BLE parameters contained in the received packet. The BLE parameters include, for example, information regarding the interval between parameters.

The ideal PCD value calculation unit 41 calculates an ideal PCD count value based on information about packet intervals included in the BLE parameters. More specifically, the ideal PCD value calculation unit 41 latches the packet interval (connection interval) included in the received packet for each access address in the PHY unit 14a, and sets the PCD count value of the master M at that time as the expected value.

The PCD difference extraction unit 42 compares the count value of the PCD counter 12a in its own device (e.g., slaves S1 and S2) latched by the PCD latch unit 17f with the ideal PCD count value to extract the difference. Since the difference extracted by the PCD difference extraction unit 42 may contain an abnormal value, the unit does not detect the difference for each time, but rather looks at the rate of change of the difference over multiple times and excludes abnormal difference values.

For example, if the PCD count value of the Nth connection interval is PCDresultN and the Nth ideal PCD count value is PCDreferN, the difference ΔPCDdiff is calculated by the following formula (1).
ΔPCDdiff={(PCDresultN−PCDresult1)−(PCDreferN−PCDrefer1)}/N
…(1)

Figure 6 is a diagram showing an example of the relationship between the PCD count value and the ideal PCD count value. The horizontal axis of Figure 6 is time, and the vertical axis is the PCD count value. The white circles in Figure 6 represent the PCD count values, and the straight line in Figure 6 represents the ideal PCD count value. The PCD count value at time t2 is excluded by the unit for excluding data outside the allowable error. The distance between the straight line and the white circle represents the difference in the PCD count value. The PCD count value contains some error each time a packet is received, but by taking into account the results of measuring the PCD count value multiple times, a highly reliable difference can be calculated.

The velocity component extraction unit 43 extracts a velocity component that indicates the value by which the difference extracted by the PCD difference extraction unit 42 changes per unit time. The acceleration component extraction unit 44 extracts an acceleration component that indicates the value by which the velocity component extracted by the velocity component extraction unit 43 changes per unit time.

The ideal PCD control value calculation unit 45 calculates the PCD control value so that the speed component and acceleration component approach zero. A state transition may be provided to calculate a PCD control value that is slightly over or under, or in some cases control may be abandoned, or the gain of the PCD control value may be adjusted so that the control value is large in the initial state and the rate of change of the control value is small in states other than the initial state.

The possible PCD control value calculation unit 46 performs a rounding process so that the PCD control value falls within a predetermined range. The PCD control value calculated by the possible PCD control value calculation unit 46 is stored in the division control register 12b in FIG. 4. The unequal division PCD clock generation unit 11e generates a clock divided by a division ratio according to the PCD control value. Based on this clock, the 1/4 divider 11f generates a reference clock signal.

Figure 7 is a flowchart showing the processing operation when the master M is an information providing terminal 2 such as a smartphone, and the slaves S1 and S2 are earphones 3a and 3b. First, ICO (Isychronous Connection Oriented) communication is performed between the master M and the slaves S1 and S2 (step S1). In ICO communication, as shown in Figure 3, multiple packets are transmitted sequentially at a predetermined interval.

Next, the master M and the slaves S1 and S2 each obtain the access address contained in the packet sent from the communication partner (step S2). The communication partner can be identified by the access address. In this case, it is determined whether the packet is from a communication partner that performs the clock recovery process described later.

If the communication partner can be identified by the access address, clock recovery processing is started (step S3). In the clock recovery processing, as described in detail later, the PCD counters 12a of the slaves S1 and S2 count the interval between packets transmitted from the information providing terminal 2 functioning as the master M, and the frequency of the reference clock signal that operates the PCD counters 12a is controlled so that the count value of the PCD counters 12a matches the ideal PCD count value.

Next, Asynchronous Connection Less (ACL) communication is started between the left slave S1, S2 (earphones 3a, 3b) and the right slave S1, S2 (earphones 3a, 3b) (step S4). ACL communication involves sending and receiving packets between the left and right earphones 3a, 3b to adjust the playback timing and check for sound lag.

First, an access address is obtained (step S5). The communication partner is identified by the access address. Next, a profile of the GATT (Genetic Attribute) included in the received packet is obtained (step S6). Next, based on the obtained GATT, it is determined whether it is the master M or the slaves S1 and S2 (step S7). In the case of the master M, the flowchart of FIG. 7 is terminated. On the other hand, in the case of the slaves S1 and S2, clock recovery processing is performed (step S8). In the clock recovery processing of step S8, the PCD count value sent from the earphones 3a and 3b that are the master M is obtained by the earphones 3a and 3b that are the slaves S1 and S2, and the difference with the PCD count value of the slaves S1 and S2 is calculated, and the frequency of the reference clock signal that operates the PCD counters 12a of the slaves S1 and S2 is adjusted so that the difference becomes small. In this way, the clock recovery processing performed after pairing is performed only by the slaves S1 and S2.

Figure 8 is a flowchart showing the processing operation when one of the master M and slave S is the left earphone 3b and the other is the right earphone 3a. First, ACL communication is started (step S11). Next, an access address is acquired (step S12). Next, a GATT profile is acquired (step S13). Next, based on the acquired GATT profile, it is determined whether it is the master M or the slave S (step S14). If it is determined to be the master M, the processing of Figure 9 is terminated, and if it is determined to be the slave S, the clock recovery processing shown in Figure 8 is performed (step S15).

The processing in FIG. 8 is performed between the left and right earphones 3a, 3b, for example, when pairing the left and right earphones 3a, 3b with each other before pairing with the information providing terminal 2, or for the purpose of synchronizing the left and right earphones 3a, 3b with each other while receiving audio data from the information providing terminal 2.

Figure 9 is a detailed flowchart of the clock recovery process in the flowcharts of Figures 7 and 8. The flowchart in Figure 9 shows the clock recovery process performed by slaves S1 and S2 (earphones 3a and 3b). First, it is determined whether or not to change the frequency of the reference clock signal that operates the PCD counter 12a (step S21). In step S21, if the master M is the information providing terminal 2 and the slaves S1 and S2 are the earphones 3a and 3b, it is determined that the frequency of the reference clock signal is to be changed.

If it is determined that the frequency of the reference clock signal is to be changed, the reference point (reference time) of the clock recovery is determined (step S22). Here, for example, the time when a specific packet is received is set as the reference point. Next, the count value (PCD count value) of the PCD counter 12a in the slaves S1 and S2 is read (step S23). Next, the difference between the count value of the PCD counter 12a and the ideal PCD count value calculated based on the packet interval is calculated (step S24). In step S24, when performing synchronization processing between the left and right earphones 3a and 3b that receive audio data from the information providing terminal 2, one of the earphones 3a and 3b is set as the master M, and the difference between the PCD count value transmitted from the master M and the PCD count value of the slave S is calculated.

Next, the frequency of the reference clock signal that operates the PCD counter 12a is adjusted based on the calculated difference (step S25). Next, the count value of the PCD counter 12a and the count value of the BLE-PHY counter 14c are paired and transmitted to the master M (step S26).

Next, it is determined whether or not to perform phase adjustment of the count value of the PCD counter 12a (step S27). If the master M is the information providing terminal 2, phase adjustment is not performed, and the process of FIG. 8 is terminated. On the other hand, if the sound output timing is to be adjusted between the left earphone 3b and the right earphone 3a, it is determined that phase adjustment is to be performed.

If it is determined that a phase adjustment is to be performed on the count value of the PCD counter 12a, a pair of the count value of the PCD counter 12a and the count value of the BLE-PHY counter 14c transmitted from the master M (one of the earphones 3a, 3b) is obtained (step S28).

Next, the difference between the PCD count value of the master M (one of the earphones 3a and 3b) and the PCD count value of the slaves S1 and S2 (the other earphones 3a and 3b) is calculated (step S29). Next, the PCD count values of the slaves S1 and S2 are adjusted based on the calculated difference (step S30).

(Clock recovery processing)
Next, the clock recovery process will be described in detail. As shown in the flowcharts of Figures 7 to 9, the clock recovery process is performed when the master M is the information providing terminal 2 and the slaves S1 and S2 are the earphones 3a and 3b, and also when the master M is one of the earphones 3a and 3b and the slave S is the other earphone 3a and 3b.

The processing blocks related to the clock recovery process are enclosed within the dashed line in the block diagram of Figure 5. For the clock recovery process, the hardware includes a PCD latch unit 17f and a PCD control unit 11g, and the software includes a dropout/wrap-around detection unit 38, an out-of-tolerance data removal unit 39, a BLE parameter extraction unit 40, an ideal PCD value calculation unit 41, a PCD difference extraction unit 42, a speed component extraction unit 43, an acceleration component extraction unit 44, an ideal PCD control value calculation unit 45, and a possible PCD control value calculation unit 46.

Figures 10 to 12 are diagrams showing the procedure of the clock recovery process performed by the slaves S1 and S2 with arrows. First, as shown by the arrows in Figure 10, for example, when a new packet is received, the PCD count value counted by the PCD counter 12a is latched by the PCD latch unit 17f. Next, as shown in Figure 11, the difference between the latched PCD count value and the ideal PCD count value calculated by the ideal PCD value calculation unit 41 is calculated by the PCD difference extraction unit 42. After that, through processing by the speed component extraction unit 43 and the acceleration component extraction unit 44, the ideal PCD control value is calculated by the ideal PCD control value calculation unit 45. Next, as shown in Figure 12, the possible PCD control value calculation unit 46 calculates the PCD control value, and the frequency of the reference clock signal that operates the PCD counter 12a is controlled based on this PCD control value.

The clock recovery process shown in Figures 10 to 12 corrects the discrepancy in the PCD count values of slaves S1 and S2.

The clock recovery process is performed by the slaves S1 and S2 when the master M is the information providing terminal 2. In addition, for example, when one of the left and right earphones 3a and 3b is the master M, the clock recovery process is also performed by the other earphone 3a or 3b. The clock recovery process in this case is the process of step S35 in FIG. 8. In the clock recovery process performed between the earphones 3a and 3b, the PCD count value of the earphones 3a and 3b of the master M is sent to the other earphones 3a and 3b, which are the slaves S1 and S2. The slaves S1 and S2 calculate the difference between the PCD count value of their own device and the PCD count value of the master M (step S14 in FIG. 9), and adjust the frequency of the reference clock signal so that the difference becomes zero (step S15).

As a result, after audio output has begun from the left and right earphones 3a, 3b, the left and right earphones 3a, 3b continue to receive audio data from the information providing terminal 2, which is the master M, and can perform synchronization processing between the left and right earphones 3a, 3b in between performing synchronization processing with the information providing terminal 2.

When the clock recovery process is completed, the sound output timing of the left and right earphones 3a and 3b is adjusted. FIG. 13 is a conceptual diagram of the sound output timing adjustment of the left and right earphones 3a and 3b. In the example of FIG. 13, either the left earphone 3b or the right earphone 3a is the master M, and the other is the slave S. While the count value (BLE-PHY count value) of the BLE-PHY counter 14c of the master M changes from 2 to 7, the count value (PCD count value) of the PCD counter 12a changes from 100 to 600. On the other hand, while the BLE-PHY count values of the slaves S1 and S2 change from 2 to 7, the PCD count value changes from 110 to 610. In this way, the BLE-PHY count values of the master M and the slaves match. This is because a process is performed to match the BLE-PHY count values of the slaves S1 and S2 to the BLE-PHY count value of the master M every time a packet is received. On the other hand, there are cases where the PCD count value is different between the master M and the slaves S1 and S2. The reason is that the frequencies of the source oscillation signals output from the crystal oscillators 11a in the master M and the slaves S1 and S2 do not necessarily match, causing a discrepancy in the PCD count value.

In adjusting the sound output timing of the left and right earphones 3a and 3b, the difference between the PCD count values is detected, and the timing at which the left and right earphones 3a and 3b will output sound is determined taking that difference into consideration. FIG. 13 shows an example in which it is determined that sound will be output when the BLE-PHY count value is 7 and the PCD count value is then counted up by 60. In this case, the sound output timing of the master M is when the BLE-PHY count value is 7 and the PCD count value is 660, whereas the sound output timing of the slaves S1 and S2 is when the BLE-PHY count value is 7 and the PCD count value is 670. In this way, by detecting the difference between the PCD count values of the master M and the slaves S1 and S2 and determining the sound output timing taking that difference into consideration, the sound output timing of the left and right earphones 3a and 3b can be matched.

Figures 14 to 18 are diagrams using arrows to show the steps of adjusting the sound output timing of the left and right earphones 3a, 3b and checking the deviation of the sound output timing, which are performed by the slave S. The processes in Figures 14 to 18 are performed with one of the left and right earphones 3a, 3b as the master M and the other as the slave S.

First, as shown by the arrow line in Figure 14, when the BLE-PCD counter pair acquisition unit 31 receives a packet from master M, it acquires the pair of count values of master M's BLE-PHY counter 14c and PCD counter 12a contained in the packet.

Also, as shown in Figure 15, the BLE-PCD counter pair acquisition unit 31 acquires a pair of count values of the BLE-PHY counter 14c and PCD counter 12a of the own device (slave S). The left/right PCD deviation calculation unit calculates the difference between the count value of the PCD counter 12a of the master M and the count value of the PCD counter 12a of the slave S. In this specification, the BLE-PHY counter 14c of the master M may be referred to as the first counter, the PCD counter 12a of the master M as the second counter, the BLE-PHY counter 14c of the slave S as the third counter, and the PCD counter 12a of the slave S as the fourth counter.

16, the Presentation Delay calculation unit 34 calculates the Presentation Delay from the Synchronous Delay included in the received packet. The output PCD calculation unit 33 calculates the count value of the PCD counter 12a corresponding to the playback time of the audio data based on the Presentation Delay and the difference between the count values of the PCD counter 12a calculated by the left/right PCD deviation calculation unit 32. When the count value of the PCD counter 12a reaches the count value corresponding to the playback time, the audio data decoded by the audio decoder 35 is output as audio from the speaker 20 via the BIF 17, the AIF 18 and the audio output unit 19.

The audio data decoded by the audio decoder 35 is also sent to the audio frame counter 36 as shown in FIG. 17. The audio frame counter 36 counts the number of audio frames. In synchronization with the timing when the audio frame counter 36 counts up, the audio PCD counter pair acquisition unit 37 acquires the count value and PCD count value of the BLE-PHY counter 14c of its own device (slave S). The acquired count value and PCD count value of the BLE-PHY counter 14c are transmitted to the master M as shown in FIG. 18.

The sound output timing adjustments and sound output timing offset adjustments shown in Figures 14 to 18 are performed while the left and right earphones 3a, 3b are receiving packets containing audio data from the information providing terminal 2. The left and right earphones 3a, 3b operate as slaves S1, S2 when receiving packets containing audio data from the information providing terminal 2. When the left and right earphones 3a, 3b are performing the sound output timing adjustments and sound output timing offset adjustments shown in Figures 14 to 18 between each other, one of the earphones 3a, 3b becomes the master M, and the other earphone 3a, 3b becomes the slave S.

As a result, after audio output has started from the left and right earphones 3a, 3b, the left and right earphones 3a, 3b continue to receive audio data from the information providing terminal 2, which is the master M, and can perform synchronization processing with the information providing terminal 2 while also performing synchronization processing between the left and right earphones 3a, 3b.

In this way, in this embodiment, when the master M and the slaves S1 and S2 perform packet communication conforming to BLE, the slaves S1 and S2 perform clock recovery processing, so that the master M and the slaves S1 and S2 can synchronize their time series data. In the clock recovery processing, when packet communication is performed between the information providing terminal 2 functioning as the master M and the slaves S1 and S2 receiving packets from the information providing terminal 2, the PCD counters 12a of the slaves S1 and S2 measure the interval between packets transmitted from the master M, calculate the ideal PCD count value from the BLE parameters included in the packets, and calculate the difference between the PCD count value and the ideal PCD count value. The frequency of the reference clock signal that operates the PCD counter 12a is controlled based on the difference, so that the PCD count value of the slaves S1 and S2 can be made to match the PCD count value of the master M, or the difference between the two can be made constant.

The synchronization device 1 according to the present embodiment performs such clock recovery processing with the information providing terminal 2 such as a smartphone as the master M and the left and right earphones 3a, 3b as the slaves S1, S2, and then adjusts the sound output timing of the left and right earphones 3a, 3b. In adjusting the sound output timing, the playback time of the audio data can be synchronized between the master M and the slaves S1, S2 using the Synchronous Delay included in the packet, the Presentation Delay calculated from the Synchronous Delay, the PCD count value, and the difference information thereof.

Once audio output has started, one of the earphones 3a, 3b can be set as the master M and the other earphones 3a, 3b as the slaves S1, S2 to check and adjust the timing discrepancy of the sound output. Here, the master M and the slaves S1, S2 exchange pairs of BLE-PHY count values and PCD count values, and the slaves S1, S2 detect the difference in the PCD count values, for example. The timing of the audio output is then adjusted according to that difference. This makes it possible to match the timing of the audio output between the left and right earphones 3a, 3b, even if the PCD count values of the left and right earphones 3a, 3b shift over time.

At least a part of the synchronization device 1 described in the above embodiment may be configured with hardware or software. If configured with software, a program that realizes at least a part of the functions of the synchronization device 1 may be stored on a recording medium such as a flexible disk or CD-ROM, and read and executed by a computer. The recording medium is not limited to removable ones such as magnetic disks and optical disks, but may be fixed recording media such as a hard disk drive or memory.

In addition, a program that realizes at least a part of the functions of the synchronization device 1 may be distributed via a communication line (including wireless communication) such as the Internet. Furthermore, the program may be encrypted, modulated, or compressed and distributed via a wired line or wireless line such as the Internet, or stored on a recording medium.

The present technology can be configured as follows.
(1) A synchronization device that synchronizes time-series data between a master and a slave by wireless communication, comprising:
The master is
a packet generator for generating a plurality of packets;
a packet transmission unit that transmits an arbitrary packet of the plurality of packets to the slave at a predetermined interval;
The slave is
A packet receiving unit for receiving the arbitrary packet;
a counter that counts the interval between the arbitrary packets based on a reference clock signal;
A synchronization device that adjusts a frequency of the reference clock signal based on the count value of the counter, thereby achieving synchronization between the master and the multiple slaves.
(2) A synchronization device that synchronizes time-series data between a master and a plurality of slaves by wireless communication, comprising:
The master is
a packet generator for generating a plurality of packets;
a packet transmission unit that transmits any one of the plurality of packets to one of the plurality of slaves at a predetermined interval;
One of the plurality of slaves
A packet receiving unit for receiving the arbitrary packet;
a counter that counts the interval between the arbitrary packets based on a reference clock signal;
A synchronization device that adjusts a frequency of the reference clock signal based on the count value of the counter, thereby achieving synchronization between the master and the multiple slaves.
(3) the plurality of packets include information regarding packet intervals and time series data;
a latch unit that latches the count value of the counter every time a new packet is received by the packet receiving unit;
an information extraction unit that extracts information regarding a packet interval included in the packet received by the packet receiving unit;
an ideal count value calculation unit that calculates an ideal count value based on the extracted information about the interval between packets;
a difference calculation unit that calculates a difference between the count value of the counter latched by the latch unit and the ideal count value;
and a frequency adjustment unit that adjusts a frequency of the reference clock signal based on the difference.
(4) The synchronization device described in (3), wherein the frequency adjustment unit lowers the frequency of the reference clock signal if the count value of the counter latched by the latch unit is greater than the ideal count value, and increases the frequency of the reference clock signal if the count value of the counter latched by the latch unit is smaller than the ideal count value.
(5) The slave is
a control value calculation unit that calculates a control value for adjusting the frequency of the reference clock signal based on a change in the difference over time so that the difference becomes equal to or smaller than a predetermined value;
The synchronization device according to (3) or (4), wherein the frequency adjustment unit adjusts the frequency of the reference clock signal based on the control value.
(6) The slave is
a speed component extracting unit that extracts a speed component indicating a change value per unit time of the difference;
an acceleration component extraction unit that extracts an acceleration component that indicates a change value per unit time of the velocity component,
The synchronization device according to (5), wherein the control value calculation unit calculates the control value based on the velocity component and the acceleration component.
(7) The slave has a control value adjustment unit that adjusts the control value so that the variation in the control value falls within a predetermined range,
The synchronization device according to (5) or (6), wherein the frequency adjustment unit adjusts the frequency of the reference clock signal based on the control value adjusted by the control value adjustment unit.
(8) The packet transmission unit transmits a packet group including the plurality of packets a plurality of times at a predetermined interval;
the counter in the slave measures an interval between each packet included in the packet group;
The slave is
an interpolation unit that interpolates count values when there is a packet interval whose count value has not been measured among the intervals between packets included in the packet group;
an exclusion unit that excludes count values that are outside a tolerance range from among the count values counted by the counter;
The synchronization device according to any one of (3) to (7), wherein the difference calculation unit calculates the difference between a count value obtained by interpolation by the interpolation unit and exclusion by the exclusion unit and the ideal count value.
(9) The synchronization device according to any one of (1) to (8), wherein the time series data is data including biometric information or audio data.
(10) A synchronization device described in any one of (3) to (9), wherein the packet receiving unit in each of the plurality of slaves performs wireless communication with the master at different times to receive the plurality of packets including unique time series data transmitted from the master.
(11) The master is an information providing terminal having a storage unit for storing audio data,
two slaves that wirelessly communicate with the information providing terminal at different times,
The synchronization device according to any one of (1) to (10), wherein one of the two slaves is an earphone that reproduces audio data for the left ear transmitted from the master, and the other is an earphone that reproduces audio data for the right ear transmitted from the master.
(12) A synchronization device that synchronizes time-series data between a master and a slave by wireless communication, comprising:
The master is
a first counter that performs a counting operation based on a first reference clock signal;
a second counter that counts intervals between a plurality of packets transmitted from the information providing terminal based on a second reference clock signal;
a first packet transmitting unit configured to transmit a packet including the count value of the first counter and the count value of the second counter to the slave;
The slave is
a third counter that performs a counting operation based on a third reference clock signal;
a fourth counter that counts intervals between the plurality of packets transmitted from the information providing terminal based on a fourth reference clock signal;
a second packet transmitting unit configured to transmit a packet including the count value of the third counter and the count value of the fourth counter to the master;
a frequency adjusting unit that adjusts a frequency of the fourth reference clock signal based on the count value of the second counter and the count value of the fourth counter transmitted from the master.
(13) A difference calculation unit is provided that calculates a difference between the count value of the second counter transmitted from the master and the count value of the fourth counter,
The synchronization device according to (12), wherein the frequency adjustment unit adjusts the frequency of the fourth reference clock signal based on the difference.
(14) A synchronization device described in (12) or (13), in which the count value of the first counter and the count value of the third counter are adjusted so that they become the same or the difference between them becomes the same each time packet communication is performed between the master and the slave.
(15) The slave is
an end time information acquiring unit that acquires information regarding a transmission end time included in a plurality of packets transmitted from the information providing terminal;
a start time calculation unit that calculates information regarding a start time of reproduction or processing of the time series data based on the information regarding the transmission end time;
and a synchronization unit that synchronizes with the master a time at which time series data is reproduced or processed based on a count value of the third counter, a count value of the fourth counter after the frequency of the fourth reference clock signal has been adjusted by the frequency adjustment unit, the difference calculated by the difference calculation unit after the frequency of the fourth reference clock signal has been adjusted by the frequency adjustment unit, and information regarding the start time.
(16) The slave is
a fifth counter for counting divisions of the reproduced or processed time series data;
a count value acquiring unit that acquires a count value of the third counter and a count value of the fourth counter every time the fifth counter counts up,
The synchronization device described in any one of (12) to (15), wherein the second packet transmitting unit transmits the count value of the third counter and the count value of the fourth counter acquired by the count value acquiring unit to the master.
(17) The time series data is audio data,
The synchronization device according to (16), wherein the fifth counter counts the number of frames of the audio data.
(18) The frequency adjusting unit adjusts a frequency of the fourth reference clock signal based on the difference when the master and the slave start packet communication.
The synchronization device according to any one of (12) to (17), wherein the synchronization unit synchronizes with the master the time at which the master and the slave play or process time series data between packet communication between the master and the information providing terminal.
(19) A synchronization device described in any one of (12) to (18), wherein one of the master and the slave is a first earphone that receives audio data for the left ear from the information providing terminal, and the other is a second earphone that receives audio data for the right ear from the information providing terminal at a timing separate from that of the first earphone.
(20) The synchronization device described in (19), wherein each of the first earphone and the second earphone transmits and receives packets to each other, and has a master/slave determination unit that determines whether the first earphone and the second earphone are the master or the slave based on profile information included in the packets received by each of the first earphone and the second earphone.
(21) The synchronization device according to any one of (1) to (20), wherein the master and the slave perform packet communication in compliance with the Bluetooth (registered trademark) Low Energy standard.
(22) A synchronization method for synchronizing time series data between a master and a plurality of slaves by wireless communication, comprising:
The master is
Generate multiple packets,
transmitting any packet among the plurality of packets to one of the plurality of slaves at a predetermined interval;
One of the plurality of slaves is
receiving said any packet;
Counting the interval between the arbitrary packets with a counter based on a reference clock signal;
A synchronization method for achieving synchronization between the master and the plurality of slaves by adjusting a frequency of the reference clock signal based on a count value of the counter.
(23) A synchronization method for synchronizing time series data between a master and a slave by wireless communication, comprising:
The master is
A first counter performs a counting operation based on a first reference clock signal;
counting intervals between a plurality of packets transmitted from the information providing terminal with a second counter based on a second reference clock signal;
Transmitting a packet including the count value of the first counter and the count value of the second counter to the slave;
The slave is
A third counter performs a counting operation based on a third reference clock signal;
counting intervals between the plurality of packets transmitted from the information providing terminal by a fourth counter based on a fourth reference clock signal;
Transmitting a packet including the count value of the third counter and the count value of the fourth counter to the master;
A synchronization method comprising: adjusting a frequency of the fourth reference clock signal based on a count value of the second counter and a count value of the fourth counter transmitted from the master.

The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by a person skilled in the art, and the effects of the present disclosure are not limited to the above. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure derived from the contents defined in the claims and their equivalents.

1 Synchronization device, 2 Information providing terminal, 3a, 3b Earphone, 11 Clock generation unit, 11a Crystal oscillator, 11b 1/2 frequency divider, 11c PLL circuit, 11d 1/N frequency divider, 11e Unequal frequency division PCD clock generation unit, 11f 1/4 frequency divider, 12 Counter unit, 12a PCD counter, 13 RF unit, 14 Baseband unit, 14a PHY unit, 14b LINK unit, 15 CPU, 16 Audio processing unit, 16a DSP, 16b DMAC, 17 BIF, 17a BIF unit, 17b Comparator, 17c Trigger generation unit, 17d FIFO, 17e I2S communication unit, 18 Audio interface unit, 19 Audio output unit, 20 Speaker, 21 Microphone, 31 BLE-PCD counter pair acquisition unit, 32 left/right PCD deviation calculation unit, 33 output PCD calculation unit, 34 presentation delay calculation unit, 35 audio decoder, 36 audio frame counter, 37 audio PCD counter pair acquisition unit, 38 dropout/wrap around detection unit, 39 outside allowable error data removal unit, 40 BLE parameter extraction unit, 41 ideal PCD value calculation unit, 42 PCD difference extraction unit, 43 velocity component extraction unit, 44 acceleration component extraction unit, 45 ideal PCD control value calculation unit, 46 possible PCD control value calculation unit

Claims (11)

A synchronization device that synchronizes time series data between a master and a slave by wireless communication,
The master is
a first counter that performs a counting operation based on a first reference clock signal;
a second counter that counts intervals between a plurality of packets transmitted from the information providing terminal based on a second reference clock signal;
a first packet transmitting unit configured to transmit a packet including the count value of the first counter and the count value of the second counter to the slave;
The slave is
a third counter that performs a counting operation based on a third reference clock signal;
a fourth counter that counts intervals between the plurality of packets transmitted from the information providing terminal based on a fourth reference clock signal;
a second packet transmitting unit configured to transmit a packet including the count value of the third counter and the count value of the fourth counter to the master;
a frequency adjusting unit that adjusts a frequency of the fourth reference clock signal based on a count value of the second counter and a count value of the fourth counter transmitted from the master.
Synchronization device. a difference calculation unit that calculates a difference between the count value of the second counter transmitted from the master and the count value of the fourth counter,
The frequency adjusting unit adjusts the frequency of the fourth reference clock signal based on the difference.
The synchronization device according to claim 1 . The count value of the first counter and the count value of the third counter are adjusted so that they become the same or the difference between them becomes the same every time packet communication is performed between the master and the slave.
3. A synchronization device according to claim 1 or 2 . The slave is
an end time information acquiring unit that acquires information regarding a transmission end time included in a plurality of packets transmitted from the information providing terminal;
a start time calculation unit that calculates information regarding a start time of reproduction or processing of the time series data based on the information regarding the transmission end time;
a synchronization unit that synchronizes with the master a time at which the time series data is reproduced or processed, based on a count value of the third counter, a count value of the fourth counter after the frequency of the fourth reference clock signal has been adjusted by the frequency adjustment unit, the difference calculated by the difference calculation unit after the frequency of the fourth reference clock signal has been adjusted by the frequency adjustment unit, and information regarding the start time .
The synchronization device according to claim 2 . The slave is
a fifth counter for counting divisions of the reproduced or processed time series data;
a count value acquiring unit that acquires a count value of the third counter and a count value of the fourth counter every time the fifth counter counts up,
the second packet transmitting unit transmits the count value of the third counter and the count value of the fourth counter acquired by the count value acquiring unit to the master;
A synchronization device according to any one of claims 1 to 4 . the time series data is audio data,
the fifth counter counts the number of frames of the audio data;
The synchronization device according to claim 5 . the frequency adjusting unit adjusts a frequency of the fourth reference clock signal based on the difference when the master and the slave start packet communication;
the synchronization unit synchronizes with the master a time for reproducing or processing time-series data during a time interval between the master and the slave performing packet communication with the information providing terminal;
5. The synchronization device according to claim 4 . one of the master and the slave is a first earphone that receives audio data for a left ear from the information providing terminal, and the other is a second earphone that receives audio data for a right ear from the information providing terminal at a timing separate from that of the first earphone;
A synchronization device according to any one of the preceding claims. Each of the first earphone and the second earphone transmits and receives packets to each other, and has a master/slave determination unit that determines whether the first earphone or the second earphone is the master or the slave based on profile information included in the packets received by each of the first earphone and the second earphone.
The synchronization device according to claim 8 . The master and the slave perform packet communication in accordance with the Bluetooth (registered trademark) Low Energy standard.
A synchronization device according to any one of the preceding claims. A synchronization method for synchronizing time series data between a master and a slave by wireless communication, comprising the steps of:
The master is
A first counter performs a counting operation based on a first reference clock signal;
counting intervals between a plurality of packets transmitted from the information providing terminal with a second counter based on a second reference clock signal;
Transmitting a packet including the count value of the first counter and the count value of the second counter to the slave;
The slave is
A third counter performs a counting operation based on a third reference clock signal;
counting intervals between the plurality of packets transmitted from the information providing terminal by a fourth counter based on a fourth reference clock signal;
transmitting a packet including the count value of the third counter and the count value of the fourth counter to the master;
adjusting a frequency of the fourth reference clock signal based on the count value of the second counter and the count value of the fourth counter transmitted from the master;
Synchronization method.