JP7695975B2 - Optical semiconductor element and its manufacturing method - Google Patents

Description

The present invention relates to an optical semiconductor element and a method for manufacturing the same.

Optical semiconductor elements are known that have two or more active layers stacked vertically with a tunnel junction layer sandwiched between them. Such optical semiconductor elements are used as light-emitting elements to improve optical output when the wavelengths of the stacked active layers are close, and to emit different wavelengths when the wavelengths of the stacked active layers are separated. Similarly, they are also used as light-receiving elements to improve light-receiving efficiency when the wavelengths of the stacked active layers are close, and to have sensitivity to different wavelength bands when the wavelengths of the stacked active layers are separated.

In such optical semiconductor elements, multiple active layers are stacked vertically, so that the active layers are connected in series. In a light-emitting element, when a forward current flows through it, each of the multiple active layers can emit light. Generally, the active layers in this case are pn junctions.

The tunnel junction layer is formed from a high-concentration p-type semiconductor layer and an n-type semiconductor layer, and when a forward voltage is applied to the active layer, a reverse voltage is applied. Normally, if the junctions are made in the order p-type, n-type, p-type (or n-type, p-type, n-type), a thyristor is formed and no current flows, but because the tunnel junction layer sandwiched between the active layers is highly doped, a tunnel effect occurs within the tunnel junction layer, allowing current to flow.

JP 2009-522755 A JP 2018-201009 A

In Patent Document 1, it is described that only Al, Ga, In, and P are preferable as basic constituent materials of the crystal lattice that constitutes the optical semiconductor element, but light emission at a long wavelength exceeding 3000 nm cannot be expected with only these materials. Also, as described in Patent Document 2, it has been conventionally preferable to form a tunnel junction layer with a high concentration of n-type dopant of 1.0×10 ¹⁹ atoms/cm ³ or more, but if an n-type semiconductor layer and a p-type semiconductor layer containing a high concentration of dopant exist between vertically stacked active layers, the dopant may diffuse into the active layer, causing a decrease in reliability or an increase in leakage current.

The present invention was made in consideration of this situation, and aims to improve the characteristics of optical semiconductor elements.

The inventors have thoroughly investigated ways to solve the above problems, and have found an optical semiconductor device and a method for manufacturing the same, in which the first and second active layers contain Sb and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer, thereby completing the present invention. It has also been found that the tunnel junction layer of the present invention exhibits a tunnel effect at a dopant concentration lower than that previously considered necessary. In other words, the gist of the present invention is as follows.

(1) An optical semiconductor element having a first active layer having an emission wavelength of a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having an emission wavelength of a second wavelength,
the first active layer and the second active layer contain Sb;
The tunnel junction layer includes a p-type InAs layer and an n-type InAs layer.
Optical semiconductor element.

(2) The optical semiconductor element according to (1) above, wherein the tunnel junction layer has a dopant concentration of not less than 1.0×10 ¹⁸ atoms/cm ³ and less than 1.0×10 ¹⁹ atoms/cm ³ .

(3) The first active layer and the second active layer have a quantum well structure,
The optical semiconductor element according to (1) or (2), wherein the first wavelength and the second wavelength are 3000 nm or longer.

(4) An optical semiconductor element according to any one of (1) to (3), in which the first wavelength and the second wavelength are identical to each other.

(5) the p-type InAs layer is located on the first active layer side of the tunnel junction layer,
a p-type electron blocking layer between the first active layer and the tunnel junction layer;
The optical semiconductor element according to any one of (1) to (4), wherein a thickness between the first active layer and the tunnel junction layer is 100 nm or less.

(6) The n-type InAs layer is located on the second active layer side of the tunnel junction layer,
a spacer layer between the tunnel junction layer and the second active layer;
The optical semiconductor element according to any one of (1) to (5), wherein the thickness between the tunnel junction layer and the second active layer is 100 nm or less.

(7) forming a first active layer on the substrate, the first active layer having a first wavelength for receiving and emitting light;
forming a tunnel junction layer on the first active layer;
forming a second active layer on the tunnel junction layer, the second active layer having a second wavelength for receiving and emitting light;
Including,
the first active layer and the second active layer contain Sb;
The step of forming the tunnel junction layer includes the steps of forming an n-type InAs layer and forming a p-type InAs layer on the n-type InAs layer.
A method for manufacturing an optical semiconductor element.

(8) The method for producing an optical semiconductor element according to (7) above, wherein the tunnel junction layer has a dopant concentration of not less than 1.0×10 ¹⁸ atoms/cm ³ and less than 1.0×10 ¹⁹ atoms/cm ³ .

It is possible to provide an optical semiconductor element with improved characteristics and a manufacturing method thereof. For example, it is possible to provide an optical semiconductor element with high light emission output and forward voltage when used as a light-emitting element, and a central wavelength of 3000 nm or more, and a manufacturing method thereof. Furthermore, since the leakage current is reduced in the light-emitting element, it is also possible to provide an optical semiconductor element with low dark current and high shunt resistance when used as a light-receiving element, and a manufacturing method thereof.

1 is a schematic cross-sectional view illustrating a first embodiment of an optical semiconductor element according to the present invention. 4 is a schematic cross-sectional view illustrating a second embodiment of an optical semiconductor element according to the present invention. FIG. 5A to 5C are schematic cross-sectional views illustrating an example of a manufacturing method for the second embodiment of the optical semiconductor element according to the present invention. FIG. 4 is a schematic cross-sectional view illustrating an example of a manufacturing method subsequent to FIG. 3. FIG. 5 is a schematic cross-sectional view illustrating an example of a manufacturing method subsequent to FIG. 4 . FIG. 11 is a schematic cross-sectional view illustrating a third embodiment of an optical semiconductor element according to the present invention. 1 is a graph showing the results of measuring the diffusion state of Te ions in Example 1 by secondary ion mass spectrometry (SIMS). 4 is a graph showing the results of measuring the diffusion state of Zn ions in Example 1 by secondary ion mass spectrometry (SIMS).

Before describing the embodiments of the present invention, the following points will be explained.

The active layer containing Sb in this embodiment means a compound also represented as InAs _x Sb _1-x (0<x<1). When it is written as an InAs layer, an AlInAs layer, or an InAsP layer, it means that Sb is not included in the composition ratio, but it is acceptable that Sb source gas is not used during the growth of the layer, and Sb is included as an inevitable dopant element due to the remaining Sb in the chamber or diffusion from an adjacent Sb-containing layer. In addition, when the composition ratio is not specified and it is simply written as "AlInAsSb" in this specification, it means an arbitrary compound in which the chemical composition ratio of group III elements (total of Al and In) and group V elements (total of As and Sb) is 1:1, and the ratio of group III elements Al and In and the ratio of group V elements As and Sb are indefinite, respectively. In this case, it includes the case where the group III element does not contain either Al or In, and also includes the case where the group V element does not contain either As or Sb. The composition ratio of each III-V group element in AlInAsSbP can be measured by photoluminescence measurement, X-ray diffraction measurement, or the like.

In this specification, the term "undoped" refers to a layer in which a specific dopant such as Zn, Te, or Si is not intentionally added. An undoped layer may contain unavoidable dopants that are present during the manufacturing process. The values of the dopant concentrations, such as Zn, Te, and Si, are determined by SIMS analysis.

The III-V compound semiconductor in this embodiment contains at least one of Al, Ga, and In as a group III element, and at least P, As, and Sb as a group V element.

The thickness of each layer formed by epitaxial growth can be calculated from cross-sectional observation of the grown layer using a SEM (scanning electron microscope) or a TEM (transmission electron microscope). It is preferable to use an SEM when the film thickness is 10 nm or more, and a TEM when the film thickness is less than 10 nm.

In this specification, the central wavelengths of the emission wavelengths of different active layers are compared, and the emission wavelengths are described as being the same, but this is not limited to the above. The central wavelengths of the emission wavelengths may be separated or may be close to each other. When the central wavelengths are separated from each other, different roles can be assigned to the respective central wavelengths. In this specification, the central wavelengths of the emission wavelengths being close to each other means that the central wavelengths are positioned so that the ranges of the full width at half maximum in the emission spectrum overlap, and for example, the wavelength difference is within the value of the full width at half maximum (for example, within 100 nm). When the central wavelengths are the same or close to each other, the emission spectra are synthesized, which is effective in improving the emission intensity. The above description is given in the case of a light-emitting element, but the same applies to the case of a light-receiving element.

The optical semiconductor element according to the present invention has a first active layer having a first wavelength of light received and emitted, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having a second wavelength of light received and emitted, the first active layer and the second active layer containing Sb, and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer.

Below, an embodiment of the present invention will be described with reference to the drawings. In addition, in each figure, for the sake of convenience, the aspect ratio of the substrate and each layer is shown exaggerated from the actual ratio. In addition, below, III-V compound semiconductors composed of three or more elements may be described with the composition ratio of each element omitted (for example, "InAsSb").

First Embodiment
With reference to Fig. 1, an example of an optical semiconductor element 100 which is a first embodiment of an optical semiconductor element according to the present invention will be described together with a manufacturing method. The optical semiconductor element 100 includes a growth substrate 105 and a semiconductor laminate 140 which is made of a plurality of semiconductor layers laminated on the growth substrate 105 and emits light when electricity is passed through it. As will be described in detail later, the semiconductor laminate 140 functions as a so-called double-stack type light-emitting diode in which a plurality of active layers made of pn junctions are stacked and a tunnel junction layer through which a current flows in the reverse direction (from the n-type layer to the p-type layer) due to the tunnel effect is sandwiched between these active layers.

The first embodiment is an embodiment of a semiconductor light emitting device in which an n-type contact layer 141, an n-type window layer 142, a first spacer layer 143, a first active layer 144, a p-type intermediate layer (first p-type electron block layer 145 and first p-type window layer 146), a tunnel junction layer 147 (p-type tunnel junction layer 1471 and n-type tunnel junction layer 1472), an n-type intermediate layer (second spacer layer 148), a second active layer 149, a second p-type electron block layer 150, a second p-type window layer 151, and a p-type contact layer 152 are sequentially formed on a growth substrate 105, and the growth substrate is used as it is.

<Substrate>
A description will be given of a substrate applicable to the optical semiconductor element 100. The substrate used in the present invention may be any substrate having a thickness sufficient to mechanically maintain the shape of the semiconductor laminate 140 including the first active layer 144, the tunnel junction layer 147, and the second active layer 149, and may be the growth substrate 105 used for epitaxial growth when forming the semiconductor laminate 140 of the optical semiconductor element 100.

<<Growth substrate>>
The growth substrate 105 may be a compound substrate such as GaAs, InP, InAs, GaSb, or InSb. To form an active layer containing Sb, it is ideal to use a substrate of InAs, GaSb, or InSb, but these substrates are expensive, so it is preferable to use a GaAs substrate from the viewpoint of cost. The GaAs substrate is preferably Si-doped to be an n-type substrate, and the semiconductor laminate 140 is preferably laminated on the (100) surface of the GaAs substrate. The thickness of the GaAs substrate is preferably 200 μm or more and 900 μm or less.

In addition, when a GaAs substrate or an InP substrate is used, it is also preferable to provide a buffer layer between the growth substrate 105 and the n-type contact layer 141 to reduce lattice mismatch, and the buffer layer may include an InAs buffer layer grown at a low temperature. The buffer layer may be a buffer layer using a composition gradient in which the compositions α and β of the In _α Ga _1-α As _β Sb _1-β layer are changed in the range of 0 to 1, or a superlattice structure.

<<N-type contact layer>>
An n-type contact layer 141 made of a III-V compound semiconductor layer may be provided on the growth substrate 105. The n-type contact layer 141 has high conductivity and is advantageous in forming an electrode. The thickness is preferably 20 nm or more and 500 nm or less. Dopants that can be used here include Si, Te, S, Ge, Sn, Se, etc. In addition, the dopant concentration is preferably higher than the dopant concentration of the n-type window layer 142 described next, and more preferably 8.0×10 ¹⁸ /cm ³ or more and 3.0×10 ¹⁹ /cm ³ or less.

<<n-type window layer>>
An n-type window layer 142 made of a III-V group compound semiconductor layer may be provided on the n-type contact layer 141, and the thickness is preferably 500 nm to 6000 nm. Examples of dopants that can be used here include Si, Te, S, Ge, Sn, Se, and the like. When the lattice constants of the growth substrate 105 and the first active layer 144 are different, defects propagate to the first active layer 144 if the thickness of the n-type window layer 142 is thinner than 500 nm. In addition, if the thickness of the n-type window layer 142 is thinner than 500 nm, a sufficient amount of carriers is not supplied to the first active layer 144, resulting in a small light emission output, which is not preferable. On the other hand, even if the thickness of the n-type window layer 142 is thicker than 6000 nm, significant improvement in characteristics cannot be expected, and the growth time becomes long and the cost of raw materials increases, which is not preferable because of problems with productivity.

The dopant concentration is preferably lower than that of the n-type contact layer 141, and is preferably 1.0×10 ¹⁸ /cm ³ or more and 8.0×10 ¹⁸ /cm ³ or less.

Furthermore, the composition of the n-type window layer 142 is preferably a composition that is lattice-matched to the composition of the first active layer 144. The composition of the n-type window layer 142 is preferably AlInAs, which has a smaller Al composition ratio (i.e., a smaller band gap) than the first p-type electron block layer 145 described below, and is more preferably InAs.

<First Spacer Layer>
A first spacer layer 143 made of an undoped III-V compound semiconductor layer may be provided on the n-type window layer 142, and the thickness of the first spacer layer 143 is preferably 1 nm or more and 100 nm or less. The first spacer layer 143 is preferably a layer having the same composition as the barrier layer of the first active layer 144 or the n-type window layer 142, and is not doped with an n-type dopant. The first spacer layer 143 reduces the amount of n-type dopant diffusing from the n-type window layer 142 to the first active layer 144.

<First active layer>
A first active layer 144 containing Sb is provided on the first spacer layer 143. The first active layer 144 includes an InAs _x1 Sb _1-x1 layer (0<x1<1) that serves as a light-emitting layer. In FIG. 1, the first active layer 144 further includes an InAs _y1 P _1-y1 layer (0<y1<1), and a quantum well structure in which the InAs _x1 Sb _1-x1 layer is the well layer 144w of the first active layer and the InAs _y1 P _1-y1 layer is the barrier layer 144b of the first active layer is illustrated as an example, but the first active layer 144 may have a single layer structure of the InAs _x1 Sb _1-x1 layer. In addition, the composition other than Sb is not limited to In and As, and another III-V group compound semiconductor may be used. It is also preferable to adjust the composition difference between the well layer 144w of the first active layer and the barrier layer 144b of the first active layer to add strain to the well layer. The first active layer 144 preferably has a multiple quantum well (MQW) structure as shown in FIG. 1 in order to improve the optical output by suppressing crystal defects. This multiple quantum well structure can be formed by a structure in which the well layer and the barrier layer are alternately repeated. When using a multiple quantum well structure, the combination of the well layer and the barrier layer is preferably 3 to 40 pairs. That is, it is preferable that the combination is 3.5 to 40.5 pairs including the first barrier layer. Furthermore, the thickness of each well layer is preferably 5 nm to 40 nm, and the thickness of each barrier layer is preferably 10 nm to 50 nm. It is also preferable that the first active layer 144 is undoped. The first active layer 144 has a wavelength range in which the central emission wavelength is 3000 nm or more. The barrier layer can be made of AlInAs other than InAsP.

<P-type intermediate layer between the first active layer and the tunnel junction layer>
Between the first active layer 144 and the tunnel junction layer is a p-type intermediate layer. The thickness between the first active layer 144 and a tunnel junction layer 147 described below is preferably 100 nm or less. The p-type intermediate layer preferably includes a p-type electron blocking layer.

<First p-type electron blocking layer>
A first p-type electron block layer 145 made of a III-V group compound semiconductor layer may be provided on the first active layer 144, and the thickness is preferably 5 nm to 60 nm. Dopants that can be used here include Mg, Zn, C, Be, etc. The p-type dopant concentration is preferably 1.0×10 ¹⁸ /cm ³ to 5.0×10 ¹⁸ /cm ^3. This first p-type electron block layer 145 is a layer that injects and confines carriers into the first active layer 144. The first p-type electron block layer 145 also has the effect of reducing the diffusion of p-type dopants from a tunnel junction layer 147 to be described later to the first active layer 144.

The composition of the first p-type electron blocking layer 145 is preferably Al _z1 In _1-z1 As (0.05≦z1≦0.40), and more preferably Al _z1 In _1-z1 As (0.10≦z1≦0.35). By making the Al composition z1 0.05 or more, the light emission efficiency of the first p-type electron blocking layer 145 can be improved, and by making it 0.40 or less, the decrease in light emission efficiency due to an increase in forward voltage can be suppressed. In addition, the p-type dopant concentration of the first p-type electron blocking layer 145 is preferably smaller than the p-type dopant concentration doped in the p-type tunnel junction layer 1471 described later.

A first p-type window layer 146 may further be provided on the first p-type electron blocking layer 145. The composition of the first p-type window layer 146 preferably has a smaller Al composition than the composition z1 of the first p-type electron blocking layer 145, and is, for example, InAs. The p-type dopant concentration is preferably 1.0×10 ¹⁸ /cm ³ or more and 5.0×10 ¹⁸ /cm ³ or less.

The p-type intermediate layer between the first active layer 144 and the tunnel junction layer 147 may include a layer other than the first p-type electron block layer 145 or the first p-type window layer 146. Even in this case, in the present invention, since the dopant concentration in the tunnel junction layer 147 can be kept low, the p-type dopant concentration in the p-type intermediate layer can be kept, for example, at 5.0×10 ¹⁸ /cm ³ or less even if diffusion of the p-type dopant from the p-type tunnel junction layer 1471 occurs, and the total film thickness between the first active layer 144 and the tunnel junction layer 147 can be kept at 100 nm or less. By making the film thin in this way while suppressing the amount of dopant diffusion, it is expected that the forward voltage of the entire element can be reduced.

<Tunnel junction layer>
A tunnel junction layer 147 consisting of a p-type tunnel junction layer 1471 and an n-type tunnel junction layer 1472 made of InAs is provided on the first p-type window layer 146. The thickness of the tunnel junction layer 147 is preferably 10 nm to 200 nm. Dopants that can be used for the p-type tunnel junction layer 1471 include Mg, Zn, C, Be, etc., and dopants that can be used for the n-type tunnel junction layer 1472 include Si, Te, S, Ge, Sn, Se, etc. The p-type tunnel junction layer 1471 faces the first active layer 144, and the n-type tunnel junction layer 1472 faces the second active layer 149. The thicknesses and dopant concentrations of the p-type tunnel junction layer 1471 and the n-type tunnel junction layer 1472 may be the same or different. Furthermore, the dopant concentrations of the p-type tunnel junction layer 1471 and the n-type tunnel junction layer 1472 do not need to be uniform within the layers, and may have a concentration gradient.

Usually, in order to form a tunnel junction, the doping rate of the semiconductor must be extremely high so that the depletion layer generated at the junction surface between the n-type semiconductor layer and the p-type semiconductor layer is thin enough to cause quantum tunneling, and therefore a dopant concentration of at least 1.0×10 ¹⁹ /cm ³ or more (preferably 1.0×10 ²⁰ /cm ³ ) is required in the compound semiconductor. However, in the present invention, a tunnel junction can be realized even with a dopant concentration of 1.0×10 ¹⁸ /cm ³ or more and less than 1.0×10 ¹⁹ /cm ^3. It is more preferable that the dopant concentration of the tunnel junction layer is 5.0×10 ¹⁸ /cm ³ or more and 9.0×10 ¹⁸ /cm ³ or less. Since the less diffusion of the dopant into the first active layer 144 and the second active layer 149 leads to improved characteristics such as reliability, it is preferable that the dopant concentration of the tunnel junction layer 147 is low as long as quantum tunneling can be caused.

<<p-type tunnel junction layer>>
The p-type dopant concentration in the p-type tunnel junction layer 1471 is preferably 1.0×10 ¹⁸ atoms/cm ³ or more and less than 1.0×10 ¹⁹ atoms/cm ³ , and more preferably 9.0×10 ¹⁸ atoms/cm ³ or less. The film thickness is preferably 5 nm or more and 100 nm or less.

<<N-type tunnel junction layer>>
The n-type dopant concentration in the n-type tunnel junction layer 1472 is preferably 1.0×10 ¹⁸ atoms/cm ³ or more and less than 1.0×10 ¹⁹ atoms/cm ³ , and more preferably 9.0×10 ¹⁸ atoms/cm ³ or less. The film thickness is preferably 5 nm or more and 100 nm or less.

<N-type intermediate layer between the tunnel junction layer and the second active layer>
Between the tunnel junction layer and the second active layer is an n-type intermediate layer. The n-type intermediate layer may be an undoped layer. The thickness between the tunnel junction layer 147 and the second active layer 149 described later is preferably 100 nm or less. The n-type intermediate layer preferably includes a spacer layer.

<Second Spacer Layer>
A second spacer layer 148 may be provided on the tunnel junction layer 147, and the thickness of the second spacer layer 148 is preferably 1 nm or more and 100 nm or less. The second spacer layer 148 may have the same composition as the n-type tunnel junction layer 1472 of the tunnel junction layer 147 or the barrier layer of the second active layer 149, or may have a composition that makes the band gap larger than that of the barrier layer. It is preferable that the second spacer layer 148 is an undoped layer that is not intentionally doped without flowing raw material gas of n-type dopant during growth. This second spacer layer 148 reduces the diffusion of n-type dopant from the n-type tunnel junction layer 1472 of the tunnel junction layer 147 to the second active layer 149.

A layer other than the second spacer layer 148 may be included between the second active layer 149 and the tunnel junction layer 147. Even in this case, in the present invention, since the dopant concentration in the tunnel junction layer 147 can be kept low, even if the n-type dopant diffuses from the n-type tunnel junction layer 1472, the n-type dopant concentration in the n-type intermediate layer can be kept, for example, 5.0×10 ¹⁸ /cm ³ or less, and the total film thickness between the second active layer 149 and the tunnel junction layer 147 can be kept to 100 nm or less. By making the film thin in this way while suppressing the amount of dopant diffusion, it is expected that the forward voltage of the entire element can be reduced.

<Second active layer>
A second active layer 149 containing Sb is provided on the second spacer layer 148. The second active layer 149 preferably has the same structure as the first active layer 144. For example, in FIG. 1, the second active layer 149 is illustrated as a quantum well structure consisting of a well layer InAs _x2 Sb _1-x2 layer (0<x2<1) and a barrier layer InAs _y2 P _1-y2 layer (0<y2<1) which are light-emitting layers, but it is preferable that the well layer 149w of the second active layer has the same structure as the well layer 144w of the first active layer, and the barrier layer 149b of the second active layer has the same structure as the barrier layer 144b of the first active layer. In addition, the first active layer 144 and the second active layer 149 have the same emission wavelength and have a wavelength range in which the emission center wavelength is 3000 nm or more.

<Second p-type electron blocking layer>
A second p-type electron block layer 150 made of a III-V compound semiconductor layer may be provided on the second active layer 149, and the thickness is preferably 5 nm to 60 nm. Dopants that can be used here include Mg, Zn, C, Be, etc. The dopant concentration is preferably 1.0×10 ¹⁸ /cm ³ to 5.0×10 ¹⁸ /cm ^3. This second p-type electron block layer 150 is a layer that injects and confines carriers into the second active layer 149. The second p-type electron block layer 150 also has the effect of reducing the diffusion of dopants from the second p-type window layer 151 to the second active layer 149.

The composition of the second p-type electron blocking layer 150 is preferably _{Alz2In1 -z2As} (0.05≦z2≦0.4), and more preferably _{Alz2In1 -z2As} (0.10≦z2≦0.35). By making the Al composition z2 0.05 or more, the light emission efficiency of the second p-type electron blocking layer 150 can be improved, and by making it 0.40 or less, the decrease in light emission efficiency due to an increase in forward voltage can be suppressed. In addition, the p-type dopant concentration of the second p-type electron blocking layer 150 is preferably smaller than the p-type dopant concentration doped in the p-type tunnel junction layer 1471.

<Second p-type window layer>
A second p-type window layer 151 made of a III-V group compound semiconductor layer may be provided on the second p-type electron blocking layer 150, and the thickness is preferably 500 nm or more and 2000 nm or less. If the second p-type window layer 151 is thicker than this, the current spreads to the edge of the LED chip, increasing surface recombination, and the ohmic resistance of the element increases, which is undesirable as it reduces the light emission efficiency. On the other hand, if the second p-type window layer 151 is thinner than this, it is undesirable as it emits light directly under the electrode and prevents light extraction. Examples of dopants that can be used here include Mg, Zn, C, and Be. The dopant concentration of the second p-type window layer 151 is preferably 1.0×10 ¹⁸ atoms/cm ³ or more and 5.0×10 ¹⁸ atoms/cm ³ or less.

<p-type contact layer>
A p-type contact layer 152 made of a III-V compound semiconductor layer may be provided on the second p-type window layer 151, and the thickness of the p-type contact layer 152 is preferably 20 nm or more and 300 nm or less. The dopant concentration of the p-type contact layer 152 is higher than that of the second p-type window layer 151, and is preferably 8.0× ¹⁰¹⁸ atoms/ ^cm3 or more and 3.0× ¹⁰¹⁹ atoms/ ^cm3 or less.

An example of an embodiment of the manufacturing method of the optical semiconductor element 100 described above will be described below. When the growth substrate 105 is n-type or undoped, the optical semiconductor element 100 is manufactured through a process of epitaxially growing the first active layer 144, the tunnel junction layer 147 made of InAs, and the second active layer 149 in order. Here, the first active layer 144 and the second active layer 149 contain Sb, and the tunnel junction layer 147 is formed by vertically stacking a p-type tunnel junction layer 1471 formed of a p-type InAs layer and an n-type tunnel junction layer 1472 formed of an n-type InAs layer. The first active layer 144 and the p-type tunnel junction layer 1471 face each other, and the n-type tunnel junction layer 1472 and the second active layer 149 face each other. The dopant concentration of the tunnel junction layer 147 is equal to or higher than 1.0×10 ¹⁸ atoms/cm ³ and lower than 1.0×10 ¹⁹ atoms/cm ³ .

A first p-type electron block layer 145 or a first p-type window layer 146 having a total thickness of 100 nm or less may be formed between the first active layer 144 and the tunnel junction layer 147, and an undoped second spacer layer 148 having a thickness of 100 nm or less may be formed between the tunnel junction layer 147 and the second active layer 149.

Furthermore, one or more layers of the n-type contact layer 141, the n-type window layer 142, and the first spacer layer 143 may be formed between the growth substrate 105 and the first active layer 144, and one or more layers of the second p-type electron block layer 150, the second p-type window layer 151, and the p-type contact layer 152 may be formed on the second active layer.

On the other hand, if the growth substrate 105 for epitaxially growing each semiconductor layer of the semiconductor laminate 140 is p-type, the second active layer 149, the tunnel junction layer 147, and the first active layer 144 are formed in this order on the growth substrate 105. At this time, the second active layer 149 faces the n-type tunnel junction layer 1472, and the p-type tunnel junction layer 1471 faces the first active layer 144.

Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) or triethylgallium (TEGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, arsine (AsH ₃ ) or tertiarybutylarsine (TBAs) as an As source, trimethylantimony (TMSb), triethylantimony (TESb) or trisdimethylaminoantimony (TDMASb) as an Sb source, and phosphine (PH ₃ ) or tertiarybutylphosphine (TBP) as a P source are used in a predetermined mixing ratio, and these raw material gases are vapor-phase grown using a carrier gas, so that a desired thickness can be formed according to the growth time. When each layer is doped to p-type or n-type, a dopant source gas according to the desire may be further used. For example, when Zn is doped, DEZn (diethylzinc) gas or the like may be used. Note that InAs is also n-type even when undoped.

In FIG. 1, a lower electrode 195 is provided on the back surface of the growth substrate 105. Furthermore, an upper electrode 191 is provided on a portion of the p-type contact layer 152. The upper electrode 191 may include a wiring portion and a pad portion of an ohmic electrode, and although not shown, the pad portion may have a metal layer or solder for bonding. The metal materials and formation methods used for the upper electrode 191 and the lower electrode 195 may be publicly known. Examples of metal materials that may be used include Ti, Pt, Au, Ag, Al, Zn, and Ni.

When a forward voltage is applied from the upper electrode 191 to the lower electrode 195, a forward voltage is applied to the first active layer 144 and the second active layer 149, and both the first active layer 144 and the second active layer 149 emit light. At this time, a reverse voltage is applied to the tunnel junction (pn junction) in the tunnel junction layer 147. This causes a current to flow in the tunnel junction layer 147 due to the tunnel effect.

Second Embodiment
An optical semiconductor element 200 according to a second embodiment of the present invention will be described with reference to FIG. 2. The optical semiconductor element 200 is a junction-type optical semiconductor element obtained by bonding a support substrate and then removing a growth substrate. In principle, the same components as those of the optical semiconductor element 100 are given the same reference numbers with the last two digits of the three-digit number, and duplicated descriptions are omitted. The optical semiconductor element 200 includes at least a support substrate 280, a metal bonding layer 279 and a metal reflective layer 271 provided on the surface of the support substrate 280, a transparent insulating layer 261 having a through hole on the metal reflective layer 271 and a power distribution section 260 having an ohmic electrode section 265 provided in the through hole, and a semiconductor laminate 240 provided on the power distribution section 260.

The semiconductor laminate 240 in the optical semiconductor element 200 in FIG. 2 has, in order from the side opposite the support substrate 280, an n-type contact layer 241, an n-type window layer 242, a first spacer layer 243, a first active layer 244, a first p-type electron blocking layer 245, a first p-type window layer 246, a tunnel junction layer 247, a second spacer layer 248, a second active layer 249, a second p-type electron blocking layer 250, a second p-type window layer 251, and a p-type contact layer 252.

The support substrate 280, which is different from the growth substrate, is preferably cheaper and has higher thermal conductivity than the growth substrate. For example, in addition to compound substrates such as Si, Ge, and GaAs, metal substrates using metals that can suppress the thermal expansion coefficient, such as copper alloys, molybdenum, tungsten, and Kovar, or submount substrates in which metal is attached to a ceramic substrate such as AlN can be used. From the standpoint of processability and cost, it is also preferable to use a Si substrate as the support substrate 280.

Below, an example of an embodiment of the optical semiconductor element 200 and a manufacturing method thereof will be described in more detail with reference to Figures 3 to 5. First, a growth substrate 205 is prepared. Then, with reference to Figure 3, a semiconductor laminate 240 is formed. At this time, an etching stop layer (not shown) may be formed on the growth substrate 205. The semiconductor laminate 240 is similar to the semiconductor laminate 140 described above.

<Formation of power distribution division>
A power distribution section 260 including a transparent insulating layer 261 with a through hole and an ohmic electrode section 265 provided in the through hole is formed on the p-type contact layer 252. Any specific method may be used to form the power distribution section 260, but an example of a specific mode for forming the power distribution section 260 will be described below with reference to FIGS.

First, the transparent insulating layer 261 is formed on the semiconductor laminate 240. As the film formation method, known methods such as plasma CVD or sputtering can be applied. After that, a resist pattern of the power distribution section is formed on the transparent insulating layer 261 using a photomask. Next, a part of the transparent insulating layer 261 is removed by etching using the resist pattern to form a through hole. By providing the through hole, a part of the outermost surface of the semiconductor laminate 240 is exposed. After that, the ohmic electrode section 265 is formed, and then lifted off using the resist pattern to form the power distribution section 260. In the power distribution section 260, the transparent insulating layer 261 and the ohmic electrode section 265 are arranged in parallel. Note that, for simplification in the drawing, the ohmic electrode section 265 is illustrated as filling the through hole, but this is not limited to this, and a gap may be formed between the transparent insulating layer 261 and the ohmic electrode section 265.

The ohmic electrode portion 265 can be formed by dispersing it in an island shape in a predetermined pattern. For example, Au, AuZn, AuBe, AuTi, etc. can be used as the ohmic electrode portion 265, and it is also preferable to use a laminated structure of these. For example, Ti/Au can be used as the ohmic electrode portion 265. There are no restrictions on the film thickness (or total film thickness) of the ohmic electrode portion 265, but it can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm.

<Formation of Metal Reflective Layer>
As shown in FIG. 4, it is also preferable to form a metal reflective layer 271 on the power distribution unit 260. The metal reflective layer 271 may include a plurality of metal layers, and the metal constituting the metal reflective layer 271 may be Al, Pt, Ti, Ag, or the like in addition to Au. For example, the metal reflective layer 271 may be a single layer made of Au only, or the metal reflective layer 271 may include two or more Au metal layers. It is preferable that the metal reflective layer 271 has 50 mass % or more of Au in its composition. In order to ensure bonding with the metal bonding layer 279 in the subsequent process, it is preferable that the outermost layer of the metal reflective layer 271 (the surface opposite to the semiconductor laminate 240) is an Au metal layer.

For example, metals can be deposited in the order of Al, Au, Pt, and Au on the power distribution section 260 (including the gap if the gap is provided) to form the metal reflective layer 271. The thickness of the Au1 layer in the metal reflective layer 271 can be, for example, 400 nm to 2000 nm, and the thickness of the metal layers made of metals other than Au can be, for example, 5 nm to 200 nm. The metal reflective layer 271 can be deposited and formed using a common method such as a vapor deposition method.

<Joining with supporting substrate>
The bonding with the support substrate will be described with reference to Fig. 4. The semiconductor stack 240 and the power distribution section 260 are bonded to the support substrate 280 via at least a metal bonding layer 279. The metal reflective layer 271 may be provided to bond the metal reflective layer 271 and the metal bonding layer 279. The metal bonding layer 279 and the metal reflective layer 271 are placed opposite each other and bonded together, and heated and compressed to bond at a temperature of about 250°C to 500°C, whereby the two can be bonded together.

<Metal bonding layer>
The metal bonding layer 279 can be formed using metals such as Ti, Pt, Au, or a metal (such as Sn) that forms a eutectic alloy with Au, or solder, and it is preferable to laminate these to form the metal bonding layer 279. For example, the metal bonding layer 279 can be formed by laminating, in order from the surface of the support substrate 280, Ti having a thickness of 400 nm to 800 nm, Pt having a thickness of 5 nm to 20 nm, and Au having a thickness of 700 nm to 1200 nm. For example, when bonding the metal reflective layer 271 and the metal bonding layer 279, the outermost layer of the metal bonding layer 279 can be made of Au metal, and the outermost layer of the metal reflective layer 271 can also be made of Au, and bonding between Au layers can be performed by Au-Au diffusion.

<Support substrate>
The support substrate 280 may be a substrate of a different type from the growth substrate 205, and may be a submount substrate based on the semiconductor substrate, metal substrate, or ceramic substrate described above. Since the above-mentioned bonding method is used, the support substrate 280 may be lattice-mismatched with each semiconductor layer formed in this embodiment. The support substrate 280 may be an insulating substrate depending on the application, but is preferably a conductive substrate. In terms of processability and cost, it is preferable to use a Si substrate for the support substrate 280. By using a Si substrate, the thickness of the support substrate 280 can be significantly reduced compared to the conventional method, and it is also suitable for mounting in combination with various semiconductor devices. In addition, the Si substrate is also advantageous in terms of heat dissipation compared to the InAs substrate.

<Removal of Growth Substrate>
The removal of the growth substrate will be described with reference to FIG. 5. After bonding the support substrate 280, the growth substrate 205 is removed. When the growth substrate 205 is a GaAs substrate, the growth substrate 205 can be wet-etched using, for example, an ammonia-hydrogen peroxide mixture. When an etching stop layer is used, the etching stop layer may be sequentially removed following the removal of the growth substrate 205. In addition, by leaving a part of the etching stop layer, it may be used as an n-type contact layer that reduces the contact resistance with the upper electrode 291.

Furthermore, as shown in FIG. 2, an upper electrode 291 may be formed on the semiconductor laminate 240, and a back electrode 295 may be formed on the back surface of the support substrate 280. The upper electrode 291 may include a wiring portion and a pad portion. The upper electrode 291 and the back electrode 295 may be formed by a known method, such as a sputtering method, an electron beam evaporation method (also referred to as an evaporation method), or a resistance heating method. The electrode pattern may be formed by using a metal mask, or by combining a photolithography method, a lift-off method, and metal etching.

The above manufacturing method can provide the optical semiconductor element 200 shown in FIG. 2. These embodiments are examples and are not limiting. The side of the element may be inclined during mesa etching, the electrode shape may be two electrodes on the upper surface, or it may be a flip chip, and other appropriate modifications are possible.

Third Embodiment
Next, an optical semiconductor device 300 according to a third embodiment of the present invention will be described with reference to Fig. 6. The third embodiment is an embodiment in which a tunnel junction layer and an active layer are further formed on the second p-type window layer of the first embodiment. Specifically, the semiconductor light emitting device in Fig. 6 has a second tunnel junction layer 352, a third active layer 354, a third tunnel junction layer 357, and a fourth active layer 359, successively formed on the second p-type window layer. Each component will be described in detail below.

The second tunnel junction layer 352 has a p-type InAs layer 3521 and an n-type InAs layer 3522, similar to the tunnel junction layer 147 of the first embodiment. The p-type InAs layer 3521 faces the second active layer, and the n-type InAs layer 3521 faces the third active layer 354. Here, the second tunnel junction layer 352 may have the same composition and film thickness as the first tunnel junction layer, or may have different thicknesses.

The third active layer 354 includes an InAs _x3 Sb _1-x3 layer (0<x3<1) which is a light emitting layer like the first active layer, and has the same emission wavelength as the first active layer. The third active layer 354 may have the same composition and film thickness as the first active layer, or may have different composition and film thickness.

The third tunnel junction layer 357 has a p-type InAs layer 3571 and an n-type InAs layer 3572, similar to the tunnel junction layer of the first embodiment. The p-type InAs layer 3571 faces the third active layer 354, and the n-type InAs layer 3572 faces the fourth active layer 359. Here, the third tunnel junction layer 357 may have the same composition and film thickness as the first tunnel junction layer, or may have different thicknesses.

The fourth active layer 359 includes an InAs _x4 Sb _1-x4 layer (0<x4<1) that serves as a light emitting layer like the first active layer, and has the same emission wavelength as the first active layer. The fourth active layer 359 may have the same composition and film thickness as the first active layer, or may have different composition and film thickness.

The layers above the fourth active layer 359 have the same configuration as the layers above the second active layer in the first embodiment.

In the above-mentioned third embodiment, the second tunnel junction layer 352, the third active layer 354, the third tunnel junction layer 357, and the fourth active layer 359 are formed on the second electron blocking layer to form a total of three tunnel junction layers and a total of four active layers. In this embodiment, instead of the embodiment shown in FIG. 6, a total of N tunnel junction layers (N is an integer equal to or greater than 3) may be formed, and a total of (N+1) active layers may be formed. For example, a total of two tunnel junction layers may be formed, and a total of three active layers may be formed, or a total of four tunnel junction layers may be formed, and a total of five active layers may be formed. The embodiment shown in FIG. 6 is a specific example in which N is 3. Even in this case, the dopant concentration of each tunnel junction layer is 1×10 ¹⁸ atoms/cm ³ or more and 1×10 ¹⁹ atoms/cm ³ or less, and the wavelengths of each active layer are the same as each other and have a central wavelength of 3000 nm or more.

(Fourth embodiment: light receiving element)
A semiconductor photodetector according to a fourth embodiment of the present invention will be described. For example, by replacing the first active layer and the second active layer in the first embodiment with a first InAsSb light absorbing layer and a second InAsSb light absorbing layer, the semiconductor photodetector according to the present invention can be used as a semiconductor photodetector. Since the semiconductor photodetector according to the present invention has two absorbing layers via a tunnel junction layer, the dark current is reduced and the shunt resistance is large compared to the case where there is only one absorbing layer, and a semiconductor photodetector with good characteristics can be realized.

[Experimental Example 1]
Example 1
Using MOCVD, first, an n-type InAs contact layer (film thickness: 0.3 μm) with a high dopant concentration (Te concentration 1.0×10 ¹⁹ /cm ³ ), a Te-doped n-type InAs window layer (film thickness: 4.9 μm, Te concentration 3.0×10 ¹⁸ /cm ³ ), and an undoped InAs spacer layer (film thickness: 75 nm) were formed in this order on the (100) surface of a Si-doped n-type GaAs growth substrate (substrate thickness: 350 μm). Next, a first active layer (total film thickness: 430 nm) with a quantum well structure having an emission central wavelength of 4300 nm was formed. The active layer of the quantum well structure was formed by alternately stacking ₁₀ layers _of undoped _{InAs0.90P0.10} barrier layers ₍ thickness: 30 nm) and _{InAs0.87Sb0.13} well layers (after film: 10 nm) in sequence, and then growing an _{InAs0.90P0.10} barrier layer, resulting in 10.5 sets including the last barrier layer. A Zn-doped p-type _{Al0.32In0.68As} electron block layer (thickness: 15 nm, Zn concentration ^2.5x1018 / ^cm3 ) and _a Zn-doped p-type InAs window layer (thickness: 50 nm, Zn concentration ^2.5x1018 / ^cm3 ) were formed on the first active layer, and a tunnel junction layer was formed thereon.

The tunnel junction layer was formed by forming a Te-doped InAs layer (thickness: 50 nm, Te concentration during growth: 8×10 ¹⁸ /cm ³ ) on a Zn-doped InAs layer (thickness: 50 nm, Zn concentration during growth: 8×10 ¹⁸ /cm ³ ), thereby obtaining a tunnel effect at the interface between them. The tunnel junction layer was grown under a pressure of 50 Torr, with the ratio of group V elements to group III elements (VIII ratio) in the source gas used being 50.

Next, an undoped InAs spacer layer (thickness: 75 nm) was formed on the tunnel junction layer, and a second active layer (total thickness: ₄₃₀ nm) was formed thereon, which was the same as the first active layer. A Zn-doped p-type _{Al0.32In0.68As} electron block layer (thickness: 15 nm, Zn concentration: ^2.5x1018 / ^cm3 ) was formed on the second active layer. Furthermore, a Zn-doped p-type InAs window layer (thickness: 900 nm, Zn concentration: ^2.5x1018 / ^cm3 ) was formed on top of the window layer, and a p-type InAs contact layer (thickness: 100 nm) with a high dopant concentration (Zn concentration: ^1.0x1019 / ^cm3 ) was formed thereon.
Table 1 below shows the composition and thickness of each layer, the type of dopant, the (designed) dopant concentration during growth, and the dopant concentration by SIMS analysis including the diffusion of the dopant after all epitaxial growth was completed and the device was removed from the MOCVD device. The source gases selected for the formation of each layer were trimethylindium (TMIn) as the In source, trimethylgallium (TMGa) as the Ga source, trimethylaluminum (TMAl) as the Al source, arsine (AsH ₃ ) as the As source, triethylantimony (TESb) as the Sb source, and phosphine (PH ₃ ) as the P source. DEZn (diethylzinc) and DETe (diethyltellurium) were used as dopant gases.

A BRUKER JV-QC3 XRD device was used to measure the composition of each layer. The composition of each layer was calculated by fitting using analysis software (Jordan Valley RADS). The thickness of each layer was calculated from cross-sectional observation of the growth layer using a SEM (scanning electron microscope) or TEM (transmission electron microscope).

Next, a transparent insulating layer (film thickness: 550 nm) made of SiO ₂ was formed on the entire surface of the p-type InAs contact layer by the plasma CVD method. A power distribution part pattern was formed thereon by resist, and the SiO ₂ in the area not covered by the resist was removed by etching to expose the Zn-doped p-type InAs contact layer. Next, Ti (film thickness: 10 nm) and Au (film thickness: 530 nm) were formed as ohmic metal parts by the deposition method, and the resist of the power distribution part pattern was removed together with the metal film formed thereon, leaving only the ohmic metal parts formed on the exposed Zn-doped p-type InAs contact layer, forming a power distribution part in which the ohmic metal parts and the transparent insulating film are arranged in parallel. Next, a metal reflective layer (Al (film thickness: 10 nm/Au (film thickness: 650 nm)/Pt (film thickness: 100 nm)/Au (film thickness: 900 nm))) was formed on the power distribution part by the deposition method.

Next, a metal bonding layer (Ti (film thickness: 650 nm)/Pt (film thickness: 20 nm)/Au (film thickness: 900 nm)) was formed on the support substrate (Si substrate) by deposition. Next, the metal reflective layer and the metal bonding layer were arranged facing each other and heated and compressed at 300°C. Next, the growth substrate was removed by wet etching using an ammonia-hydrogen peroxide mixture to expose the n-type contact layer. Next, Ti (film thickness: 150 nm)/Au (film thickness: 1250 nm) was formed on the n-type contact layer by deposition to form an n-type ohmic electrode. Next, a pad electrode (Ti (film thickness: 150 nm)/Pt (film thickness: 100 nm)/Au (film thickness: 2500 nm)) was formed on the n-type ohmic electrode by deposition, and the n-type ohmic electrode and the pad electrode were combined to form the upper electrode. Note that the lift-off method using a resist was used to form the electrode pattern.

Next, the semiconductor laminate between each element (width: 60 μm) was removed by mesa etching to form dicing lines. Then, a back electrode (Ti (film thickness: 10 nm)/Pt (film thickness: 50 nm)/Au (film thickness: 200 nm)) was formed on the back side of the support substrate by vapor deposition, and alloyed by heat treatment at 300°C for 1 minute. Next, the entire wafer was immersed in a nitric acid solution kept at 8°C ± 1°C for 5 seconds to roughen the surface of the semiconductor laminate except for the area where the upper electrode was formed. After that, it was immersed in ammonia water for 1 minute and washed with pure water for 1 minute. Finally, chips were separated by dicing to produce the optical semiconductor element according to Example 1. The chip size was 500 μm × 500 μm.

7 is a graph showing the results of measuring the diffusion state of Te ions in the optical semiconductor element produced in Example 1 by secondary ion mass spectrometry (SIMS). In FIG. 7, the horizontal axis is depth (μm), the left vertical axis is the concentration (atoms/cm ³ ) of n-type dopant (here Te, Si, C, H, O), and the right vertical axis is the secondary ion intensity (counts/sec) of Sb. In the case of Example 1, the maximum value of the concentration of Te, which is the n-type dopant doped in the semiconductor laminate 140, was 8.0×10 ¹⁸ atoms/cm ³ . The position where the maximum value was reached was the position corresponding to the n-type tunnel junction layer, and diffusion of Te from the n-type tunnel junction layer toward the undoped spacer layer and the first barrier layer was observed. However, even if the Te concentration in the spacer layer and the first barrier layer increased due to diffusion, it was not more than 4.0×10 ¹⁸ atoms/cm ³ , and the Te concentration could be kept within the preferable range.

8 is a graph showing the results of measuring the diffusion state of Zn ions in the optical semiconductor element produced in Example 1 by SIMS. In FIG. 8, the horizontal axis is depth (μm), the vertical axis on the left is the concentration (atoms/cm ³ ) of the p-type dopant (Zn here), and the vertical axis on the right is the secondary ion intensity (counts/sec). In the case of Example 1, the maximum value of the concentration of Zn, which is the p-type dopant doped in the semiconductor laminate 140, was 6.0×10 ¹⁸ atoms/cm ^3. The position where the maximum value was reached was the position corresponding to the p-type tunnel junction layer, and diffusion of Zn from the p-type tunnel junction layer toward the p-type window layer and the electron block layer was observed. However, even if the Zn concentration of the p-type window layer and the electron block layer increased due to diffusion, it was 5.0×10 ¹⁸ atoms/cm ³ or less, and the Zn concentration could be kept within a preferable range.

Example 2
In the same manner as in Example 1, each semiconductor layer was epitaxially grown up to the second active layer. Next, the second tunnel junction layer, the third active layer, the third tunnel junction layer, and the fourth active layer were formed in order on the second active layer. On the fourth active layer, an electron block layer, a p-type window layer, and a p-type contact layer were formed in order, in the same manner as on the second active layer in Example 1. The third active layer and the fourth active layer have the same film thickness and composition as the first active layer, and the second tunnel junction layer and the third tunnel junction layer have the same film thickness and composition as the first tunnel junction layer. Here, between the second active layer and the second tunnel junction layer, and between the third active layer and the third tunnel junction layer, an electron block layer having the same film thickness and composition as the electron block layer between the first active layer and the first tunnel junction layer was formed. In addition, between the second tunnel junction layer and the third active layer, and between the third tunnel junction layer and the fourth active layer, a spacer layer having the same film thickness and composition as the spacer layer between the first tunnel junction layer and the second active layer was formed. The composition and thickness of each layer, the type of dopant, the dopant concentration during growth, and the dopant concentration by SIMS analysis including dopant diffusion are shown in Table 2. The dopant concentration was diffused in the same manner as in Example 1, and the diffusion amount was kept within a preferable range.

(Comparative Example 1)
An optical semiconductor device according to Comparative Example 1 was obtained in the same manner as in Example 1, except that the film thickness of the second active layer was changed from 430 nm to 0 nm, the film thickness of the spacer layer on the tunnel junction layer was changed from 75 nm to 0 nm, the film thickness of the Te-doped InAs layer in the tunnel junction layer was changed from 50 nm to 0 nm, the film thickness of the Zn-doped InAs layer in the tunnel junction layer was changed from 50 nm to 0 nm, and the film thickness of the electron blocking layer below the tunnel junction layer was changed from 15 nm to 0 nm, and the number of well layers and barrier layers in the quantum well structure of the first active layer was set to 20.5 pairs (total film thickness: 860 nm).

<Evaluation: Light output evaluation>
A current of 100 mA was applied to the optical semiconductor devices obtained from the above examples and comparative examples using a constant current voltage power supply. The forward voltage Vf (V) and the light output Po (W) using an integrating sphere were measured. In addition, the leakage current (A) was measured when a reverse voltage of -0.1 V was applied. The results are shown in Table 3.

These results confirm that increasing the number of PN junctions (number of active layers) and tunnel junctions increases the light output and forward voltage, and also reduces the leakage current.

The present invention provides an optical semiconductor device that is composed of two or more active layers containing Sb, with a tunnel junction layer made of InAs interposed therebetween, and a method for manufacturing the same.

100 Optical semiconductor element 105 Growth substrate 140 Semiconductor laminate 141 n-type contact layer 142 n-type window layer 143 First spacer layer 144 First active layer 144b Barrier layer of first active layer 144w Well layer of first active layer 145 First p-type electron block layer 146 First p-type window layer 147 Tunnel junction layer 1471 p-type tunnel junction layer 1472 n-type tunnel junction layer 148 Second spacer layer 149 Second active layer 149b Barrier layer of second active layer 149w Well layer of second active layer 150 Second p-type electron block layer 151 Second p-type window layer 152 p-type contact layer 191 Upper electrode 195 Lower electrode 200 Optical semiconductor element 205 Growth substrate 240 Semiconductor laminate 241 n-type contact layer 242 n-type window layer 243 first spacer layer 244 first active layer 245 first p-type electron blocking layer 246 first p-type window layer 247 tunnel junction layer 248 second spacer layer 249 second active layer 250 second p-type electron blocking layer 251 p-type window layer 252 p-type contact layer 260 power distribution section 261 transparent insulating layer 265 ohmic electrode section 271 metal reflective layer 279 metal junction layer 280 support substrate 291 upper electrode 295 back electrode 300 optical semiconductor element 352 second tunnel junction layer 3521 p-type InAs layer of second tunnel junction layer 3522 n-type InAs layer of second tunnel junction layer 354 third active layer 357 third tunnel junction layer 3571 p-type InAs layer of third tunnel junction layer 3572 n-type InAs layer of third tunnel junction layer 359 Fourth active layer

Claims (9)

An optical semiconductor device having a first active layer having an emission wavelength of a first wavelength, a first electron blocking layer on the first active layer, a tunnel junction layer on the first electron blocking layer, a second active layer on the tunnel junction layer having an emission wavelength of a second wavelength, and a second electron blocking layer on the second active layer,
the first active layer and the second active layer contain Sb;
the tunnel junction layer includes a p-type InAs layer and an n-type InAs layer;
the n-type InAs layer is located on the second active layer side of the tunnel junction layer;
a spacer layer between the tunnel junction layer and the second active layer;
a thickness between the tunnel junction layer and the second active layer is 100 nm or less;
The composition of the first electron blocking layer is Al _z1 In _1-z1 As (z1 is 0.05 or more and 0.40 or less).
Optical semiconductor element. An optical semiconductor device having a first active layer having an emission wavelength of a first wavelength, a first electron blocking layer on the first active layer, a tunnel junction layer on the first electron blocking layer, a second active layer on the tunnel junction layer having an emission wavelength of a second wavelength, and a second electron blocking layer on the second active layer,
the first active layer and the second active layer contain Sb;
the tunnel junction layer includes a p-type InAs layer and an n-type InAs layer;
the n-type InAs layer is located on the second active layer side of the tunnel junction layer;
a spacer layer between the tunnel junction layer and the second active layer;
a thickness between the tunnel junction layer and the second active layer is 100 nm or less;
The composition of the second electron blocking layer is _{Alz2In1 -z2As} (z2 is 0.05 or more and 0.4 or less).
Optical semiconductor element. The tunnel junction layer has a dopant concentration of 1.0×10 ¹⁸ atoms/cm ³ or more and less than 1.0×10 ¹⁹ atoms/cm ³ .
The optical semiconductor element according to claim 1 . the first active layer and the second active layer have a quantum well structure,
The first wavelength and the second wavelength are 3000 nm or longer.
The optical semiconductor element according to claim 1 . The first wavelength and the second wavelength are the same.
The optical semiconductor element according to claim 1 . the p-type InAs layer is located on the first active layer side of the tunnel junction layer;
the first electron blocking layer having a p-type structure is disposed between the first active layer and the tunnel junction layer;
a thickness between the first active layer and the tunnel junction layer is 100 nm or less;
The optical semiconductor element according to claim 1 . forming a first active layer on a substrate, the first active layer having a first wavelength for receiving and emitting light;
forming a first electron blocking layer on the first active layer;
forming a tunnel junction layer on the first electron blocking layer;
forming a second active layer on the tunnel junction layer, the second active layer having a second wavelength for receiving and emitting light;
forming a second electron blocking layer on the second active layer;
Including,
the first active layer and the second active layer contain Sb;
the step of forming the tunnel junction layer includes the steps of: forming an n-type InAs layer on the second active layer side; forming a p-type InAs layer on the n-type InAs layer; and forming a spacer layer having a thickness of 100 nm or less between the tunnel junction layer and the second active layer;
the first electron blocking layer contains Al _z1 In _1-z1 As (z1 is 0.05 or more and 0.40 or less);
A method for manufacturing an optical semiconductor element. forming a first active layer on a substrate, the first active layer having a first wavelength for receiving and emitting light;
forming a first electron blocking layer on the first active layer;
forming a tunnel junction layer on the first electron blocking layer;
forming a second active layer on the tunnel junction layer, the second active layer having a second wavelength for receiving and emitting light;
forming a second electron blocking layer on the second active layer;
Including,
the first active layer and the second active layer contain Sb;
the step of forming the tunnel junction layer includes the steps of: forming an n-type InAs layer on the second active layer side; forming a p-type InAs layer on the n-type InAs layer; and forming a spacer layer having a thickness of 100 nm or less between the tunnel junction layer and the second active layer;
the second electron blocking layer contains _{Alz2In1 -z2As} (z2 is 0.05 or more and 0.4 or less);
A method for manufacturing an optical semiconductor element. 9. The method for producing an optical semiconductor element according to claim 7, wherein the tunnel junction layer has a dopant concentration of not less than 1.0× ¹⁰¹⁸ atoms/ ^cm3 and less than 1.0× ¹⁰¹⁹ atoms/ ^cm3 .

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