JP7661771B2 - Method for manufacturing silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device - Google Patents

Description

This disclosure relates to a method for manufacturing a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device.

Noboru Otani, "Development Trends of Large-Diameter SiC Single Crystal Substrates," Journal of the Vacuum Society of Japan, Vol. 54, No. 6, pp. 339-345, 2011 (Non-Patent Document 1), describes a method for processing silicon carbide substrates.

Noboru Otani, "Development Trends of Large-Diameter SiC Single Crystal Substrates," Journal of the Vacuum Society of Japan, Vol. 54, No. 6, pp. 339-345, 2011

The object of the present disclosure is to provide a method for manufacturing a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device that can reduce the probability of exposure failure during the manufacturing process of a silicon carbide semiconductor device.

The method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps: A plurality of first silicon carbide substrates are prepared. The LTV of each of the plurality of first silicon carbide substrates is measured. A plurality of first silicon carbide epitaxial substrates are obtained by forming a first silicon carbide epitaxial layer on each of the plurality of first silicon carbide substrates. The LTV of each of the plurality of first silicon carbide epitaxial substrates is measured. Based on the relationship between the LTV of each of the plurality of first silicon carbide substrates and the LTV of each of the plurality of first silicon carbide epitaxial substrates, a criterion for selecting a second silicon carbide substrate different from each of the plurality of first silicon carbide substrates is determined. The LTV of the second silicon carbide substrate is measured. It is determined whether the LTV of the second silicon carbide substrate satisfies the criterion. A second silicon carbide epitaxial layer is formed on the second silicon carbide substrate that satisfies the criterion.

The method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps: A plurality of first silicon carbide substrates are prepared. The LTIR of each of the plurality of first silicon carbide substrates is measured. A plurality of first silicon carbide epitaxial substrates are obtained by forming a first silicon carbide epitaxial layer on each of the plurality of first silicon carbide substrates. The LTIR of each of the plurality of first silicon carbide epitaxial substrates is measured. Based on the relationship between the LTIR of each of the plurality of first silicon carbide substrates and the LTIR of each of the plurality of first silicon carbide epitaxial substrates, a criterion for selecting a second silicon carbide substrate different from each of the plurality of first silicon carbide substrates is determined. The LTIR of the second silicon carbide substrate is measured. It is determined whether the LTIR of the second silicon carbide substrate satisfies the criterion. A second silicon carbide epitaxial layer is formed on the second silicon carbide substrate that satisfies the criterion.

The present disclosure provides a method for manufacturing a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device that can reduce the probability of exposure failure during the manufacturing process of a silicon carbide semiconductor device.

FIG. 1 is a schematic plan view showing the configuration of a silicon carbide epitaxial substrate. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. FIG. 3 is a schematic plan view showing the measurement areas of the LTV and LTIR. FIG. 4 is a schematic diagram for explaining the definition of LTV. FIG. 5 is a schematic diagram for explaining the definition of LTIR. FIG. 6 is a partial schematic cross-sectional view showing the configuration of an apparatus for manufacturing a silicon carbide epitaxial substrate. FIG. 7 is a flowchart roughly illustrating the method for manufacturing the silicon carbide epitaxial substrate according to the first embodiment. FIG. 8 is a schematic cross-sectional view showing the configuration of each of a plurality of first silicon carbide substrates. FIG. 9 is a schematic cross-sectional view showing the configuration of each of a plurality of first silicon carbide epitaxial substrates. FIG. 10 is a diagram showing the relationship between a first area ratio (area ratio of regions where LTV is less than 0.8 μm) of a first silicon carbide substrate and a second area ratio (area ratio of regions where LTV is less than 1.0 μm) of a first silicon carbide epitaxial substrate. FIG. 11 is a schematic cross-sectional view showing a configuration of a second silicon carbide substrate. FIG. 12 is a flowchart roughly illustrating the method for manufacturing a silicon carbide epitaxial substrate according to the second embodiment. FIG. 13 is a diagram showing the relationship between a first area ratio (area ratio of regions where LTIR is less than 0.8 μm) of a first silicon carbide substrate and a second area ratio (area ratio of regions where LTIR is less than 1.0 μm) of a first silicon carbide epitaxial substrate. FIG. 14 is a flowchart that roughly illustrates a method for manufacturing a silicon carbide semiconductor device according to this embodiment. FIG. 15 is a schematic cross-sectional view showing a step of forming a body region. FIG. 16 is a schematic cross-sectional view showing a step of forming a source region. FIG. 17 is a schematic cross-sectional view showing a step of forming a trench in the second main surface of the silicon carbide epitaxial layer. FIG. 18 is a schematic cross-sectional view showing a step of forming a gate insulating film. FIG. 19 is a schematic cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. FIG. 20 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment.

[Summary of the embodiment of the present disclosure]
First, an overview of the embodiments of the present disclosure will be described. In the crystallographic description in this specification, an individual orientation is represented by [ ], a collective orientation by <>, an individual plane by ( ), and a collective plane by { }. A negative index in crystallography is usually represented by placing a "-" (bar) above the number, but in this specification, a negative index in crystallography is represented by placing a negative sign before the number.

(1) The method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps: A plurality of first silicon carbide substrates 14 are prepared. The LTV of each of the plurality of first silicon carbide substrates 14 is measured. A plurality of first silicon carbide epitaxial substrates 100 are obtained by forming a first silicon carbide epitaxial layer 15 on each of the plurality of first silicon carbide substrates 14. The LTV of each of the plurality of first silicon carbide epitaxial substrates 100 is measured. Based on the relationship between the LTV of each of the plurality of first silicon carbide substrates 14 and the LTV of each of the plurality of first silicon carbide epitaxial substrates 100, a criterion for selecting a second silicon carbide substrate 24 different from each of the plurality of first silicon carbide substrates 14 is determined. The LTV of the second silicon carbide substrate 24 is measured. It is determined whether the LTV of the second silicon carbide substrate 24 satisfies the criterion. A second silicon carbide epitaxial layer 25 is formed on a second silicon carbide substrate 24 that meets the criteria.

(2) According to the method for manufacturing a silicon carbide epitaxial substrate according to (1) above, the first silicon carbide substrates 14 may have a main surface in contact with the first silicon carbide epitaxial layer 15. The main surface may be divided into a plurality of square regions. The length of one side of each of the plurality of square regions may be 10 mm. In the step of measuring the LTV of each of the first silicon carbide substrates 14, the LTV may be measured in each of the plurality of square regions. In the step of measuring the LTV of each of the first silicon carbide epitaxial substrates 100, the LTV may be measured in each of the plurality of square regions.

(3) According to the method for manufacturing a silicon carbide epitaxial substrate according to (1) or (2) above, in the step of determining whether the LTV of the second silicon carbide substrate 24 satisfies a criterion, if the area ratio of the regions in each of the multiple square regions 50 where the LTV is less than 1.0 μm is 90% or more, it may be determined that the LTV of the second silicon carbide substrate 24 satisfies the criterion.

(4) The method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure includes the following steps: A plurality of first silicon carbide substrates 14 are prepared. The LTIR of each of the plurality of first silicon carbide substrates 14 is measured. A plurality of first silicon carbide epitaxial substrates 100 are obtained by forming a first silicon carbide epitaxial layer 15 on each of the plurality of first silicon carbide substrates 14. The LTIR of each of the plurality of first silicon carbide epitaxial substrates 100 is measured. Based on the relationship between the LTIR of each of the plurality of first silicon carbide substrates 14 and the LTIR of each of the plurality of first silicon carbide epitaxial substrates 100, a criterion for selecting a second silicon carbide substrate 24 different from each of the plurality of first silicon carbide substrates 14 is determined. The LTIR of the second silicon carbide substrate 24 is measured. It is determined whether the LTIR of the second silicon carbide substrate 24 satisfies a criterion. A second silicon carbide epitaxial layer 25 is formed on the second silicon carbide substrate 24 that satisfies the criterion.

(5) According to the method for manufacturing a silicon carbide epitaxial substrate according to (4) above, the first silicon carbide substrates 14 may have a main surface in contact with the first silicon carbide epitaxial layer 15. The main surface may be divided into a plurality of square regions 50. The length of one side of each of the plurality of square regions 50 may be 10 mm. In the step of measuring the LTIR of each of the plurality of first silicon carbide substrates 14, the LTIR may be measured in each of the plurality of square regions 50. In the step of measuring the LTIR of each of the plurality of first silicon carbide epitaxial substrates 100, the LTIR may be measured in each of the plurality of square regions 50.

(6) According to the method for manufacturing a silicon carbide epitaxial substrate according to (4) or (5) above, in the step of determining whether the LTIR of the second silicon carbide substrate 24 satisfies a criterion, if the area ratio of the regions in each of the multiple square regions 50 where the LTIR is less than 1.0 μm is 90% or more, it may be determined that the LTIR of the second silicon carbide substrate 24 satisfies the criterion.

(7) The method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps: A silicon carbide epitaxial substrate manufactured by the method for manufacturing a silicon carbide epitaxial substrate described in any one of (1) to (6) above is prepared. The silicon carbide epitaxial substrate is processed.

[Details of the embodiment of the present disclosure]
Hereinafter, the details of the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

First, the configuration of the silicon carbide epitaxial substrate 200 according to this embodiment will be described. FIG. 1 is a plan view schematic diagram showing the configuration of the silicon carbide epitaxial substrate 200. FIG. 2 is a cross-sectional schematic diagram taken along line II-II in FIG. 1.

As shown in FIG. 1 and FIG. 2, the silicon carbide epitaxial substrate 200 according to this embodiment has a second silicon carbide substrate 24 and a second silicon carbide epitaxial layer 25. The second silicon carbide epitaxial layer 25 is on the second silicon carbide substrate 24. The second silicon carbide epitaxial layer 25 is in contact with the second silicon carbide substrate 24. The silicon carbide epitaxial substrate 200 has a first main surface 21 and a second main surface 22. The second main surface 22 is on the opposite side to the first main surface 21.

The first main surface 21 is formed of a second silicon carbide substrate 24. The second main surface 22 is formed of a second silicon carbide epitaxial layer 25. The second silicon carbide substrate 24 has a third main surface 23. The third main surface 23 is in contact with the second silicon carbide epitaxial layer 25. The polytype of the silicon carbide forming the second silicon carbide substrate 24 is, for example, 4H. The polytype of the silicon carbide forming the second silicon carbide epitaxial layer 25 is, for example, 4H.

As shown in FIG. 1, when viewed in the thickness direction of the silicon carbide epitaxial substrate 200, the silicon carbide epitaxial substrate 200 has an outer peripheral side surface 9. The outer peripheral side surface 9 has, for example, an orientation flat 7 and an arc-shaped portion 8. The orientation flat 7 extends along the first direction 101. As shown in FIG. 1, when viewed in the thickness direction of the silicon carbide epitaxial substrate 200, the orientation flat 7 is linear. The arc-shaped portion 8 is continuous with the orientation flat 7. When viewed in the thickness direction of the silicon carbide epitaxial substrate 200, the arc-shaped portion 8 is arc-shaped.

As shown in FIG. 1, when viewed in the thickness direction of the silicon carbide epitaxial substrate 200, the second main surface 22 extends along each of the first direction 101 and the second direction 102. When viewed in the thickness direction of the silicon carbide epitaxial substrate 200, the first direction 101 is perpendicular to the second direction 102.

The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be a direction obtained by projecting the <11-20> direction onto the second main surface 22. From another perspective, the first direction 101 may be, for example, a direction that includes a <11-20> directional component.

The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, the direction obtained by projecting the <1-100> direction onto the second main surface 22. From another perspective, the second direction 102 may be, for example, a direction that includes a <1-100> directional component.

As shown in FIG. 1, the diameter (first width W1) of the silicon carbide epitaxial substrate 200 is not particularly limited, but is, for example, 100 mm (4 inches) or more. The first width W1 may be 125 mm (5 inches) or more, or 150 mm (6 inches) or more. The upper limit of the first width W1 is not particularly limited. The first width W1 may be, for example, 200 mm (8 inches) or less.

In this specification, 4 inches means 100 mm or 101.6 mm (4 inches x 25.4 mm/inch). 5 inches means 125 mm or 127.0 mm (5 inches x 25.4 mm/inch). 6 inches means 150 mm or 152.4 mm (6 inches x 25.4 mm/inch). 8 inches means 200 mm or 203.2 mm (8 inches x 25.4 mm/inch).

The second main surface 22 of the silicon carbide epitaxial substrate 200 may be inclined at an off angle of 8° or less with respect to the {0001} plane, for example. Specifically, the second main surface 22 may be inclined at an off angle of 8° or less with respect to the (0001) plane or the (0001) plane. The first main surface 21 may be inclined at an off angle of 8° or less with respect to the (000-1) plane or the (000-1) plane.

The upper limit of the off angle is not particularly limited, but may be, for example, 6° or less, or 4° or less. The lower limit of the off angle is not particularly limited, but may be, for example, 2° or more, or 1° or more. The off direction is not particularly limited, but may be, for example, the <11-20> direction or the <0001> direction.

The second silicon carbide substrate 24 contains an n-type impurity such as nitrogen (N). The conductivity type of the second silicon carbide substrate 24 is, for example, n-type (first conductivity type). In this case, the carriers are electrons. The carrier concentration of the second silicon carbide substrate 24 is, for example, 1×10 ¹⁹ m ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less. The thickness of the second silicon carbide substrate 24 is not particularly limited, and may be, for example, 200 μm or more and 500 μm or less.

Second silicon carbide epitaxial layer 25 contains an n-type impurity such as nitrogen (N). The conductivity type of second silicon carbide epitaxial layer 25 is, for example, n-type (first conductivity type). In this case, the carriers are electrons. The carrier concentration of second silicon carbide epitaxial layer 25 is, for example, 1×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁹ cm ⁻³ or less. The thickness of second silicon carbide epitaxial layer 25 is not particularly limited, and may be, for example, 2 μm or more and 100 μm or less.

Next, we will explain how to measure the LTV (Local Thickness Variation) and LTIR (Local Total Indicated Reading) of the substrate. LTV and LTIR can be measured using, for example, the "Tropel FlatMaster (registered trademark)" manufactured by Corning Tropel.

Figure 3 is a schematic plan view showing the measurement areas of LTV and LTIR. As shown in Figure 3, the measurement surface A of the substrate is divided into a plurality of square regions 50. The length (W2) of one side of each of the plurality of square regions 50 is, for example, 10 mm. The diameter (W1) of the measurement surface A is, for example, 150 mm. First, a square of 150 mm x 150 mm circumscribing the outer peripheral side surface 9 of the substrate is assumed. The 150 mm x 150 mm square is divided into 10 mm x 10 mm square regions (15 x 15 = 225 pieces). When viewed in the thickness direction of the substrate, the number of square regions 50 surrounded by the outer peripheral side surface 9 is 145. When viewed in the thickness direction of the substrate, the square regions that intersect with the outer peripheral side surface 9 are partially missing and are not complete square regions. Therefore, the square regions that intersect with the outer peripheral side surface 9 are not considered to be square regions 50 that constitute the measurement surface A. When viewed in the thickness direction of the substrate, one side of each of the square regions 50 is parallel to the extension direction of the orientation flat 7.

As shown in FIG. 3, when the diameter of the measurement surface A is 150 mm, the measurement surface A is divided into 145 square regions 50, each of which has a side length W2 of 10 mm. The LTV and LTIR are measured in each of the 145 square regions 50.

Next, we will explain the definition of LTV. Figure 4 is a schematic diagram explaining the definition of LTV.

LTV=|T2-T1| (Formula 1)
The LTV is measured, for example, by the following procedure. First, a silicon carbide substrate or a silicon carbide epitaxial substrate is prepared. The silicon carbide substrate or the silicon carbide epitaxial substrate has a front surface and a back surface. The back surface is the surface opposite to the front surface. One of the front surface and the back surface becomes an adsorption surface B that is adsorbed to a flat chuck surface. The surface opposite to the adsorption surface B becomes a measurement surface A.

The adsorption surface B of the silicon carbide substrate or silicon carbide epitaxial substrate is entirely adsorbed to the chuck surface. Next, an image of the measurement surface A on the opposite side of the adsorption surface B is optically acquired. As shown in FIG. 4 and Equation 1, the LTV is the value obtained by subtracting the height (first height T1) from the adsorption surface B to the lowest point (first lowest point P1) of the measurement surface A from the height (second height T2) from the adsorption surface B to the highest point (first highest point P2) of the measurement surface A when the adsorption surface B is entirely adsorbed to the flat chuck surface. In other words, the LTV is the value obtained by subtracting the shortest distance between the measurement surface A and the adsorption surface B from the longest distance between the measurement surface A and the adsorption surface B in the direction perpendicular to the adsorption surface B. In other words, LTV is the distance between a plane (second plane L2) that passes through the first highest point P2 and is parallel to the suction surface B, and a plane (first plane L1) that passes through the first lowest point P1 and is parallel to the suction surface B.

Next, we will explain how to measure LTIR. Figure 5 is a schematic diagram explaining the definition of LTIR.

LTIR=|T3|+|T4| ... (Formula 2)
The LTIR is measured, for example, by the following procedure: First, the entire chucking surface B of the silicon carbide substrate or silicon carbide epitaxial substrate is chucked onto the chuck surface, and then an image of the measurement surface A on the opposite side to the chucking surface B is optically acquired.

Next, the least square plane L5 of the square area of the measurement surface A is calculated. As shown in FIG. 5 and Equation 2, LTIR is the value obtained by subtracting the height (minimum height T3) from the least square plane L5 to the fourth highest point P4 of the measurement surface A from the height (maximum height T4) from the least square plane L5 to the third lowest point P3 of the measurement surface A when the chucking surface B is entirely chucked to the flat chuck surface. The third lowest point P3 is the position where the distance between the least square plane L5 along the direction perpendicular to the least square plane L5 and the measurement surface A is maximum in the region of the measurement surface A located on the chucking surface B side with respect to the least square plane L5. The fourth highest point P4 is the position where the distance between the least square plane L5 along the direction perpendicular to the least square plane L5 and the measurement surface A is maximum in the region of the measurement surface A located on the opposite side of the chucking surface B side with respect to the least square plane L5. In other words, LTIR is the distance between a plane (fourth plane L4) that passes through the fourth highest point P4 and is parallel to the least squares plane L5, and a plane (third plane L3) that passes through the third lowest point P3 and is parallel to the least squares plane L5.

(Silicon carbide epitaxial substrate manufacturing device)
Next, the configuration of the manufacturing apparatus for silicon carbide epitaxial substrate 200 will be described. Fig. 6 is a partial cross-sectional schematic diagram showing the configuration of the manufacturing apparatus for silicon carbide epitaxial substrate 200. The manufacturing apparatus 300 for silicon carbide epitaxial substrate 200 is, for example, a hot-wall type horizontal CVD (Chemical Vapor Deposition) apparatus. As shown in Fig. 6, the manufacturing apparatus 300 for silicon carbide epitaxial substrate 200 mainly includes reaction chamber 201, gas supply unit 235, control unit 245, heating element 203, quartz tube 204, heat insulating material (not shown), and induction heating coil (not shown).

The heating element 203 has, for example, a cylindrical shape, and forms a reaction chamber 201 inside. The heating element 203 is made of, for example, graphite. The heating element 203 is provided inside a quartz tube 204. A heat insulating material surrounds the outer periphery of the heating element 203. The induction heating coil is wound, for example, along the outer periphery of the quartz tube 204. The induction heating coil is configured so that an alternating current can be supplied to it by an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the reaction chamber 201 is heated by the heating element 203.

The reaction chamber 201 is a space surrounded by the inner wall surface 205 of the heating element 203. A susceptor 210 that holds a second silicon carbide substrate 24 is provided in the reaction chamber 201. The susceptor 210 is made of silicon carbide. The second silicon carbide substrate 24 is placed on the susceptor 210. The susceptor 210 is placed on a stage 202. The stage 202 is supported by a rotating shaft 209 so that it can rotate about its own axis. The susceptor 210 rotates as the stage 202 rotates.

The manufacturing apparatus 300 for the silicon carbide epitaxial substrate 200 further includes a gas inlet 207 and a gas exhaust port 208. The gas exhaust port 208 is connected to an exhaust pump (not shown). The arrows in FIG. 6 indicate the flow of gas. Gas is introduced into the reaction chamber 201 from the gas inlet 207 and exhausted from the gas exhaust port 208. The pressure inside the reaction chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.

The gas supply unit 235 is configured to be able to supply a mixed gas containing a raw material gas, a dopant gas, and a carrier gas to the reaction chamber 201. Specifically, the gas supply unit 235 includes, for example, a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a fourth gas supply unit 234.

The first gas supply unit 231 is configured to be able to supply a first gas containing, for example, carbon _atoms . The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane ( _C3H8 ) gas. The first gas may be, for example, methane ( _CH4 ) gas, ethane _{( C2H6} ) gas, acetylene ( _C2H2 ) gas, or _the like.

The second gas supply unit 232 is configured to be able to supply a second gas including, for example, silane gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane (SiH ₄ ) gas. The second gas may be a mixed gas of silane gas and a gas other than silane.

The third gas supply unit 233 is configured to be able to supply a third gas containing, for example, nitrogen atoms. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas. The third gas is, for example, ammonia gas. Ammonia gas is more easily thermally decomposed than nitrogen gas, which has a triple bond.

The fourth gas supply unit 234 is configured to be capable of supplying a fourth gas (carrier gas) such as hydrogen. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen. The fourth gas may be argon gas.

The control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the reaction chamber 201. Specifically, the control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207.

(Method of manufacturing silicon carbide epitaxial substrate)
First Embodiment
Next, a method for manufacturing the silicon carbide epitaxial substrate 200 according to the first embodiment will be described. Fig. 7 is a flow chart that outlines the method for manufacturing the silicon carbide epitaxial substrate 200 according to the first embodiment. As shown in FIG. 7 , the manufacturing method of the silicon carbide epitaxial substrate 200 according to the first embodiment mainly includes a step of preparing a plurality of first silicon carbide substrates 14 (S11), a step of measuring the LTV of each of the plurality of first silicon carbide substrates 14 (S12), a step of obtaining a plurality of first silicon carbide epitaxial substrates 100 (S13), a step of measuring the LTV of each of the plurality of first silicon carbide epitaxial substrates 100 (S14), a step of determining a criterion for selecting the second silicon carbide substrate 24 (S15), a step of measuring the LTV of the second silicon carbide substrate 24 (S16), a step of determining whether the LTV of the second silicon carbide substrate 24 satisfies the criterion (S17), and a step of forming a second silicon carbide epitaxial layer 25 on the second silicon carbide substrate 24 (S18).

First, a step (S11) of preparing a plurality of first silicon carbide substrates 14 is performed. For example, an ingot made of silicon carbide single crystal manufactured by sublimation is sliced by a wire saw. In this way, a plurality of first silicon carbide substrates 14 are prepared. Each of the plurality of first silicon carbide substrates 14 is made of, for example, silicon carbide of polytype 4H. Each of the plurality of first silicon carbide substrates 14 contains an n-type impurity such as nitrogen. The concentration of the n-type impurity is, for example, 1×10 ¹⁵ cm ³ or more and 1×10 ¹⁹ cm ³ or less.

Figure 8 is a schematic cross-sectional view showing the configuration of each of the multiple first silicon carbide substrates 14. As shown in Figure 8, each of the multiple first silicon carbide substrates 14 has a fourth main surface 11 and a sixth main surface 13. The sixth main surface 13 is on the opposite side to the fourth main surface 11. The diameter of the fourth main surface 11 is, for example, 150 mm.

Next, a step (S12) of measuring the LTV of each of the multiple first silicon carbide substrates 14 is performed. The fourth main surface 11 is, for example, the adsorption surface B. The sixth main surface 13 is, for example, the measurement surface A. The measurement surface A of the first silicon carbide substrate 14 is divided into multiple square regions 50. The LTV is measured in the multiple square regions 50. When the diameter of the measurement surface A is 150 mm, the measurement surface A is divided into 145 square regions 50, each having a side length W2 of 10 mm. The LTV is measured in each of the 145 square regions 50.

Next, in each of the square regions 50, it is determined whether the LTV value is less than a first specific value. The first specific value is, for example, 0.8 μm. Specifically, it is determined whether the LTV value is less than 0.8 μm in each of the square regions 50. Next, the area ratio (first area ratio) of the square regions in which the LTV value is less than the first specific value is calculated. The first area ratio is the number of square regions in which the LTV value is less than the first specific value divided by the number of all square regions. For example, if the number of square regions in which the LTV value is less than 0.8 μm is 135 and the number of all square regions is 145, the first area ratio is 135/145. The first specific value may be, for example, 0.7 μm or 0.6 μm.

Next, a step (S13) of obtaining a plurality of first silicon carbide epitaxial substrates 100 is performed. A plurality of first silicon carbide substrates 14 are placed on susceptor 210. Next, reaction chamber 201 is depressurized. Specifically, the pressure in reaction chamber 201 is reduced from atmospheric pressure to, for example, about 1×10 ⁻⁶ Pa. Next, heating of the plurality of first silicon carbide substrates 14 is started. During the heating, hydrogen (H ₂ ) gas, which is a carrier gas, is introduced into reaction chamber 201 from fourth gas supply unit 234.

Next, the source gas, dopant gas, and carrier gas are supplied to the reaction chamber 201. Specifically, a mixed gas containing, for example, silane, propane, ammonia, and hydrogen is introduced into the reaction chamber 201. In the reaction chamber 201, each gas is thermally decomposed. The growth temperature is, for example, 1500°C or higher and 1750°C or lower. The mixed gas may contain argon instead of hydrogen.

The flow rate of the first gas (propane gas) is, for example, 29 sccm. The flow rate of the second gas (silane gas) is, for example, 46 sccm. The flow rate of the third gas (ammonia gas) is, for example, 1.5 sccm. The flow rate of the fourth gas (hydrogen gas or argon gas) is, for example, 100 slm. The reaction chamber 201 is maintained at a pressure of, for example, 2 kPa or more and 6 kPa or less. As a result, a first silicon carbide epitaxial layer 15 is formed on each of the multiple first silicon carbide substrates 14. As a result, a first silicon carbide epitaxial substrate 100 having the first silicon carbide substrate 14 and the first silicon carbide epitaxial layer 15 is obtained.

Figure 9 is a schematic cross-sectional view showing the configuration of each of the multiple first silicon carbide epitaxial substrates 100. As shown in Figure 9, each of the multiple first silicon carbide epitaxial substrates 100 has a fifth main surface 12 and a fourth main surface 11. The fifth main surface 12 is located opposite the fourth main surface 11. The sixth main surface 13 is located between the fourth main surface 11 and the fifth main surface 12.

Next, a step (S14) of measuring the LTV of each of the multiple first silicon carbide epitaxial substrates 100 is performed. The fourth main surface 11 is, for example, the adsorption surface B. The fifth main surface 12 is, for example, the measurement surface A. The measurement surface A of the first silicon carbide epitaxial substrate 100 is divided into multiple square regions 50. The LTV is measured in the multiple square regions 50. When the diameter of the measurement surface A is 150 mm, the measurement surface A is divided into 145 square regions 50, each having a side length W2 of 10 mm. The LTV is measured in each of the 145 square regions 50.

Next, in each of the square regions 50, it is determined whether the LTV value is less than a second specific value. The second specific value is, for example, 1.0 μm. Specifically, it is determined whether the LTV value is less than 1.0 μm in each of the square regions 50. Next, the area ratio (second area ratio) of the square regions in which the LTV value is less than the second specific value is calculated. The second area ratio is the number of square regions in which the LTV value is less than the second specific value divided by the number of all square regions. For example, if the number of square regions in which the LTV value is less than 1.0 μm is 140 and the number of all square regions is 145, the second area ratio is 140/145. The second specific value may be, for example, 0.9 μm or 0.8 μm.

Next, a step (S15) of determining criteria for selecting the second silicon carbide substrate 24 is performed. Specifically, a correlation between the LTV of each of the plurality of first silicon carbide substrates 14 and the LTV of each of the plurality of first silicon carbide epitaxial substrates 100 is obtained. FIG. 10 is a diagram showing the relationship between the first area ratio (area ratio of the region where the LTV is less than 0.8 μm) of the first silicon carbide substrate 14 and the second area ratio (area ratio of the region where the LTV is less than 1.0 μm) of the first silicon carbide epitaxial substrate 100. The horizontal axis of FIG. 10 indicates the first area ratio (area ratio of the region where the LTV is less than 0.8 μm) of the first silicon carbide substrate 14. The vertical axis of FIG. 10 indicates the second area ratio (area ratio of the region where the LTV is less than 1.0 μm) of the first silicon carbide epitaxial substrate 100.

As shown in FIG. 10, when the first area ratio of the first silicon carbide substrate 14 is high, the second area ratio of the first silicon carbide epitaxial substrate 100 obtained by forming the first silicon carbide epitaxial layer 15 on the first silicon carbide substrate 14 tends to be high. In other words, the second area ratio of the first silicon carbide epitaxial substrate 100 can be predicted from the first area ratio of the first silicon carbide substrate 14. In order to improve the prediction accuracy of the second area ratio of the first silicon carbide epitaxial substrate 100, it is desirable to have a large number of first silicon carbide substrates 14. The number of first silicon carbide substrates 14 is not particularly limited, but may be, for example, 20 or more, or 40 or more.

Next, a criterion for selecting the second silicon carbide substrate 24 is determined. First, a correlation between the first area ratio of the first silicon carbide substrate 14 and the second area ratio of the first silicon carbide epitaxial substrate 100 is determined. For example, a linear approximation is used to determine the correlation between the first area ratio of the first silicon carbide substrate 14 and the second area ratio of the first silicon carbide epitaxial substrate 100. A criterion for selecting the second silicon carbide substrate 24 may be determined based on a linear function determined by the linear approximation.

For example, in order to obtain a first silicon carbide epitaxial substrate 100 in which the second area ratio of the first silicon carbide epitaxial substrate 100 is 90% or more, the first area ratio of the first silicon carbide substrate 14 can be 80% or more. In this case, the criterion for selecting the second silicon carbide substrate 24 is to satisfy the condition that the first area ratio of the second silicon carbide substrate 24 is 80% or more. As described above, the criterion for selecting the second silicon carbide substrate 24 is determined based on the relationship between the LTV of each of the multiple first silicon carbide substrates 14 and the LTV of each of the multiple first silicon carbide epitaxial substrates 100. The criterion for selecting the second silicon carbide substrate 24 may be determined by other methods. In order to more reliably obtain a first silicon carbide epitaxial substrate 100 in which the second area ratio of the first silicon carbide epitaxial substrate 100 is 90% or more, the criterion for selecting the second silicon carbide substrate 24 may be that the first area ratio of the second silicon carbide substrate 24 satisfies the condition that the first area ratio of the second silicon carbide substrate 24 is 90% or more.

Next, a step (S16) of measuring the LTV of the second silicon carbide substrate 24 is performed. The second silicon carbide substrate 24 is different from each of the multiple first silicon carbide substrates 14. First, the second silicon carbide substrate 24 is prepared. FIG. 11 is a schematic cross-sectional view showing the configuration of the second silicon carbide substrate 24. As shown in FIG. 11, the second silicon carbide substrate 24 has a third main surface 23 and a first main surface 21. The first main surface 21 is on the opposite side to the third main surface 23. Next, the LTV of the second silicon carbide substrate 24 is measured. The first main surface 21 is, for example, the adsorption surface B. The third main surface 23 is, for example, the measurement surface A.

As shown in FIG. 3, the measurement surface A of the second silicon carbide substrate 24 is divided into a plurality of square regions 50. The LTV is measured in the plurality of square regions 50. When the diameter of the measurement surface A is 150 mm, the measurement surface A is divided into 145 square regions 50, each having a side length W2 of 10 mm. The LTV is measured in each of the 145 square regions 50.

Next, in each of the plurality of square regions 50, it is determined whether the LTV value is less than a first specific value. The first specific value is, for example, 0.8 μm. Specifically, it is determined whether the LTV value is less than 0.8 μm in each of the plurality of square regions 50. Next, the area ratio (first area ratio) of the square regions whose LTV values are less than the first specific value is calculated. The first area ratio is the number of square regions whose LTV values are less than the first specific value divided by the number of all square regions. For example, if the number of square regions whose LTV values are less than 0.8 μm is 135 and the number of all square regions is 145, the first area ratio is 135/145.

Next, a step (S17) of determining whether the LTV of the second silicon carbide substrate 24 satisfies a criterion is performed. Specifically, it is determined whether the LTV of the second silicon carbide substrate 24 satisfies the criterion determined in the step (S15) of determining the criterion for selecting the second silicon carbide substrate 24. For example, if it is determined that the criterion for selecting the second silicon carbide substrate 24 is that the first area ratio of the second silicon carbide substrate 24 is 90% or more, the second silicon carbide substrate 24 having the first area ratio of 90% or more is determined to satisfy the criterion. Conversely, the second silicon carbide substrate 24 having the first area ratio of less than 90% is determined to not satisfy the criterion. The second silicon carbide substrate 24 that does not satisfy the criterion is discarded or is subjected to a polishing process or the like until it satisfies the criterion.

Next, a step (S18) of forming a second silicon carbide epitaxial layer 25 on the second silicon carbide substrate 24 is performed. First, the second silicon carbide substrate 24 determined to satisfy the above criteria is selected. Next, the second silicon carbide epitaxial layer 25 is formed on the second silicon carbide substrate 24. The deposition conditions of the second silicon carbide epitaxial layer 25 in the step (S18) of forming the second silicon carbide epitaxial layer 25 on the second silicon carbide substrate 24 may be the same as the deposition conditions when the first silicon carbide epitaxial layer 15 is formed on the first silicon carbide substrate 14. In this manner, a silicon carbide epitaxial substrate 200 is obtained (see FIG. 1).

Second Embodiment
Next, a method for manufacturing the silicon carbide epitaxial substrate 200 according to the second embodiment will be described. Fig. 12 is a flow chart that outlines the method for manufacturing the silicon carbide epitaxial substrate 200 according to the second embodiment. As shown in FIG. 12 , the manufacturing method of the silicon carbide epitaxial substrate 200 according to the second embodiment mainly includes a step of preparing a plurality of first silicon carbide substrates 14 (S21), a step of measuring the LTIR of each of the plurality of first silicon carbide substrates 14 (S22), a step of obtaining a plurality of first silicon carbide epitaxial substrates 100 (S23), a step of measuring the LTIR of each of the plurality of first silicon carbide epitaxial substrates 100 (S24), a step of determining a criterion for selecting the second silicon carbide substrate 24 (S25), a step of measuring the LTIR of the second silicon carbide substrate 24 (S26), a step of determining whether the LTIR of the second silicon carbide substrate 24 satisfies the criterion (S27), and a step of forming a second silicon carbide epitaxial layer 25 on the second silicon carbide substrate 24 (S28).

The method for manufacturing the silicon carbide epitaxial substrate 200 according to the second embodiment differs from the method for manufacturing the silicon carbide epitaxial substrate 200 according to the first embodiment mainly in that the LTIR is measured instead of the LTV, and is otherwise similar to the method for manufacturing the silicon carbide epitaxial substrate 200 according to the second embodiment. Below, the process that differs from the method for manufacturing the silicon carbide epitaxial substrate 200 according to the first embodiment will be mainly described.

First, a process (S21) of preparing a plurality of first silicon carbide substrates 14 is performed. The process (S21) of preparing a plurality of first silicon carbide substrates 14 is similar to the process (S11) of preparing a plurality of first silicon carbide substrates 14.

Next, a step (S22) of measuring the LTIR of each of the plurality of first silicon carbide substrates 14 is performed. The fourth main surface 11 is, for example, the adsorption surface B. The sixth main surface 13 is, for example, the measurement surface A. As shown in FIG. 3, the measurement surface A of the first silicon carbide substrate 14 is divided into a plurality of square regions 50. The LTIR is measured in the plurality of square regions 50. When the diameter of the measurement surface A is 150 mm, the measurement surface A is divided into 145 square regions 50, each of which has a side length W2 of 10 mm. The LTIR is measured in each of the 145 square regions 50.

Next, in each of the square regions 50, it is determined whether the LTIR value is less than a first specific value. The first specific value is, for example, 0.8 μm. Specifically, it is determined whether the LTIR value is less than 0.8 μm in each of the square regions 50. Next, the area ratio (first area ratio) of the square regions in which the LTIR value is less than the first specific value is obtained. The first area ratio is the number of square regions in which the LTIR value is less than the first specific value divided by the number of all square regions. For example, if the number of square regions in which the LTIR value is less than 0.8 μm is 135 and the number of all square regions is 145, the first area ratio is 135/145. The first specific value may be, for example, 0.7 μm or 0.6 μm.

Next, a process (S23) of obtaining a plurality of first silicon carbide epitaxial substrates 100 is carried out. The process (S23) of obtaining a plurality of first silicon carbide epitaxial substrates 100 is similar to the process (S13) of obtaining a plurality of first silicon carbide epitaxial substrates 100.

Next, a step (S24) of measuring the LTIR of each of the multiple first silicon carbide epitaxial substrates 100 is performed. The fourth main surface 11 is, for example, the adsorption surface B. The fifth main surface 12 is, for example, the measurement surface A. The measurement surface A of the first silicon carbide epitaxial substrate 100 is divided into multiple square regions 50. The LTIR is measured in the multiple square regions 50. When the diameter of the measurement surface A is 150 mm, the measurement surface A is divided into 145 square regions 50, each having a side length W2 of 10 mm. The LTIR is measured in each of the 145 square regions 50.

Next, in each of the square regions 50, it is determined whether the LTIR value is less than a second specific value. The second specific value is, for example, 1.0 μm. Specifically, it is determined whether the LTIR value is less than 1.0 μm in each of the square regions 50. Next, the area ratio (second area ratio) of the square regions in which the LTIR value is less than the second specific value is calculated. The second area ratio is the number of square regions in which the LTIR value is less than the second specific value divided by the number of all square regions. For example, if the number of square regions in which the LTV value is less than 1.0 μm is 140 and the number of all square regions is 145, the second area ratio is 140/145. The second specific value may be, for example, 0.9 μm or 0.8 μm.

Next, a step (S25) of determining criteria for selecting the second silicon carbide substrate 24 is performed. Specifically, a correlation between the LTIR of each of the plurality of first silicon carbide substrates 14 and the LTIR of each of the plurality of first silicon carbide epitaxial substrates 100 is obtained. FIG. 13 is a diagram showing the relationship between the first area ratio of the first silicon carbide substrate 14 (area ratio of the region where the LTIR is less than 0.8 μm) and the second area ratio of the first silicon carbide epitaxial substrate 100 (area ratio of the region where the LTIR is less than 1.0 μm). The horizontal axis of FIG. 13 indicates the first area ratio of the first silicon carbide substrate 14 (area ratio of the region where the LTIR is less than 0.8 μm). The vertical axis of FIG. 13 indicates the second area ratio of the first silicon carbide epitaxial substrate 100 (area ratio of the region where the LTIR is less than 1.0 μm).

As shown in FIG. 13, when the first area ratio of the first silicon carbide substrate 14 is high, the second area ratio of the first silicon carbide epitaxial substrate 100 obtained by forming the first silicon carbide epitaxial layer 15 on the first silicon carbide substrate 14 tends to be high. In other words, the second area ratio of the first silicon carbide epitaxial substrate 100 can be predicted from the first area ratio of the first silicon carbide substrate 14.

For example, in order to obtain a first silicon carbide epitaxial substrate 100 having a second area ratio of 90% or more with a high probability, the first area ratio of the first silicon carbide substrate 14 can be set to 90% or more. In this case, the criterion for selecting the second silicon carbide substrate 24 is to satisfy the condition that the first area ratio of the second silicon carbide substrate 24 is 90% or more. As described above, the criterion for selecting the second silicon carbide substrate 24 is determined based on the relationship between the LTIR of each of the multiple first silicon carbide substrates 14 and the LTIR of each of the multiple first silicon carbide epitaxial substrates 100.

Next, a step (S26) of measuring the LTIR of the second silicon carbide substrate 24 is carried out. The second silicon carbide substrate 24 is different from each of the multiple first silicon carbide substrates 14. First, the second silicon carbide substrate 24 is prepared. The measurement surface A of the second silicon carbide substrate 24 is divided into multiple square regions 50. The LTIR is measured in the multiple square regions 50. When the diameter of the measurement surface A is 150 mm, the measurement surface A is divided into 145 square regions 50, each with a side length W2 of 10 mm. The LTIR is measured in each of the 145 square regions 50.

Next, in each of the plurality of square regions 50, it is determined whether the LTIR value is less than a first specific value. The first specific value is, for example, 0.8 μm. Specifically, it is determined whether the LTIR value is less than 0.8 μm in each of the plurality of square regions 50. Next, the area ratio (first area ratio) of the square regions in which the LTIR value is less than the first specific value is calculated. The first area ratio is the number of square regions in which the LTIR value is less than the first specific value divided by the number of all square regions. For example, if the number of square regions in which the LTIR value is less than 0.8 μm is 135 and the number of all square regions is 145, the first area ratio is 135/145.

Next, a step (S27) of determining whether the LTIR of the second silicon carbide substrate 24 satisfies a criterion is performed. Specifically, it is determined whether the LTIR of the second silicon carbide substrate 24 satisfies the criterion determined in the step (S25) of determining the criterion for selecting the second silicon carbide substrate 24. For example, if it is determined that the criterion for selecting the second silicon carbide substrate 24 is that the first area ratio of the second silicon carbide substrate 24 is 90% or more, the second silicon carbide substrate 24 having the first area ratio of 90% or more is determined to satisfy the criterion. Conversely, the second silicon carbide substrate 24 having the first area ratio of less than 90% is determined to not satisfy the criterion. The second silicon carbide substrate 24 that does not satisfy the criterion is discarded or is subjected to a polishing process or the like until it satisfies the criterion.

Next, a step (S28) of forming a second silicon carbide epitaxial layer 25 on the second silicon carbide substrate 24 is performed. The step (S28) of forming a second silicon carbide epitaxial layer 25 on the second silicon carbide substrate 24 is similar to the step (S18) of forming a second silicon carbide epitaxial layer 25 on the second silicon carbide substrate 24.

(Method of Manufacturing Silicon Carbide Semiconductor Device)
Next, a method for manufacturing the silicon carbide semiconductor device 400 according to this embodiment will be described. Fig. 14 is a flow chart that outlines the method for manufacturing the silicon carbide semiconductor device 400 according to this embodiment. As shown in Fig. 14, the method for manufacturing the silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of preparing a silicon carbide epitaxial substrate and a step (S2) of processing the silicon carbide epitaxial substrate.

First, a step (S1) of preparing a silicon carbide epitaxial substrate is performed. In the step (S1) of preparing a silicon carbide epitaxial substrate, a silicon carbide epitaxial substrate 200 manufactured by the method for manufacturing a silicon carbide epitaxial substrate 200 according to this embodiment is obtained (see FIG. 2).

Next, a step (S2) of processing the silicon carbide epitaxial substrate is performed. Specifically, the silicon carbide epitaxial substrate 200 is processed as follows. First, ions are implanted into the silicon carbide epitaxial substrate 200. Specifically, an ion-implanted region, such as the body region 113, is formed in the second silicon carbide epitaxial layer 25.

Figure 15 is a schematic cross-sectional view showing the process of forming a body region. Specifically, p-type impurities such as aluminum are ion-implanted into the second main surface 22 of the second silicon carbide epitaxial layer 25. This forms a body region 113 having p-type conductivity. The portion of the second silicon carbide epitaxial layer 25 where the body region 113 is not formed becomes a drift region 121. The thickness of the body region 113 is, for example, 0.9 μm.

Next, a step of forming a source region is carried out. FIG. 16 is a schematic cross-sectional view showing the step of forming a source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having an n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurity contained in the source region 114 is higher than the concentration of the p-type impurity contained in the body region 113.

Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed so as to penetrate the source region 114 and the body region 113 and contact the drift region 121. The concentration of the p-type impurity contained in the contact region 118 is higher than the concentration of the n-type impurity contained in the source region 114.

Next, activation annealing is performed to activate the ion-implanted impurities. The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The time of the activation annealing is, for example, about 30 minutes. The atmosphere of the activation annealing is preferably an inert gas atmosphere, for example, an argon atmosphere.

Next, a step of forming a trench in the second main surface 22 of the second silicon carbide epitaxial layer 25 is performed. FIG. 17 is a cross-sectional schematic diagram showing a step of forming a trench in the second main surface 22 of the second silicon carbide epitaxial layer 25. A mask 17 having an opening is formed on the second main surface 22 including the source region 114 and the contact region 118. Using the mask 17, the source region 114, the body region 113, and a part of the drift region 121 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used. Specifically, for example, inductively coupled plasma reactive ion etching using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reactive gas can be used. A recess is formed in the second main surface 22 by etching.

Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms, with the mask 17 formed on the second main surface 22. The at least one or more types of halogen atoms include at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere includes, for example, Cl ₂ , BCl ₃ , SF ₆ or CF _4. For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and the thermal etching is performed at a heat treatment temperature of, for example, 700° C. or more and 1000° C. or less. The reactive gas may include a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. For example, nitrogen gas, argon gas, or helium gas can be used as the carrier gas.

As shown in FIG. 17, a trench 56 is formed in the second main surface 22 by thermal etching. The trench 56 is defined by a sidewall surface 53 and a bottom wall surface 54. The sidewall surface 53 is composed of the source region 114, the body region 113, and the drift region 121. The bottom wall surface 54 is composed of the drift region 121. Next, the mask 17 is removed from the second main surface 22.

Next, a step of forming a gate insulating film is carried out. FIG. 18 is a cross-sectional schematic diagram showing the step of forming a gate insulating film. Specifically, the silicon carbide epitaxial substrate 200 having a trench 56 formed in the second main surface 22 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or more and 1400° C. or less. This forms a gate insulating film 115 that contacts the drift region 121 at the bottom wall surface 54, contacts each of the drift region 121, the body region 113, and the source region 114 at the side wall surface 53, and contacts each of the source region 114 and the contact region 118 at the second main surface 22.

Next, a step of forming a gate electrode is carried out. FIG. 19 is a schematic cross-sectional view showing a step of forming a gate electrode and an interlayer insulating film. The gate electrode 27 is formed inside the trench 56 so as to contact the gate insulating film 115. The gate electrode 27 is disposed inside the trench 56 and is formed on the gate insulating film 115 so as to face each of the side wall surface 53 and the bottom wall surface 54 of the trench 56. The gate electrode 27 is formed, for example, by the LPCVD (Low Pressure Chemical Vapor Deposition) method.

Next, an interlayer insulating film is formed. The interlayer insulating film 26 is formed so as to cover the gate electrode 27 and to be in contact with the gate insulating film 115. The interlayer insulating film 26 is formed, for example, by chemical vapor deposition. The interlayer insulating film 26 is composed of a material containing, for example, silicon dioxide. Next, a part of the interlayer insulating film 26 and the gate insulating film 115 is etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

Next, a process for forming a source electrode is carried out. The source electrode 16 is formed so as to contact each of the source region 114 and the contact region 118. The source electrode 16 is formed, for example, by a sputtering method. The source electrode 16 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon).

Next, alloying annealing is performed. Specifically, the source electrode 16 in contact with each of the source region 114 and the contact region 118 is held at a temperature of, for example, 900°C or higher and 1100°C or lower for about 5 minutes. As a result, at least a portion of the source electrode 16 is silicided. As a result, the source electrode 16 that forms an ohmic junction with the source region 114 is formed. Preferably, the source electrode 16 forms an ohmic junction with the contact region 118.

Next, the source wiring 19 is formed. The source wiring 19 is electrically connected to the source electrode 16. The source wiring 19 is formed so as to cover the source electrode 16 and the interlayer insulating film 26.

Next, a process for forming a drain electrode is carried out. First, the second silicon carbide substrate 24 is polished at the first main surface 21. This reduces the thickness of the second silicon carbide substrate 24. Next, the drain electrode 123 is formed. The drain electrode 123 is formed so as to be in contact with the first main surface 21. In this manner, the silicon carbide semiconductor device 400 according to this embodiment is manufactured.

FIG. 20 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device according to this embodiment. The silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The silicon carbide semiconductor device 400 mainly includes a silicon carbide epitaxial substrate 200, a gate electrode 27, a gate insulating film 115, a source electrode 16, a drain electrode 123, a source wiring 19, and an interlayer insulating film 26. The silicon carbide epitaxial substrate 200 includes a drift region 121, a body region 113, a source region 114, and a contact region 118. The silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like.

Next, the effects of the method for manufacturing the silicon carbide epitaxial substrate 200 and the method for manufacturing the silicon carbide semiconductor device 400 according to the present disclosure will be described.

When the flatness of a silicon carbide epitaxial substrate is low, exposure failure (defocus) may occur in the exposure process of the process of manufacturing a silicon carbide semiconductor device using the silicon carbide epitaxial substrate. If the proportion of areas where exposure failure occurs is high among the multiple exposure regions in the silicon carbide epitaxial substrate, the yield of silicon carbide semiconductor devices will be significantly reduced. Therefore, for silicon carbide epitaxial substrates where the proportion of exposure failures is high, reworking is required to increase the flatness of the silicon carbide epitaxial substrate. Specifically, for example, after removing the silicon carbide epitaxial layer from the silicon carbide epitaxial substrate, the silicon carbide substrate is again subjected to flattening processing such as polishing. In this case, the lead time of the manufacturing process of silicon carbide semiconductor devices will be significantly extended.

According to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, a criterion for selecting a second silicon carbide substrate 24 different from each of the multiple first silicon carbide substrates 14 is determined based on the relationship between the LTV of each of the multiple first silicon carbide substrates 14 and the LTV of each of the multiple first silicon carbide epitaxial substrates 100. By using this criterion, the LTV of the second silicon carbide epitaxial substrate can be accurately predicted based on the LTV of the second silicon carbide substrate 24.

Furthermore, according to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, the LTV of the second silicon carbide substrate 24 is measured. It is determined whether the LTV of the second silicon carbide substrate 24 satisfies the standard. As a result, even if the LTV of the second silicon carbide substrate 24 does not satisfy the standard, the second silicon carbide substrate 24 can be quickly polished or the like without removing the second silicon carbide epitaxial layer 25, thereby increasing the flatness of the second silicon carbide substrate 24. This makes it possible to prevent the lead time of the manufacturing process of the silicon carbide semiconductor device from being significantly longer.

Furthermore, according to the method for manufacturing a silicon carbide epitaxial substrate disclosed herein, a second silicon carbide epitaxial layer 25 is formed on a second silicon carbide substrate 24 that satisfies the LTV criteria. Therefore, silicon carbide epitaxial substrates with high flatness can be selected with high precision. As a result, the probability of exposure defects occurring in the manufacturing process of a silicon carbide semiconductor device can be reduced.

According to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, a criterion for selecting a second silicon carbide substrate 24 different from each of the multiple first silicon carbide substrates 14 is determined based on the relationship between the LTIR of each of the multiple first silicon carbide substrates 14 and the LTIR of each of the multiple first silicon carbide epitaxial substrates 100. By using this criterion, the LTIR of the second silicon carbide epitaxial substrate can be accurately predicted based on the LTIR of the second silicon carbide substrate 24.

Furthermore, according to the method for manufacturing a silicon carbide epitaxial substrate according to the present disclosure, the LTIR of the second silicon carbide substrate 24 is measured. It is determined whether the LTIR of the second silicon carbide substrate 24 satisfies the standard. As a result, even if the LTIR of the second silicon carbide substrate 24 does not satisfy the standard, the second silicon carbide substrate 24 can be quickly polished or the like without removing the second silicon carbide epitaxial layer 25, thereby increasing the flatness of the second silicon carbide substrate 24. This makes it possible to prevent the lead time of the manufacturing process of the silicon carbide semiconductor device from being significantly longer.

Furthermore, according to the method for manufacturing a silicon carbide epitaxial substrate disclosed herein, a second silicon carbide epitaxial layer 25 is formed on a second silicon carbide substrate 24 that satisfies the criteria for LTIR. Therefore, silicon carbide epitaxial substrates with high flatness can be selected with high precision. As a result, the probability of exposure defects occurring in the manufacturing process of a silicon carbide semiconductor device can be reduced.

The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is indicated by the claims rather than the above-described embodiments and examples, and is intended to include all modifications within the scope of the claims and meanings equivalent thereto.

Reference Signs List 7 Orientation flat 8 Arc-shaped portion 9 Outer peripheral side surface 11 Fourth main surface 12 Fifth main surface 13 Sixth main surface 14 First silicon carbide substrate 15 First silicon carbide epitaxial layer 16 Source electrode 17 Mask 19 Source wiring 21 First main surface 22 Second main surface 23 Third main surface 24 Second silicon carbide substrate 25 Second silicon carbide epitaxial layer 26 Interlayer insulating film 27 Gate electrode 50 Square region 53 Side wall surface 54 Bottom wall surface 56 Trench 100 First silicon carbide epitaxial substrate 101 First direction 102 Second direction 113 Body region 114 Source region 115 Gate insulating film 118 Contact region 121 Drift region 123 Drain electrode 200 Silicon carbide epitaxial substrate 201 Reaction chamber 202 Stage 203 Heating element 204 Quartz tube 205 Inner wall surface 207 Gas inlet 208 Gas exhaust port 209 Rotating shaft 210 Susceptor 231 First gas supply section 232 Second gas supply section 233 Third gas supply section 234 Fourth gas supply section 235 Gas supply section 241 First gas flow rate control section 242 Second gas flow rate control section 243 Third gas flow rate control section 244 Fourth gas flow rate control section 245 Control section 300 Manufacturing apparatus 400 Silicon carbide semiconductor device A Measurement surface B Adsorption surface L1 First plane L2 Second plane L3 Third plane L4 Fourth plane L5 Least squares plane P1 First lowest point P2 First highest point P3 Third lowest point P4 Fourth highest point T1 First height T2 Second height T3 Lowest point height T4 Highest point height W1 First width W2 Length

Claims (7)

Preparing a plurality of first silicon carbide substrates;
Measuring an LTV of each of the plurality of first silicon carbide substrates;
forming a first silicon carbide epitaxial layer on each of the plurality of first silicon carbide substrates to obtain a plurality of first silicon carbide epitaxial substrates;
measuring an LTV of each of the plurality of first silicon carbide epitaxial substrates;
determining a criterion for selecting a second silicon carbide substrate different from each of the plurality of first silicon carbide substrates based on a correlation between a first area ratio of a region in which the LTV of each of the plurality of first silicon carbide substrates is less than a first specific value and a second area ratio of a region in which the LTV of each of the plurality of first silicon carbide epitaxial substrates is less than a second specific value, such that the second area ratio is a predetermined value or more;
Measuring an LTV of the second silicon carbide substrate;
determining whether an LTV of the second silicon carbide substrate satisfies the criterion;
forming a second silicon carbide epitaxial layer on the second silicon carbide substrate that satisfies the criteria ;
The first area ratio is a value obtained by dividing the number of first square regions having an LTV value less than the first specific value by the number of all first square regions when a measurement surface of each of the plurality of first silicon carbide substrates is divided into a plurality of first square regions;
the second area ratio is a value obtained by dividing the number of second square regions having an LTV value less than the second specific value by the number of all second square regions when a measurement surface of each of the plurality of first silicon carbide epitaxial substrates is divided into a plurality of second square regions;
The method for manufacturing a silicon carbide epitaxial substrate , wherein the correlation is determined using a linear approximation . 2. The method for manufacturing a silicon carbide epitaxial substrate according to claim 1, wherein a length of one side of each of said plurality of first square regions and each of said plurality of second square regions is 10 mm. 3. The method for manufacturing a silicon carbide epitaxial substrate according to claim 2, wherein, in the step of determining whether or not the LTV of the second silicon carbide substrate satisfies the criterion, when the second specific value is less than 1.0 μm and the second area ratio is 90% or more, the LTV of the second silicon carbide substrate is determined to satisfy the criterion. Preparing a plurality of first silicon carbide substrates;
Measuring a LTIR of each of the plurality of first silicon carbide substrates;
forming a first silicon carbide epitaxial layer on each of the plurality of first silicon carbide substrates to obtain a plurality of first silicon carbide epitaxial substrates;
measuring the LTIR of each of the plurality of first silicon carbide epitaxial substrates;
determining a criterion for selecting a second silicon carbide substrate different from each of the plurality of first silicon carbide substrates based on a relationship between a first area ratio of a region in which the LTIR of each of the plurality of first silicon carbide substrates is less than a first specific value and a second area ratio of a region in which the LTIR of each of the plurality of first silicon carbide epitaxial substrates is less than a second specific value, such that the second area ratio is a predetermined value or more;
Measuring the LTIR of the second silicon carbide substrate;
determining whether the LTIR of the second silicon carbide substrate satisfies the criterion;
forming a second silicon carbide epitaxial layer on the second silicon carbide substrate that satisfies the criteria ;
The first area ratio is a value obtained by dividing the number of first square regions having an LTIR value less than the first specific value by the number of all first square regions when a measurement surface of each of the plurality of first silicon carbide substrates is divided into a plurality of first square regions;
the second area ratio is a value obtained by dividing the number of second square regions having an LTIR value less than the second specific value by the number of all second square regions when a measurement surface of each of the plurality of first silicon carbide epitaxial substrates is divided into a plurality of second square regions . 5. The method for manufacturing a silicon carbide epitaxial substrate according to claim 4, wherein a length of one side of each of said plurality of first square regions and each of said plurality of second square regions is 10 mm. 6. The method for manufacturing a silicon carbide epitaxial substrate according to claim 5, wherein, in the step of determining whether or not the LTIR of the second silicon carbide substrate satisfies the criterion, when the second specific value is 1.0 μm and the second area ratio is 90% or more, the LTIR of the second silicon carbide substrate is determined to satisfy the criterion. A step of preparing a silicon carbide epitaxial substrate manufactured by the method for manufacturing a silicon carbide epitaxial substrate according to any one of claims 1 to 6;
and processing the silicon carbide epitaxial substrate.

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