JP7533174B2 - Semiconductor inspection device and semiconductor chip inspection method - Google Patents

Description

This invention relates to a semiconductor inspection device and a method for inspecting semiconductor chips.

Conventionally, it is known to make semiconductor chips thinner (thinning) in order to improve the heat dissipation and reduce the resistance of semiconductor devices. Thinned semiconductor chips are thin, for example, about 200 μm thick, and warp occurs. Warping of a semiconductor chip refers to the occurrence of one or more of the following on a semiconductor chip placed on the stage of a semiconductor inspection device with one main surface facing the stage: a convex (hereinafter, convex downward) curved portion protruding in the direction toward the stage (curving direction), and a convex (hereinafter, convex upward) curved portion protruding in the direction away from the stage (curving direction). The state of warping within the surface of the semiconductor chip (curved location, curving direction, amount of warping) differs for each semiconductor chip depending on the element structure of the semiconductor device.

In addition, due to the influence of lighting, the photographed image of the main surface of the semiconductor chip shows a light and dark pattern due to the difference in gloss of the metal electrodes (gold (Au) plating) and insulating film on the main surface of the semiconductor chip, and the unevenness caused by the difference in height between the metal electrodes and the insulating film. In visual inspection of the appearance of a semiconductor chip, the entire surface of the semiconductor chip is inspected, and the parts of the main surface of the semiconductor chip that are dark due to the gloss are difficult to see. The light and dark pattern in the photographed image of the main surface of the semiconductor chip differs for each semiconductor chip depending on the element structure of the semiconductor device. For this reason, the worker tilts the semiconductor chip at various angles and adjusts the angle of illumination light on the main surface for each semiconductor chip, while suppressing the influence of the lighting in the work environment, and checks for any abnormalities in the appearance of the semiconductor chip (adhered foreign matter or scratches).

Fig. 13 is a perspective view showing a schematic example of the warping state of a thinned semiconductor chip. In Fig. 13, the unevenness of the main surface of the semiconductor chip is omitted. Figs. 14 and 15 are plan views showing schematic image data of the inspection surface of a conventional semiconductor chip. Fig. 14 shows a state in which a light and dark pattern has appeared on the inspection surface of a semiconductor chip due to the influence of lighting, caused by differences in glossiness of metal electrodes, insulating films, etc. on the inspection surface. Fig. 15 shows a state in which a light and dark pattern has appeared on the inspection surface of a semiconductor chip due to the unevenness of the inspection surface, caused by the influence of lighting. Figs. 14 (a) and (b) show the same location photographed using different types of lighting. Figs. 15 (a) and (b) show the same location photographed using different types of lighting.

When the appearance inspection of the semiconductor chip 101 is performed automatically, the main surface (hereinafter referred to as the inspection surface) of the semiconductor chip 101 is photographed by the photographing means of a semiconductor inspection device (not shown), and predetermined image processing is performed to detect appearance abnormalities of the inspection surface of the semiconductor chip 101. At this time, only the portion of the inspection surface of the semiconductor chip 101 that is approximately parallel to the stage (hereinafter referred to as the flat portion) is inspected. Even if the semiconductor chip 101 has a convex curved warp upward or downward (indicated by arrows 101a and 101b, respectively) or both (FIG. 13), the warp of the semiconductor chip 101 can be corrected by sucking the main surface (hereinafter referred to as the facing surface) of the semiconductor chip 101 that faces the stage and pressing it against the stage.

On the other hand, the parts of the inspection surface of the semiconductor chip 101 with different glossiness have different types of illumination that are easily recognized during image processing (Figure 14). It was confirmed that the image of the inspection surface of the semiconductor chip 101 captured using coaxial illumination that irradiates illumination light from a direction perpendicular to the flat part of the inspection surface of the semiconductor chip 101 is bright due to halation in the parts with high glossiness such as the metal electrodes 111, and is relatively dark in the parts with low glossiness such as the insulating films 112, 113 and the polysilicon film 114 (Figure 14(a)). On the other hand, it was confirmed that the image of the inspection surface of the semiconductor chip 101 captured using diffuse illumination that irradiates illumination light from an oblique direction to the flat part of the inspection surface of the semiconductor chip 101 has a reversed light and dark pattern compared to the case of coaxial illumination (Figure 14(b)).

As for the unevenness of the inspection surface of the semiconductor chip 101, different types of illumination are easily recognized during image processing for the concave and convex portions (Figure 15). Figure 15 shows an enlarged view of a portion of the inspection surface of the semiconductor chip 101. It was confirmed that the image of the inspection surface of the semiconductor chip 101 photographed using coaxial illumination is bright at the bottom surface 115a (concave portion) of the groove 115 such as a trench, and dark at the opening side of the groove 115 (convex portion) closer to the photographing means (Figure 15(a)). On the other hand, it was confirmed that the image of the inspection surface of the semiconductor chip 101 photographed using diffuse illumination is dark at the bottom surface 115a of the groove 115, and bright at the main surface 101c of the semiconductor chip 101 (Figure 15(b)).

A conventional semiconductor inspection device has been proposed that is made up of a rotationally driven θ stage, an X-Y stage that drives in two directions parallel to and perpendicular to the semiconductor wafer holding surface, and a Z stage that drives the X-Y stage up and down, with the upper surfaces of the θ stage and the X-Y stage serving as holding surfaces for the semiconductor wafer (see, for example, Patent Document 1 below). In Patent Document 1 below, the X-Y stage, Z stage, and θ stage are each driven independently. By independently driving the θ stage and the X-Y stage, the position of the semiconductor wafer held on the upper surface of the θ stage and the upper surface of the X-Y stage is adjusted in the rotational direction and in two directions parallel to and perpendicular to the semiconductor wafer holding surface.

JP 2014-036071 A

In the visual inspection of semiconductor chips, an optical microscope is used to check for minute appearance abnormalities of about 20 μm on the main surface of the semiconductor chip. Because semiconductor chips have warping and unevenness on their main surface, when visually inspecting semiconductor chips, workers must manually check for appearance abnormalities by repeatedly adjusting the focus and magnification of the microscope lens according to the warping and unevenness of the main surface for each semiconductor chip. This work is carried out in a clean room, and workers check each semiconductor chip one by one while wearing clean room wear (dust-free clothing) and a mask. This work is long and workers are prone to eye strain and fatigue from wearing the wear, so it places a heavy burden on workers, and there is a need to automate the visual inspection of the entire main surface of semiconductor chips.

In addition, visual inspection of semiconductor chips alone makes it difficult to check for visual abnormalities at uneven areas on the main surface of the semiconductor chip, and there is a risk that overlooking visual abnormalities will lead to a decrease in product quality. Irregularities on the main surface of a semiconductor chip are inevitable depending on the element structure of the semiconductor device, and are difficult to improve. On the other hand, the inspection accuracy of automated visual inspection of semiconductor chips using conventional technology is low. This is because even if leveling (height adjustment) is performed to adjust the height from the inspection surface of the semiconductor chip to the lens of the optical microscope, variations in the distance to the lens occur within the inspection surface of the semiconductor chip due to the inherent warping of each semiconductor chip and deformation of the semiconductor chip due to gripping during transportation.

As described above, the light and dark patterns of the captured image of the inspection surface of the semiconductor chip 101 vary depending on the condition of the inspection surface of the semiconductor chip 101 (there is a mixture of parts with different glossiness within the inspection surface of the semiconductor chip 101, there is variation in thickness within the surface of the semiconductor chip 101 and unevenness on the inspection surface, and the curved location, curvature direction, and amount of warping differ for each semiconductor chip 101) and the type of illumination used to capture the inspection surface of the semiconductor chip 101 (see Figures 14 and 15). However, with conventional technology, when the appearance inspection of the semiconductor chip 101 is automated, it is not possible to adjust the irradiation angle of the illumination light onto the inspection surface of the semiconductor chip 101. As a result, the inspection accuracy is reduced in areas where it is difficult to recognize the image of the inspection surface of the semiconductor chip 101.

The purpose of this invention is to provide a semiconductor inspection device and a semiconductor chip inspection method that can achieve stable inspection accuracy in order to solve the problems associated with the conventional technology described above.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor inspection device according to the present invention comprises a stage, a plurality of hollow suction means, an imaging means, a calculation means, a correction means, and an inspection means, and has the following features. A semiconductor chip is placed on the stage. The suction means adsorbs the first main surface of the semiconductor chip facing the stage, and holds the semiconductor chip on the first surface side of the stage. The imaging means images the second main surface of the semiconductor chip opposite the stage side. The calculation means digitizes the state of warping within the surface of the semiconductor chip based on image data of the second main surface of the semiconductor chip photographed by the imaging means. The correction means corrects the warping of the semiconductor chip based on the state of warping of the semiconductor chip digitized by the calculation means. The inspection means inspects the appearance abnormality of the second main surface of the semiconductor chip in a state in which the warping has been corrected by the correction means. The suction means also functions as the correction means. By sucking the suction means to suck the gas between the semiconductor chip and the suction means, an external force is applied directly or indirectly to a portion of the semiconductor chip, and the warping of the semiconductor chip is corrected.

In addition, in the semiconductor inspection device according to the present invention, in the above-mentioned invention, the suction means is supported in a state in which it can be moved vertically. After placing the semiconductor chip before the warpage is corrected on the suction means, all of the suction means are individually moved vertically to contact the first main surface of the semiconductor chip based on the warpage state of the semiconductor chip quantified by the calculation means, and then all of the suction means are sucked in to adsorb the semiconductor chip to the first main surface. Then, based on the warpage state of the semiconductor chip quantified by the calculation means, the suction means with the semiconductor chip adsorbed are individually moved vertically to apply an external force directly to a portion of the semiconductor chip, thereby controlling the correction of the warpage of the semiconductor chip.

In addition, in the semiconductor inspection device according to the present invention, in the above-mentioned invention, the suction means is supported in a state in which it can be moved in the vertical direction. The upper ends of all of the suction means are located at the same height. After the semiconductor chip before warping is corrected is placed on the suction means, one or more of the suction means are individually moved in the vertical direction based on the state of warping of the semiconductor chip quantified by the calculation means, and the distance from the suction means to the first main surface of the semiconductor chip is changed. Then, all of the suction means are sucked in to suck the semiconductor chip, and an external force is indirectly applied partially to the semiconductor chip, thereby controlling the warping of the semiconductor chip to be corrected.

In the semiconductor inspection device according to the present invention, in the above-mentioned invention, the suction means is supported in a state in which it can be moved horizontally. The upper ends of all of the suction means are located at the same height. The semiconductor chip before the warpage is corrected is placed on the suction means, and then one or more of the suction means are moved horizontally to a position facing a predetermined location on the first main surface of the semiconductor chip based on the state of the warpage of the semiconductor chip quantified by the calculation means. Then, all of the suction means are sucked in to suck the semiconductor chip, thereby applying an external force indirectly to a part of the semiconductor chip, thereby controlling the warpage of the semiconductor chip to be corrected.

In addition, in the semiconductor inspection device according to the present invention, in the above-mentioned invention, the stage also functions as the correction means and has a plurality of through holes. The suction means is supported in a state in which it can move vertically, and passes through the through holes of the stage. After the semiconductor chip before the warpage is corrected is placed on the suction means, all of the suction means are individually moved vertically based on the warpage state of the semiconductor chip quantified by the calculation means to contact the first main surface of the semiconductor chip, and then all of the suction means are sucked in to adsorb the first main surface of the semiconductor chip. Then, the suction means with the semiconductor chip adsorbed is moved vertically to press the first main surface of the semiconductor chip against the first surface of the stage, thereby applying an external force directly to a portion of the semiconductor chip, and controlling the correction of the warpage of the semiconductor chip.

In addition, in the semiconductor inspection device according to the present invention, in the above-mentioned invention, the suction means is supported in a state in which it can move vertically and in a rotational direction around its own central axis. After placing the semiconductor chip before warping correction on the suction means, based on the state of warping of the semiconductor chip quantified by the calculation means, all of the suction means are individually moved in the vertical direction to contact the first main surface of the semiconductor chip, and then all of the suction means are sucked in to adsorb to the first main surface of the semiconductor chip. Then, based on the state of warping of the semiconductor chip quantified by the calculation means, the suction means with the semiconductor chip adsorbed are individually moved in the rotational direction to apply an external force directly to part of the semiconductor chip, thereby controlling the correction of the warping of the semiconductor chip.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor chip inspection method of the present invention uses a semiconductor inspection device including a stage for placing a semiconductor chip, a plurality of hollow suction means for suctioning the first main surface of the semiconductor chip, an imaging means for imaging the second main surface of the semiconductor chip, a calculation means for quantifying the state of warpage within the surface of the semiconductor chip, a correction means for correcting the warpage of the semiconductor chip, and an inspection means for inspecting the second main surface of the semiconductor chip for visual abnormalities, and has the following features: A first step is performed in which the semiconductor chip is placed and held on the suction means on the first surface side of the stage with the first main surface facing the stage. A second step is performed in which the imaging means images the second main surface of the semiconductor chip opposite the stage side.

A third step is performed in which the calculation means quantifies the state of warpage within the plane of the semiconductor chip based on image data of the second main surface of the semiconductor chip photographed by the photographing means. A fourth step is performed in which the correction means corrects the warpage of the semiconductor chip based on the state of warpage of the semiconductor chip quantified by the calculation means. A fifth step is performed in which the inspection means inspects the second main surface of the semiconductor chip for visual abnormalities in a state in which the warpage has been corrected by the correction means. The suction means also functions as the correction means. In the fourth step, the suction means is sucked in to suck in the gas between the semiconductor chip and the suction means, thereby applying an external force directly or indirectly to a portion of the semiconductor chip to correct the warpage of the semiconductor chip.

According to the above-mentioned invention, the influence of warping of the semiconductor chip on the pattern recognition of the captured image of the inspection surface (second main surface) of the semiconductor chip can be suppressed, thereby stabilizing the pattern recognition of the inspection surface of the semiconductor chip.

The semiconductor inspection device and semiconductor chip inspection method of the present invention have the effect of providing stable inspection accuracy for thin semiconductor chips that have minute irregularities on their main surfaces due to metal electrodes, etc.

1 is a cross-sectional view showing a structure of a semiconductor inspection device according to a first embodiment; 2 is an explanatory diagram showing a part of the structure of the correction mechanism of FIG. 1; FIG. 1 is a cross-sectional view showing a schematic state in the middle of correcting a warpage of a semiconductor chip by the semiconductor inspection device according to the first embodiment; 1 is a flowchart showing an outline of a semiconductor chip inspection method according to a first embodiment; FIG. 11 is a cross-sectional view showing a structure of a semiconductor inspection device according to a second embodiment. FIG. 11 is a cross-sectional view showing a structure of a semiconductor inspection device according to a third embodiment. 13 is a cross-sectional view showing a schematic state in the middle of correcting a warpage of a semiconductor chip by the semiconductor inspection device according to the third embodiment; FIG. FIG. 11 is a cross-sectional view showing a structure of a semiconductor inspection device according to a fourth embodiment. FIG. 11 is a cross-sectional view showing a structure of a semiconductor inspection device according to a fourth embodiment. FIG. 2 is a cross-sectional view showing a schematic structure of the correction mechanism of FIG. 1 . FIG. 13 is a cross-sectional view showing a schematic diagram of a correction mechanism of a semiconductor inspection apparatus according to a sixth embodiment. FIG. 12 is a perspective view showing a part of the correction mechanism of FIG. 11 . 1 is a perspective view showing an example of a warped state of a thinned semiconductor chip; FIG. FIG. 11 is a plan view that illustrates a schematic diagram of photographed image data of an inspection surface of a conventional semiconductor chip. FIG. 11 is a plan view that illustrates a schematic diagram of photographed image data of an inspection surface of a conventional semiconductor chip.

Below, a preferred embodiment of the semiconductor inspection device and semiconductor chip inspection method according to the present invention will be described in detail with reference to the attached drawings. Note that in the following description of the embodiment and the attached drawings, similar configurations are given the same reference numerals and duplicated explanations will be omitted.

(Embodiment 1)
The structure of the semiconductor inspection device according to the first embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of the semiconductor inspection device according to the first embodiment. FIG. 2 is an explanatory diagram showing a part of the structure of the correction mechanism in FIG. 1. (a) to (c) of FIG. 2 are a plan view showing the state of the semiconductor chip 1 before the warpage is corrected from the inspection surface (second main surface) 1a side, a cross-sectional view showing the cross-sectional shape of the semiconductor chip 1 before the warpage is corrected, and a cross-sectional view showing the state of the semiconductor chip 40 after the warpage is corrected by the correction mechanism (correction means) 24 (the same applies to (a) to (c) of FIG. 5 to 7, 9, and 19). FIG. 3 is a cross-sectional view showing a schematic state of the semiconductor chip during the warpage correction by the semiconductor inspection device according to the first embodiment.

The semiconductor inspection device 10 according to the first embodiment shown in FIG. 1 is an optical microscope that automatically detects the presence or absence of visual abnormalities (such as foreign matter or scratches) in the semiconductor chip 1, and has a stage 11, a lens 12, first and second lights 13 and 14, an imaging means 15, an image recognition means 21, a calculation means 22, an actuator 23, a correction mechanism 24, a posture control mechanism 25, and a control means 26. A predetermined element structure of a semiconductor device is formed in the semiconductor chip 1. On at least one main surface of the semiconductor chip 1, various parts (metal electrodes, insulating films, polysilicon films, etc.: not shown) that constitute the element structure are formed, and unevenness is generated by the various parts with different height differences.

The semiconductor chip 1 is thinned to a thickness (e.g., about 200 μm) according to the on-resistance and withstand voltage of the semiconductor device, and warping occurs. The warping of the semiconductor chip 1 means that there is one or more convex (upwardly convex) curved portions (curved portions) protruding in the vertical direction Z1 (curved direction) away from the stage 11, and/or one or more convex (downwardly convex) curved portions (curved portions) protruding in the vertical direction Z2 (curved direction) toward the stage 11 on the semiconductor chip 1 on the stage 11. The state of warping within the plane of the semiconductor chip 1 (curved portions, curvature direction, amount of warping) differs for each semiconductor chip 1 depending on the element structure of the semiconductor device.

The semiconductor chip 1 is transported to the upper surface (first surface) of the stage 11 by a transport means not shown, and the main surface (opposing surface: first main surface) 1b facing the stage 11 is sucked and held by the upper end of a suction nozzle 31 described later. The stage 11 is a flat base with a planar shape, for example, a substantially rectangular shape, with dimensions equal to or larger than the outer dimensions of the semiconductor chip 1, and is supported in a state in which it can move in vertical directions (up and down directions) Z1 and Z2 (in a direction approaching the lens 12 and in a direction away from the lens 12). The stage 11 may be supported in a state in which it can rotate in rotation directions Rx and Ry about rotation axes parallel to horizontal directions X and Y that are perpendicular to the vertical directions Z1 and Z2 and perpendicular to each other.

The stage 11 has a number of through holes 11a (see FIG. 10, not shown in FIG. 3) that are spaced apart from each other and penetrate between both surfaces. The number of through holes 11a in the stage 11 is the same as the number of suction nozzles 31, and they are arranged at approximately equal intervals. A different suction nozzle 31 penetrates each through hole 11a of the stage 11, and one end (upper end) of the suction nozzle 31 protrudes upward from the top surface of the stage 11. The through holes 11a in the stage 11 may have any dimension that does not impede the movement of the suction nozzle 31 in the vertical directions Z1 and Z2, and have, for example, a substantially circular planar shape with a diameter larger than the diameter (diameter) of the piping 32 of the suction nozzle 31.

The lens 12 is disposed above the stage 11 and faces the principal surfaces (inspection surfaces) 1a, 40a on the opposite side to the opposing surfaces 1b, 40b of the semiconductor chips 1, 40 held on the upper surface of the stage 11. The lens 12 has the function of magnifying the transmitted light and reflected light of the illumination light irradiated onto the principal surfaces of the semiconductor chips 1, 40 from either the first or second illumination 13, 14. The focus adjustment (adjustment to focus) of the lens 12 is performed by moving the stage 11 in the vertical directions Z1, Z2 to adjust the height position of the inspection surfaces 1a, 40a of the semiconductor chips 1, 40 to a height position where the edge strength of the inspection surfaces 1a, 40a of the semiconductor chips 1, 40 is equal to or greater than a predetermined value.

The focus of the lens 12 is adjusted so that the lens 12 is focused on the flat surface of the semiconductor chip (surface perpendicular to the vertical directions Z1, Z2). Each time the height position of the inspection surface 1a, 40a of the semiconductor chip 1, 40 is changed, the inspection surface 1a, 40a of the semiconductor chip 1, 40 is photographed by the photographing means 15, and the edge strength of the inspection surface 1a, 40a is repeatedly calculated by the image recognition means 21 and the calculation means 22 based on the photographed image data. The height range in which the edge strength of the flat surface of the inspection surface 1a, 40a of the semiconductor chip 1, 40 is equal to or greater than a predetermined value is the range in which the lens 12 appears to be in focus (the depth of field of the lens 12).

The depth of field of the lens 12 can be set according to the parameters (allowable circle of confusion) related to the imaging means 15, the aperture, the focal length, and the distance between the lens 12 and the flat surface of the inspection surface 1a, 40a of the semiconductor chip 1, 40. The element structure of the part of the inspection surface 1a, 40a of the semiconductor chip 1, 40 that is within the depth of field of the lens 12 is clearly photographed. Since the inspection surface 40a of the semiconductor chip 40 in a state where the warp has been corrected is substantially flat over the entire surface, the lens 12 can be focused on substantially the entire surface of the inspection surface 40a by adjusting the focus of the lens 12. On the other hand, within the inspection surface 1a of the semiconductor chip 1 before the warp is corrected, there are curved parts (arc-shaped curved parts) where the lens 12 cannot be focused even after the focus adjustment of the lens 12.

Therefore, by utilizing the focus adjustment of the lens 12, the three-dimensional in-plane warping state (coordinates of the curved points (position and curvature range in the horizontal directions X, Y and vertical directions Z1, Z2), curvature direction of each curved point (vertical directions Z1, Z2), and amount of warping of each curved point (arrow height of each curved point)) of the semiconductor chip 1 before the warping is corrected is quantified and obtained. Specifically, the stage 11 is moved in the vertical directions Z1, Z2 to change the height position of the inspection surface 1a of the semiconductor chip 1, and the areas that were not in focus during the first lens focus adjustment are photographed at multiple different height positions by the imaging means 15.

The part that was not in focus during this first focus adjustment of the lens 12 is the curved part of the semiconductor chip 1 as described above, and the curvature direction of the curved part of the semiconductor chip 1 can be obtained from the moving direction of the stage 11 in the vertical directions Z1 and Z2 at this time. Specifically, the focus adjustment of the lens 12 is performed again at the part where the lens 12 was not in focus. At this time, the semiconductor chip 1 is curved convexly downward (vertical direction Z2) at the part where the lens 12 was in focus due to the movement of the stage 11 upward (vertical direction Z1), and is curved convexly upward at the part where the lens 12 was in focus due to the movement of the stage 11 downward.

Then, the image recognition means 21 and the calculation means 22 calculate the edge strength of each of the multiple image data captured by the imaging means 15, and calculate the amount of change in edge strength at the point where the focus was not achieved in the first focus adjustment of the lens 12 based on the edge strength of all the image data. From this amount of change in edge strength, the coordinates and amount of warping of the curved point of the semiconductor chip 1 can be obtained. In this way, the three-dimensional warping state of the semiconductor chip 1 can be obtained in advance, so that the warping of the semiconductor chip 1 can be corrected based on the three-dimensional warping state of the semiconductor chip 1 before performing an appearance inspection of the semiconductor chip 1.

The first illuminator 13 is a general coaxial illuminator that irradiates illumination light from a direction approximately perpendicular to the inspection surfaces 1a, 40a of the semiconductor chips 1, 40. The first illuminator 13 is disposed within the optical path of the lens 12 (e.g., between the photographing means 15 and the lens 12). The second illuminator 14 is a general diffuse illuminator that irradiates illumination light from an oblique direction to the inspection surfaces 1a, 40a of the semiconductor chips 1, 40. The second illuminator 14 is disposed between the photographing means 15 and the semiconductor chips 1, 40. The first and second illuminators 13, 14 are appropriately selected according to the material and unevenness of each part of the surface of the object (subject) photographed by the photographing means 15.

The photographing means 15 photographs a subject magnified through the lens 12. The subjects of the photographing means 15 are the inspection surface 1a of the semiconductor chip 1 before warping is corrected, and the inspection surface 40a of the semiconductor chip 40 after warping has been corrected. The image data photographed by the photographing means 15 is stored in a memory unit (not shown) and then output appropriately from the memory unit to the image recognition means 21, or output directly to the image recognition means 21. The image recognition means 21 has a function of performing pattern recognition on the image data photographed by the photographing means 15. Pattern recognition refers to extracting the characteristics of the image data (shape, size, number, brightness, color, etc.).

The calculation means 22 calculates the edge strength (height of surface irregularities) of the inspection surfaces 1a, 40a of the semiconductor chips 1, 40 from the difference (difference in brightness or color intensity between adjacent pixels) of the same features of the image data pattern-recognized by the image recognition means 21. The calculation means 22 acquires the curved location, curve direction, and amount of warping based on the calculated edge strength for the inspection surface 1a of the semiconductor chip 1 before the warping is corrected. The calculation means 22 also determines the presence or absence of visual abnormalities for the inspection surface 40a of the semiconductor chip 40 after the warping has been corrected based on the calculated edge strength, comparing it with previously acquired information on a normal state when no visual abnormalities have occurred (inspection means).

The actuator 23 has the function of moving the stage 11 in the vertical directions Z1 and Z2. The actuator 23 can move the entire stage 11 in the vertical directions Z1 and Z2 to change the height position of the top surface of the stage 11. By changing the height position of the top surface of the stage 11, the focal length of the lens 12 with respect to the inspection surfaces 1a and 40a of the semiconductor chips 1 and 40 on the top surface of the stage 11 can be adjusted. The actuator 23 is provided independently from the correction mechanism 24 in a position that does not interfere with the operation of the correction mechanism 24 (the operation of moving the suction nozzle 31 described later in the vertical directions Z1 and Z2).

The correction mechanism 24 has a plurality of suction nozzles 31. The suction nozzle 31 is a jig that suctions and holds the opposing surfaces 1b, 40b of the semiconductor chips 1, 40 on the upper surface side of the stage 11, and also functions as a correction means for correcting the warpage of the semiconductor chip 1. The suction nozzle 31 is composed of a hollow, circular, rod-shaped (cylindrical) pipe 32 and a suction pad 33 provided at one end of the pipe 32. The other end of the pipe 32 of the suction nozzle 31 is connected to an external suction device (e.g., a vacuum pump: not shown). The pipes 32 of all the suction nozzles 31 may be connected to one suction device, or the pipes 32 of each suction nozzle 31 may be connected to different suction devices.

The piping 32 of each suction nozzle 31 is arranged to pass through a different through hole 11a of the stage 11, and is supported so that each can move individually in the vertical directions Z1 and Z2. The piping 32 of all suction nozzles 31 moves in the vertical directions Z1 and Z2 by the same distance as the stage 11 in conjunction with the movement of the stage 11 in the vertical directions Z1 and Z2. The suction pad 33 is provided at the upper end of the piping 32 of the suction nozzle 31. The height position of the suction pad 33 of the suction nozzle 31 is a position away from the top surface of the stage 11 in the vertical direction Z1, even when the suction nozzle 31 is moved in the vertical directions Z1 and Z2, and is not in contact with the stage 11.

The semiconductor chips 1, 40 are placed on the upper surface of the stage 11 by being sucked and held by the suction pads 33 of the suction nozzles 31. The initial settings of the suction pads 33 of the suction nozzles 31 are the same for all suction nozzles 31. All suction nozzles 31 are returned to the same height position before visual inspection of the next semiconductor chip 1. When the semiconductor chip 1 transported onto the upper surface of the stage 11 is held by the suction nozzles 31, first, the suction pads 33 of all suction nozzles 31 are brought into contact with the facing surface 1b of the semiconductor chip 1. At this time, there are suction nozzles 31 that are not in contact with the facing surface 1b of the semiconductor chip 1 before the warpage is corrected.

Then, the pipes 32 of each suction nozzle 31 are individually moved in the vertical directions Z1 and Z2 to adjust the height position of the suction pads 33 for each suction nozzle 31, and the suction pads 33 of all suction nozzles 31 are brought into contact with the facing surface 1b of the semiconductor chip 1 before the warp is corrected. After that, the atmosphere (air) inside the pipes 32 of the suction nozzles 31 is sucked in (the air flow during suction is shown by thin downward arrows in Figure 2), and all the suction pads 33 are sucked into the facing surface 1b of the semiconductor chip 1. In this way, the semiconductor chip 1 is sucked and held by all the suction nozzles 31. The amount of air sucked in by the suction nozzles 31 is, for example, the same for all the suction nozzles 31.

With the semiconductor chip 1 being sucked and held by all of the suction nozzles 31, the suction nozzles 31 are individually moved in either the vertical direction Z1 or Z2 to align the suction pads 33 of all of the suction nozzles 31 at approximately the same height. This causes an external force (pulling force 41 and pushing force 42, described below) from the suction nozzles 31 to be directly applied to the semiconductor chip 1 in a direction that flattens the semiconductor chip 1 over its entirety, correcting any warping of the semiconductor chip 1. For example, the suction nozzle 31 that sucks the part of the semiconductor chip 1 furthest from the stage 11 in the vertical direction Z1 (hereinafter referred to as the suction nozzle 31 at the reference height) is not moved and maintains its height position or is pulled downward.

The remaining suction nozzles 31, except for the suction nozzle 31 at the reference height, are moved upward to raise the height position of their own suction pads 33 to the same height position as the suction pads 33 of the suction nozzle 31 at the reference height. As a result, a pulling force 41 that pulls the semiconductor chip 1 downward is generated in the portion of the semiconductor chip 1 that is suctioned by the suction nozzle 31 at the reference height. Furthermore, each suction nozzle 31 is pressed against the portion of the semiconductor chip 1 that is suctioned by the remaining suction nozzles 31, except for the suction nozzle 31 at the reference height, and a force 42 that pushes the semiconductor chip 1 upward is generated with a magnitude according to the amount of movement of each suction nozzle 31 (hereinafter referred to as a pushing force).

For example, when the semiconductor chip 1 protrudes most downward in a convex shape at the center (FIG. 2(b), left diagram of FIG. 3), the vicinity of the end of the facing surface 1b of the semiconductor chip 1 is the portion furthest from the stage 11 in the vertical direction Z1. Therefore, when suction nozzles 31 are arranged at five locations in total, at the center and near the four vertices of the semiconductor chip 1 having a roughly rectangular planar shape (FIG. 2(a)), a pushing force 42 is applied to the center of the semiconductor chip 1 by moving the suction nozzle 31 that suctions the center of the semiconductor chip 1 upward. A pulling force 41 can be applied to the vicinity of the four vertices of the semiconductor chip 1 without moving the suction nozzle 31 that suctions the vicinity of the four vertices of the semiconductor chip 1.

In this way, by individually moving the specified suction nozzles 31 of the correction mechanism 24 (24a) in either the vertical direction Z1 or Z2 depending on the warpage of the semiconductor chip 1 and applying a pulling force 41 and a pushing force 42 to the semiconductor chip 1, it is possible to obtain a semiconductor chip 40 that has been corrected to be substantially flat over the entire surface (FIG. 2(c), right diagram of FIG. 3). When the semiconductor chip 40 is substantially flat after the warpage has been corrected, this means that the absolute value of the amount of warpage at each curved point within the plane of the main surface of the semiconductor chip 40 is 0 mm or more and approximately 1/100 or less of the short side of the semiconductor chip 40. The amount of warpage of the semiconductor chip 40 is the arrow height of each curved point of the semiconductor chip 40.

The individual movement amount (pressure and movement distance) of each suction nozzle 31 should be set so that the external force (stress: tensile force 41 and upward force 42) applied to the semiconductor chip 1 is minimized when the individual movement amounts of all the suction nozzles 31 are considered together. This is because if the external force applied to the semiconductor chip 1 is large, there is a risk that the semiconductor chip 1 may crack or that suction marks of the suction nozzle 31 may be formed. The piping 32 and suction pad 33 of the suction nozzle 31 are made of materials that can be used in clean rooms. Specifically, the piping 32 is made of polyurethane, for example. The suction pad 33 is made of an elastic material such as nitrile rubber that is unlikely to leave suction marks on the semiconductor chips 1, 40.

As described above, the suction nozzles 31 can move individually in the vertical directions Z1 and Z2, and can move in the vertical directions Z1 and Z2 the same distance as the stage 11 in conjunction with the movement of the stage 11 in the vertical directions Z1 and Z2. Therefore, instead of a configuration in which the suction nozzles 31 pass through the through holes 11a of the stage 11, a configuration in which all the suction nozzles 31 are disposed between the stage 11 and the second illumination 14 may be used.

Instead of moving the stage 11 in the vertical directions Z1 and Z2 by the actuator 23, all of the suction nozzles 31 that suction the semiconductor chip 40 may be moved the same distance upward or downward while maintaining the flatness of the semiconductor chip 40, to adjust the focal length of the lens 12 relative to the inspection surface 40a of the semiconductor chip 40. Also, instead of correcting the warpage of the inspection surface 1a of the semiconductor chip 1, each suction nozzle 31 may be moved individually in the vertical directions Z1 and Z2 based on the previously acquired state of the warpage of the semiconductor chip 1, to intentionally tilt the angle of each predetermined point on the inspection surface 1a of the semiconductor chip 1 individually.

By intentionally tilting the angles of specific locations on the inspection surface 1a of the semiconductor chip 1 individually, for example, the irradiation angle of the illumination light from the first and second lights 13 and 14 on the specific locations can be adjusted individually for each specific location. As described above, in visually inspecting the appearance of semiconductor chips, an operator tilts the semiconductor chips at various angles and adjusts the irradiation angle of the illumination light on the main surface for each semiconductor chip to suppress the influence of the lighting in the work environment. For this reason, in this embodiment, by intentionally tilting the angles of each specific location on the inspection surface 1a of the semiconductor chip 1 individually, it is possible to automatically perform an appearance inspection to the same extent as an appearance inspection performed by an operator visually.

In addition, when obtaining the state of the warpage of the semiconductor chip 1 before the warpage is corrected (curved location, curvature direction, amount of warpage), when adjusting the focus of the lens 12 on the semiconductor chip 1, a specific suction nozzle 31 may be moved upwards individually to individually push up the curved locations on the inspection surface 1a of the semiconductor chip 1. In this case, instead of changing the overall height position of the semiconductor chip 1 by moving the stage 11 in the vertical directions Z1 and Z2, the suction nozzle 31 can be used to individually push up each curved location on the inspection surface 1a of the semiconductor chip 1, and the curvature direction and amount of warpage can be obtained for each curved location.

The attitude control mechanism 25 has the function of moving the stage 11 in rotation directions Rx and Ry about rotation axes that pass through the center of the stage 11 and are parallel to the upper surface of the stage 11 and are parallel to two directions X and Y that are perpendicular to each other. The attitude control mechanism 25 can tilt the entire upper surface of the stage 11 at a predetermined angle in one of the rotation directions Rx and Ry, or tilt it at a predetermined angle in each of the rotation directions Rx and Ry. This makes it possible to tilt the entire inspection surfaces 1a and 40a of the semiconductor chips 1 and 40 held on the upper surface side of the stage 11 with respect to the optical path of the lens 12. The attitude control mechanism 25 does not have to be provided.

The control means 26 controls the stage 11, the lens 12, the first and second lights 13, 14, the imaging means 15, the image recognition means 21, the calculation means 22, the actuator 23, the correction mechanism 24, the attitude control mechanism 25, the transport means, and the like. The method for inspecting semiconductor devices (semiconductor chips) according to this embodiment can be realized by executing a prepared program on a computer such as a personal computer or a workstation, a database server, or a web server. The information obtained by the imaging means 15, the image recognition means 21, and the calculation means 22 is stored in a memory unit (not shown).

The program for implementing the semiconductor chip inspection method according to this embodiment is recorded on a computer-readable recording medium such as a solid state drive (SSD), a hard disk, a Blu-ray (registered trademark) Disc (BD), a flexible disk, a USB flash memory, a CD-ROM, an MO, or a DVD, and is executed by being read from the recording medium by a computer or a server. This program may also be a transmission medium that can be distributed via a network such as the Internet.

The method of inspecting the semiconductor chip 1 according to the first embodiment will be described. FIG. 4 is a flow chart showing an outline of the method of inspecting the semiconductor chip according to the first embodiment. First, the semiconductor chip 1 before warping is corrected is placed on the suction pad 33 of the suction nozzle 31 on the upper surface side of the stage 11 of the semiconductor inspection device 10 according to the first embodiment (see FIGS. 1 to 3) (step S1). At this stage, the suction pads 33 of all the suction nozzles 31 are at the same height position (for example, the height position by the initial setting), so there are suction nozzles 31 that are not in contact with the facing surface 1b of the semiconductor chip 1 before warping is corrected (left diagram of FIG. 3).

Next, the inspection surface 1a of the semiconductor chip 1 before the warpage is corrected is photographed by the photographing means 15, and based on the image data photographed by the photographing means 15, the edge strength of the entire inspection surface 1a of the semiconductor chip 1 is calculated using the image recognition means 21 and the calculation means 22 (step S2). In the processing of step S2, the points where the edge strength is less than the predetermined value are curved points where the lens 12 was not in focus. Next, the edge strength is calculated at a plurality of predetermined points within the points where the edge strength is less than the predetermined value in step S2 (step S3). The method of calculating the edge strength in the processing of step S3 is the same as in step S2.

Next, while moving the stage 11 in the vertical directions Z1 and Z2, the edge strength is calculated at the same locations as in step S3 at multiple different height positions (step S4). The method of calculating the edge strength in the processing of step S4 is the same as in step S2. Next, based on the edge strengths obtained in steps S3 and S4, the amount of change in edge strength at the curved location on the inspection surface 1a of the semiconductor chip 1 is calculated (step S5). Next, the three-dimensional state of warping within the surface of the semiconductor chip 1 is obtained from the amount of change in edge strength calculated in step S5 and the moving direction of the stage 11 in the processing of step S4 (step S6).

Next, the amount of warpage correction of the semiconductor chip 1 is calculated based on the three-dimensional warpage state within the plane of the semiconductor chip 1 acquired in step S6 (step S7). The amount of warpage correction of the semiconductor chip 1 is the distance in the vertical direction Z2 from the opposing surface 1b of the semiconductor chip 1 to the suction pad 33 of the suction nozzle 31. Next, each suction nozzle 31 is moved individually in either the vertical direction Z1 or Z2 according to the amount of warpage correction of the semiconductor chip 1 calculated in step S7, and the suction pads 33 of all the suction nozzles 31 are brought into contact with the opposing surface 1b of the semiconductor chip 1. Next, air is sucked into the piping 32 of the suction nozzle 31, and all the suction pads 33 are sucked onto the opposing surface 1b of the semiconductor chip 1.

Next, the predetermined suction nozzles 31 are individually moved in either the vertical direction Z1 or Z2 (upward arrow 43 and downward arrow 44) according to the amount of correction of the warpage of the semiconductor chip 1 calculated in step S7, and an external force (a pulling force 41 and a pushing force 42, described later) is applied to the semiconductor chip 1 in a direction to flatten the semiconductor chip 1 over its entirety (step S8: center diagram of FIG. 3). In this way, by moving the predetermined suction nozzles 31 in either the vertical direction Z1 or Z2 according to the warpage of the semiconductor chip 1, a semiconductor chip 40 that has been corrected to be substantially flat over its entirety can be obtained (right diagram of FIG. 3).

Next, an appearance inspection of the inspection surface 40a of the semiconductor chip 40 in a state where the warpage has been corrected is performed (step S9). During the processing of step S9, since the semiconductor chip 40 has been corrected to be substantially flat over substantially the entirety, the lens 12 can be focused on substantially the entirety of the inspection surface 40a of the semiconductor chip 40. Therefore, the photographing means 15 clearly photographs the difference in shading (light and dark) due to the difference in glossiness of the element structure and unevenness, etc., over substantially the entirety of the inspection surface 40a of the semiconductor chip 40. The calculation means 22 calculates the edge intensity over substantially the entirety of the inspection surface 40a of the semiconductor chip 40 based on the clear image data of the shading differences that have been pattern-recognized.

Then, the calculation means 22 compares the edge strength of the inspection surface 40a of the semiconductor chip 40 calculated based on the image data with clear shading differences with the edge strength of the same location on the same main surface of the semiconductor chip when it is normal and there are no appearance abnormalities (foreign matter or scratches) that have been acquired in advance. The calculation means 22 determines that an appearance abnormality has occurred in the semiconductor chip 40 when there is a location where the edge strength differs between the inspection target and the comparison target. By performing these steps S1 to S9 on each semiconductor chip 1 one by one, the appearance inspection of the inspection surface 1a of the semiconductor chip 1 (the inspection surface 40a of the semiconductor chip 40 whose warpage has been corrected) is completed.

The inventors have confirmed that the possible warpage state of the semiconductor chip 1 is determined according to the element structure of the semiconductor chip 1. By acquiring the three-dimensional warpage state of the semiconductor chip 1 (the tendency of the edge strength of the inspection surface 1a of the semiconductor chip 1) in advance, the correction amount of the warpage of the semiconductor chip 1 can be acquired in advance. Therefore, when performing visual inspection of multiple semiconductor chips 1 having the same element structure, the processing of steps S2 to S7 (calculating the edge strength of the inspection surface 1a of the semiconductor chip 1 and calculating the correction amount of the warpage of the semiconductor chip 1 based on this calculation result) may be omitted for the visual inspection of the second and subsequent semiconductor chips 1.

As described above, according to the first embodiment, the suction means for suctioning and holding the semiconductor chip also functions as a correction means for correcting the warpage of the semiconductor chip. Therefore, by sucking air into the suction means, an external force can be applied directly to part of the semiconductor chip in a direction to flatten the semiconductor chip, and visual inspection of the semiconductor chip can be performed with the warpage of the semiconductor chip corrected. This makes it possible to suppress the effect of the warpage of the semiconductor chip on the pattern recognition of the captured image of the inspection surface of the semiconductor chip, thereby stabilizing the pattern recognition of the inspection surface of the semiconductor chip and automating the visual inspection of the semiconductor chip.

(Embodiment 2)
Next, the structure of the semiconductor inspection device according to the second embodiment will be described. Fig. 5 is a cross-sectional view showing the structure of the semiconductor inspection device according to the second embodiment. The overall configuration of the semiconductor inspection device according to the second embodiment is the same as that of Fig. 1. Fig. 5 shows a schematic view of a part of the structure of the correction mechanism 24 of Fig. 1. The semiconductor inspection device according to the second embodiment differs from the semiconductor inspection device 10 (see Fig. 2) according to the first embodiment in that the warpage of the semiconductor chip 2 is corrected only by the suction force of the suction nozzle 31. The number of suction nozzles 31 of the correction mechanism 24 (24b) of the second embodiment is greater than the number of suction nozzles 31 of the correction mechanism 24a (Fig. 2) of the first embodiment.

In the second embodiment, among the multiple suction nozzles 31 constituting the correction mechanism 24b, the number of first suction nozzles 31a (31) that suction the semiconductor chip 2 is adjusted according to the state of warping of the semiconductor chip 2. For example, one or more suction nozzles 31 facing the most downwardly convexly curved portion (the portion toward the right in FIG. 5(b)) within the surface of the semiconductor chip 2 and one or more suction nozzles 31 facing the most upwardly convexly curved portion (the portion toward the left in FIG. 5(b)) are set as the first suction nozzles 31a that suction the semiconductor chip 2. All the first suction nozzles 31a have the same height position of the suction pads 33 from the top surface of the stage 11.

When the semiconductor chip 2 before warping is corrected is placed on the suction pad 33 of the first suction nozzle 31a, the distance in the vertical direction Z2 from the opposing surface 2b of the semiconductor chip 2 to the suction pad 33 of the first suction nozzle 31a varies depending on the state of warping of the semiconductor chip 2, and there are first suction nozzles 31a that are not in contact with the opposing surface 2b of the semiconductor chip 2. Of the multiple suction nozzles 31 that make up the correction mechanism 24b, the remaining second suction nozzles 31b (31) other than the first suction nozzle 31a set the height position of the suction pad 33 from the top surface of the stage 11 to a position lower than the height position of the suction pad 33 of the first suction nozzle 31a.

In this state, air is sucked into the pipes 32 of all suction nozzles 31 (31a, 31b) (the air flow during suction is shown by thin arrows in Figure 5). The first suction nozzle 31a facing the most downwardly curved convex part on the surface of the semiconductor chip 2 sucks and holds the semiconductor chip 2. The first suction nozzle 31a facing the most upwardly curved part on the surface of the semiconductor chip 2 and the second suction nozzle 31b generate a tensile force 41 (41a, 41b) on the semiconductor chip 2 that pulls the semiconductor chip 2 downward with a magnitude corresponding to the distance in the vertical direction Z2 from the opposing surface 2b of the semiconductor chip 2 to the suction pad 33 of the suction nozzle 31.

The distance in the vertical direction Z2 from the facing surface 2b of the semiconductor chip 2 to the suction pad 33 of the first suction nozzle 31a is shorter than the distance in the vertical direction Z2 from the facing surface 2b of the semiconductor chip 2 to the suction pad 33 of the second suction nozzle 31b. Therefore, the tensile force 41a generated on the semiconductor chip 2 by the suction of the first suction nozzle 31a is greater than the tensile force 41b generated on the semiconductor chip 2 by the suction of the second suction nozzle 31b. In this way, by adjusting the tensile force 41 applied to the semiconductor chip 2 according to the warpage state of the semiconductor chip 2, a semiconductor chip 40 whose warpage has been corrected so that it is substantially flat over the entire surface can be obtained (FIG. 5(c)).

In this way, the tensile force 41 applied to the semiconductor chip 2 is adjusted according to the distance in the vertical direction Z2 from the opposing surface 2b of the semiconductor chip 2 to the suction pad 33 of the suction nozzle 31, so the suction volume of all suction nozzles 31 may be the same. The suction volume of each suction nozzle 31 may be adjusted individually. When the suction volume of each suction nozzle 31 is adjusted individually, the piping 32 of the suction nozzles 31 may be connected to different suction devices (not shown), or the piping 32 of all suction nozzles 31 may be connected to one suction device, and each suction nozzle 31 may be provided with a pressure control device (not shown) that adjusts the suction volume.

A method for inspecting a semiconductor chip 2 according to the second embodiment will be described. First, as in the first embodiment, the semiconductor chip 2 before warpage correction is placed on the suction pads 33 of the suction nozzles 31 on the upper surface side of the stage 11 of the semiconductor inspection device 10 (see FIG. 1) (see step S1 in FIG. 4). At this stage, as in the first embodiment, the suction pads 33 of all the suction nozzles 31 are at the same height. Next, as in the first embodiment, steps S2 to S7 (see FIG. 4) are performed to obtain the three-dimensional warpage state within the surface of the semiconductor chip 2, and the amount of warpage correction of the semiconductor chip 2 is calculated.

In the second embodiment, the amount of warpage correction of the semiconductor chip 2 is the distance in the vertical direction Z2 from the opposing surface 2b of the semiconductor chip 2 to the suction pad 33 of each suction nozzle 31 (31a, 31b). The calculation means 22 calculates the amount of intake air of the piping 32 of each suction nozzle 31 (31a, 31b) based on the amount of warpage correction of the semiconductor chip 2. Next, based on the amount of warpage correction of the semiconductor chip 2, the second suction nozzle 31b is moved downward in the vertical direction Z2 to move the height position of the suction pad 33 of the second suction nozzle 31b to a position lower than the height position of the suction pad 33 of the first suction nozzle 31a.

Next, by sucking air into the piping 32 of the suction nozzle 31 with the suction volume calculated by the calculation means 22, an external force (tensile force 41) that pulls the semiconductor chip 2 toward the suction nozzle 31 is indirectly applied to the semiconductor chip 2 without contacting the suction nozzle 31 (corresponding to step S8 in FIG. 4). As a result, the suction pads 33 of all the first suction nozzles 31a are sucked onto the opposing surface 2b of the semiconductor chip 2, and a semiconductor chip 40 that has been corrected to be substantially flat over the entire surface can be obtained (FIG. 5(c)). Thereafter, by performing the process of step S9 in the same manner as in the first embodiment, the appearance inspection of the inspection surface 2a of the semiconductor chip 2 (inspection surface 40a of the semiconductor chip 40 whose warpage has been corrected) is completed.

As described above, according to the second embodiment, it is possible to obtain the same effect as the first embodiment. Furthermore, according to the second embodiment, the warpage of the semiconductor chip can be corrected only by the suction force (tensile force) of the suction nozzle, so that the external force applied to the semiconductor chip can be reduced. This makes it possible to prevent scratches or suction marks left on the semiconductor chip by the suction nozzle. Furthermore, according to the second embodiment, it is possible to automatically change the suction nozzle that is used to suction the semiconductor chip depending on the warpage state of the semiconductor chip, so that it is possible to deal with various warpage states that may occur in the semiconductor chip.

(Embodiment 3)
Next, the structure of the semiconductor inspection device according to the third embodiment will be described. Fig. 6 is a cross-sectional view showing the structure of the semiconductor inspection device according to the third embodiment. The configuration of each part of the semiconductor inspection device according to the third embodiment, other than the movable range of the suction nozzle 31 in the vertical direction Z2, is the same as that of Fig. 1. Fig. 6 shows a schematic view of a part of the structure of the correction mechanism 24 in Fig. 1. The semiconductor inspection device according to the third embodiment differs from the semiconductor inspection device 10 according to the first embodiment (see Fig. 2) in that both the multiple suction nozzles 31 of the correction mechanism 24 (24d) and the stage 11 function as a correction means for correcting the warpage of the semiconductor chip 4.

In the third embodiment, the suction pads 33 of all suction nozzles 31 of the correction mechanism 24d are first suctioned onto the opposing surface 4b of the semiconductor chip 4, and then the suction nozzles 31 are moved downward (vertical direction Z2) to pull the semiconductor chip 4 downward and press the entire opposing surface 4b of the semiconductor chip 4 against the upper surface of the stage 11. The entire opposing surface 4b of the semiconductor chip 4 is pressed against the upper surface of the stage 11, so that the warp of the semiconductor chip 4 is corrected and the entire surface becomes substantially flat. When the semiconductor chip 4 is pressed against the upper surface of the stage 11, the suction pads 33 of the suction nozzles 31 are stored inside the through-holes 11a of the stage 11.

The method of inspecting the semiconductor chip 4 according to the third embodiment will be described. FIG. 7 is a cross-sectional view showing a schematic state of a semiconductor chip in the middle of being corrected for warpage by the semiconductor inspection device according to the third embodiment. First, as in the first embodiment, the semiconductor chip 4 before warpage correction is placed on the suction pad 33 of the suction nozzle 31 on the upper surface side of the stage 11 of the semiconductor inspection device 10 (see FIG. 1) (see step S1 in FIG. 4). At this stage, as in the first embodiment, the height positions of the suction pads 33 of all the suction nozzles 31 are at the same height position on the upper surface side of the stage 11, so there are suction nozzles 31 that are not in contact with the facing surface 4b of the semiconductor chip 4 before warpage correction (left diagram in FIG. 7).

Next, steps S2 to S7 are performed in the same manner as in the first embodiment, the three-dimensional warpage state within the plane of the semiconductor chip 4 is obtained, and the amount of warpage correction of the semiconductor chip 4 is calculated. The amount of warpage correction of the semiconductor chip 4 is the distance in the vertical direction Z2 from the facing surface 4b of the semiconductor chip 4 to the suction pad 33 of the suction nozzle 31. Next, as in the first embodiment, each suction nozzle 31 is individually moved in either the vertical direction Z1 or Z2 according to the amount of warpage correction of the semiconductor chip 4, and the suction pads 33 of all the suction nozzles 31 are brought into contact with the facing surface 4b of the semiconductor chip 4. Next, as in the first embodiment, air is sucked into the piping 32 of the suction nozzle 31, and all the suction pads 33 are sucked onto the facing surface 4b of the semiconductor chip 4.

Next, all of the suction nozzles 31 are moved in the vertical direction Z2 (downward arrow 44) (center diagram of FIG. 7) to press the entire opposing surface 4b of the semiconductor chip 4 against the upper surface of the stage 11, thereby obtaining a semiconductor chip 40 that has been corrected to be substantially flat over the entire surface (corresponding to step S8 in FIG. 4: right diagram of FIG. 7). At this time, the suction pads 33 of all of the suction nozzles 31 are stored in the through holes 11a of the stage 11. Thereafter, by performing the process of step S9 in the same manner as in embodiment 1, the appearance inspection of the inspection surface 4a of the semiconductor chip 4 (inspection surface 40a of the semiconductor chip 40 whose warpage has been corrected) is completed.

As described above, according to the third embodiment, it is possible to obtain the same effects as the first to third embodiments. Furthermore, according to the third embodiment, it is possible to correct the warpage of a semiconductor chip regardless of the size of the semiconductor chip. Furthermore, according to the third embodiment, it is not necessary to control the suction nozzle 31 when correcting the warpage of a semiconductor chip, and therefore it is possible to simplify the control by the semiconductor inspection device compared to the case where the suction nozzles are moved individually to correct the warpage of a semiconductor chip.

(Embodiment 4)
Next, the structure of the semiconductor inspection device according to the fourth embodiment will be described. Figures 8 and 9 are cross-sectional views showing the structure of the semiconductor inspection device according to the fourth embodiment. The overall configuration of the semiconductor inspection device according to the fourth embodiment is the same as that of Figure 1. Figures 8 and 9 show a schematic view of a part of the structure of the correction mechanism 24 of Figure 1. The semiconductor inspection device according to the fourth embodiment differs from the semiconductor inspection device 10 according to the first embodiment (see Figure 2) in that the suction nozzle 31 of the correction mechanism 24 (24e, 24f) rotates in one of the rotation directions R1, R2 (clockwise and counterclockwise) around the central axis (rotation axis) of the pipe 32.

In the fourth embodiment, the suction pads 33 of all the suction nozzles 31 of the correction mechanisms 24e, 24f are attached to the opposing surfaces 5b, 6b of the semiconductor chips 5, 6, and then one or more of the suction nozzles 31 are rotated in either of the rotation directions R1, R2 to apply an external force (rotational moment) to the semiconductor chips 5, 6 so that the semiconductor chips 5, 6 are substantially flat over the entire surface. Figures 8 and 9 show a case in which, of the five suction nozzles 31 attached to the five locations near the center and the four vertices of the opposing surfaces 5b, 6b of the semiconductor chips 5, 6, the suction nozzles 31 that attach to the vertices are moved in the rotation directions R1, R2 opposite to the adjacent suction nozzles 31.

By rotating the suction nozzle 31, it becomes easier to correct warpage even for semiconductor chips 5, 6 with a large surface area of a triangular region with vertices at the center of the semiconductor chip 5, 6 and each vertex that shares one side of the semiconductor chip 5, 6. For example, the suction nozzle 31 near the center of the semiconductor chip 5, 6 is not rotated, and the four suction nozzles 31 near each vertex of the semiconductor chip 5, 6 are rotated in either rotation direction R1 or R2. In this case, the suction nozzle 31 that is sucked near the vertices of the opposing surfaces 5b, 6b of the semiconductor chip 5, 6 can correct warpage within a roughly rectangular range with the center of the semiconductor chip 5, 6 and its own suction point as opposite vertices.

In the fourth embodiment, all of the suction nozzles 31 need only be movable in the rotational directions R1 and R2, and can move in the vertical directions Z1 and Z2 in conjunction with the movement of the stage 11 in the vertical directions Z1 and Z2. Instead of a configuration in which the suction nozzles 31 pass through the through holes 11a of the stage 11, all of the suction nozzles 31 may be arranged between the stage 11 and the second illumination 14. Also, the suction nozzles 31 need only be movable in the rotational directions R1 and R2, and do not need to be individually movable in the vertical directions Z1 and Z2.

A method for inspecting semiconductor chips 5, 6 according to the fourth embodiment will be described. First, as in the first embodiment, the semiconductor chips 5, 6 before warping are corrected are placed on the suction pads 33 of the suction nozzles 31 on the upper surface side of the stage 11 of the semiconductor inspection device 10 (see FIG. 1) (see step S1 in FIG. 4). At this stage, as in the first embodiment, the suction pads 33 of all the suction nozzles 31 are at the same height. Therefore, there are suction nozzles 31 that are not in contact with the opposing surfaces 5b, 6b of the semiconductor chips 5, 6 before warping is corrected.

Next, steps S2 to S7 are performed in the same manner as in the first embodiment, the three-dimensional state of the warpage within the plane of the semiconductor chips 5 and 6 is obtained, and the amount of warpage correction for the semiconductor chips 5 and 6 is calculated. The amount of warpage correction for the semiconductor chips 5 and 6 is the distance in the vertical direction Z2 from the opposing surfaces 5b and 6b of the semiconductor chips 5 and 6 to the suction pads 33 of the suction nozzle 31. Next, as in the first embodiment, each suction nozzle 31 is moved individually in either the vertical direction Z1 or Z2 by the amount of warpage correction for the semiconductor chip 4, and the suction pads 33 of all the suction nozzles 31 are brought into contact with the opposing surfaces 5b and 6b of the semiconductor chips 5 and 6.

Next, as in the first embodiment, air is sucked into the piping 32 of the suction nozzle 31 to suction all of the suction pads 33 onto the opposing surfaces 5b, 6b of the semiconductor chips 5, 6. Next, a predetermined suction nozzle 31 is rotated in either of the rotation directions R1 or R2 based on the three-dimensional warpage state within the plane of the semiconductor chips 5, 6, thereby obtaining a semiconductor chip 40 that has been corrected to be substantially flat over the entire surface (corresponding to step S8 in FIG. 4). Thereafter, as in the first embodiment, step S9 is performed to complete the visual inspection of the inspection surfaces 5a, 6a of the semiconductor chips 5, 6 (inspection surface 40a of the semiconductor chip 40 whose warpage has been corrected).

As explained above, according to the fourth embodiment, it is possible to obtain the same effects as the first to fourth embodiments. Furthermore, according to the fourth embodiment, it is possible to correct the warpage of a large semiconductor chip with a small number of suction nozzles.

(Embodiment 5)
As a fifth embodiment, the structure of the correction mechanism 24 (24a to 24f) of the first to fifth embodiments will be described. Fig. 10 is a cross-sectional view that shows a schematic structure of the correction mechanism of Fig. 1. The correction mechanism 24 shown in Fig. 10 includes a plurality of suction nozzles 31, and a ROBO cylinder 52 and a joint 53 that are provided for each suction nozzle 31. As described above, the plurality of suction nozzles 31 each pass through a different through-hole 11a of the stage 11. As described above, the suction pad 33 is provided at the upper end of the piping 32 of the suction nozzle 31. The lower end of the piping 32 of the suction nozzle 31 is connected to an external suction device (not shown) via the joint 53.

The pipes 32 of all the suction nozzles 31 may be connected to one suction device, or the pipes 32 of each suction nozzle 31 may be connected to a different suction device. When the pipes 32 of all the suction nozzles 31 are connected to one suction device, a pressure control device (not shown) that adjusts the amount of intake air is provided on the joints 53 connected to the pipes 32 of each suction nozzle 31. The pipes 32 of the suction nozzles 31 are sucked in through the joints 53 connected to them. The stage 11 is a flat plate with a roughly rectangular planar shape, and one side of the stage 11 is fixed and supported by the upper end of the vertical part of a support part 51 with an L-shaped cross section, for example.

The stage 11 is the top plate, the horizontal part of the support part 51 is the bottom surface, and in an area of a substantially rectangular cross section with an opening that connects the stage 11 and the horizontal part of the support part 51 with the vertical part of the support part 51, multiple general ROBO Cylinders 52 are arranged on the horizontal part of the support part 51. The horizontal part of the support part 51 is, for example, a flat base with a substantially rectangular planar shape. The vertical part of the support part 51 may be columnar or flat forming a side wall. The ROBO Cylinder 52 is located between the horizontal part of the support part 51 and the stage 11. The ROBO Cylinder 52 has the function of converting pressure, such as air pressure, into thrust to push an object up in the vertical direction 54.

The multiple ROBO cylinders 52 are arranged to surround all of the suction nozzles 31 when viewed from the top surface side of the stage 11. The multiple ROBO cylinders 52 each support the piping 32 of a different suction nozzle 31 in a state in which it can move in the vertical direction 54. By moving the piping 32 of the suction nozzle 31 in the vertical direction 54 by the ROBO cylinders 52, the height position of the suction pad 33 at the upper end of the suction nozzle 31 can be moved in the vertical direction 55 on the top surface side of the stage 11. Here, the double-headed arrows pointing up and down indicating the vertical directions 54, 55 correspond to the double-headed arrows indicating the vertical directions Z1, Z2 in FIG. 1.

As explained above, embodiment 5 can be applied to the correction mechanisms of embodiments 1 to 5.

(Embodiment 6)
A semiconductor inspection device according to a sixth embodiment will be described. FIG. 11 is a cross-sectional view showing a schematic diagram of a correction mechanism of the semiconductor inspection device according to the sixth embodiment. FIG. 12 is a perspective view showing a part of the correction mechanism of FIG. 11. The configuration of each part of the semiconductor inspection device according to the sixth embodiment, other than the correction mechanism 60, is the same as that shown in FIG. 1. The correction mechanism 60 of the semiconductor inspection device according to the sixth embodiment is different from the correction mechanism 24d of the semiconductor inspection device according to the third embodiment (see FIG. 6) in that only the stage 61 also functions as a correction means for correcting the warpage of the semiconductor chip 4. The groove 63 and the vent hole 64 of the stage 61 function as a suction pad and a piping for the suction nozzle 62, respectively.

Specifically, in the sixth embodiment, the correction mechanism 60 includes a stage 61, a joint 66, a mounting flange 67, and a robo cylinder 68. A groove (hereinafter referred to as a chip receiver) 65 for storing and holding the semiconductor chip 4 is provided on the upper surface of the stage 61. The chip receiver 65 has dimensions slightly larger than the outer dimensions of the semiconductor chip 40 in a state in which the warpage has been corrected, and has a planar shape that is approximately the same as the planar shape of the semiconductor chip 4. The depth of the chip receiver 65 is such that the semiconductor chip 4 inserted inside the chip receiver 65 does not jump out of the chip receiver 65 before being attracted to and fixed to the bottom surface of the chip receiver 65.

The grooves 63 are provided on the bottom surface of the chip receiver 65 at a depth that does not penetrate the stage 61 in the depth direction (vertical direction Z2 in FIG. 1). The ventilation holes 64 are provided between the bottom surface of the stage 61 and the grooves 63, and connect all the grooves 63. The ventilation holes 64 extend, for example, in a direction parallel to the bottom surface of the stage 61 and are connected to the joints 66 on the side surfaces of the stage 61. The ventilation holes 64 are connected to the suction device via the joints 66. The ventilation holes 64 are not shown in FIG. 12. It is sufficient that all the grooves 63 are connected to the suction device via the ventilation holes 64 and the joints 66, and multiple ventilation holes 64 and joints 66 may be provided.

After the semiconductor chip 4 is inserted 71 into the chip receiver 65 of the stage 61 with the surface facing downward (the bottom surface side of the chip receiver 65), the suction device sucks air 72b into the vent 64, and the groove 63 is sucked in 72a (the air flow during the suction 72a and 72b is shown by thin arrows in FIG. 11). When the groove 63 is sucked in 72a, the air between the facing surface of the semiconductor chip 4 and the bottom surface of the chip receiver 65 is sucked in, and the facing surface of the semiconductor chip 4 is adsorbed and held in the groove 63. The bottom surface of the stage 61 is joined to a mounting flange 67. The stage 61 is attached to a general ROBO cylinder 68 via the mounting flange 67.

The ROBO Cylinder 68 has the function of converting pressure, such as air pressure, into thrust to push an object up in the vertical direction 73. The stage 61 is moved in the vertical direction 73 by the ROBO Cylinder 68, thereby adjusting the height position of the inspection surface of the semiconductor chip 4 on the upper surface of the stage 61 and adjusting the focus of the lens 12. Here, the double-headed arrow pointing up and down indicating the vertical direction 73 corresponds to the double-headed arrows indicating the vertical directions Z1 and Z2 in FIG. 1. By applying the ROBO Cylinder 68 to the semiconductor inspection devices according to the first to fifth embodiments, it is possible to move the stage 11 of the first to fifth embodiments in the vertical direction 73 by the ROBO Cylinder 68.

As described above, according to the sixth embodiment, it is possible to obtain the same effects as those of the first to fifth embodiments. Furthermore, according to the sixth embodiment, the grooves and vents inside the stage function as suction nozzles, which eliminates the need to provide multiple independent suction nozzles, thereby simplifying the semiconductor inspection device.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, both sides of a semiconductor chip may be inspected. In this case, after visual inspection of one main surface of the semiconductor chip, visual inspection of the other main surface of the semiconductor chip may be performed. The present invention is also applicable to semiconductor chips in which there is no difference in glossiness or unevenness of the element structure on the main surface of the semiconductor chip. In the above-mentioned embodiments, the visual inspection of the semiconductor chip is performed in an air atmosphere, but the present invention is not limited to this, and the visual inspection of the semiconductor chip may be performed in an atmosphere of gas other than air.

As described above, the semiconductor inspection device and semiconductor chip inspection method of the present invention are useful for semiconductor chips that have been thinned and have warped.

1 to 6: Semiconductor chip before warping is corrected 1a, 2a, 3a, 4a, 5a, 6a: Main surface (inspection surface) for visually inspecting the semiconductor chip before warping is corrected
1b, 2b, 3b, 4b, 5b, 6b: Main surface (opposing surface) of the semiconductor chip facing the stage before warpage is corrected
LIST OF SYMBOLS 10 Semiconductor inspection device 11, 61 Stage 11a Through hole of stage 12 Lens 13, 14 Lighting 15 Photography means 21 Image recognition means 22 Calculation means 23 Actuator 24, 24a to 24f, 60 Correction mechanism 25 Attitude control mechanism 26 Control means 31, 31a, 31b, 62 Suction nozzle 32 Suction nozzle piping 33 Suction pad of suction nozzle 40 Semiconductor chip in a state where warpage has been corrected 40a Inspection surface of semiconductor chip in a state where warpage has been corrected 40b Opposing surface of semiconductor chip in a state where warpage has been corrected 41, 41a, 41b Pulling force 42 Push-up force 51 Support part of correction mechanism 52, 68 Robo cylinder of correction mechanism 53 Suction nozzle joint 63 Groove of stage 64 Ventilation hole of stage 65 Chip receiver of stage 66 Stage vent joint 67 Stage mounting flange R1, R2, Rx, Ry Rotation direction X, Y Horizontal direction Z1, Z2 Vertical direction

Claims (7)

a stage on which a semiconductor chip is placed;
a plurality of hollow suction means for suctioning the semiconductor chip on a first main surface of the semiconductor chip facing the stage and holding the semiconductor chip on the first surface side of the stage;
an imaging means for imaging a second main surface of the semiconductor chip on the opposite side to the stage;
a calculation means for converting a state of warpage of the semiconductor chip into a numerical value based on image data of the second main surface of the semiconductor chip photographed by the photographing means;
a correction means for correcting the warpage of the semiconductor chip based on the state of the warpage of the semiconductor chip quantified by the calculation means;
an inspection means for inspecting the second main surface of the semiconductor chip after the warpage has been corrected by the correction means for any abnormality in appearance;
Equipped with
The suction means also functions as the correction means,
A semiconductor inspection device characterized in that the suction means is sucked in to suck in the gas between the semiconductor chip and the suction means, thereby controlling the application of an external force directly or indirectly to a portion of the semiconductor chip, thereby correcting the warping of the semiconductor chip. The suction means is supported in a state in which it can move vertically,
The semiconductor chip before the warpage is corrected is placed on the suction means,
based on the state of warpage of the semiconductor chip quantified by the calculation means, all of the suction means are individually moved in a vertical direction to contact the first main surface of the semiconductor chip, and then all of the suction means are sucked in air to suction the first main surface of the semiconductor chip;
2. The semiconductor inspection device according to claim 1, wherein the suction means holding the semiconductor chip is individually moved in a vertical direction based on the state of warpage of the semiconductor chip quantified by the calculation means, thereby applying an external force directly to part of the semiconductor chip to correct the warpage of the semiconductor chip. The suction means is supported in a state in which it can move vertically,
The upper ends of all of the suction means are located at the same height,
The semiconductor chip before the warpage is corrected is placed on the suction means,
based on the state of warpage of the semiconductor chip quantified by the calculation means, one or more of the suction means are individually moved in a vertical direction to change a distance from the suction means to a first main surface of the semiconductor chip, and
2. The semiconductor inspection device according to claim 1, wherein the semiconductor chip is sucked by sucking air through all of the suction means, thereby exerting an external force indirectly on a part of the semiconductor chip, thereby correcting warpage of the semiconductor chip. The suction means is supported in a state in which it can move horizontally,
The upper ends of all of the suction means are located at the same height,
The semiconductor chip before the warpage is corrected is placed on the suction means,
Based on the state of warpage of the semiconductor chip quantified by the calculation means, one or more of the suction means are moved in a horizontal direction to a position facing a predetermined portion of a first main surface of the semiconductor chip, and
2. The semiconductor inspection device according to claim 1, wherein the semiconductor chip is sucked by sucking air through all of the suction means, thereby exerting an external force indirectly on a part of the semiconductor chip, thereby correcting warpage of the semiconductor chip. the stage also functions as the correcting means, and has a plurality of through holes;
the suction means is supported in a state in which it can move in a vertical direction, and passes through the through hole of the stage;
The semiconductor chip before the warpage is corrected is placed on the suction means,
based on the state of warpage of the semiconductor chip quantified by the calculation means, all of the suction means are individually moved in a vertical direction to contact the first main surface of the semiconductor chip, and then all of the suction means are sucked in air to suction the first main surface of the semiconductor chip;
The semiconductor inspection device according to claim 1, characterized in that the suction means, while holding the semiconductor chip, is moved vertically to press the first main surface of the semiconductor chip against the first surface of the stage, thereby applying an external force directly to part of the semiconductor chip and correcting any warping of the semiconductor chip. the suction means is supported in a state in which it can move in a vertical direction and in a rotational direction about its own central axis;
The semiconductor chip before the warpage is corrected is placed on the suction means,
based on the state of warpage of the semiconductor chip quantified by the calculation means, all of the suction means are individually moved in a vertical direction to contact the first main surface of the semiconductor chip, and then all of the suction means are sucked in air to suction the first main surface of the semiconductor chip;
2. The semiconductor inspection device according to claim 1, wherein the suction means holding the semiconductor chip is individually moved in the rotational direction based on the state of warpage of the semiconductor chip quantified by the calculation means, thereby applying an external force directly to part of the semiconductor chip to correct the warpage of the semiconductor chip. using a semiconductor inspection device including a stage for mounting a semiconductor chip, a plurality of hollow suction means for suctioning a first main surface of the semiconductor chip, an imaging means for imaging a second main surface of the semiconductor chip, a calculation means for converting a state of warpage within the surface of the semiconductor chip into a numerical value, a correction means for correcting the warpage of the semiconductor chip, and an inspection means for inspecting the second main surface of the semiconductor chip for visual abnormalities,
a first step of placing and holding the semiconductor chip on the suction means on a first surface side of the stage with a first main surface facing the stage;
a second step of photographing a second main surface of the semiconductor chip opposite to the stage side by the photographing means;
a third step of quantifying a state of warpage within the plane of the semiconductor chip by the calculation means based on image data of the second main surface of the semiconductor chip photographed by the photographing means;
a fourth step of correcting the warpage of the semiconductor chip by the correction means based on the state of the warpage of the semiconductor chip quantified by the calculation means;
a fifth step of inspecting, by the inspection means, for an appearance abnormality on the second main surface of the semiconductor chip in a state in which the warpage has been corrected by the correction means;
Including,
The suction means also functions as the correction means,
A semiconductor chip inspection method, characterized in that in the fourth step, the suction means is sucked to suck in air between the semiconductor chip and the suction means, thereby applying an external force partially to the semiconductor chip directly or indirectly, thereby correcting the warpage of the semiconductor chip.

Images