JP7523231B2 - Method and apparatus for manufacturing power semiconductor module, learning device, and inference device - Google Patents

Description

The present disclosure relates to a method for manufacturing a power semiconductor module, an apparatus for manufacturing a power semiconductor module, a learning device, and an inference device.

In a power semiconductor module that is composed of multiple semiconductor devices connected in parallel, a relatively large current may flow through a specific semiconductor device when it is in operation. As a result, the semiconductor device may fail, causing the power semiconductor module to fail.

To address this issue, an inductance means is provided on the emitter side of each semiconductor device, lowering the gate-emitter voltage of the semiconductor device with a low threshold voltage when on. This reduces the current imbalance caused by the variation in characteristics of the multiple semiconductor devices that make up the power semiconductor module, and prevents failure of the power semiconductor module (see, for example, Patent Document 1).

JP 2009-225531 A

In a power semiconductor module, the imbalance of currents flowing through multiple semiconductor elements connected in parallel is not determined solely by the switching characteristics of each semiconductor device. Therefore, the method described in Patent Document 1 can only reduce current imbalances in a limited mode, and cannot fully prevent failures in the power semiconductor module.

Therefore, the present disclosure provides a power semiconductor module manufacturing method, a power semiconductor module manufacturing apparatus, a learning device, and an inference device that can manufacture power semiconductor modules that are less prone to failure.

The present disclosure relates to a method for manufacturing a power semiconductor module in which multiple semiconductor devices are connected in parallel, comprising the steps of: acquiring learning data consisting of input data including characteristic data of each of the multiple semiconductor devices and calculation data obtained by calculating the characteristic data of each of the multiple semiconductor devices, and teacher data including data on failures in the early failure period and random failure period when the multiple semiconductor devices are connected in parallel and operated; using the learning data, generating a trained model for inferring data on failures in the early failure period and random failure period when the multiple semiconductor devices are connected in parallel and operated from the input data including the characteristic data of each of the multiple semiconductor devices and calculation data obtained by calculating the characteristic data of each of the multiple semiconductor devices; acquiring input data including characteristic data of each of multiple candidate semiconductor devices to be mounted in the power semiconductor module and calculation data obtained by calculating the characteristic data of each of the multiple candidate semiconductor devices; inferring data on failures in the early failure period and random failure period when the multiple candidate semiconductor devices are connected in parallel and operated from the acquired input data using the trained model; and determining whether the multiple candidate semiconductor devices can be mounted in the power semiconductor module based on the data on inferred failures.

The present disclosure relates to a method for manufacturing a power semiconductor module in which multiple semiconductor devices are connected in parallel, the method comprising the steps of: acquiring learning data consisting of input data including characteristic data of each of multiple normal semiconductor devices constituting a normal power semiconductor module that did not fail during the initial failure period and the random failure period, and calculation data obtained by calculating each of the characteristic data; generating a trained model using the learning data to classify the input data including the characteristic data of each of the normal semiconductor devices and the calculation data obtained by calculating each of the characteristic data into one of multiple clusters; acquiring input data including characteristic data of each of multiple candidate semiconductor devices to be mounted on the power semiconductor module and the calculation data obtained by calculating each of the characteristic data; classifying the acquired input data into one of the multiple clusters or into other than the multiple clusters using the trained model; and determining whether the multiple candidate semiconductor devices can be mounted on the power semiconductor module based on the classification result.

The present disclosure relates to a manufacturing apparatus for a power semiconductor module in which a plurality of semiconductor devices are connected in parallel, the manufacturing apparatus comprising a learning apparatus and an inference apparatus. The learning apparatus includes a data acquisition unit that acquires learning data consisting of input data including characteristic data of each of the plurality of semiconductor devices and calculation data obtained by calculation of the characteristic data, and teacher data including data on failures in the early failure period and random failure period when the plurality of semiconductor devices are connected in parallel and operated, and a model generation unit that uses the learning data to generate a trained model for inferring data on failures in the early failure period and random failure period when the plurality of semiconductor devices are connected in parallel and operated from the input data including characteristic data of each of the plurality of semiconductor devices and calculation data obtained by calculation of the characteristic data. The inference apparatus includes a data acquisition unit that acquires input data including characteristic data of each of the plurality of candidate semiconductor devices to be mounted on the power semiconductor module and calculation data obtained by calculation of the characteristic data, and an inference unit that uses the trained model to infer data on failures in the early failure period and random failure period when the plurality of candidate semiconductor devices are connected in parallel and operated from the input data acquired by the data acquisition unit. The power semiconductor module manufacturing apparatus further includes a mounting device that determines whether multiple candidate semiconductor devices can be mounted on the power semiconductor module based on data about the failure inferred by the inference device.

The learning device of the present disclosure includes a data acquisition unit that acquires learning data consisting of input data including characteristic data of each of a plurality of semiconductor devices and calculation data obtained by calculating the characteristic data of each of the semiconductor devices, and teacher data including data on failures in the early failure period and random failure period when the plurality of semiconductor devices are connected in parallel and operated, and a model generation unit that uses the learning data to generate a trained model for inferring data on failures in the early failure period and random failure period when the plurality of semiconductor devices are connected in parallel and operated, from the input data including characteristic data of each of the plurality of semiconductor devices and calculation data obtained by calculating the characteristic data of each of the semiconductor devices.

The inference device of the present disclosure includes a data acquisition unit that acquires input data including characteristic data of each of a plurality of candidate semiconductor devices to be mounted on a power semiconductor module and computational data obtained by computing the characteristic data of each of the plurality of semiconductor devices, and an inference unit that infers data about failures in the early failure period and random failure period when the plurality of semiconductor devices are connected in parallel and operated from the input data input from the data acquisition unit, using a trained model for inferring data about failures in the early failure period and random failure period when the plurality of semiconductor devices are connected in parallel and operated, from the input data including the characteristic data of each of the plurality of semiconductor devices and computational data obtained by computing the characteristic data of each of the plurality of semiconductor devices.

According to the present disclosure, a trained model is used to infer data about failures during the initial failure period and random failure period when multiple candidate semiconductor devices are connected in parallel and operated from acquired input data, making it possible to manufacture power semiconductor modules that are less prone to failures.

1 is a diagram showing a configuration of a power semiconductor module manufacturing apparatus 2 according to a first embodiment; 1 is a diagram for explaining an example of an apparatus in which a power semiconductor module is mounted; 2 is a diagram showing a configuration of a learning device 8 according to the first embodiment. FIG. 1A is a diagram showing an example of characteristic data, FIG. 1B is a diagram showing an example of calculation data, and FIG. 1C is a diagram showing an example of data regarding a failure. FIG. 1 is a diagram showing the failure rate of power semiconductor modules. FIG. 1 is a diagram showing an example of the configuration of a neural network. 1 is a diagram showing a configuration of an inference device 14 according to a first embodiment. 1 is a diagram showing a configuration of a mounting device 51 according to a first embodiment. 4 is a flowchart showing a method for manufacturing a power semiconductor module formed by connecting a plurality of semiconductor devices in parallel according to the first embodiment. FIG. 13 is a diagram showing the configuration of a learning device 8A according to a second embodiment. 13 is a diagram showing an example of data arrangement in a data arrangement unit 32 of a learning device 8A. FIG. FIG. 13 shows the configuration of an inference device 14A according to a second embodiment. 13 is a diagram showing an example of data arrangement by a data arrangement unit 33 of an inference device 14A. FIG. 13 is a flowchart showing a method for manufacturing a power semiconductor module formed by connecting a plurality of semiconductor devices in parallel according to the second embodiment. FIG. 13 is a diagram showing the configuration of a learning device 8B according to a third embodiment. FIG. 13 shows a configuration of an inference device 14B according to a third embodiment. FIG. 13 is a diagram showing the configuration of a mounting device 51B according to a third embodiment. 13 is a flowchart showing a method for manufacturing a power semiconductor module formed by connecting a plurality of semiconductor devices in parallel according to the third embodiment. A diagram showing a configuration in which the functions of a learning device, a control device, and an on-board device are realized using software.

Hereinafter, embodiments will be described with reference to the drawings.
Embodiment 1.
1 is a diagram showing a configuration of a power semiconductor module manufacturing apparatus 2 according to a first embodiment. The power semiconductor module manufacturing apparatus 2 includes a learning device 8, a learned model storage unit 7, an inference device 14, and a mounting device 51. The learning device 8 and the inference device 14 may be devices separate from the power semiconductor module manufacturing apparatus 2. The learning device 8 and the inference device 14 may be built into the power semiconductor module manufacturing apparatus 2. The learning device 8 and the inference device 14 may exist on a cloud server.

Figure 2 is a diagram for explaining an example of a device equipped with a power semiconductor module. The drive device 1 includes a battery 10, a DC/DC converter 20, an inverter 30, and a motor 40.

The DC/DC converter 20 includes switching elements Q1 and Q2, diodes D1 and D2, and a reactor L1.

Switching element Q1 consists of two switching elements Q1A and Q1B connected in parallel. Diode D1A is connected in anti-parallel to switching element Q1A. Diode D1B is connected in anti-parallel to switching element Q1B.

Switching element Q2 consists of two switching elements Q2A and Q2B connected in parallel. Diode D2A is connected in anti-parallel to switching element Q2A. Diode D2B is connected in anti-parallel to switching element Q2B.

The switching elements Q1A, Q1B, Q2A, and Q2B are configured by IGBTs (Insulated Gate Bipolar Transistors). The switching elements Q1A and Q1B and the diodes D1A and D1B configure a power semiconductor module. The switching elements Q2A and Q2B and the diodes D2A and D2B configure a power semiconductor module. Although the power semiconductor module includes two IGBTs, which are semiconductor devices connected in parallel, it may also include three or more IGBTs, which are semiconductor devices connected in parallel.

FIG. 3 is a diagram showing the configuration of the learning device 8 according to the first embodiment.
The learning device 8 includes a data acquisition unit 5 and a model generation unit 6 .

The data acquisition unit 5 acquires learning data consisting of input data including characteristic data of each of the multiple semiconductor devices and calculation data obtained by calculating the characteristic data of each of the multiple semiconductor devices, and teacher data including data on failures during the initial failure period and random failure period when the multiple semiconductor devices are connected in parallel and operated.

The semiconductor device characteristic data includes at least one of output characteristic data, transmission characteristic data, leakage characteristic data, and manufacturing information.

The output characteristic data is, for example, the collector-emitter current value when a voltage equal to or greater than the threshold voltage is applied between the gate-emitter of an IGBT, which is a semiconductor device, and a voltage is applied between the collector-emitter of the IGBT at temperature K1 for time T1. It is also possible to use output characteristic data under multiple conditions in which the temperature K1 and time T1 are changed.

The transfer characteristic data is, for example, the gate-emitter voltage value when a voltage V2 is applied between the collector and emitter of an IGBT, which is a semiconductor device, and a current I2 flows between the gate and emitter of the IGBT at a temperature K2. Transfer characteristic data under multiple conditions in which the voltage V2, temperature K2, and current I2 are changed may also be used.

The leakage characteristic data is, for example, the collector-emitter current that flows when a voltage lower than the threshold voltage is applied between the gate-emitter of an IGBT, which is a semiconductor device, and a voltage is applied between the collector-emitter of the IGBT at temperature K3 for time T3, and the gate-emitter current that flows when a voltage is applied between the collector-emitter of the IGBT, which is a semiconductor device, at temperature K4 for time T4 in a state where a voltage that causes only a very small output current to flow even when applied between the gate-emitter of the IGBT, which is a semiconductor device, is applied between the collector-emitter. It is also possible to use leakage characteristic data under multiple conditions in which the temperature K3, time T3, temperature K4, and time T4 are changed.

The calculated data is the average value or standard deviation of the multiple characteristic data obtained by arithmetic operations on the characteristic data of each of the multiple semiconductor devices. Alternatively, the calculated data may be the maximum value or minimum value of the multiple characteristic data obtained by comparative operations on the respective characteristic data.

Figure 4(a) is a diagram showing an example of characteristic data. Figure 4(b) is a diagram showing an example of calculation data. Figure 4(c) is a diagram showing an example of data regarding a failure.

For example, the output characteristic data of semiconductor device A is Doa1, Doa2, Doa3, the transfer characteristic data is Dta1, Dta2, Dta3, the leakage characteristic data of semiconductor device A is Dla1, Dla2, Dla3, Dla4, and the manufacturing information of semiconductor device A is Dma1, Dma2. The output characteristic data of semiconductor device B is Dob1, Dob2, Dob3, the transfer characteristic data is Dtb1, Dtb2, Dtb3, the leakage characteristic data of semiconductor device A is Dlb1, Dlb2, Dlb3, Dlb4, and the manufacturing information of semiconductor device A is Dmb1, Dmb2. The output characteristic data of semiconductor device C is Doc1, Doc2, Doc3, the transfer characteristic data is Dtc1, Dtc2, Dtc3, the leakage characteristic data of semiconductor device C is Dlc1, Dlc2, Dlc3, Dlc4, and the manufacturing information of semiconductor device C is Dmc1, Dmc2.

The calculation data of the characteristic data of the semiconductor devices A, B, and C includes the calculation data of the output characteristic data of the semiconductor devices A, B, and C. That is, the calculation data of the characteristic data of the semiconductor devices A, B, and C includes the calculation data of Doa1, Dob1, and Doc1 (at least one of the average, standard deviation, maximum value, and minimum value), the calculation data of Doa2, Dob2, and Doc2 (at least one of the average, standard deviation, maximum value, and minimum value), and the calculation data of Doa3, Dob3, and Doc3 (at least one of the average, standard deviation, maximum value, and minimum value).

The calculation data of the characteristic data of the semiconductor devices A, B, and C includes the calculation data of the transfer characteristic data of the semiconductor devices A, B, and C. That is, the calculation data of the characteristic data of the semiconductor devices A, B, and C includes the calculation data of Dta1, Dtb1, and Dtc1 (at least one of the average, standard deviation, maximum value, and minimum value), the calculation data of Dta2, Dtb2, and Dtc2 (at least one of the average, standard deviation, maximum value, and minimum value), and the calculation data of Dta3, Dtb3, and Dtc3 (at least one of the average, standard deviation, maximum value, and minimum value).

The calculation data of the characteristic data of the semiconductor devices A, B, and C includes the calculation data of the leakage characteristic data of the semiconductor devices A, B, and C. That is, the calculation data of the characteristic data of the semiconductor devices A, B, and C includes the calculation data of Dla1, Dlb1, and Dlc1 (at least one of the average, standard deviation, maximum value, and minimum value), the calculation data of Dla2, Dlb2, and Dlc2 (at least one of the average, standard deviation, maximum value, and minimum value), the calculation data of Dla3, Dlb3, and Dlc3 (at least one of the average, standard deviation, maximum value, and minimum value), and the calculation data of Dla4, Dlb4, and Dlc4 (at least one of the average, standard deviation, maximum value, and minimum value).

The calculation data of the characteristic data of the semiconductor devices A, B, and C includes the calculation data of the manufacturing information of the semiconductor devices A, B, and C. That is, the calculation data of the characteristic data of the semiconductor devices A, B, and C includes the calculation data of Dma1, Dmb1, and Dmc1 (at least one of the average, standard deviation, maximum value, and minimum value) and the calculation data of Dma2, Dmb2, and Dmc2 (at least one of the average, standard deviation, maximum value, and minimum value).

Figure 5 shows the failure rate of power semiconductor modules. The failure rate of power semiconductor modules is generally represented by a curve called a bathtub curve.

The data regarding failures during the early failure period and the random failure period is data indicating the presence or absence of failures during the early failure period and the random failure period. Alternatively, the data regarding failures during the early failure period and the random failure period may be data indicating the failure rate during the early failure period and the random failure period.

The data acquisition unit 5 is configured to acquire input data and teacher data simultaneously, but is not limited to this. It is sufficient if the input data and teacher data can be input in association with each other.

The data acquisition unit 5 may acquire output characteristic data, transmission characteristic data, leak characteristic data, manufacturing information, calculation data, and data regarding failures at different times.

The model generation unit 6 uses the learning data to generate a trained model for inferring data about failures during the initial failure period and random failure period when multiple semiconductor devices are connected in parallel and operated, from input data including characteristic data of each of the multiple semiconductor devices and calculation data obtained by calculating the characteristic data of each of the multiple semiconductor devices.

The learning algorithm used by the model generation unit 6 can be a known supervised learning algorithm. As an example, we will explain the case where a neural network is applied.

The model generation unit 6 generates a trained model by so-called supervised learning, for example, according to a neural network model. Here, supervised learning refers to a method in which a learning device is provided with pairs of input and result (label) data, and the device learns the features of the training data and infers the result from the input.

A neural network is composed of an input layer consisting of multiple neurons, an intermediate layer (hidden layer) consisting of multiple neurons, and an output layer consisting of multiple neurons. The intermediate layer may be one layer, or two or more layers.

FIG. 6 is a diagram showing an example of the configuration of a neural network.
For example, in a three-layered neural network as shown in Figure 6, when multiple inputs are input to the input layer (X1-X3), the values are multiplied by a weight W1 (w11-w16) and input to the intermediate layer (Y1-Y2), and the result is further multiplied by a weight W2 (w21-w26) and output from the output layer (Z1-Z3). This output result changes depending on the values of the weights W1 and W2.

In this embodiment, the neural network uses learning data consisting of input data including characteristic data of each of the multiple semiconductor devices acquired by the data acquisition unit 12 and calculation data obtained by calculating each of the characteristic data, and teacher data including data on failures during the initial failure period and random failure period when the multiple semiconductor devices are connected in parallel and operated.

In other words, the neural network learns by inputting input data and adjusting weights W1 and W2 so that the output data output from the output layer approaches the training data.

The model generation unit 6 generates a trained model by performing the above-mentioned learning, and outputs it to the trained model storage unit 7.

The learning algorithm used in the model generation unit 6 may be deep learning, which learns to extract the features themselves, or machine learning may be performed according to other known methods, such as genetic programming, functional logic programming, and support vector machines.

The model generation unit 6 may acquire learning data about multiple power semiconductor modules built into the same product, or may collect learning data about multiple power semiconductor modules built into different products and operating independently. It is also possible to add or remove power semiconductor modules from which learning data is collected midway through the process.

The trained model storage unit 7 stores the trained model output from the model generation unit 6.
FIG. 7 is a diagram showing the configuration of the inference device 14 according to the first embodiment.

The inference device 14 includes a data acquisition unit 12 and an inference unit 13 .
The data acquiring unit 12 acquires input data including characteristic data of each of a plurality of candidate semiconductor devices to be mounted on the power semiconductor module, and calculation data obtained by calculating each characteristic data.

The inference unit 13 uses the learned model stored in the learned model storage unit 7 to infer data about failures during the initial failure period and random failure period when multiple candidate semiconductor devices are connected in parallel and operated from the input data input from the data acquisition unit 12.

The inference device 14 uses a trained model generated by a model generation unit 6 in the power semiconductor module manufacturing equipment 2 in which the inference device 14 is included, but this is not limited to this. The inference device 14 may also use a trained model generated by a model generation unit in another power semiconductor module manufacturing equipment.

FIG. 8 is a diagram showing the configuration of a mounting device 51 according to the first embodiment.
The mounting device 51 includes a semiconductor device selection unit 18, a mounting unit 19, and a conversion information storage unit 27. The conversion information storage unit 27 may be a device separate from the mounting device 51. The conversion information storage unit 27 may exist on a cloud server.

The conversion information storage unit 27 stores characteristic data of the multiple semiconductor devices and calculation data obtained by calculating the characteristic data of the multiple semiconductor devices in correspondence with the individual identification information of the multiple semiconductor devices.

The semiconductor device selection unit 18 reads out, from the conversion information storage unit 27, characteristic data of the multiple semiconductor devices corresponding to the individual identification information of the multiple candidate semiconductor devices to be mounted on the power semiconductor module, and calculation data obtained by calculating the characteristic data of the multiple semiconductor devices, and sends them to the inference device 14. The semiconductor device selection unit 18 obtains data on failures during the initial failure period and random failure period when the multiple candidate semiconductor devices are connected in parallel and operated from the inference device 14.

The semiconductor device selection unit 18 determines whether or not multiple candidate semiconductor devices can be mounted in a power semiconductor module based on the acquired data on failures. For example, when the acquired data on failures represents a failure rate, the semiconductor device selection unit 18 may determine that multiple candidate semiconductor devices can be mounted in a power semiconductor module when the failure rate is smaller than a specified reference value.

The mounting unit 19 mounts multiple candidate semiconductor devices that have been determined to be mountable onto the power semiconductor module.

Figure 9 is a flowchart showing a method for manufacturing a power semiconductor module in which multiple semiconductor devices are connected in parallel according to the first embodiment.

In step S101, the data acquisition unit 5 of the learning device 8 acquires learning data consisting of input data including characteristic data of each of the multiple semiconductor devices and calculation data obtained by calculating the characteristic data of each of the multiple semiconductor devices, and teacher data including data on failures during the initial failure period and random failure period when the multiple semiconductor devices are connected in parallel and operated.

In step S102, the model generation unit 6 of the learning device 8 uses the learning data to generate a trained model for inferring data about failures in the initial failure period and random failure period when multiple semiconductor devices are connected in parallel and operated, from input data including characteristic data of each of the multiple semiconductor devices and calculation data obtained by calculating each characteristic data. The model generation unit 6 stores the generated trained model in the trained model storage unit 7.

In step S103, the data acquisition unit 12 of the inference device 14 acquires input data including characteristic data for each of multiple candidate semiconductor devices to be mounted on the power semiconductor module and calculation data obtained by calculating each characteristic data.

In step S104, the inference unit 13 of the inference device 14 uses the learned model stored in the learned model storage unit 7 to infer data about failures during the initial failure period and random failure period when multiple candidate semiconductor devices are connected in parallel and operated from the input data acquired by the data acquisition unit 12.

In step S105, the semiconductor device selection unit 18 of the mounting device 51 determines whether the multiple candidate semiconductor devices can be mounted on the power semiconductor module based on the data about the inferred failure. If they can be mounted, the mounting unit 19 of the mounting device 51 mounts the multiple candidate semiconductor devices on the power semiconductor module.

As described above, according to this embodiment, a trained model of supervised learning is used to infer data on failures during the initial failure period and random failure period when multiple semiconductor devices are connected in parallel and operated from the characteristic data of multiple semiconductor devices and the calculation data of the characteristic data of multiple semiconductor devices. This makes it possible to select a combination of multiple semiconductor devices connected in parallel that is less likely to cause failures, thereby making it possible to manufacture a power semiconductor module that is less likely to cause failures.

Embodiment 2.
FIG. 10 is a diagram showing the configuration of a learning device 8A according to the second embodiment.

The learning device 8A of the second embodiment differs from the learning device 8 of the first embodiment in that the learning device 8A of the second embodiment includes a data placement unit 32 and a model generation unit 6A instead of the model generation unit 6.

The data placement unit 32 places the characteristic data of each of the multiple semiconductor devices included in the learning data acquired by the data acquisition unit 5, the calculation data obtained by calculating each of the characteristic data, and the teacher data on the same record. The same record may be, for example, the same row in a tabular data format.

FIG. 11 is a diagram showing an example of data arrangement in data arrangement unit 32 of learning device 8A.
As shown in FIG. 11 , for example, when learning about a combination of semiconductor devices A, B, and C, the data including characteristic data of semiconductor device A, characteristic data of semiconductor device B, characteristic data of semiconductor device C, calculation data of the characteristic data of semiconductor devices A, B, and C, and data representing faults when semiconductor devices A, B, and C are connected in parallel and operated are arranged on the same record.

By arranging in this manner, domain knowledge that contributes to the current imbalance (failure) of a power semiconductor module, such as a proportional relationship such as the transfer characteristic data 1 being proportional to the transfer characteristic data M, or a trade-off relationship such as the transfer characteristic data M being small if the output characteristic data L is large, is intentionally provided to the learning device, thereby reducing the amount of data required to obtain a given prediction accuracy, i.e., improving the prediction accuracy of the current imbalance (failure) for the same amount of data.

Another advantage is that placing this data in the same record makes it easier to implement machine learning models using the library.

The model generation unit 6A generates a trained model in the same manner as in embodiment 1, using the training data arranged on the same record.

FIG. 12 is a diagram showing the configuration of an inference device 14A according to the second embodiment.
The inference device 14A of embodiment 2 differs from the inference device 14 of embodiment 1 in that the inference device 14A of embodiment 2 is equipped with a data placement unit 33 and an inference unit 13A instead of the inference unit 13.

The data placement unit 33 places, on the same record, the characteristic data of each of the multiple semiconductor devices that are candidates for inclusion in the power semiconductor module and that are included in the input data acquired by the data acquisition unit 12, and the calculation data obtained by calculating each of the characteristic data.

The inference unit 13A uses input data arranged on the same record to infer data about failures during the initial failure period and random failure period when multiple candidate semiconductor devices are connected in parallel and operated, in the same manner as in embodiment 1.

Figure 13 shows an example of data placement by the data placement unit 33 of the inference device 14A.

As shown in FIG. 13, for example, when checking the suitability of a combination of semiconductor devices A, B, and C, the characteristic data of semiconductor device A, the characteristic data of semiconductor device B, the characteristic data of semiconductor device C, and the calculation data of the characteristic data of semiconductor devices A, B, and C are arranged on the same record.

Figure 14 is a flowchart showing a method for manufacturing a power semiconductor module in which multiple semiconductor devices are connected in parallel in the second embodiment.

In step S101, the data acquisition unit 5 of the learning device 8 acquires learning data consisting of input data including characteristic data of each of the multiple semiconductor devices and calculation data obtained by calculating the characteristic data of each of the multiple semiconductor devices, and teacher data including data on failures during the initial failure period and random failure period when the multiple semiconductor devices are connected in parallel and operated.

In step S201, the data placement unit 32 places the characteristic data of each of the multiple semiconductor devices included in the learning data acquired by the data acquisition unit 5, the calculation data obtained by calculating each of the characteristic data, and the teacher data on the same record.

In step S202, the model generation unit 6 of the learning device 8 uses the learning data arranged on the same record to generate a trained model for inferring data about failures in the initial failure period and random failure period when multiple semiconductor devices are connected in parallel and operated, from input data including characteristic data of each of the multiple semiconductor devices and calculation data obtained by calculating each characteristic data. The model generation unit 6 stores the generated trained model in the trained model storage unit 7.

In step S103, the data acquisition unit 12 of the inference device 14 acquires input data including characteristic data for each of multiple candidate semiconductor devices to be mounted on the power semiconductor module and calculation data obtained by calculating each characteristic data.

In step S203, the data placement unit 33 places, on the same record, the characteristic data of each of the multiple semiconductor devices that are candidates for mounting on the power semiconductor module and that are included in the input data acquired by the data acquisition unit 12, and the calculation data obtained by calculating each of the characteristic data.

In step S204, the inference unit 13 of the inference device 14 uses the learned model stored in the learned model storage unit 7 to infer data about failures during the initial failure period and random failure period when multiple candidate semiconductor devices are connected in parallel and operated from the input data arranged on the same record.

In step S105, the semiconductor device selection unit 18 of the mounting device 51 determines whether the multiple candidate semiconductor devices can be mounted on the power semiconductor module based on the data about the inferred failure. If they can be mounted, the mounting unit 19 of the mounting device 51 mounts the multiple candidate semiconductor devices on the power semiconductor module.

Embodiment 3.
In the third embodiment, an unsupervised learning algorithm is used as the learning algorithm.

FIG. 15 is a diagram showing the configuration of a learning device 8B according to the third embodiment.
The learning device 8B of embodiment 3 differs from the learning device 8 of embodiment 1 in that the learning device 8B of embodiment 3 has a data acquisition unit 5B and a model generation unit 6B instead of the data acquisition unit 5 and the model generation unit 6.

The data acquisition unit 5B acquires learning data consisting of input data including characteristic data of each of a plurality of semiconductor devices constituting a normal power semiconductor module that did not fail during the initial failure period and the random failure period, and calculation data obtained by calculating each of the characteristic data.

The model generation unit 6B uses the learning data acquired by the data acquisition unit 5B to generate a trained model for classifying input data, including characteristic data of each of a plurality of semiconductor devices constituting a normal power semiconductor module that did not fail during the initial failure period and the random failure period, and calculation data obtained by calculating each characteristic data, into one of a plurality of clusters through unsupervised learning.

In a power semiconductor module consisting of multiple semiconductor devices connected in parallel, if a particular one of the semiconductor devices has low output characteristics, low transfer characteristics, high leakage characteristics, or an abnormally different correlation between output characteristics and transfer characteristics compared to the other semiconductor devices, the current imbalance of the power semiconductor module becomes abnormal. As a result, it is known that the power semiconductor module fails during the initial failure period and the random failure period.

Therefore, by unsupervised learning, a trained model can be generated for classifying input data, which includes characteristic data of each of a plurality of semiconductor devices constituting a normal power semiconductor module that did not fail during the initial failure period and the random failure period, and calculation data obtained by calculating each of the characteristic data, into one of a plurality of clusters.

As an example of a case where the learning algorithm used by the model generation unit 6B is unsupervised learning, a case where K-means (clustering) is applied will be described. Unsupervised learning refers to a method of learning features in learning data that does not contain results (labels) by providing the learning device with the learning data. Note that the unsupervised learning algorithm is not limited to this embodiment, and a model may be generated according to other known machine learning algorithms capable of clustering, such as OneClassSVM or LOF (Local Outlier Factor).

The model generation unit 6B performs so-called unsupervised learning, for example, according to a grouping method using the K-means method. The K-means method is a non-hierarchical clustering algorithm that uses the cluster average to classify a given number of clusters into k.

Specifically, the K-means algorithm is processed as follows. First, a cluster is randomly assigned to each data x i . Next, the center V j of each cluster is calculated based on the assigned data. Next, the distance between each x i and each V j is found, and x i is reassigned to the closest central cluster. Then, if the cluster assignment for all x i has not changed in the above process, or if the amount of change falls below a certain threshold value set in advance, it is determined that convergence has occurred and the process ends. In this way, clusters C j (j = 1 to k) are generated.

The model generation unit 6B generates a trained model by performing the above-mentioned learning and outputs it to the trained model storage unit 7.

FIG. 16 is a diagram showing the configuration of an inference device 14B according to the third embodiment.
The inference device 14B of the third embodiment differs from the inference device 14 of the first embodiment in that the inference device 14B of the third embodiment includes an inference unit 13B instead of the inference unit 13.

The inference unit 13B uses the learned model stored in the learned model storage unit 7 to classify the input data acquired by the data acquisition unit 12 into one of the multiple clusters generated by unsupervised learning, or into other than the multiple clusters. For example, it is assumed that a distance di from the center of the cluster Cj to the farthest data is set for the cluster Cj. The cluster closest to the input data acquired by the data acquisition unit 12 is assumed to be the cluster Cs. The inference unit 13B may determine that the input data belongs to the cluster Cs when the distance between the input data and the center of the cluster Cs is equal to or less than ds. The inference unit 13B may determine that the input data does not belong to any of the clusters C1 to Ck when the distance between the input data and the center of the cluster Cs exceeds ds.

FIG. 17 is a diagram showing the configuration of a mounting device 51B according to the third embodiment.
The mounting device 51B of the third embodiment differs from the mounting device 51 of the first embodiment in that the mounting device 51B of the third embodiment includes a semiconductor device selection unit 18B instead of the semiconductor device selection unit 18.

The semiconductor device selection unit 18B reads input data from the conversion information storage unit 27, which is composed of characteristic data of multiple semiconductor devices corresponding to the individual identification information of multiple candidate semiconductor devices to be mounted on the power semiconductor module, and calculation data obtained by calculating the characteristic data of the multiple semiconductor devices, and sends the input data to the inference device 14B. The semiconductor device selection unit 18B obtains a classification result of the input data from the inference device 14B into one of the multiple clusters generated by unsupervised learning, or into other than the multiple clusters.

The semiconductor device selection unit 18B determines whether or not multiple candidate semiconductor devices can be mounted on a power semiconductor module based on the classification results.

For example, if the input data belongs to any of multiple clusters generated by unsupervised learning, the semiconductor device selection unit 18B determines that multiple candidate semiconductor devices can be mounted on a power semiconductor module. This is because it is possible to predict that no failures will occur in the power semiconductor module during the initial failure period and the random failure period when multiple candidate semiconductor devices are connected in parallel and operated.

When the input data does not belong to any of the multiple clusters generated by unsupervised learning, the semiconductor device selection unit 18B determines that the multiple candidate semiconductor devices cannot be mounted on the power semiconductor module. This is because it is possible to predict that failures will occur in the power semiconductor module during the initial failure period and the random failure period if the multiple candidate semiconductor devices are connected in parallel and operated.

Figure 18 is a flowchart showing a method for manufacturing a power semiconductor module in which multiple semiconductor devices are connected in parallel in the third embodiment.

In step S301, the data acquisition unit 5B of the learning device 8B acquires learning data consisting of input data including characteristic data of each of the multiple semiconductor devices and calculation data obtained by calculating each characteristic data.

In step S302, the model generation unit 6B of the learning device 8B uses the learning data acquired by the data acquisition unit 5B to generate a trained model for classifying input data, including characteristic data of each of a plurality of semiconductor devices constituting a normal power semiconductor module that did not fail during the initial failure period and the random failure period, and calculation data obtained by calculating each of the characteristic data, into one of a plurality of clusters through unsupervised learning. The model generation unit 6B stores the generated trained model in the trained model storage unit 7.

In step S303, the data acquisition unit 12 of the inference device 14B acquires input data including characteristic data for each of a plurality of candidate semiconductor devices to be mounted on the power semiconductor module and calculation data obtained by calculating each characteristic data.

In step S304, the inference unit 13B of the inference device 14B uses the learned model stored in the learned model storage unit 7 to classify the input data acquired by the data acquisition unit 12 into one of the multiple clusters generated by unsupervised learning, or into other than the multiple clusters.

In step S305, the semiconductor device selection unit 18B of the mounting device 51B determines whether the multiple candidate semiconductor devices can be mounted on the power semiconductor module based on the classification results. If they can be mounted, the mounting unit 19 of the mounting device 51B mounts the multiple candidate semiconductor devices on the power semiconductor module.

As described above, according to this embodiment, a trained model of unsupervised learning is used to infer data on failures during the initial failure period and random failure period when multiple semiconductor devices are connected in parallel and operated from the characteristic data of multiple semiconductor devices and the calculation data of the characteristic data of multiple semiconductor devices. This makes it possible to select a combination of multiple semiconductor devices connected in parallel that is less likely to cause failures, thereby making it possible to manufacture a power semiconductor module that is less likely to cause failures.

The learning device, inference device, and on-board device described in the first to third embodiments may have their corresponding operations configured using digital circuit hardware or software.

Figure 19 shows a configuration in which the functions of the learning device, control device, and on-board device are realized using software.

The system includes a processor 5002 and a memory 5001 connected to a bus 5003. The processor 5002 executes a program stored in the memory 5001.

The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is indicated by the claims rather than the above description, and is intended to include all modifications within the meaning and scope of the claims.

1 Drive device, 2 Power semiconductor module manufacturing device, 5, 5B, 12 Data acquisition unit, 6, 6A, 6B Model generation unit, 7 Learned model storage unit, 8, 8A, 8B Learning device, 10 Battery, 13, 13A, 13B Inference unit, 14, 14A, 14B Inference device, 18, 18B Semiconductor device selection unit, 19 Mounting unit, 20 Converter, 27 Conversion information storage unit, 30 Inverter, 32, 33 Data placement unit, 40 Motor, 51, 51B Mounting device, 5001 Memory, 5002 Processor, 5003 Bus, D1A, D1B, D1, D2A, D2B, D2 Diode, L1 Reactor, Q1A, Q1, Q1B, Q2, Q2A, Q2B Switching element.

Claims (14)

A method for manufacturing a power semiconductor module configured by connecting a plurality of semiconductor devices in parallel, comprising the steps of:
a learning data acquiring step of acquiring learning data including input data including characteristic data of each of a plurality of semiconductor devices and calculation data obtained by calculating the characteristic data of each of the semiconductor devices, and teacher data including data on failures in an early failure period and a random failure period when the plurality of semiconductor devices are connected in parallel and operated;
generating a trained model for inferring data on failures in an early failure period and a random failure period when the plurality of semiconductor devices are connected in parallel and operated, from input data including characteristic data of each of the plurality of semiconductor devices and operation data obtained by operating the characteristic data of each of the plurality of semiconductor devices, using the training data;
an input data acquisition step of acquiring input data including characteristic data of each of a plurality of candidate semiconductor devices to be mounted on the power semiconductor module and calculation data obtained by calculating the characteristic data of each of the candidate semiconductor devices;
a step of inferring data on failures in an early failure period and a random failure period when the plurality of candidate semiconductor devices are connected in parallel and operated from the input data acquired in the input data acquisition step, using the trained model;
determining whether the plurality of candidate semiconductor devices can be mounted on a power semiconductor module based on data on the inferred failure;
A method for manufacturing a power semiconductor module comprising the steps of: The method for manufacturing a power semiconductor module according to claim 1, wherein the characteristic data includes output characteristic data of one or more of the semiconductor devices. The method for manufacturing a power semiconductor module according to claim 1, wherein the characteristic data includes transmission characteristic data of one or more of the semiconductor devices. The method for manufacturing a power semiconductor module according to claim 1, wherein the characteristic data includes leakage characteristic data of one or more of the semiconductor devices. The method for manufacturing a power semiconductor module according to claim 1, wherein the characteristic data includes manufacturing information for one or more of the semiconductor devices. The method for manufacturing a power semiconductor module according to claim 1, wherein the calculation data is an average value or standard deviation of a plurality of the characteristic data obtained by arithmetic calculation of each of the characteristic data. The method for manufacturing a power semiconductor module according to claim 1, wherein the calculation data is a maximum or minimum value of a plurality of the characteristic data obtained by a comparison calculation of each of the characteristic data. The method for manufacturing a power semiconductor module according to claim 1, wherein the data about the failure is data indicating the presence or absence of a failure. The method for manufacturing a power semiconductor module according to claim 1, wherein the data on failures is data representing a failure rate. a step of arranging, on the same record, characteristic data of each of the plurality of semiconductor devices included in the learning data acquired in the step of acquiring the learning data, calculation data obtained by calculating each of the characteristic data, and the teacher data;
In the step of generating the trained model, the arranged training data is used,
a step of arranging, on the same record, characteristic data of each of a plurality of candidate semiconductor devices to be mounted on the power semiconductor module, the characteristic data being included in the input data acquired in the step of acquiring the input data, and calculation data obtained by calculating the characteristic data of each of the candidate semiconductor devices;
10. The method for manufacturing a power semiconductor module according to claim 1, wherein the inferring step uses the arranged input data. A method for manufacturing a power semiconductor module configured by connecting a plurality of semiconductor devices in parallel, comprising the steps of:
a learning data acquisition step of acquiring learning data consisting of input data including characteristic data of each of a plurality of normal semiconductor devices constituting a normal power semiconductor module that did not fail during the initial failure period and the random failure period, and calculation data obtained by calculating the characteristic data of each of the normal semiconductor devices;
generating a trained model for classifying input data, including characteristic data of each of a plurality of normal semiconductor devices and operation data obtained by operation of each of the characteristic data, into one of a plurality of clusters, using the training data;
an input data acquisition step of acquiring input data including characteristic data of each of a plurality of candidate semiconductor devices to be mounted on the power semiconductor module and calculation data obtained by calculating each of the characteristic data;
A step of classifying the input data acquired in the input data acquisition step into any one of a plurality of clusters or into other than the plurality of clusters by using the trained model;
determining whether or not the plurality of candidate semiconductor devices can be mounted on a power semiconductor module based on a result of the classification;
A method for manufacturing a power semiconductor module comprising the steps of: A manufacturing apparatus for a power semiconductor module configured by connecting a plurality of semiconductor devices in parallel,
A learning device;
an inference device;
The learning device includes:
a data acquisition unit that acquires learning data including input data including characteristic data of each of a plurality of semiconductor devices and calculation data obtained by calculating the characteristic data of each of the plurality of semiconductor devices, and teacher data including data on failures in an early failure period and an accidental failure period when the plurality of semiconductor devices are connected in parallel and operated;
a model generation unit that uses the learning data to generate a trained model for inferring data on failures in an early failure period and a random failure period when the plurality of semiconductor devices are connected in parallel and operated, from input data including characteristic data of each of the plurality of semiconductor devices and calculation data obtained by calculating the characteristic data of each of the plurality of semiconductor devices;
The inference device comprises:
a data acquisition unit that acquires input data including characteristic data of each of a plurality of candidate semiconductor devices to be mounted on the power semiconductor module and calculation data obtained by calculating each of the characteristic data;
an inference unit that uses the learned model to infer data about failures in an early failure period and a random failure period when the plurality of candidate semiconductor devices are connected in parallel and operated from input data acquired by the data acquisition unit of the inference device ,
The power semiconductor module manufacturing apparatus further comprises:
a mounting device that determines whether or not the plurality of candidate semiconductor devices can be mounted on a power semiconductor module based on data on the failure inferred by the inference device;
A power semiconductor module manufacturing apparatus comprising: a data acquisition unit that acquires learning data including input data including characteristic data of each of a plurality of semiconductor devices and calculation data obtained by calculating the characteristic data of each of the plurality of semiconductor devices, and teacher data including data on failures in an early failure period and an accidental failure period when the plurality of semiconductor devices are connected in parallel and operated;
a model generation unit that uses the learning data to generate a trained model for inferring data on failures in an early failure period and a random failure period when the plurality of semiconductor devices are connected in parallel and operated, from input data including characteristic data of each of the plurality of semiconductor devices and calculation data obtained by calculating the characteristic data of each of the plurality of semiconductor devices;
A learning device comprising: a data acquisition unit that acquires input data including characteristic data of each of a plurality of candidate semiconductor devices to be mounted on the power semiconductor module and calculation data obtained by calculating the characteristic data;
an inference unit that infers, from the input data input from the data acquisition unit, data on failures in the early failure period and the random failure period when the multiple semiconductor devices are connected in parallel and operated, using a trained model for inferring data on failures in the early failure period and the random failure period when the multiple semiconductor devices are connected in parallel and operated, from input data including characteristic data of each of the multiple semiconductor devices and operation data obtained by operating the characteristic data of each of the multiple semiconductor devices;
An inference device comprising:

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