JP7586587B2 - Memory Cell Structure - Google Patents

Description

The present invention relates to a memory cell structure, and in particular to a memory cell structure having a denser structure, a smaller area, a lower leakage current, a higher capacitance, etc.

One of the most important volatile memory integrated circuits is the DRAM (Dynamic Random Access Memory) with 1T1C memory cells, which not only offers the best cost-performance capabilities as main memory and/or buffer memory for computing and communication applications, but also serves as the best driver of technology scaling down to maintain Moore's Law by shrinking the minimum feature size on silicon from a few micrometers to around 20 nanometers. Recently, logic technology, which continues to use embedded SRAM (Static Random Access Memory) as a scaling down driver, has made a claim to bring the achievement of the leading edge technology node near 5 nanometers to manufacturing. In comparison, the best claim of the technology node of DRAM is still above 10-12 nanometers. The main problem is that the structure of 1T1C memory cells is very difficult to scale further, even with very challenging design rules, scaled access transistor (i.e. 1T) design, and the use of three-dimensional storage capacitors (i.e. 1C), such as stacked capacitors or very deep trench capacitors on parts of the access transistor and isolation region.

Difficulties with 1T1C memory cells are well known issues with huge funding and R&D investments in technology, design and equipment, but they are detailed here. Some examples of difficulties are: (1) the structure of the access transistor suffers from unavoidable and more serious current leakage problems that degrade the 1T1C memory cell storage function, for example shortening the DRAM refresh time; (2) the complexity of placing the word lines, bit lines and storage capacitors on those geometric and topographic structures, as well as the connections to the gate, source and drain of the access transistor, becomes even worse due to scaling down; (3) trench capacitors suffer from excessive aspect ratios of depth to opening size, and are almost stuck at the 14 nm node; (4) stacked capacitors suffer from topography degradation, and there is almost no space for contact space between the storage capacitor and the source of the access transistor after twisting the active area from 20 degrees to over 50 degrees. Furthermore, the space allowed for the bit line contact to the drain of the access transistor is becoming much smaller, yet we still have to struggle to maintain self-alignment, (5) the worsening leakage current problem will require us to continue to increase the height of the capacitor to increase capacitance and have a larger capacitance area unless we can find a much higher-k dielectric insulator material for the storage capacitance, (6) without a technology breakthrough to solve the above problems, it will become increasingly difficult to meet all of the increasing demands for better reliability, quality and resilience of DRAM chips that increasingly demand higher density/capacity and performance, etc.

The present invention provides a new HCoT (H-shaped capacitor (i.e., 1C) placed directly above the access transistor (i.e., 1T) to clamp it) using a process to implement a 1T-1C memory cell structure.

One embodiment of the present invention provides a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, the transistor including a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, the capacitor overlies the transistor, and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery within which the transistor is disposed.

According to another aspect of the present invention, the storage electrode has an outer periphery, and the transistor is disposed within the outer periphery.

According to another aspect of the invention, the capacitor further includes a counter electrode covering the transistor.

According to another aspect of the invention, the memory cell structure further includes a bit line electrically coupled to the first conductive region of the transistor, the bit line being located below the silicon surface.

According to another aspect of the invention, the memory cell structure further includes a bit line electrically coupled to the first conductive region of the transistor through a bridge contact, the bridge contact being located below the silicon surface, a first sidewall of the bridge contact being aligned with an edge of the bit line, the bridge contact having an upper portion and a lower portion, the upper portion of the bridge contact abutting the silicon substrate and the lower portion of the bridge contact being spaced from the silicon substrate by a first isolation layer.

According to another aspect of the present invention, the capacitor includes a first protruding region, a second protruding region, and a connection region, the connection region being above a gate structure of a transistor and connecting the first protruding region and the second protruding region, and confining the transistor with the first protruding region and the second protruding region.

According to another aspect of the invention, the transistor further includes a first spacer covering a first side of the gate structure and located above the silicon surface, and a second spacer covering a second side of the gate structure and located above the silicon surface, a second protruding region of the capacitor extends upward from the silicon surface and abuts the second spacer, and a first protruding region of the capacitor abuts the first spacer and extends upward from an isolation region on the silicon surface.

Another embodiment of the present invention provides a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, the transistor including a gate structure, a first conductive region, and a second conductive region. The capacitor is electrically coupled to the second conductive region of the transistor, the capacitor completely covering the transistor.

According to another aspect of the invention, the capacitor includes a storage electrode including a first protruding region, a second protruding region, and a connection region vertically stacked on a top surface of the transistor to connect the first protruding region and the second protruding region, the second protruding region connecting to a second conductive region of the transistor.

According to another aspect of the present invention, the transistor is clamped by the first protruding region and the second protruding region.

According to another aspect of the present invention, the memory cell structure further includes a counter electrode, a plurality of first transistors, and a plurality of first storage electrodes respectively corresponding to the plurality of first transistors, the counter electrode covering the plurality of first transistors and the plurality of first storage electrodes, and the counter electrode being coupled to a first voltage source.

According to another aspect of the invention, the memory cell structure further includes a bit line electrically coupled to the first conductive region of the transistor, the bit line being located below the silicon surface and electrically coupled to the first conductive region of the transistor via a bridge contact.

According to another aspect of the invention, the bridge contact is located below the silicon surface and a first sidewall of the bridge contact is aligned with an edge of the bitline.

According to another aspect of the present invention, the bridge contact includes an upper portion and a lower portion, the upper portion of the bridge contact abutting the silicon substrate and the lower portion of the bridge contact being separated from the silicon substrate by a first isolation layer.

According to another aspect of the invention, the transistor further includes a first spacer and a second spacer, the first spacer covering a first side of the gate structure and located above the silicon surface, and the second spacer covering a second side of the gate structure and located above the silicon surface. A second protruding region of the storage electrode extends upward from the silicon surface and abuts the second spacer, and a first protruding region of the storage electrode abuts the second spacer and extends upward from an isolation region on the silicon surface.

According to another aspect of the invention, the top surface of the first protruding region is rectangular in shape and the top surface of the second protruding region is another rectangular in shape.

Another embodiment of the present invention provides a memory cell structure including a cell region and an inner region within the cell region. The memory cell structure includes a transistor and a capacitor. The transistor is within the inner region. The capacitor is within the cell region, the capacitor including a plurality of protruding regions and a connection region, the connection region being above the transistor and connecting the plurality of protruding regions.

According to another aspect of the invention, the cell regions are rectangular in shape and the top surface of one protruding region is another rectangular in shape.

According to another aspect of the invention, a transistor includes a gate structure, a cap isolation layer over the gate structure, a first conductive region, and a second conductive region, and a first of the plurality of protruding regions extends upward and downward from a top surface of the cap isolation layer.

According to another aspect of the present invention, a second protruding region of the plurality of protruding regions extends upward and downward from the top surface of the cap isolation layer, and the second protruding region connects to a second conductive region of the transistor.

According to another aspect of the present invention, the multiple protruding regions confine the transistor.

Another embodiment of the present invention provides a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface and includes a gate structure, a cap isolation layer over the gate structure, a first conductive region, and a second conductive region. The capacitor is electrically coupled to the second conductive region of the transistor, the capacitor overlies the transistor, and has a capacitor periphery that is rectangular in shape.

According to another aspect of the invention, the transistor is positioned within the outer edge of the capacitor.

According to another aspect of the present invention, the capacitor further includes a storage electrode, the storage electrode including a first protruding region, a second protruding region, and a connection region on the cap isolation layer connecting the first protruding region and the second protruding region, the first protruding region and the second protruding region extending upward and downward from a top surface of the cap isolation layer.

According to another aspect of the invention, the first protruding region extends upward from the top surface of the cap isolation layer to a position higher than the connection region, and extends downward from the top surface of the cap isolation layer to an isolation region on the silicon surface.

According to another aspect of the invention, the second protruding region extends upward from the top surface of the cap isolation layer to another location higher than the connection region, and extends downward from the top surface of the cap isolation layer to the silicon surface.

Another embodiment of the present invention provides a memory cell structure. The memory cell structure includes a counter electrode, a plurality of first transistors, and a plurality of first storage electrodes. The plurality of first storage electrodes correspond to the plurality of first transistors, respectively, and a counter electrode covers the plurality of first transistors and the plurality of first storage electrodes, and the counter electrode is coupled to a first voltage source.

These and other objects of the present invention will no doubt become obvious to those skilled in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

2 is a flow chart showing a method for manufacturing a DRAM cell (1T1C cell) array according to one embodiment of the present invention. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. FIG. 13 shows a top view and a cross-sectional view along the X direction after pad nitride and pad oxide layers are deposited and STI is formed. FIG. 13 shows depositing and etch-back a nitride 1 layer to form nitride 1 spacers, and depositing an SOD and photoresist layer. FIG. 13 shows etching away the top edge nitride 1 spacers and SOD that are not covered by the photoresist layer. FIG. 13 shows stripping the photoresist layer and SOD and depositing an oxide 1 layer. FIG. 2 shows that a metal layer is deposited in the trench and planarized by CMP techniques. FIG. 2 shows that a photoresist layer is deposited. FIG. 13 shows that the metal layer corresponding to the edge of the active area is etched. FIG. 13 shows the photoresist layer being removed and the metal layer being etched to form underground bitlines. FIG. 1 shows that an oxide 2 layer is deposited in the trench. FIG. 2 shows that an oxide 3 layer, a nitride 2 layer, and photoresist are deposited, and then unwanted portions of the oxide 3 layer, nitride 2 layer, and photoresist are removed. FIG. 1 shows that the photoresist layer, the pad nitride layer, and the pad oxide layer are removed. FIG. 13 shows a U-shaped recess being created, a high-k insulator layer being formed as the gate dielectric layer for the access transistor, and a gate material being deposited and then etched back to form the word line and gate structure for the access transistor. FIG. 1 shows a nitride 3 layer and an oxide 4 layer being deposited, and then the nitride 3 layer and the oxide 4 layer being polished. FIG. 1 shows that the nitride 2 layer and the oxide 3 layer are etched away. The pad nitride layer 206 is removed, the CVD-STI-oxide 2 is etched back, and then nitride 4, oxide 5 and polysilicon 1 layers are deposited and etched. FIG. 2 shows that SOD is deposited and polished, a portion of the top of the polysilicon 1 layer is etched, and then a cap oxide 1 layer is deposited and planarized. FIG. 18 shows that the SOD is etched away and a nitride 5 layer 1802 is deposited. FIG. 1 shows that SOD is deposited, photoresist is deposited, and then the SOD corresponding to the areas reserved for the source regions is removed. FIG. 13 shows the exposed nitride 5 layer and pad oxide layer in the center of the source region being etched away and the silicon material corresponding to the center of the source region being excavated to create a hole 1/3. FIG. 13 shows oxide 7 layer thermally grown in hole 1/3. FIG. 2 shows another SOD layer being deposited and etched back. FIG. 13 shows that photoresist is deposited to cover the area corresponding to the source region and expose the area reserved for the drain region, and then the exposed SOD, exposed nitride 5 layer, exposed pad oxide layer underneath, and silicon material are removed to create hole 1/2. FIG. 13 shows the photoresist is removed and an oxide 8 layer is thermally grown to create oxide 8 spacers. FIG. 13 is a cross-sectional view of the DRAM cell array taken along the Y2 direction, showing a cross section of a half hole. FIG. 13 shows that the bottom edge nitride 1 spacer inside the hole 1/2 is etched. FIG. 1 shows that the nitride 5 layer is removed. FIG. 13 shows a metal layer is deposited and etched back to leave a tungsten plug inside the hole 1/2, and a nitride 6 layer is deposited and etched. FIG. 13 shows that a portion of the top of the tungsten plug below the HSS is etched back. FIG. 13 shows a tungsten plug being connected to a UGBL. FIG. 13 shows the top part of the oxide 8 layer is removed. FIG. 13 shows that an n+ in-situ doped silicon layer is grown laterally to form an n+ silicon drain collar. FIG. 13 shows an oxide 9 layer thermally grown locally on top of the n+ silicon drain collar. FIG. 1 shows that the oxide 9 layer is etched back and then a polysilicon a layer is deposited and etched back. FIG. 13 shows that the nitride 6 spacers are removed and a polysilicon b layer is deposited and etched back. FIG. 1 shows that all SOD and nitride 5 layers are removed. FIG. 1 shows a top view of the structure of an HCoT cell array. FIG. 13 shows that a metal layer is deposited and portions of the metal layer are etched back to form W buffer walls. FIG. 13 shows that the cap oxide 1 layer, polysilicon 1 spacer, and pad oxide layer are removed to expose the HSS corresponding to the source and drain regions. FIG. 1 shows that an elevated source electrode EH-1S and an elevated drain electrode EH-1D are grown. FIG. 13 shows a post-RTA (rapid temperature annealing) step to form a better electrical connection between the elevated source electrode EH-1S (or the elevated drain electrode EH-1D) and the channel region of the transistor. FIG. 13 shows that the oxide 5 spacers are etched and then the oxide a-layer is thermally grown and etched. FIG. 1 shows that an elevated source electrode EH-2S and an elevated drain electrode EH-2D are grown. FIG. 2 shows that a thick SOD-1 layer is deposited and etched back. FIG. 13 shows that the WBW is etched away. FIG. 2 shows that a nitride a-layer is deposited and etched using an anisotropic etching technique. FIG. 13 shows that the polysilicon a layer and the polysilicon b layer are removed, and a bottom portion of a portion of the elevated drain electrode EH-1D is removed. FIG. 1 shows that the oxide bb layer is thermally grown. FIG. 1 shows that the nitride a-spacers and the SOD-1 layer are removed. FIG. 1 shows that one layer of high-k dielectric insulator is formed. FIG. 2 shows a metal layer being deposited and etched back. FIG. 2 shows that the high-k dielectric insulator 1 metal layer over the oxide 4 layer is removed, and then the oxide 4 layer is etched away. FIG. 13 shows that the top of the nitride 3 layer is removed, and that the tops of the nitride 4 spacers are also removed. FIG. 1 shows that LGS-2S and LGS-2D are grown laterally. FIG. 1 shows that a nitride cc-layer is deposited and then LGS-2D, LGS-2S and the nitride cc-layer is polished by CMP technique. FIG. 1 shows that MCEPW-1 is eliminated. FIG. 13 shows that a twin-tower storage electrode for a storage capacitor is grown by using the exposed LGS-2D and exposed LGS-2S as seeds. FIG. 2 shows that an oxide d-layer is thermally grown and anisotropically etched. FIG. 2 shows that an n+ in-situ doped silicon layer is grown laterally and vertically. FIG. 1 shows that the oxide d-spacers are removed. FIG. 1 shows that high-k dielectric insulator 1 is removed and high-k dielectric insulator 2 is formed. FIG. 2 shows that a metal layer is deposited and polished by CMP techniques. FIG. 1 shows that MCEPW-2 is etched back and the high-k dielectric insulator 2 on top of STSEC-1 is etched away. FIG. 1 shows how, by using the exposed silicon material on STSEC-1 as a seed, a taller n+ in-situ doped silicon tower is grown as the storage electrode of the storage capacitor, high-k dielectric insulator 2 is etched, and high-k dielectric insulator 3 is formed. FIG. 2 shows the formation of photoresist. FIG. 1 shows that the high-k dielectric insulator 3 on the exposed edge regions of MCEPW-2 is etched away. FIG. 2 shows the photoresist being removed. FIG. 13 shows that a metal layer is deposited to complete the counter electrode plate of the storage capacitor. FIG. 1 shows a schematic structure of a new HCoT cell. FIG. 1 shows a simplified top view of an HCoT cell.

Please refer to Figures 1A-1F, Figure 1A is a flow chart illustrating a method for fabricating an HCoT cell array according to one embodiment of the present invention.
Step 10: Start.
Step 15: Based on a substrate (eg, a p-type silicon substrate), define the active area of the DRAM cell array and form a shallow trench isolation (STI).
Step 20: Form asymmetric spacers along the sidewalls of the active area.
Step 25: Form underground conductive lines (eg, bitlines, etc.) between the asymmetric spacers and below the horizontal silicon surface (HSS).
Step 30: Form the word lines and the gates of the access transistors of the DRAM cell array.
Step 35: Define the drain regions (ie, first conductive regions) and source regions (ie, second conductive regions) of the access transistors of the DRAM cell array.
Step 40: Form a connection between the underground bit line and the drain region of the access transistor.
Step 45: Form the drain and source regions.
Step 50: Form a capacitor tower over the access transistor.
Step 55: End.

See Figures 1B and 2. Step 15 may include:
Step 102: Deposit a pad oxide layer 204 and a pad nitride layer 206 on a horizontal silicon surface (hereinafter "HSS") 208 of a substrate.
Step 104: Defining the active areas of the DRAM cell array, and removing portions of the substrate material (eg, silicon material) corresponding to the horizontal silicon surfaces 208 outside the active areas to create trenches 210.
Step 106: Deposit an oxide layer 214 in the trench 210 and etch back the oxide layer 214 to form a shallow trench isolation (STI) below the horizontal silicon surface 208.

See Figure 1C and Figures 3-5. Step 20 may include:
Step 108: A nitride 1 layer is deposited and etched back to form nitride 1 spacers (FIG. 3).
Step 110: A spin-on dielectric (SOD) 304 is deposited in the trench 210 and planarized by chemical mechanical polishing (CMP) techniques (FIG. 3).
Step 112: A photoresist layer 306 is deposited over the SOD 304 and the pad nitride layer 206 (FIG. 3).
Step 114: The top edge nitride 1 spacers and SOD 304 not covered by photoresist layer 306 are etched away (FIG. 4).
Step 116: The photoresist layer 306 and SOD 304 are stripped and an oxide 1 layer 502 is grown, for example by thermal growth (FIG. 5).

See Figures ID and 6-10. Step 25 may include:
Step 118: A metal layer 602 is deposited in the trench 210 and planarized by CMP techniques (FIG. 6).
Step 120: A photoresist layer 702 is deposited and patterned (Figure 7).
Step 122: The metal layer 602 corresponding to the edges of the active areas is etched to form a plurality of conductive lines (FIG. 8).
Step 124: The photoresist layer 702 is removed and the metal layer 602 (the conductive lines) is etched back to form underground bit lines (UGBLs) 902 or underground conductive lines (FIG. 9).
Step 126: Oxide 2 layer 1002 is deposited in trench 210 and planarized by CMP techniques (FIG. 10).

See Figure 1E and Figures 11-15. Step 30 may include:
Step 128: A thick oxide 3 layer 1102, a thick nitride 2 layer 1104, and a patterned photoresist layer 1106 are deposited, and then unwanted portions of the oxide 3 layer 1102 and nitride 2 layer 1104 are etched or removed (FIG. 11).
Step 130: The patterned photoresist layer 1106, the pad nitride layer 206, and the pad oxide layer 204 may be removed to reveal the HSS (FIG. 12).
Step 132: The exposed HSS is etched to create a U-shaped recess, a high-k insulator layer 1304 is formed, and a gate material 1306 (such as tungsten) is deposited and then etched back to form the word line and gate structures of the access transistors (FIG. 13). Such access transistors may be referred to as U-transistors.
Step 134: Deposit nitride 3 layer 1402 and then etch back, followed by deposit oxide 4 layer 1404 and then etch back or planarize oxide 4 layer 1404 (Figure 14).
Step 136: Etch away nitride 2 layer 1104 and oxide 3 layer 1102 (Figure 15).

See Figure 1F and Figures 16-22. Step 35 may include:
Step 138: Remove pad nitride layer 206 and etch back CVD-STI-oxide 2 to the top of pad oxide layer 204.
Step 140: Deposit and anisotropically etch nitride 4 layer 1602, oxide 5 layer 1604, and polysilicon 1 layer 1606, respectively (Figure 16).
Step 142: Deposit spin-on dielectric (SOD) 1702 followed by CMP, etch the top of polysilicon 1 layer 1606, and deposit cap oxide 1 layer 1704 followed by CMP (FIG. 17).
Step 144: Remove SOD 1702 and then deposit nitride 5 layer 1802 (Figure 18).
Step 146: Deposit SOD 1902, then CMP, deposit photoresist 1904, then etch back the unwanted SOD 1902 (FIG. 19).
Step 148: Etch away the exposed nitride 5 layer 1802, pad oxide layer 204, and silicon material corresponding to HSS-1/3 to create hole 1/3 (FIG. 20).
Step 150: Remove photoresist 1904 and thermally grow oxide 7 layer 2102 (Figure 21).
Step 152: Deposit another SOD layer 2202 on the oxide 7 layer 2102, then etch back the another SOD layer 2202 (Figure 22).

See Figure 1G and Figures 23-33. Step 40 may include:
Step 154: Deposit photoresist 2302, remove exposed SOD 1902, exposed nitride 5 layer 1802, and exposed pad oxide layer 204, then excavate and remove silicon material corresponding to HSS-1/2 to create hole 1/2 (FIG. 23).
Step 156: The photoresist 2302 is removed and an oxide 8 layer 2402 is thermally grown (FIGS. 24 and 25).
Step 158: Remove bottom nitride 1 spacers to reveal the underground bitline sidewalls and remove nitride 5 layer 1802 (FIGS. 26 and 27).
Step 160: Deposit a metal layer 2802 into the holes 1/2 to contact the sidewalls of the UGBL, then deposit and etch back a nitride 6 layer 2804 to create nitride 6 spacers (FIG. 28).
Step 162: Etch back the top of metal layer 2802 (FIGS. 29 and 30).
Step 164: Etch back the top of oxide 8 layer 2402 to reveal the silicon material corresponding to hole 1/2 (FIG. 31).
Step 166: Based on the exposed silicon material, an n+ in-situ doped silicon layer 3202 is grown laterally to contact the drain region and the tungsten plug (FIG. 32).
Step 168: Thermally grow Oxide 9 layer 3302 on n+ in-situ doped silicon layer 3202 (Figure 33).

See Figure 1H and Figures 34-42. Step 45 may include:
Step 170: Etch back oxide 9 layer 3302 and deposit and etch back polysilicon a layer 3402 (FIG. 34).
Step 171: Remove the nitride 6 spacers and deposit and etch back polysilicon b layer 3502 (FIG. 35).
Step 172: Remove all SOD and Nitride 5 layers 1802 (Figure 36).
Step 173: Deposit and etch back metal layer (e.g., tungsten) 3802 (FIG. 38).
Step 174: Etch away cap oxide 1 layer 1704, polysilicon 1 spacers, and pad oxide layer 204 (FIG. 39).
Step 175: Grow both the elevated source electrode EH-1S and the elevated drain electrode EH-1D by using selective epitaxy silicon growth techniques (FIG. 40).
Step 176: Etch away the oxide 5 spacers and thermally grow and etch oxide a layer 4102 (Fig. 41).
Step 177: By using the exposed silicon surfaces of the elevated source electrode EH-1S and the elevated drain electrode EH-1D, the elevated source electrode EH-2S and the elevated drain electrode EH-2D are grown (FIG. 42).

See Figures 1I, 1J and 43-67. Step 50 may include:
Step 178: Deposit and etch back SOD-1 layer 4302 (Figure 43).
Step 179: Etch away the W buffer wall (WBW) (FIG. 44).
Step 180: Deposit and etch nitride a-layer 4502 (Figure 45).
Step 181: The polysilicon a layer 3402 and the polysilicon b layer 3502 are removed, and a part of the bottom of the elevated drain electrode EH-1D is etched by using an isotropic etching technique (FIG. 46).
Step 182: Thermally grow oxide bb layer 4702 (Figure 47).
Step 183: Remove the nitride spacers and SOD-1 layer 4302 by using isotropic etching techniques (FIG. 48).
Step 184: Form high-k dielectric insulator 1 layer 4902 (Figure 49).
Step 185: Deposit and etch back metal layer 5002 to produce MCEPW-1 (FIG. 50).
Step 186: Remove high-k dielectric insulator 1 4902 over oxide 4 layer 1404 and etch away oxide 4 layer 1404 (FIG. 51).
Step 187: Etch nitride 3 layer 1402 and nitride 4 spacers (Fig. 52).
Step 188: Grow n+ in-situ doped silicon material laterally on top of nitride 3 layer 1402 by using the exposed silicon sidewalls of the EH-2 electrode (FIG. 53).
Step 189: Deposit nitride cc layer 5402 (Figure 54).
Step 190: Remove MCEPW-1 (Figure 55).
Step 191: Perform selective epitaxy silicon growth using the exposed LGS-2D and exposed LGS-2S as seeds to create twin tower storage electrodes (FIG. 56).
Step 192: Thermally grow and anisotropically etch oxide d-layer 5702 and remove nitride cc-layer 5402 (Fig. 57).
Step 193: Grow a more heavily n+ in-situ doped silicon layer laterally and vertically from the exposed silicon areas of both the LGS-2D and LGS-2S by using selective epitaxy silicon growth techniques (FIG. 58).
Step 194: Remove the oxide d-spacers (Fig. 59).
Step 195: Remove high-k dielectric insulator 1 4902 and form high-k dielectric insulator 2 6002 (Figure 60).
Step 196: Deposit a metal layer (eg, tungsten) 6102 and then polish the metal layer 6102 using CMP techniques (FIG. 61).
Step 197: Etch back the MCEPW-2 and then etch away the high-k dielectric insulator 2 6002 on top of the STSEC-1 (FIG. 62).
Step 198: Grow larger heavily n+ in-situ doped silicon towers 6301, etch high-k dielectric insulator 2 6002, and form high-k dielectric insulator 3 6302 (Figure 63).
Step 199: A photoresist 6402 is formed (FIG. 64).
Step 200: Etch away the high-k dielectric insulator 3 6302 on the exposed edge areas of the MCEPW-2 (FIG. 65).
Step 201: Remove the photoresist 6402 (Figure 66).
Step 202: Deposit and etch back a thick metal layer 6702 to complete the HCoT cell (Fig. 67).

A possible material for the metal layers used in the aforementioned process steps (such as those shown in FIG. 6 for the underground bit lines and in FIG. 13 for the word lines, electrodes, and/or counter electrodes of the capacitor) can be tungsten, but due to the susceptibility of tungsten materials to oxides or oxidation processes, it is better to cover the tungsten layer with another TiN layer or suitable layer. This invention does not describe a detailed protection process for the tungsten layer, but assumes that the metal layer including the tungsten layer is well treated to avoid oxidation directly above it. Of course, there are several suitable metal layers that are suitable for use in the underground bit lines and word lines, and are not limited to a specific type of metal material that is not suitable for insertion into the integration process.

A detailed description of the above-mentioned manufacturing method is as follows. Starting with a p-type silicon wafer (i.e., a p-type substrate 202), in step 102, as shown in FIG. 2(a), a pad oxide layer 204 is formed on a horizontal surface 208 (i.e., when the substrate is a silicon substrate, it is called a horizontal silicon surface (HSS) or an original silicon surface (OSS), and hereinafter, the horizontal silicon surface or HSS is used as an example), and then a pad nitride layer 206 is deposited on the pad oxide layer 204.

In step 104, the active areas of the DRAM cell array can be defined by photolithography mask techniques, and as shown in FIG. 2(a), the active areas of the DRAM cell array correspond to the pad oxide layer 204 and the pad nitride layer 206, and the horizontal silicon surfaces 208 outside the active area pattern are exposed accordingly. With the horizontal silicon surfaces 208 outside the active area pattern exposed, the portions of the silicon material corresponding to the horizontal silicon surfaces 208 outside the active area pattern can be removed by anisotropic etching techniques to create trenches (or canals) 210, for example, the trenches 210 can be 250 nm deep below the HSS.

In step 106, an oxide layer 214 is deposited to completely fill the trench 210, and then the oxide layer 214 is etched back so that the STI inside the trench 210 is formed below the HSS. Also, FIG. 2(b) is a top view corresponding to FIG. 2(a), and FIG. 2(a) is a cross-sectional view along the X direction shown in FIG. 2(b). Furthermore, as shown in FIG. 2(a), for example, the STI has a thickness of about 50 nm, and the top surface of the STI is about 200 nm deep below the HSS when the trench 210 is 250 nm deep below the HSS.

In step 108, a nitride 1 layer is deposited and etched back by anisotropic etching to create nitride 1 spacers along both edges (i.e., top and bottom edges) of the trench 210, as shown in FIG. 3(a). In step 110, an SOD 304 is deposited in the trench 210 over the STI to fill the trench 210, as shown in FIG. 3(a). The SOD 304 is then planarized by a CMP technique to make the top surface of the SOD 304 flush with the top surface of the pad nitride layer 206.

In step 112, as shown in FIG. 3(a), the bottom edge nitride 1 spacer along the bottom edge of the trench 210 is protected by the photoresist layer 306 by utilizing a photolithography mask technique, and the top edge nitride 1 spacer along the top edge of the trench 210 is not protected. That is, after the photoresist layer 306 is deposited on the SOD 304 and the pad nitride layer 206, the portion of the photoresist layer 306 above the top edge nitride 1 spacer is removed, but the portion of the photoresist layer 306 above the bottom edge nitride 1 spacer is retained, so that the bottom edge nitride 1 spacer can be protected and the top edge nitride 1 spacer can be removed later. Also, FIG. 3(b) is a top view corresponding to FIG. 3(a), and FIG. 3(a) is a cross-sectional view along the Y-direction cutting line shown in FIG. 3(b). In step 114, as shown in FIG. 4, the top edge nitride 1 spacers and SOD 304 that are not covered by the photoresist layer 306 are etched away by an etching process.

In step 116, as shown in FIG. 5, both the photoresist layer 306 and the SOD 304 are stripped, where the SOD 304 has a much higher etch rate than the thermal oxide and some of the deposited oxide. Next, an oxide 1 layer 502 is thermally grown to form an oxide 1 spacer covering the top edge of the trench 210, where the oxide 1 layer 502 is not grown on the pad nitride layer 206, and the STI only has a much thinner oxide layer added on top of it (referred to as oxide 1/STI layer 504). As shown in FIG. 5, step 116 results in asymmetric spacers (bottom edge nitride 1 spacer and oxide 1 spacer) on the two symmetric edges (top and bottom edges) of the trench 210, respectively. For example, the thickness of the oxide 1 spacer is 4 nm, and the thickness of the bottom edge nitride 1 spacer is 3 nm. In other words, an asymmetric spacer is formed along the sidewall of the active area. The structure of the asymmetric spacer (shown in FIG. 5) and the associated process described above are the key inventions of the present invention and are referred to as asymmetric spacers on two symmetrical edges of a trench or a canal (ASoSE).

In step 118, as shown in FIG. 6, a metal layer 602 (or a conductive material that needs to withstand subsequent processing conditions) is deposited to completely fill the trench 210 and is then planarized by CMP techniques to make the top surface of the metal layer 602 flush with the top surface of the pad nitride layer 206 (as shown in FIG. 6). Also, in one embodiment of the present invention, the metal layer 602 can be tungsten, abbreviated as W.

In step 120, a photoresist layer 702 is deposited, covering both the bottom nitride 1 spacer and the oxide 1 spacer, but exposing two edges of the bottom nitride 1 spacer and the oxide 1 spacer that correspond to the edges of the active areas, as shown in FIG. 7.

In step 122, as shown in FIG. 8, the metal layer 602 corresponding to the edges of the active areas is etched until the tops of the oxide 1/STI layer 504 are exposed, separating the conductive lines (i.e., the metal layer 602).

In step 124, as shown in FIG. 9(a), after the photoresist layer 702 is removed, the metal layer 602 is etched back to a reasonable thickness inside the trench 210 to form a conductive line or underground bit line (UGBL) 902, where the top surface of the underground bit line 902 is far below the HSS (e.g., the thickness of the underground bit line 902 is about 40 nm). Also, as shown in FIG. 9(a), the underground bit line 902 is above the STI, and both side walls of the underground bit line 902 are bounded by asymmetric spacers, i.e., bottom edge nitride 1 spacer and oxide 1 spacer, respectively. Also, FIG. 9(a) is a cross-sectional view along the Y direction shown in FIG. 9(b).

In step 126, as shown in FIG. 10 (cross-sectional view along the Y direction shown in FIG. 9(b)), the oxide 2 layer 1002 (called CVD-STI-oxide2) needs to be thick enough to fill the trench 210 above the underground bitline 902, and then the oxide 2 layer 1002 is polished to ensure that it is flush with the top surface of the pad nitride layer 206, covering both the bottom edge nitride 1 spacer and the oxide 1 spacer. As shown in FIG. 10, step 126 can embed and bound the underground bitline 902 (i.e., interconnect line) with all the insulator (i.e., isolation region) inside the trench 210 (and later, the underground bitline 902 will be connected to the drain of the access transistor of the DRAM cell array), which is called the underground bitline surrounded by insulator (UGBL). The UGBL is another important invention of the present invention.

The following description shows how to form both the access transistors and the word lines of a DRAM cell (1T1C cell) array, where the word lines simultaneously connect all associated gate structures of the access transistors in a self-aligned manner, so that both the gate structures and the word lines are connected as a single piece of metal, e.g. tungsten (W).

In step 128, as shown in FIG. 11(a), first, a thick oxide 3 layer 1102, a thick nitride 2 layer 1104, and a patterned photoresist 1106 are deposited. Then, by using etching techniques, the unnecessary portions of the oxide 3 layer 1102 and the nitride 2 layer 1104 are removed. The transistor/word line pattern is defined by the composite layer of oxide 3 layer 1102 and nitride 2 layer 1104, which is composed of multiple stripes in a direction perpendicular to the direction of the active areas. Thus, as shown in FIG. 11(a) and FIG. 11(b), longitudinal (Y-direction) stripes (oxide 3 layer 1102 and nitride 2 layer 1104) defining the access transistors and word lines are formed, and the active areas are located at the cross-point squares between the longitudinal stripes. FIG. 11(a) is a cross-sectional view along the X-direction shown in FIG. 11(b).

As shown in FIG. 11(b), the top view reveals a woven checkerboard pattern with longitudinal stripes of oxide 3 layer 1102 and nitride 2 layer 1104 on top of pad nitride layer 206 and pad oxide layer 204, with both active areas and STI in the horizontal direction (i.e., X direction as shown in FIG. 11(b)). The active areas allow the access transistors to be fabricated by a kind of self-aligned technique. Such a checkerboard woven proposal to create a self-aligned structure in which the gate structure of the access transistor and the word line are fabricated in one processing step is another key invention of the present invention.

In step 130, the photoresist layer 1106 is left intact so that the pad nitride layer 206 is etched but the pad oxide layer 204 is preserved, as shown in FIG. 12(a), and then both the photoresist layer 1106 and the pad oxide layer 204 are removed, as shown in FIG. 12(b). As a result, horizontal silicon surfaces 208 (i.e., HSS) are exposed at the cross-point squares (shown in FIG. 12(b)) that correspond to the active areas.

In step 132, as shown in FIG. 13, the exposed HSS at the cross point square position is etched by anisotropic etching technique to form a recess (e.g., U-shaped, etc.), where the U-shaped recess is for the U-shaped channel 1302 of the access transistor, for example, the vertical depth of the U-shaped recess can be about 60 nm from the HSS. Since this U-shaped recess of the access transistor is exposed, the channel doping design can be achieved by some well-designed boron (p-type dopant) concentration to dope the U-shaped channel 1302 of the U-shaped recess for the desired threshold voltage of the access transistor after the subsequent high-k metal gate structure formation. A suitable high-k insulator layer 1304 is formed as the gate dielectric layer of the access transistor, and the top surface of the two edges of the high-k insulator layer 1304 is higher than the HSS. Then, select a suitable gate material 1306 that is suitable for the wordline conductance and can achieve the targeted work function performance of the access transistor to have a lower threshold voltage (the goal in selecting a suitable gate material 1306 is to lower the boosted wordline voltage level as low as possible, but provide enough device drive to support faster charge transfer for signal sensing while completing the restoration of a sufficient amount of charge in the capacitor).

The gate material 1306 is thick enough to fill the U-shaped recess (shown in FIG. 13) between two adjacent longitudinal stripes (oxide 3 layer 1102 and nitride 2 layer 1104). The gate material 1306 is then etched back to result in a longitudinal (Y-direction) word line sandwiched between two adjacent longitudinal stripes (oxide 3 layer 1102 and nitride 2 layer 1104). For example, the gate material 1306 can be tungsten (W) which forms a high-k metal gate structure that, with suitable channel doping concentration, allows for the design of a lower threshold voltage, which is desirable for the access transistor.

The newly proposed access transistor with U-shaped channel 1302 (hereafter referred to as U-transistor) is different from the recessed transistor commonly used in state-of-the-art buried wordline designs. The U-transistor has its body bounded on both sides by CVD-STI-oxide2 along the Y direction (i.e., channel width direction), and its channel length includes the depth of one edge of the U-shaped channel 1302 on the side corresponding to the drain of the U-transistor, the length of the bottom surface of the U-shaped channel 1302, and the depth of another edge of the U-shaped channel 1302 on the side corresponding to the source of the U-transistor. For example, if the vertical depth of the U-shaped recess is about 60 nm and the U opening of the U-shaped recess is about 7 nm along the X direction (i.e., channel length direction), the total channel length of the U-transistor is about 127 nm. In contrast, the channel length of the recessed transistor must depend more on how deeply the gate material of the recessed transistor is recessed and how deeply the source and drain junctions of the recessed transistor are formed.

Due to the difference in structure between the U-transistor and the recessed transistor, the channel length of the U-transistor can be much better controlled, especially when the channel length of the U-transistor does not depend on the height of the gate of the U-transistor. Furthermore, as will be described later on how to complete the drain and source of the U-transistor, the dopant concentration profile of each of the drain and source of the U-transistor is much more controllable, with smaller variations in device design parameters as will be more clearly demonstrated, since the HSS is fixed. Furthermore, the simultaneous formation of the gate structure and word line of the U-transistor in the longitudinal direction by self-alignment between two adjacent longitudinal stripes (oxide 3 layer 1102 and nitride 2 layer 1104) ensures that the word line is not below the HSS, which presents significantly different design and performance parameters than the commonly used buried word line. In addition, the height of the word line (i.e., gate material 1306) is designed to be lower than the height of the composite layer (composed of oxide 3 layer 1102 and nitride 2 layer 1104) by using an etch-back technique (shown in FIG. 13). The structural design of the gate structure of the U-transistor, which is self-aligned to the word line, is another important invention of the present invention.

14, a nitride 3 layer 1402 (i.e., a dielectric cap) is deposited, followed by an oxide 4 layer 1404, where the nitride 3 layer 1402 and the oxide 4 layer 1404 are stacked with a combined thickness large enough to fill the space between two adjacent longitudinal stripes (oxide 3 layer 1102 and nitride 2 layer 1104). The oxide 4 layer 1404 and the nitride 3 layer 1402 are then etched back (or polished back) to be flush with the top surface of the nitride 2 layer 1104 to form a composite stack of the oxide 4 layer 1404 and the nitride 3 layer 1402 directly above the word line (i.e., the gate material 1306).

At step 136, as shown in FIG. 15, the nitride 2 layer 1104 is etched away by anisotropic etching techniques, leaving the oxide 4 layer 1404/nitride 3 layer 1402 over the word lines. The oxide 3 layer 1102 is then also etched away by anisotropic etching, exposing the pad nitride layer 206. The gate structure (e.g., oxide 4 layer 1404/nitride 3 layer 1402/gate material 1306, etc.) is achieved for both the gate of the U transistor and the word line in the longitudinal direction (i.e., Y direction) within the U-shaped recess.

In step 138, as shown in FIG. 16, the pad nitride layer 206 is removed everywhere, leaving the pad oxide layer 204. The CVD-STI-oxide2 (i.e., oxide2 layer 1002) is etched back to be flush with the top surface of the pad oxide layer 204.

In step 140, as shown in FIG. 16, a nitride 4 layer 1602 is deposited and etched by anisotropic etching techniques to create nitride 4 spacers with a well-designed preferred thickness. Next, an oxide 5 layer 1604 is deposited and etched by anisotropic etching techniques to create oxide 5 spacers. Then, a polysilicon 1 layer 1606 (intrinsic and undoped) is deposited over the entire surface and etched by anisotropic etching techniques to create polysilicon 1 spacers, making the polysilicon 1 spacers surround the word lines (e.g., word line-1, word line-2, word line-3). So, in summary, the polysilicon 1 spacers are outside the oxide 5 spacers, the oxide 5 spacers are outside the nitride 4 spacers, and all of the above spacers are surrounded along the gate structure (e.g., oxide 4 layer 1404/nitride 3 layer 1402/gate material 1306, etc.).

As shown in Figures 16 and 17, for convenience and clarity in describing a DRAM cell array having word lines and bit lines, the word line located in the center is labeled word line-1 (corresponding to access transistor AQ1), the word line adjacent to the left of word line-1 is labeled word line-2 (corresponding to access transistor AQ2 adjacent to the left of access transistor AQ1), and the drain regions (drain-1 and drain-2) between word line-1 and word line-2, still covered by pad oxide layer 204, are reserved for the drain of access transistor AQ1 and the drain of access transistor AQ2. The word line to the right of word line-1 is labeled word line-3 (corresponding to access transistor AQ3 to the right of access transistor AQ1), and the source regions (source-1 and source-3) between word line-1 and word line-3, still covered by pad oxide layer 204, are reserved for the source of access transistor AQ1 and the source of right access transistor AQ3.

In step 142, as shown in FIG. 17, SOD 1702 is deposited to a thickness sufficient to fill the gaps between the wordlines (corresponding to the drain and source regions), and then the SOD 1702 is polished by CMP to a level flush with the top surface of the oxide 4 layer 1404. Then, a portion of the upper portion of the polysilicon 1 layer 1606 is etched by anisotropic etching. Then, cap oxide 1 layer 1704 is deposited to fill the gaps above the polysilicon 1 spacers, and then planarized by CMP to be flush with the top surface of the oxide 4 layer 1404.

In step 144, as shown in FIG. 18, the SOD 1702 is etched away, where the SOD 1702 has a much higher etch rate than the etch rate of the deposited or thermally grown oxide layers, which are well preserved. Then, a nitride 5 layer 1802 is deposited over the entire surface, as shown in FIG. 18.

In step 146, as shown in FIG. 19, SOD 1902 is deposited to a thickness sufficient to fill the gaps between all the wordlines, and then the SOD 1902 is polished to a level planar with the top surface of the nitride 5 layer 1802. Photoresist 1904 is then deposited on the planar surface to cover the areas reserved for the drain regions (i.e., drain-1 and drain-2) and expose the areas reserved for the source regions (i.e., source-1 and source-3). The SOD 1902 corresponding to the areas reserved for the source regions is then removed by using the nitride 5 layer 1802 surrounding all the wordlines as a self-aligned mask. Once the desired pattern has been transferred to the SOD 1902, all the unnecessary photoresist is removed, and thus the SOD 1902 is planarized, as shown in FIG. 19.

In step 148, the nitride 5 layer 1802 and pad oxide layer 204 exposed in the center of the source region between the two word lines (word line-1 and word line-3) are etched away to expose the HSS, as shown in FIG. 20. The exposed HSS is located between source-1 of access transistor AQ1 and source-3 of access transistor AQ3, so the exposed HSS between source-1 and source-3 can be called HSS-1/3. As shown in FIG. 20, the HSS-1/2 between word line1 and word line2 will be used as the location for drain-1 (i.e., the drain of access transistor AQ1) and drain-2 (i.e., the drain of access transistor AQ2) and also to vertically connect access transistors AQ1, AQ2 to the UGBL. Furthermore, on the other right side of word line-1, HSS-1/3 between word line-1 and word line-3 will be used for source-1 (i.e., the source of access transistor AQ1) and source-3 (i.e., the source of access transistor AQ3), but source-1 and source-3 are separate and cannot be connected. This is because source-1 and source-3 will later be connected to additional cell storage nodes CSN1 and CSN3 (not shown in FIG. 20), respectively.

In addition, to summarize, although this photolithography mask technique is used to cover HSS-1/2, the mask utilized by this photolithography mask technique is not a critical mask, and its function is only to allow processing HSS-1/3 separately from processing on HSS-1/2. As mentioned above, SOD 1902 is deposited with a thickness sufficient to create a smooth surface topology, and then photoresist 1904 is deposited to act as a mask material that protects SOD 1902 covering the drain region but exposes the source region. Also, the reason for using SOD is that SOD has a very high etch rate, so it is removed without damaging other materials present, and SOD is resistant to thermal processes other than photoresist.

As shown in FIG. 20, the silicon material below the HSS-1/3 (corresponding to the center of the source region) is excavated by anisotropic etching techniques to create a hole-1/3 surrounded by bottom edge nitride-1 and oxide-1 spacers on two opposing sides (not shown in FIG. 20) and by silicon substrate 202 on the other two opposing sides.

21, the photoresist 1904 is then removed and an oxide-7 layer 2102 is thermally grown to fill the hole 1/3. The oxide-7 layer 2102 is partially grown on the cap oxide-1 layer 1704 and not elsewhere due to the lack of oxide growth on the nitride-5 layer 1802. The oxide-7 layer 2102 filling the hole 1/3 is called the oxide-7 plug, which has a smooth surface that is flush with the top surface of the pad oxide layer 204.

In step 152, as shown in FIG. 22, another SOD layer 2202 is deposited, the other SOD layer 2202 being thick enough to fill the void above the oxide 7 layer 2102 in the hole-1/3, and the top material of the other SOD layer 2202 is removed by CMP techniques until the top surface of the other SOD layer 2202 is flush with the top surface of the nitride 5 layer 1802.

In step 154, as shown in FIG. 23, photoresist 2302 is deposited to cover the areas corresponding to the source regions and expose the areas reserved for the drain regions. The mask used in step 154 is not a critical mask, and its function is only to allow processing of HSS-1/2 separately from the processing above HSS-1/3. The exposed SOD 1902, exposed nitride 5 layer 1802, and the exposed pad oxide layer 204 below are then removed to expose the HSS (i.e., HSS-1/2). The silicon material corresponding to HSS-1/2 is then excavated and removed by anisotropic etching to create hole-1/2. The hole-1/2 is physically surrounded on two opposite sides by the silicon substrate 202, on a third side by a bottom edge nitride 1 spacer, and on a fourth side by an oxide 1 spacer. Both the third and fourth sides are further bounded on the outside by CVD-STI-oxide2 (not shown in FIG. 23).

24, the photoresist 2302 is removed and an oxide 8 layer 2402 is thermally grown to produce an oxide 8 spacer that covers three of the four sidewalls of the hole 1/2 and the bottom of the hole 1/2, except for the third sidewall covered by the bottom nitride 1 spacer. Furthermore, the oxide 8 layer 2402 is partially grown on the cap oxide 1 layer 1704. FIG. 25 shows a cross-sectional view of the DRAM cell array along the Y2 direction that runs perpendicular to the X direction along the center of the hole 1/2, and as shown in FIG. 25, the active area is sandwiched by the CVD-STI-oxide 2, the bit line (UGBL), the oxide 1 spacer, and the bottom nitride 1 spacer.

At step 158, as shown in Figures 26 and 27, the bottom edge nitride 1 spacer on the third sidewall in hole 1/2 is removed by an isotropic etching technique while simultaneously removing the nitride 5 layer 1802 (as shown in Figure 27, since the bottom edge nitride 1 spacer is very thin, this isotropic etching technique should not damage other structures above the HSS and should not remove the oxide 8 layer 2402 in hole 1/2).

In step 160, as shown in FIG. 28, a metal layer (e.g., tungsten) 2802 is deposited thick enough to fill hole 1/2, and then all metal layer 2802 above the HSS is etched back by an isotropic etching technique to leave a tungsten plug in hole 1/2. The tungsten plug is connected to the UGBL through an opening in the third sidewall of hole 1/2 that was originally covered by the bottom edge nitride 1 spacer. A nitride 6 layer 2804 is then deposited and etched by an anisotropic etching technique to create a nitride 6 spacer surrounding the polysilicon 1 spacer corresponding to the reserved drain region.

In step 162, a portion of the top of the tungsten plug under the HSS is etched back as shown in FIG. 29. The tungsten plug is connected to the UGBL from the sidewall of the tungsten plug to the sidewall of the UGBL in the hole 1/2 as shown in FIG. 30.

In step 164, as shown in FIG. 31, the top portion of the oxide 8 layer 2402 is removed by a well-designed amount through anisotropic etching techniques, resulting in oxide 8 spacers having a height less than that of the tungsten plugs. A portion of the cap oxide 1 layer 1704 may be etched as well, as shown in FIG. 31.

In step 166, as shown in FIG. 32, by utilizing selective epitaxy silicon growth (SEG) technique, an n+ in-situ doped silicon layer 3202 is grown laterally from the two exposed silicon edges (adjacent to and above the oxide 8 layer 2402 and the tungsten plug), thus resulting in necklace-shaped conductive n+ silicon drains (referred to as n+ silicon drain collars) that connect to the HSS on both sides of the hole 1/2 as drain-1 and drain-2 of the access transistors AQ1, AQ2, respectively, and also as a conductive bridge (i.e., bridge contact) between the UGBL and the access transistors AQ1, AQ2.

In step 168, as shown in FIG. 33, an oxide-9 layer 3302 with a well-designed thickness is thermally grown locally on the n+ silicon drain collar to be the cap of HSS-1/2 (and such oxide-9 layer 3302 may cover the cap oxide-1 layer 1704). The above connection method, which creates the underline bridge contact between UGBL and drain-1 (drain-2), is another important invention of this invention, where drain-1 and drain-2 are oxide-capped n+ drains.

In step 170, as shown in FIG. 34, a portion of the oxide 9 layer 3302 covering the n+ silicon drain collar may be etched back to a thickness that is the height of the pad oxide 204, and the oxide 9 layer 3302 covering the cap oxide 1 layer 1704 is etched away. A thick intrinsic polysilicon a layer 3402 is then deposited in the space above the oxide 9 layer 3302 over the hole 1/2, and the polysilicon a layer 3402 is etched back.

In step 171, the nitride 6 spacers (nitride 6 layer 2804) are removed by an isotropic etching technique, as shown in FIG. 35. An intrinsic polysilicon b layer 3502 is deposited and then etched back using an anisotropic etching technique to leave a void-filling residue immediately adjacent to the polysilicon a layer 3402 and to form approximately the same thickness in both the polysilicon a layer 3402 and the polysilicon b layer 3502.

In step 172, as shown in FIG. 36, all SOD (i.e., SOD layer 1902 and another SOD layer 2202) are removed and nitride 5 layer 1802 is removed by isotropic etching techniques. FIG. 37 also shows a top view of the HCoT cell array structure up to this stage, particularly the geometry of the word lines (word line-1, word line-2, word line-3), underground bit lines (UGBL), source regions (source-1 and source-3) of access transistors AQ1, AQ3, and drain regions (drain-1 and drain-2) of access transistors AQ1, AQ2.

In step 173, as shown in FIG. 38, a metal layer (e.g., tungsten) 3802 is deposited and a portion of the metal layer 3802 is etched back to form a W-Buffer-Wall (WBW).

In step 174, as shown in FIG. 39, the cap oxide 1 layer 1704 on top of the polysilicon 1 spacers is removed. The polysilicon 1 spacers are then etched away, and the pad oxide layer 204 underneath the polysilicon 1 spacers is also removed, thus exposing the HSS corresponding to the source and drain regions (referred to as seed HSS regions for source and drain regions, SHAR), respectively.

In step 175, both the elevated source electrode EH-1S and the elevated drain electrode EH-1D are vertically grown on the HSS using selective epitaxy silicon growth technique by using the exposed HSS (SHAR) as a seed, as shown in FIG. 40. The elevated source electrode EH-1S and the elevated drain electrode EH-1D can be pure silicon material instead of polycrystalline or amorphous silicon material, since they are grown gradually and well by using the exposed HSS (SHAR) as a seed. Both the elevated source electrode EH-1S and the elevated drain electrode EH-1D are surrounded by WBW and oxide 5 spacers on the left and right sidewalls along the X direction. Although the other two sidewalls along the Y direction are wide open, the CVD-STI-oxide2 cannot provide a seed function for selective epitaxial silicon to grow on, so this selective epitaxial silicon growth should stop at the edge of the CVD-STI-oxide2, resulting in some laterally overgrown pure silicon material that may not cause adjacent electrodes to connect. Furthermore, after the elevated source electrode EH-1S and the elevated drain electrode EH-1D are grown, an optional RTA (rapid temperature annealing) step can be used to form an NLDD (n+ lightly doped drain) 4012 under the elevated source electrode EH-1S or the elevated drain electrode EH-1D so that the elevated source electrode EH-1S or the elevated drain electrode EH-1D has a better electrical connection to the channel region of the transistor.

The new process design to achieve elevated source electrode EH-1S and elevated drain electrode EH-1D is described as follows: (1) By using SHAR as a seed to grow elevated source electrode EH-1S and elevated drain electrode EH-1D by selective epitaxy silicon growth technique, the key is to design suitable in-situ n-type doping concentration during silicon growth and use rapid temperature annealing process to achieve suitable interface conductance of the channel region of the access transistor (which includes the conductance of silicon surface directly under the gate dielectric, HSS under nitride4/oxide5 spacer, and elevated source electrode EH-1S or elevated drain electrode EH-1D, respectively) and achieve lower leakage current, especially for gate-induced drain leakage (GIDL), drain-induced barrier lowering (DIBL), subthreshold leakage due to short channel effect, and junction leakage.

(2) As shown in FIG. 40, the elevated source electrode EH-1S and the elevated drain electrode EH-1D are grown to a specified height that is lower than the height of the final EH-1+2 electrode (i.e., the elevated source electrode EH-1+2S and the elevated drain electrode EH-1+2D). In step 176, as shown in FIG. 41, the oxide 5 spacer is first etched by an isotropic etching technique to leave a seam between the nitride 4 spacer and the elevated drain electrode EH-1D (and between the nitride 4 spacer and the elevated source electrode EH-1S). Then, an oxide a layer 4102 is thermally grown (referred to as an oxide a cap layer) to cover the elevated drain electrode EH-1D (or the elevated source electrode EH-1S) on three sidewalls and its top surface except for the last fourth sidewall bounded by the WBW. The purpose of performing the careful stepwise source electrode formation process as described below is to ensure that the thermal oxide a layer has a very high quality silicon dioxide-silicon electrode bond, thereby achieving a high quality oxide-silicon interface on the top surface of the source electrode EH-1S (or the top surface of the drain electrode EH-1D) (though there is a suspicion that the selective epitaxy silicon growth process may instead result in amorphous or low quality silicon material, which may degrade the quality of the silicon source electrode, causing reduced carrier mobility that cannot provide sufficient on-current when the access transistor is turned on, or additional defect amounts that may increase leakage when the access transistor is turned off). The cap portion of the oxide a layer 4102 is then etched by anisotropic etching techniques, leaving the oxide a layer 4102 present between the nitride 4 spacer and the source electrode EH-1S (or between the nitride 4 spacer and the drain electrode EH-1D).

(3) In step 177, as shown in FIG. 42, a second selective epitaxial silicon growth is performed by using the exposed silicon surfaces of the source electrode EH-1S and the drain electrode EH-1D as high-quality silicon seeds to grow the elevated source electrode EH-2S and the elevated drain electrode EH-2D, respectively. During the second selective epitaxial silicon growth, a well-designed higher in-situ n+ doping concentration can be achieved in the elevated source electrode EH-2S and the elevated drain electrode EH-2D in preparation for a low-resistance connection between the elevated source electrode EH-2S (or the elevated drain electrode EH-2D) and the storage electrode of a stacked storage capacitor (SSC) to be fabricated later. The combination of the elevated source electrode EH-1S and the elevated source electrode EH-2S is called the elevated source electrode EH-1+2S (similarly, the combination of the elevated drain electrode EH-1D and the elevated drain electrode EH-2D is called the elevated drain electrode EH-1+2D). Furthermore, taking the elevated source electrode EH-1+2S as an example, as shown in FIG. 42, the upper part of the elevated source electrode EH-1+2S, i.e., the elevated source electrode EH-2S, has a high-quality n+ doped silicon material that directly abuts the nitride 4 spacer on one sidewall, the opposite sidewall abuts the WBW, and the other two sidewalls are widely open in the Y direction along the longitudinal word line. The height of the elevated source electrode EH-1+2S (the height of the elevated drain electrode EH-1+2D) is often designed to be lower than the height of the nitride 4 spacer.

In step 178, as shown in FIG. 43, a thick SOD-1 layer 4302 is deposited on the surfaces of the elevated drain electrode EH-2D and the elevated source electrode EH-2S, respectively, and the SOD-1 layer 4302 is etched back.

In step 179, the WBW is etched away over the entire wafer surface, as shown in FIG. 44.

In step 180, as shown in FIG. 45, a nitride a layer 4502 is deposited and etched by using anisotropic etching technique to form nitride a spacers surrounding all sidewalls of the elevated source electrode EH-1+2S and the elevated drain electrode EH-1+2D, respectively. The difference is that the nitride a spacers surrounding the elevated source electrode EH-1+2S (elevated drain electrode EH-1+2D) stand on the polysilicon a layer 3402 and polysilicon b layer 3502 acting like a mattress layer (but there is no such polysilicon a layer 3402 and polysilicon b layer 3502 acting like a mattress layer on the sides of the elevated source electrode EH-1+2S (elevated drain electrode EH-1+2D)).

46, in step 181, first, the polysilicon a layer 3402 is removed using an anisotropic silicon etching technique (at this time, the remaining silicon regions such as the elevated drain electrode EH-2D and the elevated source electrode EH-2S are sufficiently protected by the SOD-1 layer 4302 and the nitride a spacer, respectively). Next, the polysilicon b layer 3502 and a part of the bottom of the elevated drain electrode EH-1D are etched away using an isotropic etching technique due to the seam (or void) caused by the buffer space due to the thickness occupied by the removed polysilicon a layer 3402 and polysilicon b layer 3502. Please note that (1) the remaining bottom of the elevated drain electrode EH-1D maintains the strength to hold the top of the elevated drain electrode EH-1D due to high quality silicon bonding force, and (2) the nitride a spacers are not completely suspended on air because the nitride a spacers surround the EH-1+2 electrodes with their feet standing on the CVD-STI-oxide2 (i.e., oxide 2 layer 1002) and with strong adhesion of the nitride a spacers by chemical bonding. The end result of creating this novel process design is to make the HSS under the elevated drain electrode EH-1D exposed.

In step 182, as shown in FIG. 47, a thermal oxidation process is performed to grow a high quality oxide bb layer 4702 on the exposed HSS surface shown in FIG. 46 by a thermal chemical reaction between silicon and silicon dioxide, thus providing oxide isolation that sufficiently isolates the drain region from the bottom of the EH-1+2D electrode that it can now be used as part of the storage electrode for the storage capacitor.

In step 183, as shown in FIG. 48, an isotropic etching technique is used to remove the nitride a-spacers and SOD-1 layer 4302 associated with the EH-1+2 electrodes (i.e., the elevated source electrode EH-1+2S and the elevated drain electrode EH-1+2D). Then, in step 184, a high-k dielectric insulator 1 layer 4902 is formed as shown in FIG. 49.

In step 185, as shown in FIG. 50, a thick metal layer (e.g., tungsten, etc.) 5002 is deposited and etched back to leave its remnants well designed to provide a height slightly higher than the EH-1+2 electrodes (i.e., elevated source electrode EH-1+2S and elevated drain electrode EH-1+2D) but similar to the height of the nitride-4 spacers. The metal layer 5002 that extends over the wafer surface is called metal-counter-electrode-plate&wall-1 (MCEPW-1). MCEPW-1 covers the high-k cap-1 of the high-k dielectric insulator 1 4902 above the EH-1+2 electrodes, but may also cover the oxide-4 layer 1404 and the top surface of the nitride-4 spacers of the composite stack.

In step 186, as shown in FIG. 51, the high-k dielectric insulator 1 4902 on the oxide 4 layer 1404 is removed by anisotropic etching techniques, and then the top layer of the composite stack, the oxide 4 layer 1404, is etched away without damaging the high-k cap 1 covered by MCEPW-1 and the high-k dielectric insulator 1 4902. Hence, there is a canal-like recessed area on top of the composite stack with the nitride 4 spacers on two sides, which stand like a taller fence with a height above the thickness of the nitride 3 layer 1402, but with an exposed top facing the canal-like recessed area.

In step 187, as shown in FIG. 52, the top of the nitride-3 layer 1402 above the composite stack is removed by an isotropic etching technique for a well-designed thickness. At the same time, the top of the nitride-4 spacer is also removed by an isotropic etching technique so that the top surface of the remaining nitride-4 spacer and the top surface of the nitride-3 layer 1402 are at the same height as the horizontal flat surface of both the nitride-3 layer 1402 and the nitride-4 spacer. The isotropic etching technique, which caused the height of the nitride-4 spacer to be reduced after the nitride-4 spacer loses its top portion, exposes the upper silicon sidewall of the EH-2 electrode facing the nitride-4 spacer.

In step 188, as shown in Figure 53, a selective epitaxial silicon growth technique is used to grow n+ in-situ doped silicon material laterally on top of the nitride 3 layer 1402 by using the exposed silicon sidewalls of the EH-2 electrodes (i.e., elevated source electrode EH-2S and elevated drain electrode EH-2D) facing the word line direction. With word line-1 as the reference, there is an elevated source electrode EH-1+2S on one side of word line-1, and there is an elevated drain electrode EH-1+2D on the other side of word line-1. By controlling the growth time, both the epitaxial silicon grown laterally from the elevated source electrode EH-2S (called LGS-2S) and the epitaxial silicon grown laterally from the elevated drain electrode EH-2D (called LGS-2D) are not allowed to meet each other in the center of word line-1, but instead there is a well-designed gap in the horizontal space (or vacancy).

In step 189, as shown in FIG. 54, a thick high quality nitride cc layer 5402 is deposited, and then CMP technique is used to expose both LGS-2D and LGS-2S, leaving a nitride cc isolation layer (nitride cc layer 5402) between LGS-2D and LGS-2S to completely isolate them. At the same time, the tops of both MCEPW-1 and high-k dielectric insulator 1 4902 are removed by either CMP technique or etch-back, leaving the remaining parts at the same height as LGS-2D and LGS-2S, respectively.

In step 190, MCEPW-1 (i.e., metal layer 5002) is removed, as shown in FIG. 55.

In step 191, as shown in FIG. 56, by using the exposed LGS-2D and exposed LGS-2S as seeds (referred to as SBSES-D and SBSES-S, respectively, with the abbreviation SBSES as Seeding Base for Growing Storage-Electrode Skyscraper), selective epitaxy silicon growth is performed to create twin-tower storage electrodes for the storage capacitor, as shown in the following description how they are completed (here there are two twin towers of electrodes, one elevated electrode on the drain side called LGS-2D-Tower and the other elevated electrode on the source side called LGS-2S-Tower).

In step 192, as shown in FIG. 57, a thin oxide d layer 5702 is thermally grown and then anisotropic etching techniques are used to remove the oxide d layer 5702 on the LGS-2D-Tower and LGD-2S-Tower to form oxide d spacers. An isotropic etching technique is used to remove the nitride cc layer 5402 to expose the side edges of the LGS-2D and LGS-2S, respectively.

In step 193, as shown in FIG. 58, a more highly n+ in-situ doped silicon layer is grown laterally from the exposed silicon regions of both LGS-2D and LGS-2S using selective epitaxy silicon growth techniques until a new connected silicon layer (called LGS-2DS) is formed. Furthermore, as shown in FIG. 58, a more highly n+ in-situ doped silicon layer is grown vertically from the top surfaces of the LGS-2D-Tower and LGD-2S-Tower, also using selective epitaxy silicon growth techniques. As shown in FIG. 58, a horizontal connection region (which may include LGS-2DS) connects one vertical protruding region (e.g., elevated drain electrode EH-1+2D) to the other vertical protruding region (e.g., elevated source electrode EH-1+2S) of the H-capacitor. The horizontal connection region does not need to be coupled to the center of each protruding region, but can be higher or lower.

Then, in step 194, the oxide d-spacers are removed as shown in FIG. 59. In step 195, an isotropic etching technique is used to remove the high-k dielectric insulator 1 4902 and form the high-k dielectric insulator 2 6002 surrounding the grown twin tower storage electrodes as shown in FIG. 60.

In step 196, a thick metal layer (e.g., tungsten) 6102 (MCEPW-2) is deposited and then etched back or polished using CMP techniques to produce a planar surface, as shown in Figure 61. This shows the newly invented HCoT cell with a twin tower H-shaped (storage capacitor) storage electrode completely surrounded by high-k dielectric insulator 2 6002, which is completely surrounded on the outside by a counter electrode plate metal layer (i.e., metal layer 6102) that is bussed to a fixed voltage (e.g., half VCC). As shown in FIG. 61, the newly constructed storage capacitor surrounds the access transistor AQ1 like a saddle tightly clamped on the access transistor AQ1, with the fully extended surface area of the storage electrode rising straight up from the HSS at the bottom of the elevated source electrode EH-1S of the access transistor AQ1 to the top of the signal tower storage electrode (called STSEC-1) of the storage capacitor, surrounding the entire surface area of the LGS-2S-Tower, and then crossing all four sidewalls of the LGS-2D-Tower down through the other three sidewalls of the LGS-2S to the top of the oxide bb layer 4702 at the bottom of the elevated drain electrode of the access transistor AQ1. Nearly all four sidewall surfaces surrounding the twin towers are used to create a near maximum dielectric area to maximize the storage capacitance of the storage capacitor as much as possible.

In addition, if the height of the twin-tower storage node needs to be further extended, the process from FIG. 62 to FIG. 67 can be used to extend the height of the storage node to further increase the storage capacitance of the storage capacitor. Furthermore, the connection region between the two protruding regions of the H capacitor can include multiple horizontal sub-connection regions after repeating the process from FIG. 62 to FIG. 67 several times. Each sub-connection region can connect two protruding regions of the H capacitor.

In step 197, as shown in FIG. 62, the MCEPW-2 is etched back to a height that is lower than the height of the storage electrode (i.e., STSEC-1). The high-k dielectric insulator 2 6002 on top of the STSEC-1 is then etched away by anisotropic etching techniques, retaining only the high-k dielectric insulator 2 6002 surrounding the STSEC-1.

In step 198, as shown in FIG. 63, a higher highly n+ in-situ doped silicon tower 6301 is grown as the storage electrode of the storage capacitor using selective epitaxial silicon growth technique by using the exposed silicon material on the top surface of STSEC-1 as a seed. Then, the high-k dielectric insulator 2 6002 is etched by isotropic etching technique, and a high-k dielectric insulator 3 6302 is formed to cover the entire sidewall and top surface of the higher highly n+ in-situ doped silicon tower without allowing any possible electrical connection or leakage mechanism from the exposed n+ doped silicon storage electrode to MCEPW-2.

In step 199, photoresist 6402 is formed to cover all cell array areas except for exposing edge regions of MCEPW-2, as shown in FIG. 64. Then, in step 200, the high-k dielectric insulator 3 6302 on the exposed edge regions of MCEPW-2 is etched away, as shown in FIG. 65. Then, in step 201, the photoresist 6402 is removed, as shown in FIG. 66.

In step 202, as shown in FIG. 67, a thick metal (e.g., tungsten W) layer 6702 is deposited and etched back, which wraps around all the sidewalls of the higher n+ in-situ doped silicon towers and other valley regions above the silicon surface to form a planar plateau, which we call MCEPW-3. The sum of MCEPW-3 and the existing MCEPW-2 with all their edge regions connected together can function well not only as a counter electrode plate biased to a constant voltage level, e.g., half VCC, but also as a metal shield plate that can achieve better heat dissipation like a metal heat sink and can suppress noise or improve noise immunity for the wordline and access transistor gate structures (because the electric field can be more evenly distributed and distributed and shielded across the capacitor plate). FIG. 67 shows the newly invented HCoT cell, whose storage capacitor that clamps the access transistor has a maximized capacitor storage area with an H-shaped twin tower storage electrode. Figure 68 shows a schematic diagram of an HCoT cell.

Figure 69 shows a simplified top view of an HCoT cell (1T1C cell), focusing on the twin tower capacitor storage electrodes connected through their bottoms down to the elevated source electrodes of the access transistors. The cell area of the HCoT cell is rectangular in shape, the H-capacitor includes the capacitor periphery that is also rectangular in shape, and the access transistors are located within the capacitor periphery. The capacitor footprint is approximately the same size as the cell area, except that some isolation tolerance is required to separate adjacent storage electrodes. This should be the most efficient design for the ratio of storage capacitor planar area to 1T1C cell planar area that the inventors are aware of.

In summary, the present invention provides a new architecture of DRAM cells that not only reduces the size of the DRAM cells but also enhances the signal-to-noise ratio during DRAM operation. Because the capacitor is located above and mostly surrounds the access transistors, and because we have invented both vertical and horizontal self-aligning techniques to place and connect these basic microstructure geometries in the DRAM cell, the new HCoT cell architecture can ensure at least 4-10 square units of advantage even when the minimum physical feature size is much smaller than 10 nanometers. The area of the H-capacitor can occupy 50% to 70% of the HCoT cell area.

Also, the metal electrodes of the capacitors in this new HCoT cell architecture provide an efficient route for heat dissipation and therefore the temperature of the HCoT cell during operation can be lowered accordingly, which reduces both the leakage current from the capacitor and the thermal/operational noise. In addition, the metal electrodes also surround the word lines passing through the access transistors, and the combination of such surrounded word lines and underground bit lines (UGBLs) fabricated below the silicon surface can effectively shield the cross-coupling noise between different word lines/bit lines, and therefore the troublesome pattern sensitivity problem in traditional DRAM cell array operation can be dramatically reduced.

GIDL leakage can also be reduced by well-designed transistor structures, and such reduced GIDL leakage, combined with the reduced leakage resulting from lower operating temperatures, can lead to even higher signal-to-noise ratios and the possibility of using much smaller sized capacitors in HCoT cells without adversely affecting the reliability of the stored data.

In addition, the UGBL below the silicon surface of the present invention can flexibly reduce the resistivity and capacitance of the bit line, thus improving the signal sensitivity during charge sharing between the capacitor and the bit line, and thus increasing the operating speed of the HCoT cell of the new architecture as well.

In summary, the HCoT cell of the present invention is illustrated diagrammatically in FIG. 68, which corresponds to FIG. 67. In contrast to state-of-the-art DRAM cell structures, the new HCoT cell structure demonstrates the following features that help achieve cell sizes on the order of 4 to 10 sq. units at less than 10 nanometers: (1) storage electrode of the storage capacitor surrounding the access transistor; (2) counter electrode plate containing the access transistor and covering the entire cell array; (3) underground bit lines below the HSS to reduce cell topography; (4) elevated source electrode with tunable conductance self-aligned to the edge of the channel to minimize cell leakage; (5) self-aligned storage electrode extending from the elevated source as a saddle with self-aligned capacitor tower and straddling the access transistor; (6) most cell features are scalable with proven materials and process steps with sufficient reliability and quality; (7) for most of the disclosed DRAM cells (to the best of the inventors' knowledge), the cell geometry is L (length) x 10 sq. units; Very efficiently kept as a rectangle occupying the planar surface of the silicon die as W (width), the HCoT cell is considered to have the largest extent of storage capacitor area on this L×W landscape, except that some distance must be reserved for storage electrode isolation between adjacent capacitors of different memory cells; (8) As described in the embodiment, the height of the storage electrode can be built up stepwise in a desirable and good linear tower shape by using multiple technologies and techniques as invented; With the cell area further reduced by device scaling requirements, the ratio of cell height to the planar area of the cell is effectively increased to increase the surface area of the capacitor; (9) By creating multiple storage electrodes in a protruding shape and connecting them as DRAM capacitor storage nodes, the storage area can be expanded, thus providing a large capacitance within the limited and reduced planar surface area of the cell.

While the invention has been illustrated and described with reference to embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements within the spirit and scope of the appended claims.

Claims (7)

a semiconductor substrate having an original semiconductor surface;
a transistor coupled to the original semiconductor surface, the transistor having a gate structure, a first conductive region, and a second conductive region, the gate structure having a gate conductive region ;
a capacitor having a storage electrode, the capacitor overlying the transistor, the storage electrode being electrically coupled to the second conductive region of the transistor , the storage electrode being a bottom electrode of the capacitor and covering two side surfaces and a top surface of the gate structure of the transistor ;
having
the storage electrode comprises an epitaxial silicon layer ;
A memory cell structure. 2. The memory cell structure of claim 1, wherein the storage electrode comprises a first protruding region, a second protruding region connected to the second conductive region of the transistor, and a connection region connecting the first protruding region and the second protruding region, the second protruding region comprising an epitaxial silicon layer . The memory cell structure of claim 2 , wherein said connection region comprises an epitaxial silicon layer . The memory cell structure of claim 2, wherein the connection region is above a top surface of the gate structure, the first protruding region covers one sidewall of the gate structure, and the second protruding region covers another sidewall of the gate structure. The memory cell structure of claim 1, further comprising a bit line electrically coupled to the first conductive region of the transistor, the bit line being located below the original semiconductor surface. The memory cell structure of claim 1, further comprising a bit line electrically coupled to the first conductive region of the transistor through a bridge contact, the bridge contact being located below the original semiconductor surface, a first sidewall of the bridge contact being aligned with an edge of the bit line, the bridge contact having an upper and lower portion, the upper portion of the bridge contact abutting the first conductive region of the transistor, and the lower portion of the bridge contact being separated from the semiconductor substrate by a first isolation layer. The memory cell structure of claim 2, wherein the transistor further comprises a first spacer covering a first side of the gate structure and located above the original semiconductor surface, and a second spacer covering a second side of the gate structure and located above the original semiconductor surface, the second protruding region extending upward from the original semiconductor surface and abutting the second spacer, and the first protruding region abutting the first spacer and extending upward from an isolation region on the original semiconductor surface.