JP7582944B2 - High density coil design and processing - Google Patents

Description

The present invention generally relates to coil structures and manufacturing processes.

Electroplating processes for fabricating structures such as copper or copper alloy circuit structures, such as leads, traces, via interconnects, etc., are generally known and are disclosed, for example, in U.S. Patent No. 5,399,433 to Castellani et al., entitled Fine-Line Circuit Fabrication and Photoresist Application Therefor. These types of processes have been used in connection with the manufacture of disk drive head suspensions, as disclosed, for example, in U.S. Patent No. 5,399,433 to Bennin et al., entitled Low Resistance Ground Joints for Dual Stage Actuation Disk Drive Suspensions. U.S. Patent No. 5,333,436 to Rice et al., entitled "Integrated Lead Suspension with Multiple Trace Configurations," U.S. Patent No. 5,333,436 to Hentges et al., entitled "Multi-Layer Ground Plane Structures for Integrated Lead Suspensions," and U.S. Patent No. 5,333,436 to Hentges et al., entitled "Multi-Layer Ground Plane Structures for Integrated Lead Suspensions." Swanson et al., U.S. Patent No. 6,363,436 (Method for Making Noble Metal Conductive Leads for Suspension Assemblies); Peltoma et al., U.S. Patent No. 6,363,436 (Plated Ground Features for Integrated Lead Suspensions). These types of processes have also been used to manufacture camera lens suspensions, as disclosed, for example, in Miller, U.S. Patent No. 6,363,436 (Camera Lens Suspension with Polymer Bearings).

Superfilling and superconformal plating processes and compositions are also known and are disclosed, for example, in the following articles: "Electroplating in a trench (e.g., a photoresist masked trench defining a space for a structure to be electroplated)" (J. Appl. Phys. 2003, 143:1311-1323, 2003). In these processes, electroplating in a trench (e.g., a photoresist masked trench defining a space for a structure to be electroplated) occurs preferentially at the bottom. This avoids voids in the deposited structure. All of the above-mentioned patents and articles are incorporated herein by reference in their entirety and for all purposes.

U.S. Pat. No. 4,315,985 U.S. Pat. No. 8,885,299 U.S. Pat. No. 8,169,746 U.S. Pat. No. 8,144,430 U.S. Pat. No. 7,929,252 U.S. Pat. No. 7,388,733 U.S. Pat. No. 7,384,531 U.S. Pat. No. 9,366,879

Vereecken et al., “The chemistry of additives in damascene copper plating,” IBM J. of Res. &Dev. , vol. 49, no. 1, January 2005 Andricos et al., “Damascene copper electroplating for chip interconnections,” IBM J. of Res. &Dev. , vol. 42, no. 5, September 1998 Moffat et al., “Curvature enhanced adsorbage mechanism for bottom-up superfilling and bump control in damascene process ng,” Electrochimica Acta 53, pp. 145-154, 2007

There is a continuing need for enhanced circuit structures. There is also a continuing need for efficient and effective processes, including electroplating processes, for producing circuit structures and other structures.

An apparatus including a high aspect ratio electroplated structure and a method for forming the high aspect ratio electroplated structure are described. The method for producing a metal structure includes providing a substrate having a metal base characterized by a height-to-width aspect ratio and electroplating a metal crown onto the metal base to form a metal structure having a height-to-width aspect ratio greater than the aspect ratio of the metal base.

Other features and advantages of the embodiments of the present invention will become apparent from the accompanying drawings and from the detailed description that follows.
Embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like references indicate similar elements and in which:

1 shows a coil manufactured using current printed circuit technology. FIG. 1 illustrates a high density precision coil with high aspect ratio electroplated structures according to one embodiment. FIG. 2 is used to represent the electromagnetic force generated by a high density precision coil comprising high aspect ratio electroplated structures according to an embodiment. FIG. 1 illustrates an apparatus including multiple layers of high aspect ratio electroplated structures according to an embodiment configured for a linear motor type application. 1 illustrates a high aspect ratio electroplated structure according to some embodiments. 1 illustrates a high aspect ratio electroplated structure according to some embodiments. 1 illustrates a high aspect ratio electroplated structure according to some embodiments. 1 illustrates a device having multiple layer, high aspect ratio electroplated structures with dense cross-sectional areas according to some embodiments. 1 is a graph showing SPS coverage during high current density plating techniques and low current density plating techniques according to an embodiment. 1A-1D illustrate a process for forming high aspect ratio electroplated structures according to an embodiment. 1A-1D illustrate a process for forming high aspect ratio electroplated structures according to an embodiment. 1A-1D illustrate a process for forming high aspect ratio electroplated structures according to an embodiment. 1A-1D illustrate a process for forming high aspect ratio electroplated structures according to an embodiment. 1A-1D illustrate a process for forming high aspect ratio electroplated structures according to an embodiment. 1A-1D illustrate a process for forming high aspect ratio electroplated structures according to an embodiment. 1 illustrates a high aspect ratio electroplated structure according to some embodiments. 1 is a perspective view of a high aspect ratio electroplated structure according to some embodiments. 1 illustrates a high density precision coil formed using a high aspect ratio electroplated structure according to an embodiment. 1 illustrates a high density precision coil formed using a high aspect ratio electroplated structure according to an embodiment. 1 illustrates a high aspect ratio electroplated structure with high resolution laminate conductor layers according to an embodiment. 1 illustrates a high density precision coil with high aspect ratio electroplated structures according to an embodiment. 4 illustrates a process for forming high aspect ratio electroplated structures according to another embodiment. 4 illustrates a process for forming high aspect ratio electroplated structures according to another embodiment. 4 illustrates a process for forming high aspect ratio electroplated structures according to another embodiment. 1 illustrates selective formation of high aspect ratio electroplated structures according to one embodiment. 1 illustrates a perspective view of a high aspect ratio electroplated structure formed with a metal crown selectively formed on a trace, according to an embodiment. 1 illustrates a hard drive disk suspension flexure with high aspect ratio electroplated structures according to an embodiment. 20 is a cross-sectional view of the hard disk drive suspension flexure shown in FIG. 19. 1A-1C illustrate a process for forming high aspect ratio electroplated structures using photoresist during a conformal plating process according to an embodiment. 1A-1C illustrate a process for forming high aspect ratio electroplated structures using photoresist during a conformal plating process according to an embodiment. 1A-1C illustrate exemplary chemistries used in processes for forming an initial metal layer, standard/conformal plating processes, and crown plating processes, according to various embodiments. 1 is a top perspective view of an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment; FIG. 24 is a perspective view of the back side of the embodiment of the inductively coupled coil shown in FIG. 23 . FIG. 25 is a top perspective view of an inductively coupled coil 2502 according to an embodiment coupled to a radio frequency identification chip. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 1A-1C illustrate a method of forming an inductively coupled coil formed from high aspect ratio electroplated structures according to an embodiment. 2 is a plan view of a flexure for a hard disk drive suspension having high aspect ratio electroplated structures according to an embodiment; FIG. A cross-sectional view of the gap of the flexure at the gap taken along line A as shown in FIG. 27. 1 illustrates a gimbal portion having a mass structure according to an embodiment. 28 is a cross-sectional view of a mid-portion of a flexure with high aspect ratio electroplated structures according to an embodiment taken along line B as shown in FIG. 27. FIG. 28 is a cross-sectional view of a proximal portion of a flexure with high aspect ratio structures according to an embodiment taken along line C shown in FIG. 27. 13 is a plan view of a proximal portion of a flexure comprising a high aspect ratio structure according to an embodiment. FIG. 1A-1D illustrate a process for forming high aspect ratio electroplated structures according to an embodiment. FIG. 34 shows a more detailed process similar to the type described with reference to FIG. 33. 1 illustrates a coil according to an embodiment manufactured using processes described herein. 38 shows a cross section of the coil shown in FIG. 37. 1 illustrates a C-coil configuration with multiple coil sections, according to an embodiment. 1 illustrates a C-coil configuration according to an embodiment. FIG. 13 illustrates a formable/Z-plane shaped coil structure according to an embodiment. 1 illustrates a C-coil structure with a bridge according to an embodiment. 1 illustrates a C-coil structure with a bridge according to an embodiment. 1 illustrates an embodiment of a C-coil structure with a bridge, according to an embodiment. 1 illustrates an embodiment of a C-coil structure with a bridge, according to an embodiment. 1 illustrates an embodiment of a C-coil structure with a bridge, according to an embodiment. 1 illustrates a C-coil structure with a bridge according to an embodiment. 46 shows a cross section of a bridge of a C-shaped coil structure according to the embodiment shown in FIG. 45. 1 illustrates a coil structure according to an embodiment formed from multiple individual sections. 1 illustrates a coil structure according to an embodiment comprising multiple individual sections. 11A-11C illustrate alternative shapes for at least a portion of a coil structure according to an embodiment. 1A-1C illustrate surface mount coils for forming a coil structure according to an embodiment. 1 illustrates a surface mounted coil configured to be disposed on a substrate according to an embodiment. 2 is a top view of a substrate having multiple surface mounted coils attached thereto in accordance with an embodiment. 1 illustrates a surface mount coil with integrated trace jumpers according to an embodiment. 1 illustrates multiple surface mounted coil sections according to an embodiment. 1 illustrates a circuit board configured to mount coil portions to form a coil structure according to an embodiment. 1A-1D are multiple views of a coil structure according to an embodiment. 1A-1C show multiple views of a coil structure comprising a surface mounted coil according to an embodiment. FIG. 4 illustrates a coil portion according to an embodiment. 1 illustrates a coil structure according to an embodiment including solder joints for attaching one or more surface mounted coils. 1 illustrates a top view of a structure with solder joints for mechanically and electrically coupling a surface mounted circuit to the structure according to an embodiment. 61 is a bottom view of a structure with solder joints for mechanically and electrically coupling a surface mounted circuit to the structure of FIG. 60. FIG. 1 illustrates a structure including solder joints according to an embodiment. 1A and 1B are diagrams illustrating solder joints according to an embodiment. 1 is a cross-sectional view of a solder joint according to an embodiment. 1 is a flow diagram of a manufacturing process using solder joints according to an embodiment. 1A and 1B are diagrams illustrating a coil structure according to an embodiment. 1A and 1B are diagrams illustrating a coil structure according to an embodiment.

High-aspect ratio electroplated structures and methods for fabrication thereof according to embodiments of the present invention are described. High-aspect ratio electroplated structures provide tighter conductor pitch than current technology. For example, high-aspect ratio electroplated structures according to various embodiments include conductor stacks with cross-sectional areas of the conductor stacks greater than 50%. Additionally, high-aspect ratio electroplated structures according to embodiments allow for multiple conductor layers. Additionally, high-aspect ratio electroplated structures according to various embodiments allow for precise alignment from layer to layer. For example, high-aspect ratio electroplated structures can have layer-to-layer alignment of less than 0.030 mm. According to various embodiments, high-aspect ratio electroplated structures allow for a reduction in overall stack height.

The high aspect ratio electroplated structures of the embodiments allow for a thinner dielectric between the coil and magnet formed using the high aspect ratio electroplated structures. This allows the coil to generate a stronger electric field than current printed circuit coils such as that shown in FIG. 1. Thus, the high aspect ratio electroplated structures provide a more cost-effective, higher performance device and reduced device footprint compared to current technology.

Figure 2 shows a high-density precision coil with high-aspect ratio electroplated structures according to one embodiment. The high-aspect ratio electroplated structures 202 are formed in a row with a dielectric material between each row and each high-aspect ratio electroplated structure 204. The high-density precision coil can be formed as a helical coil or other coil types.

Figure 3 is a diagram used to represent the electro-magnetic force generated by a high density precision coil with a high aspect ratio electroplated structure according to an embodiment. The diagram shows a coil cross section 302 in close proximity to a magnet 304. The highest electromagnetic force 306 is at the coil layer 308 closest to the magnet 304. The coil layer 310 farther from the magnet 304 exerts a smaller force. The main factor influencing the force comes from the Lorentz equation: F (with → just above F) = J (with → just above J) x B (with → just above B). The magnitude of B (with → just above B) decreases with the distance between the coil and the magnet, so J (with → just above J) is the current flowing through the copper. The non-conducting portions of the coil cross section 302 do not contribute to the force (with → just above F).

The main factors that affect the force of a coil include the number of turns in the magnetic field (turns closest to the poles of the magnet exert the most force), the distance of the coil from the magnet (layers closer to the magnet exert more force), and the percentage of the total cross-sectional area of copper in the magnetic field. The high aspect ratio electroplated structures of some embodiments provide improvements in these areas compared to coils using current coil technology.

For example, a current technology two-layer coil has a total thickness of about 210 μm, a conductor pitch of 38 μm, a copper cross-sectional area percentage of about 20%, an estimated resistance of 3.1 Ω, an estimated force ratio of 1.0 (estimated B ratio of 1.0, estimated J ratio of 1.0), and an estimated power ratio of 1.0. In comparison, a high-density precision coil with a high aspect ratio electroplated structure according to various embodiments has a total thickness of about 116 μm, a conductor pitch of 40 μm, a copper cross-sectional area percentage of about 60%, an estimated resistance of 5.5 Ω, an estimated force ratio of 1.2 (estimated B ratio of 1.5, estimated J ratio of 0.8), and an estimated power ratio of 0.71. Thus, the high-density precision coil with a high aspect ratio electroplated structure according to various embodiments can be said to be a higher performance device. Thus, according to some embodiments, such a high-density precision coil is half the thickness of a coil using the current state of the art, and provides 20% more force with 30% less power.

Figure 4 shows an apparatus with multiple layers of high aspect ratio electroplated structures according to an embodiment configured for a linear motor type application. Due to dimensional advantages over current technology, each layer 402a-402d of the high aspect ratio electroplated structure is closer to the magnet 404 than is possible with current technology as shown in Figure 1. Furthermore, the proximity of each layer 402a-402d to the magnet 404 improves the force capability of the linear motor by utilizing the field (magnetic flux density) of volume B (directly above). Thus, the use of multi-layer high aspect ratio electroplated structures in linear motors requires fewer layers than current technology. Such structures also provide greater freedom to achieve electrical properties such as low resistance.

Figure 5 illustrates a stage in the manufacturing process of a high aspect ratio electroplated structure according to some embodiments. The layers of the high aspect ratio electroplated structure 602 at this stage in the manufacturing process are formed using semi-additive techniques to create fine pitch resist defined conductors with an initial height to width aspect ratio (A/B) of about 1:1. For example, the high aspect ratio electroplated structure may be 20 μm high and 20 μm wide. In some embodiments, the plating process is stopped at this point and the defining work, such as the photoresist mask and seed layers, are removed using techniques known in the art.

Figure 6 shows a high aspect ratio electroplated structure according to some embodiments at another stage in the manufacturing process. The layer of high aspect ratio electroplated structure 702 at this stage in the manufacturing process is formed using crown plate techniques to convert semi-additive conductors into high aspect ratio, high percentage metal conductor circuits. For example, the high aspect ratio electroplated structure has a final height to width ratio (A/S) greater than 1:1. The final height to width ratio may range from 1.2 to 3.0 according to various embodiments. Other embodiments have a final height to width ratio greater than 3.0. However, one skilled in the art will appreciate that any final height to width ratio can be obtained using the techniques described herein to meet design and performance criteria. At the stage of formation as shown in Figure 6 formed from the previous stage shown in Figure 5, there is no particular limit to the final height of the high aspect ratio electroplated structure disclosed in various embodiments.

Figure 7 illustrates a high aspect ratio electroplated structure at yet another stage in the manufacturing process, according to some embodiments. At this stage in the manufacturing process, the layers of high aspect ratio electroplated structures 802a, 802b are formed using planarization techniques to convert the multiple layers of high aspect ratio electroplated structures to be stacked using semi-additive techniques to form subsequent layers. Figure 8 illustrates a device having multiple layers of high aspect ratio electroplated structures with a high percentage of conductor cross-sectional area 901, according to some embodiments.

The method used to form the high aspect ratio electroplated structures from structures such as that shown in FIG. 5 includes using a low current density plating technique that plates the sidewalls until the desired spacing between the high aspect ratio electroplated structures is achieved. If the spacing between the high aspect ratio electroplated structures is not narrowed sufficiently, in various embodiments, undesirable pinching can occur at the top. Pinching occurs when the top edges of adjacent structures grow together and pinch the gap, resulting in a short circuit. In various embodiments, the low current density plating process is enhanced by sufficient fluid exchange to ensure that fresh plating bath is continually available to the surface where the copper plating is occurring. Additionally, the method for forming the high aspect ratio electroplated structures includes a high current density plating technique that is performed at a high percentage of the mass transfer limit. This results in plating primarily or solely on the conductive material forming high aspect ratio electroplating structures. High current density plating processes are enhanced by precisely controlling the current density. FIG. 9 shows a graph with an upper line 1002 showing high SPS coverage during a high current density plating technique in accordance with an embodiment, and a lower line 1004 showing low, highly uniform, accelerator coverage during a low current density plating technique in accordance with an embodiment.

10a-10f illustrate a process for forming a high aspect ratio electroplated structure according to an embodiment. FIG. 10a illustrates a trace 1102 formed at the thickness limit of resist capability at time T1 of the process. In some embodiments, pre-plated conventional traces are formed of copper using a process such as a damascene process or using etching and deposition techniques comprising those known in the art. FIG. 10b illustrates the formation of a high aspect ratio electroplated structure at time T2 during a low current density or conformal plating process. A conformal plating process according to an embodiment grows all surfaces of the trace at approximately the same rate. Additionally, the conformal plating process inhibits plating kinetics (low accelerator coverage). Also, the conformal plating process provides a fairly uniform metal concentration with high uniform inhibition coverage to compensate. Such plating kinetic inhibition effects can be increased by including a leveller in the plating bath. A lower current density is required to obtain uniform metal concentration and high uniform inhibition coverage. According to some embodiments, a conformal plating process using 2 amps per square decimeter is used to plate copper, brightener additives, plater temperature and fluid dynamics, etc. Examples of such conformal plating processes include, but are not limited to, low current density plating processes. At low current densities, the plating bath maintains a uniform inhibition state, allowing conformal plating. In another embodiment, the addition of a leveller to the plating bath allows for faster plating at higher current densities. In yet another embodiment, to further increase the current density, the copper content can be increased to near the solubility limit of copper sulfate in the plating bath. This allows the current density to be more than doubled to obtain the same conformal plating quality. For example, the copper content can be as high as 40 grams per liter with a reduced acid content to prevent general ionic effects.

In some embodiments, the low current density plate process deposits a conductive material, such as copper, on the top and sidewalls of the traces 1102, e.g., T2 is about 5 minutes into the low current density plate process (T1+5 minutes). FIG. 10c shows the formation of a high aspect ratio electroplated structure at time T3 into the low current density plate process. For embodiments, the low current density plate process deposits a conductive material, such as copper, on the top and sidewalls of the traces 1102, e.g., T3 is about 5 minutes into the low current density plate process (T1+15 minutes).

10d illustrates the formation of high aspect ratio electroplated structures at time T4 into the process during a crown plating process, such as a high current anisotropic super plating process. For example, T4 is about 15 minutes and 10 seconds into the process (T1+15 minutes and 10 seconds). In some embodiments, the high current anisotropic super plating process is crown plating. Crown plating is based on balancing the interactions between the following factors: metal concentration in solution; brightener additive; suppressor additive; mass transfer-fluid exchange rate to surface; leveler; and current density at the substrate. The metal concentration in the solution may include, but is not limited to, copper. Brightener additives may include, but are not limited to, SPS (bis(3-sulfopropyl) disulfide), DPS (3-N,N-dimethylaminodithiocarbamoyl-1-propanesulfonic acid), and MPS (mercaptopropylsulfonic acid). Suppressor additives include, but are not limited to, straight PEG of various molecular weights, poloxamines, coblock polymers of polyethylene and polypropylene glycol such as water-soluble poloxamers known under various trade names such as BASF pluronic f127, random copolymers such as the DOW® UCON family of high performance fluids, again with various ratios of monomers and various molecular weights, polyvinylpyrrolidone of various molecular weights, etc., including those known to those skilled in the art.

The high current anisotropic super plating process according to some embodiments has a suppressed exchange current that is 1% of the accelerating current. Additionally, the sidewalls of the high aspect ratio electroplated structures formed have near zero accelerator coverage. Near zero accelerator coverage is achieved by shifting the Nernst potential for copper deposition to favor suppressed coverage. Additionally, high overpotential and copper availability (transport phenomenon) provide high accelerator coverage at the top of the structures formed. Additionally, the copper bulk concentrate may be adjusted to support near zero accelerator coverage during the process. For example, the copper bulk concentrate for the high current anisotropic super plating process is 14 grams per liter or less. In some embodiments, the copper bulk concentrate depends on the specific fluid dynamics. Since various embodiments of the process are performed at a high percentage of mass transport limit, small differences in fluid velocity across the article being plated will affect what the mass transport limit is. Thus, without advanced control of the fluid velocity over all areas of the article being plated, it is difficult to achieve sufficient control of the gap between plating lines. The high current anisotropic super plating process according to some embodiments includes a leveler additive that defeats the accelerator coating to minimize or eliminate plating on the sidewalls of the structures being formed. In other embodiments, plating baths are used without the use of a leveler additive.

At high current densities, such as those used in high current anisotropic super plating processes, a threefold feedback mechanism operates according to some embodiments. Mass transport effects reduce copper in the spaces between the traces. Additionally, high current densities support accelerator (e.g., SPS) dominated surfaces. To maintain suppressed sidewalls, mass transport effects of copper are tuned to lower the Nernst potential. For example, the thickness of the fluid boundary layer and the spacing of each trace are engineered to lower the Nernst potential.

Additionally, some embodiments of the high current anisotropic super plating process are provided to operate with copper concentrations where these differences can produce a concentration difference of 4 times or more. During such conditions, the reduction in copper concentration and Nernst potential contributes to a reduction in plating rate. For example, a change in Nernst potential from about 50 millivolts (hereafter mV) to about 60 mV can result in a 20 times reduction in plating rate. Such conditions trigger Tafel kinetics, where for copper plating, the current changes 10 times for every 120 mV change in applied voltage, not the rectifier voltage. The low sidewall current is fed back to the top surface of the forming structure, which has a short diffusion length, thereby promoting faster delivery of metal from the plating bath (solution) to the surface, resulting in high accelerator coverage and high Nernst potential, not inhibition. In some embodiments, a two-additive system (e.g., brightener and inhibition) is used. The leveler counteracts the feedback mechanism by blocking the action of SPS at the top surface of the plated feature.

As the spacing between metal conductors or traces continues to shrink, the aspect ratio of the height to width of the spaces between the metal conductors increases significantly. According to some embodiments, the electroplating process methods provided herein achieve plating at spaces between metal conductors with aspect ratios of 7:1 or greater.

According to some embodiments, a method for forming high aspect ratio electroplated structures provides for selective formation of metal crown plating at selective locations or regions. In one exemplary embodiment, the selective formation of metal crown is achieved by performing an electroplating process according to the relationship C/(C∞)≦0.33, where C is the concentration of the metal (copper in this example) where plating is occurring, and C∞ is the bulk concentration of the plating bath. This relationship can also be expressed as performing an electroplating process where C/(C∞) is 67% or greater than the mass transport limit. According to other embodiments, the selective formation of metal crown is achieved by performing an electroplating process according to the relationship C/(C∞)≦0.2, i.e., C/(C∞) is 80% or greater than the mass transport limit. In another aspect, the selective formation of metal crown is achieved by performing an electroplating process according to the relationship i/(i limit)≧0.8, where i is the current density and (i limit) is the current density limit.

Figure 10e illustrates the formation of high aspect ratio electroplated structures at time T5 during the high current anisotropic super plating process. For example, T5 is about 15 minutes 30 seconds from the start of the process (T1 + 15 minutes 30 seconds). In another embodiment, the formation of high aspect ratio electroplated structures as illustrated in Figure 10e occurs at time T5 = T1 + 5 minutes. Figure 10f illustrates the formation of high aspect ratio electroplated structures at time T6 during the high current anisotropic super plating process. This illustrates the end of the crown plating process that ultimately results in the formation of high aspect ratio electroplated structures according to some embodiments. For example, T6 is about 20 minutes from the start of the process (T1 + 20 minutes). For another embodiment, the formation of high aspect ratio electroplated structures as illustrated in Figure 10f occurs at time T6 = T1 + 10 minutes.

For some embodiments, the method of forming high aspect ratio electroplated structures uses a process comprising conformal plating and anisotropic plating as described herein. According to some embodiments, the conformal plating process uses 2/3 of the total plating time. In other embodiments, the conformal plating process uses 1/3 of the total plating time. Furthermore, the conformal plating process starts at 2 amps per square decimeter ("ASD") for low metal plating baths and 4 ASD for high metal plating baths. For example, the plating baths include 12 grams of copper per liter and 1.85 moles (moles/liter) of sulfuric acid. Alternatively, the conformal plating process is a process that plates at a rate of 0.4 to 1.2 μm per minute. According to embodiments, the conformal plating process continues until the spacing between the traces is in the range of 6 to 8 μm. The current density gradually decreases as the surface area of the structure being formed increases. However, the process achieves a uniform current density and growth rate on all surfaces being formed. In some embodiments, the current can be increased to maintain the current density as the surface area of the high aspect ratio structures formed increases.

An anisotropic plating process according to some embodiments uses 1/3 of the total plating time to form high aspect ratio electroplated structures. Anisotropic plating increases the ASD to 7 ASD (3.5 times the current of conformal plating), but on average doubles it on the top of the metal structure being formed. Also, the same fluid flow as the conformal plating process can be maintained. For example, the plating rate is 3 μm per minute on the top of the structure being formed, and the plating rate is nearly zero on the sidewalls of the structure. As the structure grows, the average current drops by half, but the peak current density is maintained at about 14 ASD on the top of the structure according to embodiments. For example, the peak current density is just over 50% of the mass transport limit on the top surface, and even though the sidewalls are exposed to about 3 grams of copper per liter, the sidewalls are plated at less than 10% of the mass transport limit, or a plating rate of 5:1. At a higher fraction of the mass transport limit, a higher plating rate ratio can be obtained.

Embodiments of the method for forming high aspect ratio electroplated structures include variations on those described above to form high aspect ratio electroplated structures with different properties. For example, the copper content in a plating bath configured as an anisotropic bath can be different from the 13.5 grams per liter described above. Varying the copper content in the flat trace bath while using the same current density can be used to control the spacing between the high aspect ratio electroplated structures. Another embodiment of the method described herein includes using a flat trace bath with a copper content of 12 grams per liter to form high aspect ratio electroplated structures spaced 8 μm apart. Yet another embodiment of the method described herein includes using a flat trace bath with a copper content of 15 grams per liter to form high aspect ratio electroplated structures spaced 4 μm apart. Thus, one skilled in the art will appreciate that other parameters of the method described herein can be adjusted to vary the properties of the high aspect ratio electroplated structures. Some embodiments of the method described herein include adjusting the current density to match the conditions of the current plating equipment, such as mass transfer rate, metals contained in the plating bath, fluid velocity, copper concentration, additives used, and temperature.

The method of forming high aspect ratio electroplated structures also includes using a thin dielectric process. According to some embodiments, a photosensitive polyimide is used as the dielectric between each of the high aspect ratio electroplated structures. Liquid photosensitive polyimide provides small diameter vias, good coverage between high aspect ratio conductors, good registration/margins, is a highly reliable material, and has a coefficient of thermal expansion ("CTE") close to that of copper. Liquid photosensitive polyimide can easily fill the gaps between the high aspect ratio electroplated structures. In some embodiments, photosensitive polyimide is used to provide 0.030 mm via access. Other dielectrics that can be used include, but are not limited to, KMPR and SU-8.

11 illustrates high aspect ratio electroplated structures according to some embodiments formed using methods described herein. Each high aspect ratio electroplated structure 1202 includes a number of grain lines 1204 that indicate how the electroplating process progresses to form the structure. A thin dielectric 1206 is formed between and over the high aspect ratio electroplated structures 1202. FIG. 12 illustrates a perspective view of a high aspect ratio electroplated structure 1302 according to some embodiments formed using methods described herein.

The methods described herein can be used to form high aspect ratio electroplated structures that form high density precision coils. FIG. 13a shows a high density precision coil formed using a high aspect ratio electroplated structure according to one embodiment. A coil 1402 is formed with a high aspect ratio electroplated structure as described herein. The high density precision coil also includes a center coil via 1404. The center coil via 1404 reduces the voltage drop across the coil during the manufacturing process described herein. Additionally, the center coil via 1404 allows for the ability to better control pitch variations within the coil through better control of voltage drop and current during the anisotropic plating process described herein. The center coil via 1404 also allows for better control of the voltage drop of the formed high density precision coil. FIG. 13b shows a cross section of the center coil via 1404 as part of a high density precision coil as described herein.

14 illustrates high aspect ratio electroplated structures comprising high resolution stacked conductor layers according to one embodiment. The first conductor layer 1502a comprises high aspect ratio electroplated structures 1504 formed using techniques including those described herein. The first dielectric layer 1508 is formed using a thin dielectric process using techniques including those described herein. The first dielectric layer 1508 fills all spaces between the high aspect ratio electroplated structures of the first conductor layer 1502a and forms a coating on the high aspect ratio electroplated structures 1504. The first dielectric layer 1508 is planarized using techniques known in the art. The second conductor layer 1502b comprises high aspect ratio electroplated structures 1506 formed on the planarized surface of the first dielectric layer 1508. The second dielectric layer 1510 is formed using a thin dielectric process using techniques including those described herein to fill all spaces between the high aspect ratio electroplated structures 1506 of the second conductor layer 1502b and form a coating over the high aspect ratio electroplated structures 1506. The second dielectric layer 1510 may also be planarized. Additional layers comprising high aspect ratio electroplated structures may be formed using techniques described herein.

15 shows a high density precision coil with high aspect ratio electroplated structures according to an embodiment with high resolution laminate conductor layers. The first conductor layer 1602a includes high aspect ratio electroplated structures formed using techniques including those described herein. The first dielectric layer 1608 is formed using a thin dielectric process using techniques including those described herein. The first dielectric layer 1608 fills all spaces between the high aspect ratio electroplated structures of the first conductor layer 1602a and forms a coating over the high aspect ratio electroplated structures. The first dielectric layer 1608 is planarized using techniques known in the art. The second conductor layer 1602b includes high aspect ratio electroplated structures formed on the planarized surface of the first dielectric layer 1608. The second dielectric layer 1610 is formed using a thin dielectric process using techniques including those described herein to fill all spaces between the high aspect ratio electroplated structures of the second conductor layer 1602b and form a coating over the high aspect ratio electroplated structures. The second dielectric layer 1610 can also be planarized. Additional layers comprising high aspect ratio electroplated structures can be formed using the techniques described herein.

The high density precision coil is formed having a first distance 1614 between the high aspect ratio electroplated structures of the first conductor layer 1602a and the high aspect ratio electroplated structures of the second conductor layer 1602b. For various embodiments, the first distance 1614 is less than 0.020 mm. In another embodiment, the first distance 1614 is 0.010 mm. The high density precision coil is formed having a second distance 1616 between the surface 1618 of the second dielectric layer 1610 and the high aspect ratio electroplated structures of the first conductor layer 1602a. For various embodiments, the second distance 1616 is less than 0.010 mm. For some embodiments, the second distance 1616 is 0.005 mm. For some embodiments, the second distance 1616 can be the starting gap minus the final desired gap divided by two. The high density precision coil is formed having a third distance 1620 between the high aspect ratio electroplated structure of the first conductor layer 1602a and the surface of the first dielectric layer 1622. For various embodiments, the third distance 1620 is less than 0.020 mm. For some embodiments, the third distance 1620 is less than 0.015 mm. In another embodiment, the third distance 1620 is 0.010 mm. For various embodiments, the first dielectric layer is formed on a substrate 1624 using techniques including those described herein. For some embodiments, the substrate 1624 is a stainless steel layer. Those skilled in the art will appreciate that the substrate 1624 can be formed of other materials including, but not limited to, steel alloys, copper alloys such as bronze, pure copper, nickel alloys, beryllium copper alloys, and other metals comprising those known in the art.

Other advantages of forming devices using the high aspect ratio electroplated structures described herein include devices with high structural strength, high reliability, and high heat dissipation capabilities. High structural strength is provided by the ability to form very dense metal high aspect ratio electroplated structures on all layers of the device. Additionally, the processes for forming metal high aspect ratio electroplated structures described herein allow for lateral alignment of structures from layer to layer, providing high structural strength. The high structural strength of devices formed using the processes for forming metal high aspect ratio electroplated structures described herein is also a result of good adhesion of dielectric layer materials, such as photosensitive polyimide layers, to the structures. In some embodiments, the high aspect ratio electroplated structures formed using the techniques described herein are coated with a non-magnetic nickel layer to enhance adhesion of the dielectric layer. This can further enhance the high structural strength of the final devices formed using the high aspect ratio electroplated structures described herein.

The reliability of devices formed using the high aspect ratio electroplated structures described herein is also high due to the use of highly reliable materials, such as photosensitive polyimide, for the dielectric layer, resulting in robust electrical performance. Use of the techniques described herein provides the ability to form devices using less dielectric material, reducing the overall thickness of the formed devices, thereby providing greater thermal conductivity and increased heat dissipation over devices using current processing techniques.

Figures 16a-c show a process for forming a high aspect ratio electroplated structure according to another embodiment. Figure 16a shows traces 1802 formed on a substrate 1804 using a subtractive etch. According to some embodiments, there is a metal layer formed on the substrate 1804. A photoresist layer is formed on the metal layer using techniques including those known in the art. In some embodiments, the photoresist layer is a photosensitive polyimide deposited in liquid form on the metal layer. The photoresist is patterned and developed using techniques known in the art. The metal layer is then etched using techniques known in the art. After the etching process, the traces 1802 are formed.

16b illustrates the formation of a high aspect ratio electroplated structure using a conformal plating process as described herein. FIG. 16c illustrates the formation of a high aspect ratio electroplated structure using a crown plating process as described herein. In various embodiments, the high aspect ratio electroplated structure is formed without using a conformal plating process as described with reference to FIG. 16b. Instead, a crown plating process as described with reference to FIG. 16c is used after the formation of the trace 1802 as shown in FIG. 16a.

17 illustrates selective formation of high aspect ratio electroplated structures according to embodiments. Once the traces 1902 are formed using techniques including those described herein, a photoresist layer 1904 is formed on one or more sections of the formed traces 1902. The photoresist layer 1904 can be a photosensitive polyimide and is deposited and formed using techniques including those described herein. A metal crown 1906 is formed on the traces 1902 using one or both of the conformal plating and crown plating processes described herein. FIG. 18 illustrates a perspective view of a high aspect ratio electroplated structure according to an embodiment formed with a metal crown portion selectively formed on the trace. According to some embodiments, selectively forming a metal crown portion on the trace is used to improve structural properties of the high aspect ratio electroplated structure, improve electrical performance of the high aspect ratio electroplated structure, improve heat transfer properties, and meet custom dimensional requirements of devices formed with the high aspect ratio electroplated structure. Examples of improved electrical performance include, but are not limited to, capacitance, inductance, and resistance properties of the high aspect ratio electroplated structure. Additionally, selective formation of metal crowns on the traces can be used to tailor the mechanical or electrical properties of circuits formed using high aspect ratio electroplated structures.

19 illustrates a hard drive disk suspension flexure 2102 with high aspect ratio electroplated structures according to embodiments formed using selective formation as described herein. FIG. 20 illustrates a cross-sectional view of the hard drive suspension flexure shown in FIG. 19 taken along line A-A. The cross-section of the hard drive disk suspension flexure 2102 includes high aspect ratio electroplated structures 2104 and traces 2106. The high aspect ratio electroplated structures 2104 are formed using selective formation techniques as described herein. The high aspect ratio electroplated structures 2104 can be formed to serve as conductors in predefined areas of the flexure to achieve reduced DC resistance. This allows fine lines and spaces to be provided where needed in the flexure while still meeting DC resistance design requirements, improving the electrical performance of the flexure.

21a-b show a process for forming high aspect ratio electroplated structures using photoresist during a conformal plating process according to an embodiment. FIG. 21a shows traces 2302 formed on a substrate 2304 using techniques including those described herein. FIG. 21b shows the formation of high aspect ratio electroplated structures using a plating process as described herein. Photoresist portions 2306 are formed on the substrate 2304 using deposition and patterning techniques including those described herein. Once the photoresist portions 2306 are formed, one or both of a conformal plating process and a crown plating process are performed to form metal portions 2308 on the traces 2302. The photoresist portions 2306 can be used to provide more defined spacing between the high aspect ratio electroplated structures.

FIG. 22 illustrates exemplary chemistries used in processes for forming the initial metal layer, standard/conformal plating processes, and crown plating processes, according to various embodiments.
23 is a perspective view of a top surface 2501 of an inductively coupled coil 2502 formed from a high aspect ratio electroplated structure 2504 according to an embodiment with an integrated tuning capacitor. The use of a high aspect ratio electroplated structure to form the inductively coupled coil allows the footprint of the inductively coupled coil to be reduced as compared to inductively coupled coils using current technology to form the coil. This allows the inductively coupled coil 2502 to be used in applications where space is limited. Additionally, the use of an integrated capacitor in the inductively coupled coil further reduces the footprint of the inductively coupled coil by eliminating the extra space requirements to accommodate a discrete capacitor, such as a surface mount technology ("SMT") capacitor.

FIG. 24 shows a perspective view of the backside 2604 of an embodiment of the inductively coupled coil 2502 shown in FIG. 23. FIG. 25 shows a perspective view of the top side of the inductively coupled coil 2502 according to an embodiment coupled to a radio frequency identification ("RFID") chip 2704.

26a-26j illustrate a method of forming an inductively coupled coil 2502 formed from high aspect ratio electroplated structures 2504 according to an embodiment. According to various embodiments, the inductively coupled coil includes an integrated tuning capacitor. FIG. 26a illustrates a substrate 2802 formed using techniques including those known in the art. In some embodiments, the substrate 2802 is formed of stainless steel. Other materials that can be used for the substrate include, but are not limited to, steel alloys, copper, copper alloys, aluminum, and non-conductive materials that can be metallized using techniques including plasma deposition, chemical vapor deposition, and electroless chemical vapor deposition. A shadow mask 2804 is formed over the substrate 2802. The shadow mask 2804 is a high K dielectric according to some embodiments. Examples of high-K dielectrics that can be used include, but are not limited to, titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, SU-8, KMPR, and other high-k dielectric materials. According to some embodiments, the shadow mask 2804 is formed using a sputtering process using techniques including those known in the art. For some embodiments, the shadow mask 2804 is formed to have a thickness ranging from 500 to 1000 angstroms, inclusive. For other embodiments, the shadow mask 2804 is formed using screen printing of a high-permittivity ink. Examples of high-k inks include inks comprising epoxies loaded with particles made from one or more of titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, and other high-k dielectric materials. In yet another embodiment, the shadow mask 2804 is formed using a slot die application of a photoimageable dielectric doped with a high-K filler. An example of a high-K filler includes zirconium dioxide (ZrO2).

Figure 26b shows a metal capacitor plate 2806 formed on a shadow mask 2804. The metal capacitor plate 2806 and the substrate 2802 form the two capacitor plates of the integrated capacitor. The thickness of the shadow mask 2804 can be used to set the effective capacitance of the integrated capacitor. Additionally, the purity of the high-K dielectric used to form the shadow mask 2804 can be used to set the effective capacitance of the integrated capacitor. The surface area of the metal capacitor plate 2806 can also be used to set the effective capacitance of the integrated capacitor.

26c shows a base dielectric layer 2808 formed over the shadow mask 2804, the metal capacitor plate 2806, and at least a portion of the substrate 2802. In some embodiments, the base dielectric layer 2808 is formed by depositing a dielectric material, patterning the dielectric material, and curing the dielectric material using techniques including those known in the art. Examples of dielectric materials that can be used include, but are not limited to, polyimide, SU-8, KMPR, or hard baked photoresist such as those available from IBM®. The base dielectric layer 2808 may be patterned or etched to form vias. For example, jumper vias 2812 and shunt capacitor vias 2810 are formed in the base dielectric layer 2808. The shunt capacitor vias 2810 are formed to interconnect the integrated capacitors to the remainder of the circuit being formed. Similarly, jumper vias 2812 are used to interconnect the circuit elements to be formed to the substrate 2802.

26d shows a coil 2814 formed on a base dielectric layer 2808 using high aspect ratio electroplating structures to form the coil using techniques including those described herein. In some embodiments, the coil 2814 is a single layer coil. The coil 2814 includes a center connect portion 2816 that connects one of the shunt capacitor vias 2810 to one of the jumper vias 2812 that is in electrical contact with the metal capacitor plate 2806 of the integrated capacitor. The coil 2814 also includes a capacitor connection portion 2818 that connects the coil 2814 to the other of the shunt capacitor vias 2810 that is in electrical contact with the substrate 2802 that is configured as the bottom plate of the integrated capacitor. According to various embodiments, a terminal pad 2820 is formed with high aspect ratio electroplating structures using techniques including those described herein. The terminal pad 2820 can be formed during the same process used to form the coil 2814.

Figure 26e shows a covercoat 2822 formed over the coil 2814, over the terminal pads 2820, and over the base dielectric layer 2808 to enclose the coil side of the inductively coupled coil. The covercoat 2822 is formed using deposition, etching, and patterning processes including those known in the art. The covercoat 2822 can be formed, for example, from polyimide solder mask, SU-8, KMPR, or epoxy.

Figure 26f shows a backside of an inductively coupled coil formed in accordance with an embodiment. At least a first solder pad 2824 and a second solder pad 2826 are formed on the opposite side of the substrate 2802 from the coil 2814. According to some embodiments, the first solder pad 2824 and the second solder pad 2826 are formed of gold using deposition and patterning techniques comprising those known in the art. The first solder pad 2824 and the second solder pad 2826 are formed to provide electrical contacts for attaching an integrated circuit chip, such as an RFID chip, to the substrate 2802.

26g illustrates a backside dielectric layer 2828 formed on the backside of an inductively coupled coil formed according to an embodiment. The method of forming the inductively coupled coil may optionally include forming a backside dielectric layer 2828 on the substrate 2802. The backside dielectric layer 2828 is formed using a technique similar to that of forming the base dielectric layer 2808. According to some embodiments, the backside dielectric layer 2828 is patterned to prevent shorts between the substrate 2802 and an attached integrated circuit chip. The backside dielectric layer 2828 according to various embodiments is patterned to provide a jumper pattern 2830 for etching the substrate 2802 to form a jumper path in a subsequent process. Other patterns of the backside dielectric may also be formed to etch other portions of the substrate 2802.

Figure 26h shows an inductively coupled coil 2834 according to an embodiment formed into its final shape. Portions of the substrate 2802 not covered by the backside dielectric layer 2828 are etched. Such etched portions include a jumper pattern 2830 to form a jumper path 2832. Etching is performed using techniques including those known in the art. Those skilled in the art will appreciate that other portions of the substrate 2802 may be etched to form other conductive paths similar to the jumper path 2832. Figure 26i shows the coil side of the inductively coupled coil 2834 according to an embodiment, including the jumper path 2832.

Figure 26j illustrates the coil side of an inductively coupled coil 2834 according to one embodiment, with an integrated chip 2836 attached to the back side of the inductive coil. The method of forming the inductively coupled coil 2834 can optionally include attaching an integrated chip 2836, such as an RFID chip, to the inductively coupled coil 2834 using techniques including those known in the art. Such integrated chips 2836 can be attached using adhesives including but not limited to conductive epoxies, solders, and other materials used for electrical connections.

Integrating capacitors into devices that include high aspect ratio electroplated structures can take advantage of the small footprint requirements that are realized by using high aspect ratio electroplated structures. Other embodiments of inductively coupled coils include inductively coupled coils with multiple integrated capacitors. The integrated capacitors can be connected in parallel or in series as known in the art. Other devices that include high aspect ratio electroplated structures that may also include integrated capacitors include, but are not limited to, step-down transformers, signal conditioners, tuning devices, and other devices that may include one or more inductors and one or more capacitors.

High aspect ratio electroplated structures according to embodiments described herein can be used to form devices or form part of devices to optimize performance and achieve small footprints. Such devices include power converters (e.g., step-down transformers, voltage dividers, AC transformers), actuators (e.g., linear, VCM), antennas (e.g., RFID, wireless power for battery charging, security chips, etc.), wireless passive coils, mobile phones with charging capabilities, batteries for medical devices, proximity sensors, pressure sensors, contactless connectors, micromotors, microfluidics, on-package cooling sinks, elongated flexible circuits with air-core capacitance-inductance (e.g., for catheters), digitized acoustic wave transducers, tactile vibrators, implantable devices (pacemakers, stimulators, bone growth devices, etc.). Applications include medical devices, such as medical devices, medical equipment, medical devices ... Other interconnect applications with high aspect ratio electroplated structures can integrate one or more circuits of different currents (e.g., signal and power). Using high aspect ratio electroplated structures, circuits with different cross sections or circuits capable of carrying more current can be fabricated in close proximity, reducing the overall package size. High aspect ratio electroplated structures can also be used in interconnects for mechanical purposes. For example, it may be desirable to have some areas of a circuit protrude beyond other areas to act as mechanical stops, bearings, electrical contact zones, or to provide additional rigidity.

27 is a plan view of a flexure for a hard disk drive suspension having a high aspect ratio electroplating structure according to an embodiment. The flexure 2900 includes a distal portion 2901, a gimbal portion 2902, an intermediate portion 2904, a gap portion 2906, and a proximal portion 2908. The proximal portion 2908 is configured to be attached to a base plate such that the distal portion 2901 extends above a rotating disk medium. According to some embodiments, the gimbal portion 2902 is configured to include one or more motors, such as a piezoelectric motor, and one or more electrical components, such as a head slider for reading or writing to the disk medium or components for thermally assisted magnetic recording ("HAMR")/temperature assisted magnetic recording ("TAMR") or microwave assisted magnetic recording ("MAMR"). The motor(s) and electrical component(s) are electrically connected to other circuitry via one or more traces formed in the conductor layer of the flexure that extend from the distal portion 2901 of the flexure 2900 through the intermediate portion 2904, across the gap portion 2906, and across the proximal portion 2908. The gap portion 2906 is a portion of the flexure where a substrate layer, such as a stainless steel layer, has been partially or completely removed. Thus, the trace(s) in the conductor layer of the flexure extend across the gap portion 2906 without support. One skilled in the art will appreciate that a flexure may have one or more gap portions 2906 at any location along the flexure.

28 shows a cross section of the gap of the flexure at the gap taken along line A as shown in FIG. 27. The gap 2906 includes a trace 3002 disposed on a dielectric layer 3004. The dielectric layer, such as a polyimide layer, is disposed on a substrate 3006, such as a stainless steel layer. The substrate 3006 and the dielectric layer 3004 define a void 3008 such that the trace 3002 extends over the void 3008. The trace 3002 includes a metal crown to form a high aspect ratio structure. The metal crown is selectively formed on the trace 3002 using techniques described herein. The metal crown is formed on the trace 3002 to provide additional strength to span the void 3008 when used to electrically couple with an interconnect in the region of the void 3008.

29 illustrates a gimbal portion 2902 having a mass structure 3102 according to an embodiment. The mass structure 3102 is formed using a high aspect ratio electroplating structure using techniques described herein. In some embodiments, the mass structure 3102 is used as a weight to tune the resonance of the gimbal portion 2902. Thus, the shape, size, and location of the mass structure 3102 can be determined to tune the resonance of the gimbal portion 2902 and improve the performance of the hard drive suspension. The process described herein used to form the high aspect ratio structure can be used to maintain the size of the high aspect ratio structure so that the resonance can be fine-tuned. Additionally, the process is capable of forming high aspect ratio structures with dimensions beyond the capabilities of current lithographic processes, allowing for greater control over the final structure formed.

The mass structure 3102 can also be configured for use as a mechanical stop. For example, one or more mechanical stops can be formed in any shape to act as a backstop and/or be used to align the attachment of a component to the gimbal portion 2902 or other portion of the flexure.

30 shows a cross-section of a middle (proximal) portion of a flexure with a high aspect ratio electroplated structure according to an embodiment taken along line B as shown in FIG. 27. The middle portion 2904 includes a conductor layer with traces 3002a, 3002b, 3002c, 3002d disposed on a dielectric layer 3004. The dielectric layer 3004 is disposed on a substrate 3006. A cover layer 3001 is disposed on the conductor layer and the dielectric layer. The conductor layer includes conventional traces 3002a, 3002b and traces 3002c, 3002d formed with at least a portion of the traces having metal crowns 3202a, 3202b to form a high aspect ratio electroplated structure using the techniques described herein. One or more portions of the traces 3002a, 3002b, 3002c, 3002d can be formed with metal crowns 3202a, 3202b to adjust the impedance of each trace. For example, the resistance of the traces can be adjusted as needed to meet desired performance characteristics. Another example is that the metal crowns can be used to reduce the distance between adjacent traces 3002a, 3002b, 3002c, 3002d to adjust the impedance.

31 shows a cross-section of a proximal portion of a flexure with a high aspect ratio structure according to an embodiment taken along line C as shown in FIG. 27. The proximal portion of the flexure includes a conductor layer including at least a trace 3002 disposed on a dielectric layer 3004. The dielectric layer 3004 is disposed on a substrate 3006. A cover layer 3001 is disposed thereon, which is further formed with a metal crown to form a high aspect ratio electroplated structure using the techniques described herein. The trace 3002 is configured as a high aspect ratio structure to match the impedance of the trace with a terminating connector and to provide strength to the joint electrically coupling the trace 3002 to the connector. FIG. 32 is a plan view of a proximal portion 2908 of a flexure with a high aspect ratio structure according to an embodiment. The use of high aspect ratio structures described with reference to their use in flexures is applicable to other circuit board technologies, for example, for use in microcircuits and radio frequency ("RF") circuits.

FIG. 33 illustrates a process for forming a high aspect ratio electroplated structure according to an embodiment. As shown, a copper layer 3318 is used as the substrate. However, other conductive materials can be used as the substrate. In 3301, a dielectric layer 3320 is placed on the copper layer 3318 as described herein, marked and punched. The dielectric layer 3320 can be formed using materials including, but not limited to, photoimageable or non-photoimageable materials, polymers, ceramics, and other insulating materials. The copper layer 3318 is, for some embodiments, a copper alloy layer as described herein. For some embodiments, one or more through holes or vias 3322 are marked and punched in the dielectric layer to expose the copper layer 3318. According to some embodiments, the dielectric layer 3320 is a photoimageable dielectric material and the one or more through holes or vias 3322 are created using patterning and development techniques including those described herein. Other embodiments include using a laser, drilling, or etching the dielectric layer 3320 to create one or more through holes or vias 3322. In some embodiments, the copper alloy layer has a thickness in the range comprising 15 μm to 40 μm. At 3302, traces 3324 or other conductive features are disposed on the dielectric layer 3320 on the side of the dielectric layer opposite the copper layer 3318. In some embodiments, a seed layer is sputtered to form a pattern on the dielectric layer 3320 using techniques including those described herein. Other embodiments include using electroless plating to form the seed layer. A plating process including those described herein is used to form one or more traces 3324 and conductive features to a desired thickness using techniques including those described herein.

At 3304, a conformal plating process such as those described herein is used to build up one or more traces and conductive features to increase their thickness or further enhance their shape on the side of the dielectric layer 3320 opposite the copper layer 3318 using techniques such as those described herein. In some embodiments, at 3304, a crown plating process such as those described herein is used in addition to the conformal plating process on the side of the dielectric layer 3320 opposite the copper layer 3318. In some embodiments, a crown plating process is used instead of a conformal plating process.

At 3306, a dielectric layer 3326, such as a cover coat, is disposed over the one or more traces 3324 and conductive features on the side of the dielectric layer opposite the copper layer 3318, using techniques including those described herein. In some embodiments, a cover coat is not included. For example, the formed one or more traces 3324 and conductive features may be plated with a gold layer. At 3308, the copper layer 3318 is etched to form a pattern, using techniques including those described herein. In some embodiments, the copper layer 3318 is etched to form one or more traces 3328 and/or one or more conductive features.

At 3310, a conformal plating process such as those described herein is used to build up one or more traces 3328 and conductive features formed in the copper layer 3318 to increase their thickness or further enhance their shape using techniques such as those described herein. In some embodiments, at 3310, a crown plating process such as those described herein is used in addition to the conformal plating process on the copper layer 3318. In some embodiments, a crown plating process is used instead of a conformal plating process.

At 3312, a dielectric layer 3330, such as a cover coat, is disposed over the one or more traces 3328 and conductive features formed from the copper layer 3318 using techniques including those described herein. In some embodiments, a cover coat is not included. For example, the one or more traces 3328 and conductive features formed may be plated with a gold layer. For some embodiments, this process is used to fabricate multiple circuits or devices on a single substrate. At 3316, for such embodiments, the circuits or devices may be singularized and optionally packaged using techniques including those known in the art. In some embodiments, the circuits and/or devices are singularized using techniques including, but not limited to, laser ablation, fracturing, cutting, etching, and the like. For some embodiments, the cover coat described herein may be patterned using patterning techniques described herein. For example, the cover coat is applied in a blanket layer. According to some embodiments, the cover coat is applied using a slot die coat to apply the photoimageable dielectric material. Other techniques may be used, such as roller coating, spray coating, dry film lamination, or other known methods for applying photoimageable or non-photoimageable materials. If the material is non-photoimageable, it may be patterned using other methods (e.g., laser or etching). In some embodiments, one or both dielectric layers/covercoats may be formed with a surface finish, for example to aid in attachment to other structures or substrates. In some embodiments, the surface finish is formed on the dielectric layer/covercoat by texturing or patterning the dielectric layer/covercoat.

At 3314, for some embodiments, terminal pads 3332, such as nickel terminals plated with a gold layer, are formed on the copper layer (substrate) 3318 using electroless plating and may include solder. According to some embodiments, the surface finish formed on the exposed copper layer disposed on the top and/or bottom surfaces is plated using electroless or electrolytic plating of nickel, gold, or other industry standard surface finishes. Solder may also be applied to these portions.

FIG. 34 illustrates a more detailed process similar to the type described with reference to FIG. 33 that is used to form high aspect ratio electroplated structures according to some embodiments.
FIG. 35 illustrates a coil fabricated using the processes described herein. Coil 3501 comprises multiple coil sections, e.g., three or more coil sections, electrically coupled to form coil 3501. In some embodiments, as illustrated in FIG. 35, the outer coil section 3504 has the same number of turns as the inner coil section 3502 between the two outer coil sections 3504. In some embodiments, the inner coil section 3502 comprises more turns than the outer coil section 3504. Other embodiments comprise multiple coil sections where a subset of the multiple coil sections are electrically coupled, e.g., referring to FIG. 35, two of the multiple coil sections are electrically coupled and the remaining coil sections are not electrically coupled to the other two coil sections. In this manner, any combination of any number of coil sections may comprise any number of coil sections electrically coupled to any of the other coil sections.

Multiple layers containing any one or more of the traces and conductive features manufactured using the techniques described herein can be formed by laminating the layers together, with connections between the layers being made using vias through the layers filled with a conductive material, such as a conductive adhesive.

According to some embodiments, the processes described herein are used to form coils that are integrated with other circuit components, such as, for example, resistance temperature detectors (RTDs), strain gauges, and other sensors.

Figure 36 shows a cross section of the coil shown in Figure 37, which includes a first dielectric/cover layer 3602, a first copper layer 3604, a second dielectric layer 3606, a second copper layer 3608, and a third dielectric layer 3610. Figure 37 shows a C-shaped coil structure 3701 including multiple coil sections 3702 according to one embodiment. In some embodiments, the multiple coil sections are connected at corners. The C-shaped coil structure 3701 according to some embodiments is formed using techniques including those described herein. The C-shaped coil structure 3701 can provide improved manufacturing efficiency over current coil geometries. Figure 38 shows an arrangement of the C-shaped coil structure 3701 according to one embodiment that allows for manufacturing efficiency. The interleaved configuration allows for more coil structures to be produced during the manufacturing process than current coil structures.

Figure 39 illustrates a formable/Z-plane formed (e.g., formed with offset) coil structure 3901 according to an embodiment. The coil structure 3901 is configured such that at least one portion or section 3902 can be moved to form the component after circuit fabrication to provide other features such as coils or bond pads in a substantially different plane than other sections 3902 of the coil structure, e.g., the Z plane instead of the X, Y planes. For example, section 3902 can be mechanically formed along dashed line 3904 to present the coil on the left side of the component in the Z plane.

FIG. 40 illustrates a C-shaped coil structure 4001 with a bridge according to one embodiment. The bridge 4002 is configured to add structural strength to the structure to reduce damage during handling or post-fabrication processing, for example. FIG. 41 illustrates a cross-section of a bridge 4002 in a C-shaped coil structure 4001 according to the embodiment shown in FIG. 40. Other embodiments of the bridge include structures formed in any free space between portions of the C-shaped coil structure. In some embodiments, the bridge can be an extension formed on at least one side of the C-shaped coil structure, connected by a joint, and then bent at the joint to cross the opening of the C-shaped coil structure and attached to the other side of the C-shaped coil structure to form the bridge. FIGS. 42-44 illustrate an embodiment of a C-shaped coil structure 4201 with a bridge 4202 formed as an extension on at least one side of the C-shaped coil. The thickness of the bridge can be less than the remainder of the part in some embodiments. For some embodiments, the bridge is configured to, for example, make one or more surfaces of the coil structure flush with the mounting surface of the coil structure. In other embodiments, the bridge is configured to be recessed or lower than one or more surfaces of the coil structure. In some embodiments, the bridge is attached to the coil structure using an adhesive.

FIG. 45 shows a C-shaped coil structure 4501 with a bridge 4502 according to one embodiment. The bridge 4502 is an adhesive placed in the gap between the coil portions 4504 to create a rigid structure. The adhesive can be any attachment material that can be applied and cured. In some embodiments, the portion of the adhesive placed on the coil is thinner than that placed in the gap. FIG. 46 shows a cross-section of the bridge 4502 in the C-shaped coil structure 4501 according to the embodiment shown in FIG. 45.

FIG. 47 illustrates a coil structure 4701 according to an embodiment formed from a plurality of individual coil sections 4702. For some embodiments, each section includes an assembly tab 4704 for mating with a corresponding section of the coil structure. In some embodiments, the assembly tabs 4704 are configured with solder paste or other adhesive for attachment to the corresponding section. Such a coil structure 4701 may further optimize the number of coil structures that can be manufactured at a given time, further reducing costs and enhancing other manufacturing efficiencies.

FIG. 48 illustrates a coil structure 4801 according to an embodiment, comprising a number of individual coil sections 4802 that are assembled into a coil. FIG. 49 illustrates an alternative shape for at least one section 4902 of the coil structure 4901 according to an embodiment. Thus, each section can be configured in any shape and configured to mate with other corresponding sections to form the coil structure.

FIG. 50 illustrates a surface mount coil for forming a coil structure according to an embodiment. For some embodiments, the surface mount coil 5002 is configured to be placed on a substrate 5104 including a stiffener 5106 before the surface mount coil is attached, for example as shown in FIG. 51. FIG. 52 illustrates a top view of a substrate 5202 with a surface mount coil 5204 attached according to an embodiment. For some embodiments, the substrate 5202 includes one or more traces 5206 and an optional stiffener 5106 on the substrate 5202. According to some embodiments, the substrate includes one or more trace jumpers 5208 for electrically coupling the surface mount coil 5204 to another one or more surface mount coils 5204. The trace jumpers 5208 may also be used to electrically couple the one or more surface mount coils 5204 to other components. Alternatively, the trace jumpers 5208 may be integrated into the surface mount coil 5204, for example as shown in FIG. 53. In this configuration, according to some embodiments, the integrated trace jumper 5302 does not add to the z-height or footprint of the final assembly, eliminating the need for jumpers to be added at a later stage. The stiffener as described herein can be copper or other materials such as solder mask or polyimide disposed on a substrate, according to some embodiments. The substrate, according to some embodiments, includes connector pads for electrically coupling the surface mount coil to other portions of the coil and/or other circuitry. The individual coils can generally be surface mount structures attached to a planar surface that can later be formed into a 3D shape, or to an already formed 3D shape (which may be curved). Additionally, in some embodiments, the surface mount structures can have rounded corners to conform to shapes, can be incorporated with or attached to other structures (NFC, RFID, transformers, etc.), and/or can be stacked.

The surface mount coil or coils can be attached to the substrate by connections including, but not limited to, ACF (structural and electrical connections), ultrasonic gold ball bonds, and solder (plating, hot bar reflow, etc.). Surface mount coils can also be formed separately from the substrate to form coil structures of any number of shapes and sizes. Furthermore, forming surface mount coils can allow more coils to be formed simultaneously, for example, using the techniques described herein, reducing coil costs and increasing manufacturing efficiency. Additionally, fabrication of surface mount coils allows for higher copper plating density, helping to reduce the cost of forming coil structures without adversely affecting coil performance.

54 shows a surface mount coil section 5402 according to one embodiment. As with other embodiments of surface mount coil sections described herein, such surface mount coil sections 5402 allow for direct attachment of high density coil(s) to a substrate such as a circuit board (e.g., FPC). For example, some coil sections may include internal electrical connector pads 5404 and/or external electrical connector pads 5406. FIG. 55 shows a circuit board 5501 configured to mount coil sections such as surface mount coils as described herein to form a coil structure according to an embodiment. Furthermore, assembly of the coil structure, e.g. mounting the surface mount coil to a substrate, can include using pick and place assembly processes as used in current manufacturing processes. Thus, manufacturing costs for incorporating the coil structure are reduced. Furthermore, surface mount coils to form a coil structure eliminate the need for an additional substrate (circuitry and support structures designed directly into the FPC).

Figure 56 shows multiple views of a coil structure 5601 according to an embodiment. Figure 57 shows multiple views of a coil structure 5701 comprising multiple surface mounted coils according to an embodiment.
58 illustrates a coil section according to an embodiment. Coil section 5801 includes coils 5802 that are substantially trapezoidal in shape and formed using techniques including those described herein. One or more coil sections 5801 having coils 5802 formed in a substantially trapezoidal shape can be used in coil configurations such as those described herein. Such coil sections 5801 having coils 5802 formed in a substantially trapezoidal shape can be used with one or more other coil sections having coils formed in other shapes. Additionally, other embodiments of coil sections include having coils formed in shapes other than substantially trapezoidal.

FIG. 59 illustrates a coil structure according to an embodiment comprising solder joints for attaching one or more surface mounted coils. The coil structure 5901 comprises one or more surface mounted coils 5902. The one or more surface mounted coils 5902 are formed using techniques including those described herein. The coil structure 5901 comprises solder joints 5904 for mechanically and electrically coupling the one or more surface mounted coils 5902 to one or more traces 5906 and/or one or more trace jumpers 5908, such as those described herein. For some embodiments, the surface mounted coils 5902 are affixed to the coil structure prior to soldering the surface mounted coils 5902 to the solder joints 5904. According to some embodiments, the surface mounted coils 5902 are affixed to the coil structure using an adhesive. For some embodiments, a spacer is disposed between the surface mounted coils 5902 and the coil structure 5901. In some embodiments, the spacer is configured to have a height to position the surface mounted coil 5902 at a desired distance from another component.

60 is a top view of a structure with solder joints for mechanically and electrically coupling a surface mounted circuit to the structure, according to one embodiment. The structure 6001 includes a surface mounted circuit 6002. The surface mounted circuit 6002 can be any circuit and is not limited to a surface mounted coil as described herein. The surface mounted circuit 6002 is mechanically and electrically coupled to the structure using solder joints as described herein. According to some embodiments, the surface mounted circuit 6002 is affixed to the structure 6001 using an adhesive prior to soldering the surface mounted circuit 6002 to the solder joints of the structure using techniques including those described herein.

61 shows a bottom view of a structure with solder joints for mechanically and electrically coupling a surface mounted circuit to the structure of FIG. 60. In some embodiments, the solder joints are formed to access a surface of the structure 6001, e.g., a bottom surface as opposed to a top surface as the surface on which the surface mounted circuit is placed. Once the surface mounted circuit is placed on the structure using techniques including those described herein, solder is placed at the solder joints 6004. Solder may be placed at the solder joints 6004 using techniques including, but not limited to, solder jet application, solder paste, and manual application. For other embodiments, the surface mounted circuit with the surface mounted coil is bonded to the solder joints using conductive adhesive or resistance welding.

FIG. 62 illustrates a structure including a solder joint according to one embodiment. The first solder joint 6204a includes a substrate solder pad 6206a and a surface mounted circuit solder pad 6208a. The substrate solder pad 6206a is formed by forming a void 6214 in a substrate 6212 of the structure to expose a portion of the conductive layer 6210. For some embodiments, the void 6214 can be formed in the substrate (6210) using etching techniques, including those known in the art. For other embodiments, drilling or laser ablation is used to form the void 6214 in the substrate (6210) to expose a portion of the conductive layer 6210. The conductive layer 6210 is disposed on the substrate using techniques, including those described herein. The portion of the conductive layer 6210 exposed by the formation of the void 6214 is the substrate solder pad 6206. For some embodiments, the solder joint 6204 includes a datum 6210. In some embodiments, the datum is a via, void, conductive layer, fiducial, or other reference point used for alignment. The datum is used to align the surface mount solder pad to the substrate solder pad. For example, optical inspection techniques as known in the art can be used to detect the datum 6210 in the void 6214 to ensure that the surface mount circuit is properly aligned prior to applying solder to the solder joint 6204.

FIG. 63 illustrates a solder joint according to an embodiment. The solder joint 6304 comprises a substrate solder pad 6306, as described herein, exposed through a gap 6314 in a substrate 6312. The gap 6314 is formed using techniques including those described herein. The solder joint 6304 also comprises a circuit solder pad 6308. The circuit solder pad 6308 comprises a solder pad such as those described herein. The circuit solder pad 6308 can be formed on any substrate, including but not limited to a substrate of a surface mount coil, a substrate of a surface mount circuit, or a substrate of another component.

64 is a cross-sectional view of a solder joint according to one embodiment. The solder joint 6404 comprises a substrate solder pad 6406, such as those described herein, exposed through a void 6414 in a substrate 6412. The void 6414 is formed using techniques including those described herein. The solder joint 6404 also comprises a circuit solder pad 6408. The circuit solder pad 6408 comprises a solder pad as described herein. The circuit solder pad 6408 can be formed on any substrate, including but not limited to a substrate of a surface mount coil, a substrate of a surface mount circuit 6420, or a substrate of any type of component. According to some embodiments, solder 6416 is disposed within the void 6414 to mechanically and electrically couple the substrate solder pad 6406 and the circuit solder pad 6408. The solder 6416 is disposed in the void using techniques including those described herein. In other embodiments, an adhesive, such as a conductive adhesive, is disposed in the gap 6414.

The solder joints according to the embodiments described herein can reduce or eliminate shorted electrical connections by providing solder or conductive adhesive in the area of the void. The solder joints can also be used to attach components such as surface mount circuits or coils to a substrate before adding solder to the solder joints because the voids of the solder joints are formed on the opposing surface to which the components such as surface mount circuits or coils are attached. The distance between the substrate and the components such as surface mount circuits or coils can also be minimized, improving flatness and eliminating voids such as between a surface mount coil and a substrate. The improved flatness of the surface mount circuits, coils, or other components disposed on the substrate allows for the use of components having a large thickness (i.e., height from the substrate). According to some embodiments, the flatness of the surface mount circuits, coils, or other components is 100 μm or less.

Additionally, the void allows for visual inspection of the solder joint after solder has been applied to it, which aids in verifying electrical connectivity. Access to the solder joint allowed by the void also allows for rework of the solder joint after it has been manufactured, such as reapplication of solder or adhesive. Additionally, the solder joint can be configured to fit industry standard soldering processes by resizing for changes in required solder volume or gap height. The solder joint also allows for stronger board traces that improve yields in the manufacturing process.

65 is a flow diagram of a manufacturing process using solder joints according to an embodiment. The process includes applying (6502) an adhesive onto a substrate as described herein. The adhesive is placed on the substrate to attach a surface mount component, such as a surface mount coil, a surface mount circuit, or other component, to the substrate. The surface mount component is placed on the adhesive (6504), for example, using pick-and-place techniques known in the art. The adhesive is cured (6506), using techniques including those known in the art, to attach one or more surface mount components to the substrate. Solder is placed in the voids of the solder joints according to an embodiment described herein, using techniques including those described herein. Alternatively, a conductive adhesive is placed in the voids of the solder joints according to an embodiment described herein, using techniques including those known in the art. Optionally, the manufacturing process includes testing (6510) the surface mount components. Such testing may include, but is not limited to, visual inspection of solder joints, electrical verification of surface mount components and circuits created by the addition of surface mount components, and other manufacturing tests.

66 illustrates a coil structure according to one embodiment. The coil structure is formed using techniques including those described herein. The coil structure 6601 includes a surface mounted coil 6602. The surface mounted coil 6602 is affixed to the coil structure 6601 using techniques including those described herein. The surface mounted coil 6602 is disposed in a center portion 6610 of the coil structure 6601. The center portion 6610 is attached to an outer portion 6606 by one or more connections 6608. In some embodiments, one or more traces are disposed on a substrate including the center portion 6610, the outer portion 6606, and at least one connection 6608 to electrically couple the surface mounted coil 6602 to one or more terminal pads 6604 formed on the outer portion 6606.

67 illustrates a coil structure according to an embodiment. The coil structure 6701 is formed using techniques including those described herein. The coil structure 6701 includes an in-plane portion and an out-of-plane portion. The in-plane portions 6702 are arranged such that the in-plane portions 6702 are substantially coplanar. The in-plane and out-of-plane portions are each configured to have a surface mounted component, such as a surface mounted coil, disposed thereon. The out-of-plane portion 6704 is substantially in a different plane than the in-plane portions 6702. This configuration allows for a coil structure in a non-planar configuration, where one or more portions of a substrate are not substantially coplanar with other portions of the substrate. This allows for space and design requirements to be met while still allowing the use of the coil structure. Some embodiments include multiple non-planar portions.

All of the coil structures, surface mounted coils, surface mounted circuits, and coil sections described herein can be manufactured using techniques including those described herein.
According to some embodiments, the processes described herein are used to form any one or more of the mechanical and electromechanical structures.

Although described with reference to these embodiments, workers skilled in the art will recognize that changes can be made in form and detail without departing from the spirit and scope of the invention.
<Item 1>
a metal substrate having opposed first and second surfaces and including a plurality of solder joints, each of the solder joints having a void formed in the first surface of the metal substrate, the metal substrate having a substrate solder pad exposed in each of the voids, the plurality of solder joints including at least a first solder joint and a second solder joint; and
a plurality of surface mount circuits disposed on the second side of the metal substrate, the plurality of surface mount circuits having circuit solder pads exposed in each of the voids, the first solder joint and the second solder joint configured to provide electrical contact to at least one surface mount circuit of the plurality of surface mount circuits;
A coil structure comprising:
each of the plurality of surface mount circuits is disposed on a separate portion of the metal substrate and is electrically coupled to one another via the plurality of solder joints, each of the solder joints comprising solder disposed from the first side of the metal substrate into the gap to mechanically and electrically couple the substrate solder pad to the circuit solder pad;
Coil structure.
<Item 2>
At least one of the plurality of surface mount circuits is a surface mount coil.
2. The coil structure according to item 1.
<Item 3>
the metal substrate having a central portion coupled to an outer portion by one or more connections;
At least one of the plurality of surface mounted circuits is disposed in the central portion.
2. The coil structure according to item 1.
<Item 4>
one or more terminal pads disposed on said outer portion;
the one or more terminal pads are coupled to at least one of the centrally located surface mount circuits by one or more traces having a portion disposed on at least one of the one or more connections;
4. The coil structure according to item 3.
<Item 5>
the metal substrate having at least one outer surface such that the metal substrate is non-planar;
2. The coil structure according to item 1.
<Item 6>
At least one of the plurality of surface mount circuits is disposed outside the surface.
6. The coil structure according to item 5.

Claims (8)

A substrate;
a coil structure including a plurality of coil sections disposed on the substrate , the plurality of coil sections including a first coil section, a second coil section, and a third coil section, a first end of the first coil section being connected to a first end of the second coil section and a first end of the third coil section being connected to a second end of the second coil section, the second coil section being disposed perpendicular to the first coil section and the third coil section to form a C -shaped coil structure, and a bridge being disposed in a free space formed between the second end of the first coil section and the second end of the third coil section of the C- shaped coil structure ;
An apparatus comprising:
Each of the coil portions includes a metallic crown portion formed over at least a portion of the trace;
the metal crown is formed on a top surface and a sidewall of the portion of the trace;
the metal crown portion has a final height-to-width aspect ratio greater than an initial height-to-width aspect ratio of the trace.
Device. The coil portion is a surface mount coil.
2. The apparatus of claim 1. the coil portion being electrically coupled to traces on the substrate via solder joints;
3. The apparatus of claim 2. The substrate is a circuit board.
2. The apparatus of claim 1. The bridge is formed of an adhesive.
2. The apparatus of claim 1. At least one of the one or more coil sections includes a trace jumper integral to the coil section.
2. The apparatus of claim 1. The substrate is formed from multiple parts.
2. The apparatus of claim 1. At least one of the portions includes an assembly tab.
8. The apparatus of claim 7.

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