JP7571255B2 - Semiconductor Device - Google Patents

Description

One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention is
Process, machine, manufacture, or composition of matter
Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically relates to a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device,
Examples include a storage device, a processor, an electronic device, a driving method thereof, a manufacturing method thereof, an inspection method thereof, or a system having at least one of them.

In recent years, electronic components such as central processing units (CPUs), graphics processing units, storage devices, and sensors are used in a variety of electronic devices, including personal computers, smartphones, and digital cameras. These electronic components are being improved in various aspects, such as miniaturization and low power consumption.

In particular, in recent years, the amount of data handled by the above-mentioned electronic devices has been increasing, and there is a demand for memory devices with large storage capacity. Patent Documents 1 and 2 disclose semiconductor devices that enable writing and reading of multi-value data. In addition, in order to realize a memory device with a large storage capacity, there is a demand for technology to miniaturize the circuits of the memory device.

JP 2012-256400 A JP 2014-199707 A

An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a memory device including the novel semiconductor device.An object of one embodiment of the present invention is to provide an electronic device using a memory device including the novel semiconductor device.An object of one embodiment of the present invention is to provide a memory device having a large data capacity.An object of one embodiment of the present invention is to provide a highly reliable memory device.

The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems.

(1)
One embodiment of the present invention is a semiconductor device including first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor. The first conductor is provided on a top surface of the first insulator.
The insulator is on a top surface of the first conductor, the second conductor is on a first top surface of the second insulator, and the second
The conductor is provided on a first lower surface of the third insulator, and the fourth insulator is provided on a side surface of the first insulator, a side surface of the first conductor, a side surface of the second insulator, a second upper surface of the second insulator, a side surface of the second conductor, and the third
the first semiconductor is connected to a region including a second lower surface of the insulator and a side surface of the third insulator, the first semiconductor is connected to a surface on which the fourth insulator is formed, the third conductor is in a region of the region on which the first semiconductor is formed that overlaps with a side surface of the second conductor, the fifth insulator is in the surface on which the third conductor is formed, and in a region of the region on which the first semiconductor is formed that overlaps with a side surface of the first insulator, a region that overlaps with a side surface of the second conductor, a region that overlaps with a side surface of the second insulator, and a region that overlaps with a side surface of the third insulator, and the second semiconductor is on the surface on which the fifth insulator is formed.

(2)
Another embodiment of the present invention is a semiconductor device including first to fifth insulators, first to third conductors, and first to third semiconductors, in which the first conductor is provided on a first top surface of the first insulator,
The first conductor is on a first lower surface of the second insulator, the second conductor is on a first upper surface of the second insulator, the second conductor is on a first lower surface of the third insulator, the third semiconductor is in a region including a second upper surface of the first insulator, a side surface of the first conductor, and a second lower surface of the second insulator, and the fourth insulator is in a region including a side surface of the first insulator, a formation surface of the first semiconductor, a side surface of the second insulator, and a second lower surface of the second insulator.
the first semiconductor is connected to a region including the upper surface, the side surface of the second conductor, the second lower surface of the third insulator, and the side surface of the third insulator; the first semiconductor is connected to a surface on which the fourth insulator is formed;
The conductor is provided in a region where the first semiconductor is formed and overlaps a side surface of the second conductor, and the fifth insulator is provided between the formation surface of the third conductor and the region where the first semiconductor is formed.
The semiconductor device has a region overlapping with a side surface of a first insulator, a region overlapping with a formation surface of a third semiconductor, a region overlapping with a side surface of a second insulator, and a region overlapping with the third insulator, and the second semiconductor is located on the formation surface of a fifth insulator.

(3)
Alternatively, one embodiment of the present invention is a semiconductor device including first to fourth insulators, first to fourth conductors, a first semiconductor, and a second semiconductor, in which the first insulator is provided on a first top surface of the first conductor, the second conductor is provided on a first top surface of the first insulator, the second insulator is provided on a first bottom surface of a third conductor, and the second conductor is provided on a first bottom surface of the second insulator, and the third insulator is provided on a side surface of the first conductor, a second top surface of the first conductor, a side surface of the first insulator, a second top surface of the first insulator, a side surface of the second conductor, a second bottom surface of the second insulator, a side surface of the second insulator, and a second bottom surface of the third conductor. , and a side of the third conductor, the first semiconductor is continuous on the formation surface of the fourth insulator, the fourth conductor is in a region where the first semiconductor is formed that overlaps with a side of the first insulator, a region where it overlaps with a side of the second conductor, and a region where it overlaps with a side of the second insulator, the fourth insulator is in the formation surface of the fourth conductor and in a region where the first semiconductor is formed that overlaps with the first conductor and a region where it overlaps with the third conductor, and the second semiconductor is on the formation surface of the fourth insulator.

(4)
Alternatively, one aspect of the present invention is a semiconductor device characterized in that, in the above (1) to (3), it has a sixth insulator and a fifth conductor, the sixth insulator is provided on the formation surface of the second semiconductor, and the fourth conductor is provided on the formation surface of the sixth insulator.

(5)
Another aspect of the present invention is the semiconductor device according to any one of (1) to (4) above, wherein the first semiconductor includes a metal oxide.

(6)
Another aspect of the present invention is the semiconductor device according to any one of (1) to (5) above, wherein the second semiconductor has a metal oxide.

(7)
Alternatively, one aspect of the present invention is the semiconductor device according to any one of (1) to (5) above, characterized in that the second semiconductor has silicon.

(8)
Another embodiment of the present invention is a memory device including the semiconductor device described in any one of (1) to (7) and a peripheral circuit.

(9)
Another embodiment of the present invention is an electronic device including the storage device according to (8) above and a housing.

According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a storage device including the novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device using a storage device including the novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a storage device with a large data capacity can be provided. Alternatively, according to one embodiment of the present invention, a storage device with high reliability can be provided.

The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. 11 is a flowchart showing an example of the operation of the semiconductor device. 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. 1 is a cross-sectional view illustrating a semiconductor device. 1 is a cross-sectional view illustrating a semiconductor device. 1 is a cross-sectional view illustrating a semiconductor device. FIG. 1 is a block diagram illustrating an example of a storage device. FIG. 4 is a diagram for explaining the range of the atomic ratio of metal oxides. FIG. 2 is a block diagram illustrating a CPU. FIG. 1 is a perspective view showing an example of an electronic device. FIG. 1 is a perspective view showing an example of an electronic device.

In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides include oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as "oxide semiconductors" or simply "OS").
For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be called an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide is called a metal oxide semiconductor.
In addition, an OS FET can be referred to as a transistor including a metal oxide or an oxide semiconductor.

In this specification and the like, a transistor having silicon in a channel formation region is referred to as a Si
It may also be referred to as a transistor.

In the present specification and the like, the term "metal oxide" also refers to a metal oxide having nitrogen.
Metal oxides containing nitrogen are sometimes collectively referred to as metal oxynitrides (me
It may also be called tal oxygenide.

(Embodiment 1)
In this embodiment, a circuit configuration, an operation method, and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. Note that in the following description, for example, "[x, y]" means an element in the xth column and the yth column, and "[z]" means an element in the zth row or the zth column.
When there is no need to specify rows or columns, these notations are omitted.

<Circuit configuration example>
First, a circuit configuration of a semiconductor device will be described with reference to FIG.
) shows a circuit diagram of n memory cells (n is an integer of 1 or more). That is, memory cells MC[1] to MC[n], wirings WWL[1] to WWL[n], wirings RWL[1] to RWL[n] for controlling the memory cells MC[1] to MC[n], and wirings RWL[1] to RWL[n] for controlling the memory cells MC[1] to MC[n] are shown.
], a wiring WBL, and a wiring RBL. Note that the wiring WWL functions as a write word line, the wiring RWL functions as a read word line, the wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

Each memory cell MC includes a transistor WTr, a transistor RTr, and a capacitance element C
S. The transistor RTr illustrated in FIG. 1A is a transistor having a back gate, and the threshold voltage of the transistor RTr can be changed by applying a potential to the back gate. Note that the wiring BGL illustrated in FIG. 1A is electrically connected to the back gates of the transistors RTr included in the memory cells MC[1] to MC[n]. The semiconductor device illustrated in FIG. 1 may have a configuration in which the wiring BGL is not electrically connected to each of the back gates of the transistors RTr included in the memory cells MC[1] to MC[n], but is electrically connected independently to the back gates and supplies different potentials to each of the back gates.

The channel formation region of the transistor WTr preferably includes the metal oxide described in embodiment 3. In particular, in the case of a metal oxide selected from one or more of indium, an element M (the element M is, for example, aluminum, gallium, yttrium, tin, or the like), and zinc, the metal oxide functions as a wide-gap semiconductor, and therefore a transistor including the metal oxide in its channel formation region has a characteristic of having a very low off-state current. By applying a transistor having this characteristic as the transistor WTr that retains data, data can be retained in the memory cell MC for a long time. This reduces the number of times that the retained data is refreshed, thereby reducing the power consumption of the semiconductor device.

In addition, it is preferable to use a material that increases the field effect mobility of the transistor for the channel formation region of the transistor RTr.
The semiconductor device can operate faster. For example, the material contained in the channel formation region of the transistor RTr can include a semiconductor material such as metal oxide or silicon, which will be described in the third embodiment.

The transistor WTr functions as a write transistor, and the transistor RTr functions as a read transistor. The transistor WTr is switched between an on state and an off state by a potential applied to the wiring WWL. The potential of one electrode of the capacitance element CS is controlled by the wiring RWL. The other electrode of the capacitance element CS is electrically connected to the gate of the transistor RTr. The other electrode of the capacitance element CS can be referred to as a memory node. The memory node of each memory cell MC is electrically connected to a first terminal of the transistor WTr of the memory cell MC.

In addition, in terms of the circuit configuration, the second terminal of the transistor WTr is electrically connected in series with the first terminal of the transistor WTr of the adjacent memory cell MC. Similarly, the first terminal of the transistor RTr is electrically connected in series with the second terminal of the transistor RTr of the adjacent memory cell.
The second transistor WTr of the memory cell MC[n] is electrically connected to the
The terminal is electrically connected to the wiring WBL, and the transistor R
The second terminal of the transistor RTr in the memory cell MC[n] is electrically connected to the wiring RBL. In this embodiment, the connection point between the second terminal of the transistor RTr in the memory cell MC[n] and the wiring RBL is called a node N1, and the first terminal of the transistor RTr in the memory cell MC[1] is called a node N2. In order to control the conduction state between the node N1 and the wiring RBL,
A selection transistor may be connected in series with the transistor RTr.
2 and a node N2.
A selection transistor may be connected in series with Tr.

Note that one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. 1A. One embodiment of the present invention may have a circuit configuration in which the semiconductor device illustrated in FIG. 1A is appropriately modified depending on the situation or as needed. For example, one embodiment of the present invention may be a semiconductor device in which a backgate is provided in the transistor WTr as well, if necessary, as illustrated in FIG. 1B. Note that the semiconductor device illustrated in FIG. 1B has a structure in which, in addition to the structure of the semiconductor device illustrated in FIG. 1A, backgates are provided in the transistors WTr included in the memory cells MC[1] to MC[n], and the backgates are electrically connected to the wiring BGL. For example, one embodiment of the present invention may be a semiconductor device in which the transistors RTr and WTr do not have backgates, as illustrated in FIG. 1C.

In order to further increase the storage capacity of the semiconductor device shown in Figures 1A, 1B, and 1C, the semiconductor devices shown in Figures 1A, 1B, and 1C may be arranged in a matrix. For example, when the semiconductor devices shown in Figure 1B are arranged in a matrix, the circuit configuration becomes the configuration shown in Figure 2.

The semiconductor device shown in FIG. 2 is configured by arranging m columns (m is an integer equal to or greater than 1) of the semiconductor device shown in FIG. 2B as one column, and electrically connecting the wiring RWL and the wiring WWL to the memory cells MC in the same row. In other words, the semiconductor device shown in FIG. 2 is a matrix-shaped semiconductor device with n rows and m columns, and has memory cells MC[1,1] to MC[n,m]. Therefore, the semiconductor device shown in FIG. 2 has the wiring RWL and the wiring WWL.
Wirings RWL[1] to RWL[n], wirings WWL[1] to WWL[n], and wiring RBL
[1] to wiring RBL[m], wiring WBL[1] to WBL[m], and wiring BGL[1
Specifically, the memory cells MC[j,i] (j is an integer from 1 to n, and i is an integer from 1 to m) are electrically connected to the wirings BGL[m].
One electrode of the capacitance element CS is electrically connected to the wiring RWL[j], and the memory cell MC
The gate of the transistor WTr of the memory cell MC[n, i] is electrically connected to the wiring WWL[j]. The wiring WBL[i] is electrically connected to the second terminal of the transistor WTr of the memory cell MC[n, i], and the wiring RBL[i] is electrically connected to the second terminal of the transistor RT of the memory cell MC[n, i].
r and the second terminal of the first terminal of the second transistor.

FIG. 2 shows memory cell MC[1,1], memory cell MC[1,i], memory cell M
C[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC
[j, m], memory cell MC[n, 1], memory cell MC[n, i], memory cell MC[
n, m], wiring RWL[1], wiring RWL[j], wiring RWL[n], wiring WWL[1]
, wiring WWL[j], wiring WWL[n], wiring RBL[1], wiring RBL[i], wiring R
BL[m], wiring WBL[1], wiring WBL[i], wiring WBL[m], wiring BGL[1]
], the wiring BGL[i], the wiring BGL[m], the capacitor CS, the transistor WTr, the transistor RTr, the node N1, and the node N2 are illustrated, and other wirings, elements, symbols, and characters are omitted.

In addition, the semiconductor device shown in FIG. 2C is regarded as one row, and m rows (m is an integer of 1 or more) are arranged.
The arrangement is shown in FIG. 3. Note that the semiconductor device shown in FIG. 3 is configured such that no back gate is provided for each transistor of each memory cell MC.
Therefore, the semiconductor device shown in Fig. 3 does not have the wiring BGL. Note that the description of the semiconductor device shown in Fig. 2 should be referred to for the semiconductor device shown in Fig. 3.

<Example of operation method>
Next, an example of a method for operating the semiconductor device shown in FIG. 1A to FIG. 1C will be described. Note that the low-level potential and the high-level potential used in the following description do not mean specific potentials, and the specific potentials may be different depending on the wiring. For example,
The low level potential and the high level potential applied to the wiring L may be different from the low level potential and the high level potential applied to the wiring RWL.

In this example of the operation method, a potential within a range in which the transistors RTr and WTr operate normally is applied in advance to the wirings BGL shown in FIGS. 1A and 1B and BGW[1] to BGW[n] shown in FIG. 1B.
The operations of the semiconductor devices shown in A) to C) can be considered to be similar to each other.

4A is a timing chart showing an example of an operation of writing data to a semiconductor device, and FIG. 4B is a timing chart showing an example of an operation of reading data from the semiconductor device. The timing charts in FIG. 4A and FIG. 4B show an example of an operation of reading data from the semiconductor device.
[n], the potentials of the nodes N1 and N2 are changed.
BL indicates data supplied to the wiring WBL.

FIG. 4A shows data D[1] to data D[n] stored in memory cell MC[1].
The data D[1] to D[n] can be binary or multi-valued.
[n] is supplied from the wiring WBL. That is, in the circuit configuration of the semiconductor device illustrated in FIGS. 1A to 1C, data is written to the memory cells MC[1] to MC[n] in sequence.

Conversely, if an attempt is made to write data to memory cell MC[1] after writing data to memory cell MC[2], the data stored in memory cell MC[2] will be lost at the stage of writing data to memory cell MC[1] unless the data written in memory cell MC[2] is first read and saved in another location.

In the circuit configuration of the semiconductor device shown in FIG.
When data is written to the memory cells MC[1] to MC[i-1], the wiring WWL is used to prevent the data stored in the memory cells MC[1] to MC[i-1] from being overwritten.
A low-level potential is supplied to the wirings WWL[1] to WWL[i-1] to turn off the transistors WTr included in the memory cells MC[1] to MC[i-1], thereby protecting the data held in the memory cells MC[1] to MC[i-1].

When data is written to the memory cell MC[i], the data is supplied from the wiring WBL, so that a high-level potential is supplied to the wirings WWL[i] to WWL[n] to turn on the transistors WTr included in the memory cells MC[i] to MC[n] sufficiently, thereby allowing the data to be held in the memory node of the memory cell MC[i].

1A to 1C, the wiring RBL does not need to be set to a specific potential because it can be controlled independently, but can be set to, for example, a low-level potential. The potential of the wiring RWL, that is, the node N1, can be set to a low-level potential. In addition, the potential of the node N2 can also be set to a low-level potential.

In consideration of the above, an operation example shown in the timing chart of Fig. 4A will be described. At time T10, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL, the node N1, and the node N2 are all low-level potentials.

At time T11, a high-level potential is supplied to the wirings WWL[1] to WWL[n]. This causes the transistors WTr in the memory cells MC[1] to MC[n] to be fully turned on.
Since the transistors WTr of the memory cells MC[1] to MC[n] are each fully on, the data D[1] reaches the memory node of the memory cell MC[1] and is written thereto.

At time T12, a low-level potential is supplied to the wiring WWL[1],
A high-level potential is continuously supplied to the wirings WWL[2] to WWL[n]. As a result, the transistor WTr in the memory cell MC[1] is turned off, and the transistor WTr in the memory cell MC[2] is turned off.
Each of the transistors WTr in the memory cells MC[2] to MC[n] is fully on. Then, data D[2] is supplied to the wiring WBL. Since each of the transistors WTr in the memory cells MC[2] to MC[n] is fully on, the data D[2] reaches the memory node of the memory cell MC[2] and is written therein. Also, since the transistor WTr in the memory cell MC[1] is off, the data D[1] held in the memory cell MC[1] is not lost by the write operation from time T12 to time T13.

Between time T13 and time T14, similar to the write operation of data D[1] to memory cell MC[1] between time T11 and time T12, and the write operation of data D[2] to memory cell MC[2] between time T12 and time T13,
Data D[3] to data D[n-1] are sequentially written to the memory cells MC[3] to MC[n-1], respectively. Specifically, the transistors WTr included in the memory cells MC[1] to MC[j-1] (j is an integer between 3 and n-1) to which data has already been written are turned off, and the memory cells MC[1] to MC[j-1] to which data has not been written are turned off.
The transistors WTr in the memory cells MC[j] to MC[n] are turned on sufficiently, and data D[j] is supplied from the wiring WBL to be written to the memory node of the memory cell MC[j]. When writing of data D[j] to the memory cell MC[j] is completed, the transistors WTr in the memory cell MC[j] are turned off, and data D[j+1] is supplied from the wiring WBL to be written to the memory node of the memory cell MC[j+1]. Note that the write operation when j is n-1 is performed at time T14 described below.
This refers to the operation from time T11 to time T15.

At time T14, a low-level potential is supplied to the wirings WWL[1] to WWL[n-1], and a high-level potential is still supplied to the wiring WWL[n]. This causes the transistors WTr in the memory cells MC[1] to MC[n-1] to be turned off, and each of the transistors WTr in the memory cell MC[n] to be fully turned on. Then, data D[n] is supplied to the wiring WBL. The memory cell MC
Since each of the transistors WTr in the memory cells MC[n] is fully on, the data D[n] reaches the memory node of the memory cell MC[n] and is written therein. Also, since the transistors WTr in the memory cells MC[1] to MC[n-1] are off, the data D[1] to D[n-1] stored in the memory cells MC[1] to MC[n-1] are written therein from time T14 to time T15.
will not be lost by any write operations up to

By the above-described operation, in any one of the semiconductor devices shown in FIGS.
Data can be written to the memory cells MC of the semiconductor device.

FIG. 4B shows data D[1] to data D[n] stored in memory cell MC[1].
1 shows an example of reading data from the memory cells MC[1] to MC[n]. Note that at this time, in order to maintain the data held in each memory cell MC, the transistor WTr is required to be in an off state. Therefore, during the operation of reading data from the memory cells MC[1] to MC[n], the potentials of the wirings WWL[1] to WWL[n] are set to low level potentials.

1, when reading data from a specific memory cell MC, the transistors RTr of the other memory cells MC are turned on sufficiently, and then the transistor RTr of the specific memory cell MC is operated in a saturated region. In other words, the current flowing between the source and drain of the transistor RTr of the specific memory cell MC is determined according to the source-drain voltage and the data stored in the specific memory cell MC.

For example, consider a case where data stored in a memory cell MC[k] (k is an integer between 1 and n) is to be read. In this case, the memory cells M excluding the memory cell MC[k] are
In order to turn on each of the transistors RTr included in the memory cells MC[1] to MC[n] sufficiently, a high-level potential is supplied to the wirings RWL[1] to RWL[n] except for the wiring RWL[k].

On the other hand, in order to turn on the transistor RTr included in the memory cell MC[k] according to the stored data, the wiring RWL[k] needs to have the same potential as the wiring RWL[k] when the data is written to the memory cell MC[k]. Note that the potential of the wiring RWL[k] during a write operation and a read operation is considered to be a low-level potential here.

For example, a potential of +3 V is applied to the node N1, and a potential of 0 V is applied to the node N2.
is floated, and the potential of the node N2 is measured thereafter. When the potentials of the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] are set to a high level potential, the transistors RTr included in the memory cells MC[1] to MC[n] excluding the memory cell MC[k] are fully turned on. On the other hand, the voltage between the first terminal and the second terminal of the transistor RTr included in the memory cell MC[k] is determined by the potential of the gate of the transistor RTr and the potential of the node N1, so that the potential of the node N2 is determined according to the data held in the memory node of the memory cell MC[k].

In this manner, the data held in the memory cell MC[k] can be read.

Based on the above, an operation example shown in the timing chart of Fig. 4B will be described. At time T20, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL, the node N1, and the node N2 are low-level potentials. In particular, the node N2 is in a floating state. Data D[1] to D[n] are stored in the memory nodes of the memory cells MC[1] to MC[n], respectively.

At time T21, a low-level potential is supplied to the wiring RWL[1], and
A high-level potential is supplied to the wirings WWL[2] to WWL[n].
The transistors RTr of the memory cells MC[1] to MC[n] are fully turned on.
In response to data D[1] stored in the memory node N1, a potential V _R is supplied to the wiring RBL. As a result, the potential of the node N1 becomes V _R , and the potential of the node N
The potential of node N2 is determined according to the potential _VR of node N1 and the data stored in the memory node of memory cell MC[1]. Here, the potential of node N2 is determined according to VD _[1
] . Then, the potential _VD[1] of the node N2 is measured to determine whether the memory cell M
The data D[1] stored in the memory node of C[1] can be read.

At time T22, a low-level potential is supplied to the wirings RWL[1] to WWL[n]. A low-level potential is supplied to the node N2, and then the node N2 is in a floating state. That is, between time T22 and time T23, the wirings RWL[1] to WWL[n] are supplied with a low-level potential.
The potentials of the wirings WWL[1] to WWL[n] and the node N2 are changed from time T20 to time T
The situation is the same as that between time T21 and time T22. Note that the potential _V2R may continue to be supplied to the wiring RBL, or a low-level potential may be supplied to the wiring RBL.
After 21, the potential V _R continues to be supplied.

At time T23, a low-level potential is supplied to the wiring RWL[2],
A high-level potential is supplied to the memory cell MC[1], the wirings RWL[3] to WWL[n]. As a result, the transistors RTr included in the memory cell MC[1], the memory cell MC[3] to the memory cell MC[n] are fully turned on.
The transistor RTr is turned on in response to the data D[2] stored in the memory node of the memory cell MC[2]. The potential V _R is still supplied to the wiring RBL. As a result, the potential of the node N2 is determined in response to the potential V _R of the node N1 and the data stored in the memory node of the memory cell MC[2]. Here, the potential of the node N2 is set to V _D[2] . By measuring the potential V _D[2] of the node N2, the data D[2] stored in the memory node of the memory cell MC[2] can be read.

Between time T24 and time T25, data D[1] is sequentially read from each of memory cells MC[3] to MC[n-1], similar to the read operation of data D[1] from memory cell MC[1] between time T20 and time T22, and the read operation of data D[2] from memory cell MC[2] between time T22 and time T24.
Specifically, when data D[j] is read from a memory cell MC[j] (j is an integer from 3 to n-1), the potential of the node N2 is set to a low-level potential and the node N2 is put into a floating state, and then the wiring RWL
A high-level potential is supplied to the wirings RWL[1] to RWL[n] excluding the memory cell MC[j] to turn on the transistors RTr included in the memory cells MC[1] to MC[n] excluding the memory cell MC[j], and the transistors RT
r is turned on in accordance with the data D[j]. Next, the potential of the node N1 is set to V _R , so that the potential of the node N2 becomes a potential corresponding to the data D[j], and the data D[j] can be read by measuring this potential. After the data D[j] stored in the memory cell MC[j] has been read, the wiring RWL is turned on in preparation for the next read operation.
A low-level potential is supplied to the wirings WWL[1] to WWL[n], and a low-level potential is supplied to the node N2, and then the node N2 is set in a floating state. Note that when j is n-1, this preparation refers to an operation from time T25 to time T26.

At time T25, a low-level potential is supplied to the wirings RWL[1] to WWL[n]. A low-level potential is supplied to the node N2, and then the node N2 is in a floating state. That is, between time T25 and time T26, the wirings RWL[1] to WWL[n] are supplied with a low-level potential.
The potentials of the wirings WWL[1] to WWL[n] and the node N2 are changed from time T20 to time T
The situation is the same as that between time T21 and time T22. Note that the potential _V2R may continue to be supplied to the wiring RBL, or a low-level potential may be supplied to the wiring RBL.
After 21, the potential V _R continues to be supplied.

At time T26, a low-level potential is supplied to the wiring RWL[n].
A high-level potential is supplied to the wirings WWL[n-1] to WWL[n-1]. This causes the transistors RTr in the memory cells MC[1] to MC[n-1] to be fully on. The transistor RTr in the memory cell MC[n] is turned on in accordance with the data D[n] stored in the memory node of the memory cell MC[n].
The potential V _R is still supplied to the wiring RBL. As a result, the potential of the node N2 is determined according to the potential V _R of the node N1 and the data stored in the memory node of the memory cell MC[n]. Here, the potential of the node N2 is set to V _D[n] . By measuring the potential V _D[n] of the node N2, the potential of the memory cell MC[n] is determined.
], data D[n] stored in the memory node can be read.

By the above-described operation, data can be read from each memory cell MC of the semiconductor device shown in FIGS.

<Structure example and manufacturing method example>
In order to facilitate understanding of the structure of the semiconductor device of this embodiment mode, a manufacturing method thereof will be described below.

5A and 5B are schematic diagrams showing the semiconductor device shown in Fig. 1A to 1C, in which Fig. 5A shows a top view of the semiconductor device, and Fig. 5B shows a cross-sectional view corresponding to the dashed line A1-A2 in Fig. 5A.

The semiconductor device has a structure in which wirings RWL, wirings WWL, and insulators (regions not hatched in FIG. 5 ) are stacked, an opening is provided in the structure, and a conductor PG is formed so as to fill the opening. A wiring ER is formed on the conductor PG, and the wiring ER is electrically connected to the wiring RWL or the wiring WWL.

In addition, an opening is formed in the structure so as to penetrate the wiring RWL and the wiring WWL together. Then, in order to provide a memory cell MC in a region AR through which the wiring RWL and the wiring WWL penetrate, an insulator, a conductor, and a semiconductor are formed in the opening. Note that the conductor functions as the wiring WBL and the wiring RBL, and the semiconductor functions as a channel formation region of the transistor WTr and the transistor RTr. In FIG. 5,
A region in which an insulator, a conductor, and a semiconductor are formed in the opening is illustrated as a region HL. Note that when a backgate is provided in a transistor included in the memory cell MC, the conductor included in the region HL may also function as a wiring BGL for electrically connecting to the backgate.

That is, in FIG. 5, the semiconductor device shown in any one of FIG. 1(A), (B), and (C) is
2 or 3 is configured in the region SD2. In FIG.

In the following manufacturing method example 1 and manufacturing method example 2, a method for forming a memory cell MC in the region AR will be described.

<<Production Method Example 1>>
6 to 10 are cross-sectional views for explaining a manufacturing example of the semiconductor device shown in FIG. 1A, and in particular, cross-sectional views of the transistors WTr and RTr in the channel length direction are shown. In addition, in the cross-sectional views of FIG. 6 to 10, some elements are omitted for clarity.

As shown in FIG. 6A, the semiconductor device in FIG. 1A includes an insulator 101A disposed above a substrate (not shown), a conductor 131A disposed on the insulator 101A, an insulator 101B disposed on the conductor 131A, and a conductor 132 disposed on the insulator 101B.
The laminate has a plurality of conductors and a plurality of insulators, an insulator 101A arranged on the conductor 132A, an insulator 101C arranged on the conductor 131B, an insulator 101D arranged on the conductor 131B, a conductor 132B arranged on the insulator 101D, and an insulator 101E arranged on the conductor 132B. Note that hereinafter, a laminate having these plurality of conductors and a plurality of insulators will be referred to as laminate 1.
It is written as 00.

The substrate may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates.
Examples of the semiconductor substrate include single semiconductor substrates of silicon, germanium, etc., and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, the semiconductor substrates having an insulating region inside the semiconductor substrate, such as SOI (Silicon On Insulator)
) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of conductive substrates include substrates having metal nitrides, and substrates having metal oxides. Examples of conductive substrates include substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates in which elements are provided on these substrates may be used. Examples of elements provided on the substrate include capacitance elements, resistance elements, switching elements, light-emitting elements, and memory elements.

A flexible substrate may be used as the substrate. A method of providing a transistor on a flexible substrate may include a method of manufacturing a transistor on a non-flexible substrate, peeling the transistor, and transferring the transistor to a flexible substrate. In this case, a peeling layer may be provided between the non-flexible substrate and the transistor. A sheet, film, or foil having woven fibers may be used as the substrate. The substrate may be stretchable.
The substrate may also have the property of returning to its original shape when bending or pulling is stopped.
Alternatively, the substrate may have a property of not returning to its original shape.
m or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less.
The substrate has a region with a thickness of 1 μm or less. By making the substrate thinner, the weight of a semiconductor device having a transistor can be reduced. Furthermore, by making the substrate thinner, even when glass or the like is used, the substrate may have elasticity, or may have the property of returning to its original shape when bending or pulling is stopped. Therefore, it is possible to reduce the impact applied to the semiconductor device on the substrate when it is dropped, etc. In other words, a robust semiconductor device can be provided.

As the flexible substrate, for example, metal, alloy, resin, glass, or fibers thereof can be used. The lower the linear expansion coefficient of the flexible substrate, the more preferable it is since deformation due to the environment is suppressed. As the flexible substrate, for example, a material having a linear expansion coefficient of 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵ /K or less may be used. As the resin, for example, polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. can be used. In particular, aramid has a low linear expansion coefficient and is therefore suitable as the flexible substrate.

In the manufacturing example described in this embodiment mode, since a heat treatment is included in the process, it is preferable to use a material having high heat resistance and a low thermal expansion coefficient as the substrate.

The conductor 131A (the conductor 131B) functions as the wiring WWL shown in FIG. 1A, and the conductor 132A (the conductor 132B) functions as the wiring RWL shown in FIG.

The conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B can be made of a material containing one or more metal elements selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

The conductors, particularly the conductors 131A and 131B, are made of a semiconductor 1
A conductive material containing oxygen and a metal element contained in a metal oxide applicable to the semiconductor 51, the semiconductor 152, the semiconductor 153a, and the semiconductor 153b may be used. A conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon has been added may be used. Indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen mixed in from a surrounding insulator or the like may be captured in some cases.

In addition, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen as the conductors, particularly the conductors 132A and 132B. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like, which may be formed as a single layer or a stacked layer.

In addition, a plurality of conductors formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. In addition, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. In addition, a stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen. In addition, by applying an insulator having an excess oxygen region as an insulator in contact with the periphery of the conductor, oxygen may diffuse in the region of the conductor in contact with the insulator. This makes it possible to form a stacked structure by combining a material containing a metal element and a conductive material containing oxygen. Similarly,
By using an insulator having an excess nitrogen region as an insulator in contact with the periphery of a conductor, nitrogen may diffuse into the region of the conductor in contact with the insulator, thereby forming a laminated structure that combines a material containing a metal element and a conductive material containing nitrogen.

Note that the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B may be made of the same material or different materials.
, and the materials applied to the conductor 132B can be appropriately selected and used.

The insulators 101A to 101E are preferably made of a material in which the concentrations of impurities such as water or hydrogen are reduced. For example, the amount of desorption of hydrogen from the insulators 101A to 101E can be measured by thermal desorption spectroscopy (TDS).
In the case of a method for observing the desorption amount of hydrogen molecules, the amount of hydrogen molecules desorbed per area of any one of the insulators 101A to 101E is 2×10 ¹⁵ molecules/cm 2 or less, preferably 1×10 ¹⁵ molecules/cm ² or less, in the range of 50° C. to 500° C.
The insulators 101A ^{to 101E} may be formed using an insulator that ^releases oxygen by heating.
The conductive material 31B, the conductor 132A, and the conductor 132B can have a layered structure that combines a material containing a metal element and a conductive material containing oxygen.

As the insulators 101A to 101E, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Also, for example, a material containing silicon oxide or silicon oxynitride can be used.

In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

In the next step, as shown in FIG. 6B, an opening 191 can be formed in the stacked body 100 shown in FIG. 6A by forming a resist mask and performing etching treatment or the like.

The resist mask can be formed by appropriately using a lithography method, a printing method, an inkjet method, etc. When the resist mask is formed by the inkjet method, a photomask is not used, so that the manufacturing cost can be reduced. In addition, the etching process may be a dry etching method or a wet etching method, or both may be used.

7A, the conductor 132A and the conductor 132B on the side surface of the opening 191 are removed by etching or the like to form a recess 192A (recess 192B) on the side surface. Here, the conductor 132A (conductor 132B) is made of a material (a material having a higher etching rate than the insulators 101A to 101E and the conductor 131A (conductor 131B)) that allows the conductor 132A (conductor 132B) to be selectively removed from the stack 100.

In addition, recess 192A (recess 192B) may be formed together with opening 191 in the manufacturing process of the semiconductor device shown in FIG. 6(B) by providing a sacrificial layer in the area where opening 191 and recess 192A (recess 192B) are to be formed during the manufacturing process of the semiconductor device shown in FIG. 6(A).
In addition, when the opening 191 is formed without providing a sacrificial layer, the recess 192A (recess 19
2B) may also be formed.

In the next step, as shown in FIG. 7B, an insulator 102 is formed on the side surface of the opening 191 shown in FIG. 7A and in the recessed portion described above.

It is preferable to use an insulating material having a function of suppressing oxygen permeation as the insulator 102. For example, it is preferable to use silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like as the insulator 102. By forming such an insulator 102, it is possible to prevent a decrease in the conductivity of the conductor 133, which would be caused by oxygen penetrating the insulator 102 and entering the conductor 133, which will be described later, and oxidizing the conductor 133.

In the next step, as shown in Fig. 8A, a conductor 133 is formed on the side surface of the opening 191 shown in Fig. 7B and on the formed recess. That is, the conductor 133 is formed on the formation surface of the insulator 102.

The above-mentioned materials that can be used for the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B can be used as the conductor 133. In particular, it is preferable to use a material with high conductivity for the conductor 133 among the above materials.

In the next step, as shown in FIG. 8B, the conductor 133 included in the opening 191 is removed by forming a resist mask and performing an etching process, etc., so that the conductor 133 remains only in the recessed portion.
33 is removed. As a result, the conductors 133a and 133b are formed. Note that at this time, the insulators 101A to 101E, the conductor 131A, and the conductor 131B are
A part of the insulator 102 may be removed so long as it is not exposed in the opening 191 .

Note that the description of FIG. 6B can be referred to for the formation of the resist mask and the etching treatment.

The conductor 133a (conductor 133b) functions as the other electrode of the capacitance element CS shown in Fig. 1A. That is, the capacitance element CS is formed in the region 181A (region 181B) shown in Fig. 8B.

In the next step, as shown in FIG. 9A, the insulator 10 located on the side of the opening 191 is
2. A semiconductor 151 is formed on the surfaces on which the conductors 133a and 133b are formed.

The semiconductor 151 is preferably made of a material containing a metal oxide described in Embodiment 3.

When the semiconductor 151 contains a metal oxide, the insulator 102 in contact with the semiconductor 151 is preferably made of an insulating material that has a function of suppressing the permeation of impurities such as water or hydrogen as well as oxygen.
Impurities such as water or hydrogen can be prevented from entering through the semiconductor 151 and reacting with oxygen contained in the semiconductor 151 to become water.
In some cases, oxygen vacancies are formed in the semiconductor 151. When impurities such as hydrogen enter the oxygen vacancies, electrons that serve as carriers may be generated. Therefore, when a region containing a large amount of hydrogen exists in the semiconductor 151, a transistor in which the region is included in the channel formation region is likely to have normally-on characteristics. To prevent this, it is preferable to use, as the insulator 102, an insulating material that has a function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen.

In addition, when the semiconductor 151 contains a metal oxide, the conductivity of the semiconductor 151 may differ depending on the region in which the semiconductor 151 is formed. In FIG. 9A, among the regions in which the semiconductor 151 is formed, the regions on the formation surface of the insulator 102 are illustrated as regions 151a and 151b.
A region on the formation surface of the conductor 133a (conductor 133b) is illustrated as a region 151c. In particular, the region 151a is a region overlapping with a side surface of the conductor 131A (conductor 131B), and the region 151b is a region overlapping with a side surface of the insulator 101A (insulators 101B to 101E). Since the region 151c is in contact with the conductor 133a (conductor 133b), impurities such as hydrogen or water contained in the conductor 133a may diffuse to the region 151c. As described above, when impurities such as water or hydrogen diffuse into the semiconductor 151, electrons that become carriers may be generated, and the resistance of the region 151c may be reduced. Therefore, the region 151c has higher conductivity than the regions 151a and 151b.

The region 151a is a region that becomes a channel formation region of the transistor. Therefore, when the transistor is in an on state, the region 151a has a low resistance and is therefore more conductive than the region 151b.

In the next step, as shown in FIG. 9B, the semiconductor 15 located on the side of the opening 191 is
An insulator 103 and a semiconductor 152 are formed in this order on the formation surface of the semiconductor substrate 101 .

The insulator 103 can be any of the above-mentioned materials that can be used for the insulator 102. In particular, when the semiconductor 151 contains a metal oxide, the insulator 102 is preferably an insulating material that has a function of suppressing permeation of not only oxygen but also impurities such as water or hydrogen.

1A is formed in the region 182A (region 182B) shown in FIG 9B. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as a channel formation region of the transistor WTr, each of the two regions 151b of the semiconductor 151 functions as a source electrode and a drain electrode of the transistor WTr, and the conductor 132A functions as a gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, the transistor WTr is an OS transistor.

As the semiconductor 152, a material containing a metal oxide described in Embodiment 3 can be used, similarly to the semiconductor 151. Alternatively, instead of the semiconductor 152, a semiconductor material such as silicon can be used.

In the next step, as shown in FIG. 10A, an insulator 104 is formed on the surface on which the semiconductor 152 is formed, and a conductor 134 is formed so as to fill the remaining openings 191 .

As the insulator 104, the material that can be used for the insulators 102 and 103 described above can be used.

The conductor 134 may be the above-mentioned conductor 131A, conductor 131B, conductor 132A,
Materials that can be used for the conductor 132B, the conductor 133a, and the conductor 133b can be used.

Incidentally, the transistor RTr shown in FIG. 1A is configured in the region 183A (region 183B) shown in FIG. 10A. Specifically, in the region 183A (region 183B),
In the semiconductor 151, the region 151c, the two regions 151b, and the conductor 133a (the conductor 133b) function as a gate electrode of the transistor RTr, the semiconductor 152 functions as a channel formation region of the transistor RTr, and the conductor 134 functions as a backgate electrode of the transistor RTr. In particular, when a material containing a metal oxide is used as the semiconductor 152, the transistor RTr is an OS transistor.

By performing the steps shown in FIG. 6A to FIG. 10A, the semiconductor device shown in FIG. 1A can be manufactured.

One embodiment of the present invention is not limited to the configuration example of the semiconductor device illustrated in Fig. 10A. One embodiment of the present invention can have a configuration in which the semiconductor device illustrated in Fig. 10A is modified as appropriate depending on the case, situation, or need.

For example, as described above, one embodiment of the present invention is a transistor W
In the case of manufacturing the semiconductor device shown in FIG. 1C, the process shown in FIG. 10B may be performed instead of the process shown in FIG.
10A ) shows a process of depositing an insulator 105 so as to fill the opening 191 instead of the conductor 134 in FIG. 10A . Note that the insulator 105 can be formed using, for example, a material that can be used as the insulator 104.

Furthermore, for example, in one embodiment of the present invention, in order to improve the switching characteristics of the transistor WTr, the structure of the gate electrode of the transistor WTr may be changed from that shown in FIG. 10A. FIGS. 11A, 11B, and 12A and 12B show an example of a method for manufacturing the semiconductor device. FIG. 11A shows a step in which the conductor 131A (conductor 131B) on the side surface of the opening 191 in FIG. 6B is removed to form a recess 193A (recess 193B). Here, the conductor 131A (conductor 131B) is
It is assumed that a material (a material having a higher etching rate than conductor 132A (conductor 132B) and insulators 101A to 101E) is used that allows the conductor 131A (conductor 131B) to be selectively removed from the laminate 100.

6A, a sacrificial layer may be provided in the region where the opening 191 and the recess 193A (recess 193B) are to be formed, and the recess 193A (recess 193B) may be formed together with the opening 191 in the process of fabricating the semiconductor device shown in FIG. 6B. When the opening 191 is formed without providing a sacrificial layer, the recess 193A (recess 193B) may be formed automatically.
93B) may also be formed.

In the next step, as shown in FIG. 11B, the side surface of the opening 191 shown in FIG.
A semiconductor 153 is formed in the recess 193A (recess 193B).

The semiconductor 153 is made of a material containing a metal oxide described in Embodiment Mode 3.

12A, in the next step, the semiconductor 153 included in the opening 191 is removed by forming a resist mask and performing an etching process or the like so that the semiconductor 153 remains only in the recess 193A (recess 193B) described above. Moreover, simultaneously with or after this process, an etching process is performed to remove the conductor 132A (conductor 132B) and form the recess 192A (recess 192B).

Next, in the same manner as in the process of FIG. 8B, the insulator 102 is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b).
When a material containing a metal oxide is used as the semiconductor 153a (semiconductor 153b
When the semiconductor 153a (semiconductor 153b) is in contact with the insulator 102, impurities such as hydrogen and water contained in the insulator 102 are diffused to the semiconductor 153a (semiconductor 153b). When the semiconductor 153a (semiconductor 153b) is in contact with the conductor 133a (conductor 133b), the conductor 133a (conductor 133b)
Impurities such as hydrogen and water contained in the semiconductor 153a (153b) diffuse into the semiconductor 153a (153b). In other words, the semiconductor 153a (153b) has a role of collecting impurities such as hydrogen and water. As a result, the resistance of the semiconductor 153a (153b) is reduced, and the transistor WT
9A to 10A, the semiconductor device shown in FIG.

For example, one embodiment of the present invention is a transistor having a first terminal
Alternatively, in order to reduce the electrical resistance between the second terminal and the gate of the transistor RTr, the structure of the gate electrode of the transistor RTr may be changed from the structure shown in FIG.
7A shows a process in which not only the conductor 132A (conductor 132B) on the side surface of the opening 191 in FIG. 7A is removed, but the insulators 101A to 101E are also removed to form a recess 194B (recess 194A, recess 194C). Here, for the conductor 132A (conductor 132B) and the insulators 101A to 101E, a material (a material having an etching rate higher than that of the conductor 131A (conductor 131B)) from which the conductor 132A (conductor 132B) and the insulators 101A to 101E of the stack 100 are selectively removed is used.

In addition, the recess 194B (recess 194A, recess 194C) is formed by providing a sacrificial layer in the region where the opening 191 and the recess 194B (recess 194A, recess 194C) are to be formed in the manufacturing process of the semiconductor device shown in FIG. 6A, and then forming the opening 191 in the manufacturing process of the semiconductor device shown in FIG.
91. Also, when the opening 191 is formed without providing a sacrificial layer, the recess 194B (recess 194A, recess 194C) may be automatically formed in some cases.

In FIG. 13A, in the recess 194B (recess 194A, recess 194C), the conductor 132A (conductor 132B) is removed to a greater extent than the insulators 101B and 101C (insulators 101A, 101D, and 101E).
The insulators 101B and 101C (insulators 101A, 101D, and 101E) may be removed to a greater extent than the conductor 132A (conductor 132B).
, insulator 101C (insulator 101A, insulator 101D, insulator 101E), and conductor 13
2A (conductor 132B) may be formed to the same depth.

Fig. 13B shows an example of the configuration of a semiconductor device after the process of Fig. 13A. After the process of Fig. 13A, a conductor 133 is formed so as to fill the recess 194B (recess 194A, recess 194C), and the gate electrode of the transistor RTr is formed.
3A illustrates a conductor 133a, a conductor 133b, and a conductor 133c that function as the gate electrode of the transistor RTr. After that, the same steps as those in FIG. 9A to FIG. 10A are performed to form the semiconductor device shown in FIG. 13B. This semiconductor device has a semiconductor 151 and a conductor 133c that are larger than the semiconductor device shown in FIG. 10A.
When a material containing a metal oxide is used for the semiconductor 151, the semiconductor device shown in FIG.
Since the region 151b shown in FIG. 1 does not exist, the electrical resistance between the first terminal or the second terminal of the transistor WTr and the gate of the transistor RTr can be reduced.

<<Production Method Example 2>>
Here, as a semiconductor device of this embodiment mode, an example of a structure different from that of Manufacturing Method Example 1 will be described with reference to FIGS.

14 to 16 are cross-sectional views for explaining a manufacturing example of the semiconductor device shown in FIG. 1A, and in particular, cross-sectional views in the channel length direction of the transistors WTr and RTr are shown, similarly to FIGS.
As with FIG. 0, some elements have been omitted for clarity of illustration.

For the first step, the description of FIGS. 6A to 7B in Manufacturing Method Example 1 will be referred to.

The process shown in FIG. 14A is a continuation of the process shown in FIG.
7A, a semiconductor 151 is formed on the side surface of the opening 191 and the formed recessed portion shown in FIG.

It is preferable to use the semiconductor described in embodiment 3 as the semiconductor 151.

In the next step, as shown in FIG. 14B, the side surface of the opening 191 shown in FIG.
A conductor 133 is formed in the formed recess.

For the conductor 133, please refer to the description of the conductor 133 explained in the example fabrication method 1.

15A, in the next step, the conductor 133 included in the opening 191 is removed by forming a resist mask and performing etching treatment or the like so that the conductor 133 remains only in the recessed portion described above. As a result, the conductors 133a and 133b are formed. At this time, a part of the semiconductor 151 may be removed as long as the insulator 102 is not exposed in the opening 191.

Note that the description of FIG. 6B can be referred to for the formation of the resist mask and the etching treatment.

The conductor 133a (conductor 133b) functions as the other electrode of the capacitance element CS shown in Fig. 1A. That is, the capacitance element CS is formed in the region 181A (region 181B) shown in Fig. 15A.

For the semiconductor 151, the description of the semiconductor 151 in Manufacturing Method Example 1 can be referred to. When the semiconductor 151 contains a metal oxide, the semiconductor 151 can be divided into a region 151a, a region 151b, and a region 151c.
Regarding 51c, the regions 151a, 151b, and 151c described in the manufacturing method example 1 are
Please refer to the description below.

In the next step, as shown in FIG. 15B, the conductor 1 located on the side surface of the opening 191 is
The insulator 103 is formed on the surfaces on which the insulating film 33a, the conductor 133b, and the semiconductor 151 are formed, and then the semiconductor 152 is formed on the surface on which the insulator 103 is formed.

For the insulator 103, please refer to the description of the insulator 103 explained in the example fabrication method 1.

For details about the semiconductor 152, please refer to the description of the semiconductor 152 explained in the example fabrication method 1.

Incidentally, the transistor WTr shown in FIG. 1A is configured in the region 182A (region 182B) shown in FIG. 15B. Specifically, in the region 182A (region 182B),
In the semiconductor 151, a region 151a of the semiconductor 151 functions as a channel formation region of the transistor WTr, two regions 151b of the semiconductor 151 function as a source electrode and a drain electrode of the transistor WTr, and the conductor 132A functions as a gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, the transistor WTr is an OS transistor.

In the next step, as shown in FIG. 16A, an insulator 104 is formed on the surface on which the semiconductor 152 is formed, and a conductor 134 is formed so as to fill the remaining openings 191 .

For the insulator 104, please refer to the description of the insulator 104 explained in the example fabrication method 1.

For the conductor 134, please refer to the description of the conductor 134 explained in the example fabrication method 1.

Incidentally, the transistor RTr shown in FIG. 1A is configured in the region 183A (region 183B) shown in FIG. 16A. Specifically, in the region 183A (region 183B),
In the semiconductor 151, the region 151c, the two regions 151b, and the conductor 133a (the conductor 133b) function as a gate electrode of the transistor RTr, the semiconductor 152 functions as a channel formation region of the transistor RTr, and the conductor 134 functions as a backgate electrode of the transistor RTr. In particular, when a material containing a metal oxide is used as the semiconductor 152, the transistor RTr is an OS transistor.

By performing the steps shown in FIGS. 6A to 7B and 14A to 16A, the semiconductor device shown in FIG. 1A can be manufactured.

One embodiment of the present invention is not limited to the configuration example of the semiconductor device illustrated in Fig. 16A. One embodiment of the present invention can have a configuration in which the semiconductor device illustrated in Fig. 16A is modified as appropriate depending on the case, situation, or need.

For example, as described above, one embodiment of the present invention is a transistor W
In the case of manufacturing the semiconductor device shown in FIG. 1C, the process shown in FIG. 16B may be performed instead of the process shown in FIG.
16A shows a process of depositing an insulator 105 so as to fill the opening 191 instead of the conductor 134 in FIG. 16A. Note that the insulator 105 can be formed using, for example, a material that can be used as the insulator 104.

In addition, for example, in one embodiment of the present invention, in order to improve the switching characteristics of the transistor WTr, the structure of the gate electrode of the transistor WTr may be changed from that shown in FIG. 16A. FIG. 17 shows a structural example of the semiconductor device. When manufacturing the semiconductor device shown in FIG. 17, the recess 19 is formed as in the structural example shown in FIG. 12B described in the manufacturing method example 1.
14A to 16A, the semiconductor device shown in FIG. 17 can be fabricated. The effect of fabricating the semiconductor device shown in FIG. 17 can be obtained by forming the semiconductor 153a (semiconductor 153b) so as to fill the recess 193B (recess 193B) of the opening 191. Next, the insulator 102 is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b). After that, the same steps as those shown in FIG. 14A to FIG. 16A are performed. Note that the effect of fabricating the semiconductor device shown in FIG. 17 can be obtained by forming the semiconductor device shown in FIG. 11A, FIG. 11B, FIG. 12A, and FIG. 13B described in the manufacturing method example 1.
Please refer to the explanation in B).

For example, one embodiment of the present invention is a transistor having a first terminal
Alternatively, in order to reduce the electrical resistance between the second terminal and the gate of the transistor RTr, the configuration of the gate electrode of the transistor RTr may be changed from the configuration shown in Fig. 16A. Fig. 18 shows an example of the configuration of the semiconductor device. When manufacturing the semiconductor device shown in Fig. 18, the example of the configuration shown in Fig. 13A described in the manufacturing method example 1 is manufactured. Thereafter,
By performing steps similar to those shown in Fig. 14A to Fig. 16A, the semiconductor device shown in Fig. 18 can be formed. Note that for effects obtained by forming the semiconductor device shown in Fig. 18, refer to the description of Fig. 13B described in Manufacturing method example 1.

By the above-described Manufacturing Method Example 1 or Manufacturing Method Example 2, a semiconductor device capable of holding a lot of data can be manufactured.

FIG. 19 shows a structure in which the cross-sectional view of the semiconductor device shown in FIG. 10A (circuit configuration of FIG. 1A) is applied to the region SD2 of the semiconductor device shown in FIG. 5B. Note that the region SD1 corresponds to a memory cell MC. As shown in FIG. 19, an opening is provided in a stacked structure of the conductor and the insulator, which are the wiring RWL and the wiring WWL, to form the above-described manufacturing method example 1.
Alternatively, the circuit configuration in FIG. 1A can be realized by performing the manufacturing method as described in Manufacturing Method Example 2.

<Example of connection to peripheral circuits>
The semiconductor device shown in Manufacturing Method Example 1 or Manufacturing Method Example 2 may have peripheral circuits of a memory cell array, such as a read circuit and a precharge circuit, formed thereunder. In this case, the peripheral circuits may be formed by forming Si transistors on a silicon substrate or the like, and then the semiconductor device of one embodiment of the present invention may be formed over the peripheral circuits by Manufacturing Method Example 1 or Manufacturing Method Example 2. FIG. 20A is a cross-sectional view in which the peripheral circuits are formed of planar Si transistors and the semiconductor device of one embodiment of the present invention is formed thereover. FIG. 21A is a cross-sectional view in which the peripheral circuits are formed of FIN-type Si transistors and the semiconductor device of one embodiment of the present invention is formed thereover. Note that the semiconductor devices shown in FIG. 20A and FIG. 20B have the configuration shown in FIG. 10A as an example.

20A and 21A, Si transistors constituting the peripheral circuit are formed on a substrate 1700. An element isolation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as the sources and drains of the Si transistors.
The conductor 1730 is formed to extend in the channel width direction and is connected to another Si transistor or the conductor 1712 (not shown).

As the substrate 1700, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used.

The substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a lamination film, paper containing a fibrous material, or a base film. A semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. In FIG. 20A and FIG. 21A, the substrate 170 is, for example,
0 shows an example in which a single crystal silicon wafer is used.

Here, the details of the Si transistor will be described. The planar type Si transistor shown in Fig. 20A is a cross-sectional view in the channel length direction, and the planar type Si transistor shown in Fig. 20B is a cross-sectional view in the channel width direction. The Si transistor includes a channel formation region 1793 provided in a well 1792, a low concentration impurity region 1794 and a high concentration impurity region 1795 (collectively referred to simply as impurity regions), a conductive region 1796 provided in contact with the impurity region, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797,
The gate electrode 1790 has a sidewall insulating layer 1798 and a sidewall insulating layer 1799 provided on the side surfaces of the gate electrode 1790. Note that the conductive region 1796 may be made of a metal silicide or the like.

21A shows a cross-sectional view in the channel length direction, and FIG. 21B shows a cross-sectional view in the channel width direction. The Si transistors shown in FIG. 21A and FIG. 21B have a channel formation region 1793.
has a convex shape, and the gate insulating film 1797 and the gate electrode 179 are formed along the side and upper surfaces of the convex shape.
In this embodiment mode, the case where the convex portion is formed by processing a part of the semiconductor substrate has been described, but the semiconductor layer having a convex shape may be formed by processing an SOI substrate.
The reference symbols shown in FIGS. 21A and 21B are the same as those shown in FIGS. 20A and 20B.

In addition, the insulators, conductors, semiconductors, etc. disclosed in the present specification and the like may be formed by PVD (Physical Vapor Deposition).
cal vapor deposition) method, CVD (Chemical Vapo
The PVD method can be, for example, a sputtering method, a resistance heating deposition method, an electron beam deposition method, a PLD (Pulsed Laser Deposition) method, etc.
Examples of the CVD method include plasma CVD and thermal CVD. In particular, examples of the thermal CVD method include MOCVD (Metal Organic Chemical Vapor Deposition).
Examples of such a method include an atomic layer deposition (ALD) method and an atomic orientation method.

The thermal CVD method is a film formation method that does not use plasma, and therefore has the advantage that defects caused by plasma damage are not generated.

In the thermal CVD method, a source gas and an oxidizing agent may be fed simultaneously into a chamber, the pressure in the chamber may be atmospheric or reduced, and the two may be reacted near or on a substrate to deposit the film on the substrate.

In addition, in the ALD method, the chamber may be kept at atmospheric pressure or reduced pressure, raw material gases for the reaction may be sequentially introduced into the chamber, and the order of gas introduction may be repeated to form a film. For example, two or more types of raw material gases may be sequentially supplied to the chamber by switching each switching valve (also called a high-speed valve), and an inert gas (argon, nitrogen, etc.) may be introduced simultaneously with or after the first raw material gas so that the multiple raw material gases are not mixed,
The second source gas is introduced. When an inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time as the introduction of the second source gas. Alternatively, instead of introducing an inert gas, the first source gas may be discharged by vacuum evacuation, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first thin layer, and reacts with the second source gas introduced later, so that the second thin layer is laminated on the first thin layer to form a thin film. By repeating this gas introduction sequence multiple times until the desired thickness is reached, a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, making it possible to precisely adjust the film thickness, and is suitable for producing fine FETs.

Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described above. For example, In-G
When forming an a-Zn-O film, trimethylindium (In(CH ₃ ) ₃ ), trimethylgallium (Ga(CH ₃ ) ₃ ), and dimethylzinc (Zn(CH ₃ ) ₂ ) are used. The combination is not limited to these, and triethylgallium (Ga(C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (
Zn( _{C2H5 ) 2} ) can also be used.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamidohafnium (TDMAH, Hf[N(CH ₃ ) ₂ ] ₄ ) is used.
Two types of gases are used: a raw material gas obtained by vaporizing the above-mentioned and ozone (O ₃ ) as an oxidizing agent.
Other materials include tetrakis(ethylmethylamido)hafnium.

For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor compound (trimethylaluminum (TMA, Al(C
Two types of gases are used: a source gas made by vaporizing aluminum oxide (H ₃ ) ₃ ) and an oxidizing agent, H ₂ O. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, when a silicon oxide film is formed by a film formation apparatus using ALD, hexachlorodisilane is adsorbed onto the film formation surface, and radicals of an oxidizing gas (O ₂ , dinitrogen monoxide) are supplied to react with the adsorbed material.

For example, when a tungsten film is formed using a film forming apparatus that uses ALD, WF ₆
Gas and _B2H6 gas are introduced in sequence to form _an initial tungsten film, and then WF
The tungsten film is formed _by repeatedly introducing _B2H6 gas and _H2 gas in sequence. Note that _SiH4 gas may be used instead of _B2H6 gas.

For example, an oxide semiconductor film, such as In--Ga--Zn--
When forming an InO film, In(CH ₃ ) ₃ gas and O ₃ gas are introduced in sequence and repeatedly to form an In
After that, Ga(CH ₃ ) ₃ gas and O ₃ gas are repeatedly introduced to form a Ga
O layer is formed, and then Zn(CH ₃ ) ₂ gas and O ₃ gas are repeatedly introduced in sequence to form Zn
In addition, the order of these layers is not limited to this example. Also, using these gases, mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers may be formed. Note that, instead of _O3 gas, _H2O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use _O3 gas that does not contain H. Also, In
Instead of the (CH ₃ ) ₃ gas, In(C ₂ H ₅ ) ₃ gas may be used.
_{Ga(C 2 H 5 ) 3 gas may} be used instead of Zn(CH ₃ ) ₂
A gas may also be used.

Note that the respective structural examples of the semiconductor device described in this embodiment mode can be combined with each other as appropriate.

Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

(Embodiment 2)
In this embodiment mode, a memory device including the semiconductor device described in the above embodiment mode will be described.

22 shows an example of the configuration of a memory device. The memory device 2600 has a peripheral circuit 2601 and a memory cell array 2610. The peripheral circuit 2601 has a row decoder 2621, a word line driver circuit 2622, a bit line driver circuit 2630, an output circuit 2640, and a control logic circuit 2660.

The semiconductor device illustrated in FIG. 1A, 1B, or 1C described in Embodiment 1 can be applied to the memory cell array 2610 .

The bit line driver circuit 2630 includes a column decoder 2631 and a precharge circuit 263
2, a sense amplifier 2633, and a write circuit 2634.
32 has a function of precharging the node N1 (not shown in FIG. 22) of the wiring RBL described in the embodiment 1 to a predetermined potential. The sense amplifier 2633 has a function of acquiring the potential of the read node N2 as a data signal and amplifying the data signal.
The amplified data signal is output via output circuit 2640 as a digital data signal RDATA.
The signal is output to the outside of the storage device 2600 as a signal.

In addition, the memory device 2600 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 2601, and a high power supply voltage (VI
L) is provided.

The memory device 2600 also includes control signals (CE, WE, RE), an address signal ADDR,
, a data signal WDATA is input from the outside. The address signal ADDR is input to a row decoder 2621 and a column decoder 2631, and the data signal WDATA is input to a write circuit 2634.

The control logic circuit 2660 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 2621 and column decoder 2631. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 2660 are not limited to these, and other control signals may be input as necessary.

The above-mentioned circuits and signals can be selected or removed as needed.

Moreover, by using a p-channel Si transistor and a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) described in an embodiment described later in a channel formation region, and applying the transistor to the memory device 2600, a small-sized memory device 2600 can be provided. In addition, the memory device 2600 capable of reducing power consumption can be provided. In addition, the memory device 2600 capable of improving the operation speed can be provided. In particular, by using only p-channel Si transistors, the manufacturing cost can be kept low.

The configuration of this embodiment is not limited to the configuration shown in FIG.
26. The configuration may be modified as appropriate, for example, by providing a part of the semiconductor memory device 2601, such as a precharge circuit 2632 and/or a sense amplifier 2633, below the memory cell array 2610.

Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

(Embodiment 3)
In this embodiment, a metal oxide contained in a channel formation region of the OS transistor used in the above embodiment will be described.

The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to the above, aluminum, gallium,
It is preferable that yttrium or tin is contained. Also, boron, silicon,
It may contain one or more elements selected from titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

Here, the case where the metal oxide is an In-M-Zn oxide having indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like. However, there are cases where a combination of a plurality of the above-mentioned elements may be used as the element M.

Next, a preferred range of the atomic ratio of indium, element M, and zinc in the metal oxide according to the present invention will be described with reference to Figures 23(A), 23(B), and 23(C). The atomic ratio of oxygen is not shown in Figures 23(A), 23(B), and 23(C). The terms of the atomic ratio of indium, element M, and zinc in the metal oxide are [In], [M], and [Zn], respectively.

In Fig. 23(A), Fig. 23(B), and Fig. 23(C), the dashed lines indicate [In]:[M
]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1),
The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2 is
The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1−α):3 is
These lines represent the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):4, and the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5.

The dashed dotted line indicates the line where the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0), and the line where the atomic ratio of [In]:[M]:[Zn]=2:1:β,
The line where the atomic ratio of [In]:[M]:[Zn]=1:1:β is
] = 1:2:β, a line where the atomic ratio of [In]:[M]:[Zn] = 1:3:β, and a line where the atomic ratio of [In]:[M]:[Zn] = 1:4:β.

In addition, the [In]:[M]:
Metal oxides with an atomic ratio of [Zn]=0:2:1 and values close to this ratio tend to have a spinel-type crystal structure.

In addition, multiple phases may coexist in a metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, two phases, a spinel-type crystal structure and a layered crystal structure, tend to coexist.
When the ratio [M]:[Zn] is close to 1:0:0, two phases, a bixbyite-type crystal structure and a layered crystal structure, tend to coexist. When multiple phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures.

A region A shown in FIG. 23A shows an example of a preferable range of the atomic ratio of indium, the element M, and zinc contained in the metal oxide.

By increasing the indium content of the metal oxide, the carrier mobility of the metal oxide (
Therefore, a metal oxide having a high indium content has a higher carrier mobility than a metal oxide having a low indium content.

On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility is low. Therefore, when the atomic ratio [In]:[M]:[Zn] is 0:1:0 or a value close to it (e.g., region C shown in FIG. 23C), the insulating property is high.

Therefore, the metal oxide of one embodiment of the present invention preferably has an atomic ratio shown in region A in FIG. 23A , which is likely to have a layered structure with high carrier mobility and few crystal grain boundaries.

In particular, in the region B shown in FIG. 23B, the CAAC (c-axis a
In this way, an excellent metal oxide having high carrier mobility can be obtained.

CAAC-OS has a crystal structure that has c-axis orientation, in which multiple nanocrystals are connected in the a-b plane direction and has distortion. Note that the distortion refers to a portion where the direction of the lattice arrangement changes between a region where a lattice arrangement is aligned and a region where a different lattice arrangement is aligned, in a region where multiple nanocrystals are connected.

Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes and may be non-regular hexagonal. The distortion may have a lattice arrangement such as a pentagon or a heptagon. In CAAC-OS, no clear crystal grain boundary (also called grain boundary) can be confirmed even in the vicinity of the distortion. That is, it is found that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the bond distance between atoms changes due to substitution of a metal element.

CAAC-OS is a metal oxide with high crystallinity. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, it can be said that the decrease in electron mobility caused by the crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of a metal oxide can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be a metal oxide with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of a metal oxide having CAAC-OS are stable.
Therefore, a metal oxide having CAAC-OS is resistant to heat and has high reliability.

Region B includes [In]:[M]:[Zn]=4:2:3 to 4.1 and their neighboring values. Neighboring values include, for example, [In]:[M]:[Zn]=5:3:4. Region B also includes [In]:[M]:[Zn]=5:1:6 and their neighboring values, and [In]:[M]:[Zn]=5:1:7 and their neighboring values.

The properties of metal oxides are not uniquely determined by the atomic ratio. Even if the atomic ratio is the same, the properties of metal oxides may differ depending on the formation conditions. For example, when a metal oxide film is formed using a sputtering device, a film with an atomic ratio that is different from the atomic ratio of the target is formed. In addition, depending on the substrate temperature during film formation, the atomic ratio of the target [Zn] may be higher than that of the target [Zn].
[Zn] of the film may become small. Therefore, the illustrated region is a region showing an atomic ratio where the metal oxide tends to have specific properties, and the boundary between region A to region C is not strict.

Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

(Embodiment 4)
In this embodiment, a CPU that can include the semiconductor device of the above embodiment will be described.

FIG. 24 is a block diagram showing a configuration of an example of a CPU that uses the semiconductor device described in the first embodiment as a part thereof.

The CPU shown in FIG. 24 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190.
The semiconductor device 1190 includes an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I/F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I/F). The substrate 1190 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 are
Alternatively, the CPU may be provided on a separate chip. Of course, the CPU shown in FIG. 24 is merely an example showing a simplified configuration, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 24 may be one core, and multiple such cores may be included, with each core operating in parallel, in other words, a GPU-like configuration. Also, the number of bits that the CPU can handle in its internal arithmetic circuit or data bus may be, for example, 8 bits, 16 bits, or 16 bits.
It can be 32-bit, 64-bit, etc.

An instruction input to the CPU via the bus interface 1198 is input to an instruction decoder 1193 , decoded, and then input to an ALU controller 1192 , an interrupt controller 1194 , a register controller 1197 , and a timing controller 1195 .

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 judges and processes interrupt requests from external input/output devices and peripheral circuits based on their priority and mask state while the CPU is executing a program. The register controller 1197 generates an address for the register 1196, and reads and writes data from and to the register 1196 depending on the state of the CPU.

The timing controller 1195 controls the ALU 1191 and the ALU controller 11
92, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

24, a memory cell is provided in a register 1196. As the memory cell of the register 1196, the transistor described in the above embodiment can be used.

In the CPU shown in FIG. 24, a register controller 1197 selects a hold operation in a register 1196 in accordance with an instruction from an ALU 1191.
In the memory cells of register 1196, whether data is to be held by a flip-flop or by a capacitive element is selected. When holding data by a flip-flop is selected, a power supply voltage is supplied to the memory cells in register 1196. When holding data in a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power supply voltage to the memory cells in register 1196 can be stopped.

Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

(Embodiment 5)
A memory card (e.g., an SD card) that can be equipped with the storage device of the above embodiment
, USB (Universal Serial Bus) memory, SSD (Solid
The present invention can be applied to various removable storage devices such as a removable state drive (RAM, USB flash drive, etc.). In this embodiment, some configuration examples of removable storage devices will be described with reference to FIG.

FIG. 25A is a schematic diagram of a USB memory. The USB memory 5100 has a housing 5101.
, a cap 5102, a USB connector 5103, and a substrate 5104.
are housed in a housing 5101. A memory device and a circuit for driving the memory device are provided on a substrate 5104. For example, a memory chip 5105 and a controller chip 5106 are attached to the substrate 5104. The memory chip 5105 includes the memory cell array 2610, the word line driver circuit 2622, the row decoder 26, and the like, which are described in the third embodiment.
21, a sense amplifier 2633, a precharge circuit 2632, a column decoder 2631, etc. are incorporated in the controller chip 5106. Specifically, a processor, a work memory, an ECC circuit, etc. are incorporated in the controller chip 5106. Note that the circuit configurations of the memory chip 5105 and the controller chip 5106 are not limited to those described above, and may be changed as appropriate depending on the situation or circumstances. For example, the word line driver circuit 2622,
The row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, and the column decoder 2631 may be incorporated in the controller chip 5106 instead of in the memory chip 5105. The USB connector 5103 functions as an interface for connecting to an external device.

Fig. 25(B) is a schematic diagram of the external appearance of an SD card, and Fig. 25(C) is a schematic diagram of the internal structure of an SD card. The SD card 5110 has a housing 5111, a connector 5112, and a board 5113. The connector 5112 functions as an interface for connecting to an external device. The board 5113 is housed in the housing 5111. A memory device and a circuit for driving the memory device are provided on the board 5113. For example, a memory chip 5114 and a controller chip 5115 are attached to the board 5113. The memory chip 511
4 includes the memory cell array 2610 and the word line driver circuit 26
The memory chip 5114 and the controller chip 5115 are provided with a memory chip 5114, a row decoder 2621, a sense amplifier 2633, a precharge circuit 2632, a column decoder 2631, etc. The controller chip 5115 is provided with a processor, a work memory, an ECC circuit, etc. The circuit configurations of the memory chip 5114 and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation or circumstances. For example, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 263
2. The column decoder 2631 is not in the memory chip 5114 but in the controller chip 511
5 may be incorporated therein.

By providing a memory chip 5114 on the back side of the substrate 5113, the SD card 5110
The capacity of the memory chip 5114 can be increased. In addition, a wireless chip having a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the memory chip 5114.

Fig. 25D is a schematic diagram of the external appearance of the SSD, and Fig. 25E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a board 5153. The connector 5152 functions as an interface for connecting to an external device.
The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a memory device and a circuit for driving the memory device. For example, the substrate 5153 includes a memory chip 5154.
, a memory chip 5155, and a controller chip 5156 are attached to the memory chip 5154. The memory chip 5154 includes the memory cell array 2610, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2640, and the like, which are described in the third embodiment.
32, a column decoder 2631, etc. are incorporated. By providing a memory chip 5154 on the back side of the substrate 5153 as well, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 includes a processor, an E
A CC circuit and the like are built in. The memory chip 5154 and the memory chip 515
The circuit configurations of the controller chip 5115 and the controller chip 5116 are not limited to those described above, and may be changed as appropriate depending on the situation or circumstances. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

(Embodiment 6)
In this embodiment, an example of an electronic device to which the memory device in the above embodiment can be applied will be described.

<Notebook personal computer>
FIG. 26A shows a notebook personal computer, which includes a housing 5401 and a display unit 540.
2, a keyboard 5403, and a pointing device 5404. The storage device of one embodiment of the present invention can be provided in a notebook personal computer.

<Smartwatch>
FIG. 26B shows a smart watch, which is a type of wearable terminal.
, a display unit 5902, an operation button 5903, an operator 5904, a band 5905, and the like. The storage device of one embodiment of the present invention can be provided in a smartwatch. A display device to which a function as a position input device is added may be used for the display unit 5902. The function as the position input device can be added by providing a touch panel in the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element also called a photosensor in a pixel portion of the display device. The operation button 5903 can be provided with any of a power switch for starting the smartwatch, a button for operating an application of the smartwatch, a volume control button, and a switch for turning on or off the display unit 5902. Although the number of operation buttons 5903 is two in the smartwatch shown in FIG. 26B, the number of operation buttons of the smartwatch is not limited to this. The operator 5904 functions as a crown for setting the time of the smartwatch. The operator 5904 may be used as an input interface for operating an application of the smartwatch in addition to setting the time. In addition, in the smart watch shown in FIG. 26(B), the operation element 590
However, the present invention is not limited to this and may be configured without the operation element 5904.

<Video Camera>
FIG. 26C shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 5
The storage device of one embodiment of the present invention can be provided in a video camera.
A display unit 5805 is provided in a first housing 5801, and a display unit 5803 is provided in a second housing 5802. The first housing 5801 and the second housing 5802 are connected to each other by a connection unit 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection unit 5806. A configuration in which an image on the display unit 5803 is switched according to the angle between the first housing 5801 and the second housing 5802 at the connection unit 5806 may be used.

<Mobile Phones>
FIG. 26D shows a mobile phone having an information terminal function.
5502, a microphone 5503, a speaker 5504, and an operation button 5505. The storage device of one embodiment of the present invention can be provided in a mobile phone. A display device to which a function as a position input device is added may be used for the display portion 5502. The function as the position input device can be added by providing a touch panel in the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element also called a photosensor in a pixel portion of the display device. The operation button 5505 can be provided with any of a power switch for starting the mobile phone, a button for operating an application of the mobile phone, a volume adjustment button, a switch for turning on or off the display portion 5502, or the like.

In addition, although the mobile phone shown in Fig. 26D has two operation buttons 5505, the number of operation buttons of the mobile phone is not limited to this. Although not shown, the mobile phone shown in Fig. 26D may have a light-emitting device for use as a flashlight or illumination.

<Television Device>
FIG. 26E is a perspective view showing a television device.
000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared ray), etc. The storage device of one embodiment of the present invention can be provided in a television device. The television device has a large screen, for example, 50 inches or more, or 100
It is possible to incorporate a display unit 9001 having a size of 1 inch or more.

<Mobile>
The above-mentioned display device can also be applied to the vicinity of the driver's seat of an automobile, which is a moving body.

For example, FIG. 26(F) is a diagram showing the vicinity of the windshield in the interior of an automobile.
In FIG. 26(F), a display panel 5701 and a display panel 5702 are attached to the dashboard.
702, display panel 5703, and also a display panel 5704 attached to a pillar.

The display panels 5701 to 5703 can provide various information such as navigation information, a speedometer, a tachometer, a mileage, a fuel amount, a gear state, and an air conditioner setting. In addition, the display items and layouts displayed on the display panels can be changed as appropriate according to the user's preferences, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

The display panel 5704 can complement the field of view (blind spot) blocked by the pillar by displaying an image from an imaging means provided on the vehicle body. In other words, by displaying an image from an imaging means provided on the outside of the vehicle, blind spots can be complemented and safety can be improved. In addition, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

The storage device of one embodiment of the present invention can be provided in a mobile object. For example, the storage device of one embodiment of the present invention can be used as a frame memory for temporarily storing image data used for displaying images on the display panels 5701 to 5704, a storage device for storing a program for driving a system included in the mobile object, and the like.

Although not shown, the electronic devices shown in Figures 26A to 26C, 26E, and 26F may have a microphone and a speaker. With this configuration, for example, the electronic devices described above can be provided with a voice input function.

Although not shown, the electronic devices shown in FIGS. 26A, 26B, 26D to 26F may have a camera.

Although not shown, the electronic devices shown in FIGS. 26A to 26F have sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, etc.) inside the housing.
26D includes a detection device having a sensor for detecting tilt such as a gyro or an acceleration sensor, so that the orientation of the mobile phone (the orientation of the mobile phone relative to the vertical direction) can be determined and the screen display of the display portion 5502 can be automatically switched according to the orientation of the mobile phone.

Although not shown, the electronic devices shown in FIGS. 26A to 26F can also be used to identify fingerprints, veins,
The present invention may be configured to include a device for acquiring biometric information such as an iris or a voiceprint, etc. By applying this configuration, an electronic device having a biometric authentication function can be realized.

26A to 26F may be formed using a flexible substrate as a display portion of the electronic device. Specifically, the display portion may have a structure in which a transistor, a capacitor, a display element, and the like are provided over a flexible substrate. By applying this structure,
In addition to the electronic devices having housings with flat surfaces like those shown in FIGS. 26A to 26F, electronic devices having housings with curved surfaces can be realized.

Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

(Additional notes regarding the present specification, etc.)
The following additional notes will be given regarding the description of each component in the above embodiment.

<Additional Notes on One Aspect of the Present Invention Described in the Embodiments>
The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

In addition, the content described in one embodiment (or a part of the content) can be applied, combined, or replaced with at least one of another content described in that embodiment (or a part of the content) and one or more other content described in another embodiment (or a part of the content).

The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and/or with one or more figures (or a part thereof) described in another embodiment or embodiments to form even more figures.

<Notes on ordinal numbers>
In this specification, the ordinal numbers "first,""second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

<Notes regarding the description of the drawings>
The embodiments are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the forms and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations thereof will be omitted.

In addition, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in order to explain the positional relationship between components with reference to the drawings. The positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, terms indicating arrangement are not limited to the descriptions explained in the specification, and can be rephrased appropriately depending on the situation.

Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

In addition, in the drawings, such as perspective views, some components may be omitted in order to ensure clarity of the drawings.

In addition, in the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same symbols, and repeated explanations thereof may be omitted.

<Notes on possible alternative descriptions>
In this specification and the like, when describing the connection relationship of a transistor, one of the source and drain is expressed as "one of the source or drain" (or first electrode or first terminal), and the other of the source and drain is expressed as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation. Also, in this specification and the like, the two terminals other than the gate are referred to as the first terminal and the second terminal.
In this specification and the like, the terminal may be called a terminal, a third terminal, or a fourth terminal.
The channel formation region refers to a region in which a channel is formed by applying a potential to a gate, and the formation of this region allows a current to flow between the source and drain.

Furthermore, the functions of the source and drain may be interchangeable when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

Furthermore, when a transistor described in this specification has two or more gates (this configuration may be referred to as a dual gate structure), the gates may be referred to as a first gate, a second gate, a front gate, and a back gate. In particular, the term "front gate" may be interchangeably replaced with the term "gate."
The term "back gate" can be simply interchangeably referred to as "gate." Note that a bottom gate refers to a terminal that is formed before a channel formation region is formed during the manufacture of a transistor, and a top gate refers to a terminal that is formed after a channel formation region is formed during the manufacture of a transistor.

In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" may be used to refer to a plurality of "electrodes" or "wirings".
This also includes cases where the wiring is formed integrally.

In this specification and the like, the terms voltage and potential can be interchanged as appropriate. A voltage is a potential difference from a reference potential. For example, if the reference potential is a ground potential (earth potential), then voltage can be interchanged with potential. The ground potential is not necessarily 0 V.
It is important to note that potential is relative, and depending on the reference potential,
The potential applied to wiring etc. may be changed.

In this specification, terms such as "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the circumstances, terms such as "film" and "layer" may not be used and may be replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

In this specification, terms such as "wiring", "signal line", and "power line" can be interchanged depending on the circumstances. For example, the term "wiring" can be changed to the term "signal line".
The term "wiring" may be changed to a term such as "power line". Also, vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring". A term such as "power line" may be changed to a term such as "signal line". Also, vice versa, terms such as "signal line" may be changed to a term such as "power line". Also, depending on the situation, the term "potential" applied to the wiring may be changed to a term such as "signal". Also, vice versa, terms such as "signal" may be changed to the term "potential".

<Notes on definitions of terms>
The following provides definitions of terms used in the above embodiments.

<<About impurities in semiconductors>>
An impurity in a semiconductor refers to, for example, anything other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. When an impurity is contained, for example, density of states (DOS) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, and the like.
In particular, there are hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, oxygen vacancies may be formed by the inclusion of impurities such as hydrogen. In addition, when the semiconductor is a silicon layer, impurities that change the characteristics of the semiconductor include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, and Group 1 elements.
Group 3 elements, Group 15 elements, etc.

<<About switches>>
In this specification and the like, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a switch refers to a device that has a function of selecting and switching a path through which a current flows.

As an example, an electrical switch or a mechanical switch can be used. In other words, the switch is not limited to a specific one as long as it can control the current.

An example of an electrical switch is a transistor (e.g., a bipolar transistor,
MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes,
Examples of such diodes include Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, and logic circuits that combine these diodes.

When a transistor is used as a switch, the "conduction state" of the transistor is
A "non-conducting state" of a transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically short-circuited. In addition, a "non-conducting state" of a transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically cut off. Note that when a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

An example of a mechanical switch is a switch using MEMS (microelectromechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be mechanically moved, and operates by controlling conduction and non-conduction by the movement of the electrode.

<<About connection>>
In this specification, when it is stated that X and Y are connected, this includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, this is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, but also includes connection relationships other than those shown in a figure or text.

X, Y, etc. used here are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display element, a light-emitting element, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on/off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows.

As an example of a case where X and Y are functionally connected, a circuit that enables the functional connection between X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (
One or more of the following may be connected between X and Y: power supply circuits (such as a step-up circuit or a step-down circuit, a level shifter circuit that changes the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or amount of current, such as an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, a signal generation circuit, a memory circuit, a control circuit, etc.). As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., when they are connected with another element or circuit between them), the case where X and Y are functionally connected (i.e., when they are functionally connected with another circuit between them), and the case where X and Y are directly connected (i.e., when they are connected without another element or circuit between them). In other words, when it is explicitly stated that X and Y are electrically connected, this is the same as when it is explicitly stated that they are simply connected.

For example, the source (or the first terminal, etc.) of the transistor is electrically connected to X through (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is
In the case where the transistor is electrically connected to Y through (or without) Z2, or where the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, and the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows.

For example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to each other.
, Y are provided in this connection order." By specifying the order of connections in a circuit configuration using expressions similar to these examples, the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor can be distinguished to determine the technical scope. Note that these expressions are merely examples, and the present invention is not limited to these expressions. Here, X, Y, Z1, and Z2 represent objects (e.g., a device,
elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has the functions of both components, that is, the wiring function and the electrode function. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

<<About parallel and perpendicular>>
In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the angle also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less.
In addition, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle also includes the case of 85° or more and 95° or less. In addition, "substantially perpendicular" means that
This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

MC[1] Memory cell MC[2] Memory cell MC[n] Memory cell MC[1,1] Memory cell MC[j,1] Memory cell MC[n,1] Memory cell MC[1,i] Memory cell MC[j,i] Memory cell MC[n,i] Memory cell MC[1,m] Memory cell MC[j,m] Memory cell MC[n,m] Memory cell WWL[1] Wiring WWL[2] Wiring WWL[j] Wiring WWL[n] Wiring RWL[1] Wiring RWL[2] Wiring RWL[j] Wiring RWL[n] Wiring WBL Wiring WBL[1] Wiring WBL[i] Wiring WBL[m] Wiring RBL Wiring RBL[1] Wiring RBL[i] Wiring RBL[m] Wiring BGL Wiring BGL[1] Wiring BGL[i] Wiring BGL[m] Wiring WTr Transistor RTr Transistor CS Capacitive element N1 Node N2 Node PG Conductor WWL Wiring RWL Wiring ER Wiring HL Region AR Region SD1 Region SD2 Region 100 Stacked body 101A Insulator 101B Insulator 101C Insulator 101D Insulator 101E Insulator 102 Insulator 103 Insulator 104 Insulator 105 Insulator 131A Conductor 131B Conductor 132A Conductor 132B Conductor 133 Conductor 133a Conductor 133b Conductor 133c Conductor 134 Conductor 151 Semiconductor 151a Region 151b Region 151c Region 152 Semiconductor 153 Semiconductor 153a Semiconductor 153b Semiconductor 181A Region 181B Region 182A Region 182B Region 183A Region 183B Region 191 Opening 192A Recess 192B Recess 193A Recess 193B Recess 194A Recess 194B Recess 194C Recess 1191 ALU
1192 ALU controller 1193 instruction decoder 1194 interrupt controller 1195 timing controller 1196 register 1197 register controller 1198 bus interface 1199 ROM
1189 ROM interface 1190 Substrate 1700 Substrate 1701 Element isolation layer 1712 Conductor 1730 Conductor 1790 Gate electrode 1792 Well 1793 Channel formation region 1794 Low concentration impurity region 1795 High concentration impurity region 1796 Conductive region 1797 Gate insulating film 1798 Side wall insulating layer 1799 Side wall insulating layer 2600 Storage device 2601 Peripheral circuit 2610 Memory cell array 2621 Row decoder 2622 Word line driver circuit 2630 Bit line driver circuit 2631 Column decoder 2632 Precharge circuit 2633 Sense amplifier 2634 Write circuit 2640 Output circuit 2660 Control logic circuit 5100 USB memory 5101 Housing 5102 Cap 5103 USB connector 5104 Substrate 5105 Memory chip 5106 Controller chip 5110 SD card 5111 Housing 5112 Connector 5113 Board 5114 Memory chip 5115 Controller chip 5150 SSD
5151 Housing 5152 Connector 5153 Board 5154 Memory chip 5155 Memory chip 5156 Controller chip 5401 Housing 5402 Display section 5403 Keyboard 5404 Pointing device 5501 Housing 5502 Display section 5503 Microphone 5504 Speaker 5505 Operation button 5701 Display panel 5702 Display panel 5703 Display panel 5704 Display panel 5801 First housing 5802 Second housing 5803 Display section 5804 Operation key 5805 Lens 5806 Connection section 5901 Housing 5902 Display section 5903 Operation button 5904 Operator 5905 Band 9000 Housing 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor

Claims (4)

The semiconductor device includes a first transistor, a second transistor, a third transistor, and a capacitor.
one of a source and a drain of the first transistor is electrically connected to a gate of the third transistor;
one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor;
a gate of the first transistor is electrically connected to a first wiring;
a gate of the second transistor is electrically connected to a second wiring;
a gate of the third transistor is electrically connected to a first electrode of the capacitance element;
a back gate of the third transistor is electrically connected to a third wiring,
a first conductor having a function as the third wiring;
a first insulator having a region disposed above the first conductor;
a first semiconductor having a region disposed above the first insulator and having a channel formation region of the third transistor;
a second insulator having a region disposed above the first semiconductor;
a second semiconductor having a region disposed above the second insulator and having a channel formation region of the first transistor and a channel formation region of the second transistor;
a second conductor having a region disposed above the second semiconductor, electrically connected to the second semiconductor, and functioning as a first electrode of the capacitance element;
a third conductor having a region disposed above the second semiconductor via a third insulator and functioning as the first wiring;
a fourth conductor having a region disposed above the second semiconductor via the third insulator and functioning as the second wiring;
a fifth conductor having a region disposed above the second conductor and functioning as a second electrode of the capacitance element;
having
the second conductor has a region in contact with the second semiconductor;
the second conductor overlaps with the first semiconductor via the second insulator;
Semiconductor device. The semiconductor device includes a first transistor, a second transistor, a third transistor, and a capacitor.
one of a source and a drain of the first transistor is electrically connected to a gate of the third transistor;
one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor;
a gate of the first transistor is electrically connected to a first wiring;
a gate of the second transistor is electrically connected to a second wiring;
a gate of the third transistor is electrically connected to a first electrode of the capacitance element;
a back gate of the third transistor is electrically connected to a third wiring,
a first conductor having a function as the third wiring;
a first insulator having a region disposed above the first conductor;
a first semiconductor having a region disposed above the first insulator and having a channel formation region of the third transistor;
a second insulator having a region disposed above the first semiconductor;
a second semiconductor having a region disposed above the second insulator and having a channel formation region of the first transistor and a channel formation region of the second transistor;
a second conductor having a region disposed above the second semiconductor, electrically connected to the second semiconductor, and functioning as a first electrode of the capacitance element;
a third conductor having a region disposed above the second semiconductor via a third insulator and functioning as the first wiring;
a fourth conductor having a region disposed above the second semiconductor via the third insulator and functioning as the second wiring;
a fifth conductor having a region disposed above the second conductor and functioning as a second electrode of the capacitance element;
having
the second conductor has a region in contact with the second semiconductor;
the second conductor overlaps with the first semiconductor via the second insulator;
The second conductor overlaps with the first conductor.
Semiconductor device. The semiconductor device includes a first transistor, a second transistor, a third transistor, and a capacitor.
one of a source and a drain of the first transistor is electrically connected to a gate of the third transistor;
one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor;
a gate of the first transistor is electrically connected to a first wiring;
a gate of the second transistor is electrically connected to a second wiring;
a gate of the third transistor is electrically connected to a first electrode of the capacitance element;
a back gate of the third transistor is electrically connected to a third wiring,
a first conductor having a function as the third wiring;
a first insulator having a region disposed above the first conductor;
a first semiconductor having a region disposed above the first insulator and having a channel formation region of the third transistor;
a second insulator having a region disposed above the first semiconductor;
a second semiconductor having a region disposed above the second insulator and having a channel formation region of the first transistor and a channel formation region of the second transistor;
a second conductor having a region disposed above the second semiconductor, electrically connected to the second semiconductor, and functioning as a first electrode of the capacitance element;
a third conductor having a region disposed above the second semiconductor via a third insulator and functioning as the first wiring;
a fourth conductor having a region disposed above the second semiconductor via the third insulator and functioning as the second wiring;
a fifth conductor having a region disposed above the second conductor and functioning as a second electrode of the capacitance element;
having
the second conductor has a region in contact with the second semiconductor;
the second conductor overlaps with the first semiconductor via the second insulator;
the third conductor overlaps with the first conductor;
the fourth conductor overlaps with the first conductor;
Semiconductor device. The semiconductor device includes a first transistor, a second transistor, a third transistor, and a capacitor.
one of a source and a drain of the first transistor is electrically connected to a gate of the third transistor;
one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor;
a gate of the first transistor is electrically connected to a first wiring;
a gate of the second transistor is electrically connected to a second wiring;
a gate of the third transistor is electrically connected to a first electrode of the capacitance element;
a back gate of the third transistor is electrically connected to a third wiring,
a first conductor having a function as the third wiring;
a first insulator having a region disposed above the first conductor;
a first semiconductor having a region disposed above the first insulator and having a channel formation region of the third transistor;
a second insulator having a region disposed above the first semiconductor;
a second semiconductor having a region disposed above the second insulator and having a channel formation region of the first transistor and a channel formation region of the second transistor;
a second conductor having a region disposed above the second semiconductor, electrically connected to the second semiconductor, and functioning as a first electrode of the capacitance element;
a third conductor having a region disposed above the second semiconductor via a third insulator and functioning as the first wiring;
a fourth conductor having a region disposed above the second semiconductor via the third insulator and functioning as the second wiring;
a fifth conductor having a region disposed above the second conductor and functioning as a second electrode of the capacitance element;
having
the second conductor has a region in contact with the second semiconductor;
the second conductor overlaps with the first semiconductor via the second insulator;
the second conductor has an overlap with the first conductor;
the third conductor overlaps with the first conductor;
the fourth conductor overlaps with the first conductor;
Semiconductor device.

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