JP7554280B2 - Data receiving circuit, data receiving system and storage device - Google Patents

Description

The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a data receiving circuit, a data receiving system, and a storage device.

This application claims priority from Chinese Patent Application No. 202210787529.7, filed on July 4, 2022, entitled "Data Receiving Circuit, Data Receiving System, and Storage Device," the entire contents of which are incorporated herein by reference.

In memory applications, as signal transmission speeds become faster, channel loss has a greater impact on signal quality, making it easier to cause inter-symbol interference. In addition, the difference in level between the data signal received by the memory's data receiving circuit and the reference signal affects how the data receiving circuit judges the data signal, thereby affecting the accuracy of the signal output by the data receiving circuit.

Currently, a balanced circuit is generally used to compensate the channel, and the balanced circuit may be a Continuous Time Linear Equalizer (CTLE) or a Decision Feedback Equalizer (DFE). However, there is room for improvement in the accuracy of the signal output by the currently used balanced circuit, the receiving performance of the balanced circuit, and the processing speed of the data signal by the balanced circuit.

The embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device, and contribute to at least improving the receiving performance of the data receiving circuit and improving the processing speed of data signals.

According to some embodiments of the present disclosure, one aspect of the embodiments of the present disclosure provides a data receiving circuit, comprising a first amplification module and a second amplification module, the first amplification module receiving an enable signal, a first feedback signal, a second feedback signal, a data signal, a first reference signal, and a second reference signal, and while the enable signal has a first level value, the first amplification module is responsive to a sampling clock signal, and based on the first feedback signal, selects the data signal and the first reference signal to perform a first comparison and output a first signal pair as a result of the first comparison, or is responsive to the sampling clock signal, and based on the second feedback signal, selects the data signal and the second reference signal to perform a second comparison and output a second signal pair as a result of the second comparison; The first comparison is performed in response to the sampling clock signal to output the first signal pair while the enable signal has a second level value, the first feedback signal is inverse to a level of the second feedback signal, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal, the first amplification module comprises an amplification unit, a first NMOS field effect transistor and a second NMOS field effect transistor, and a third NMOS field effect transistor and a fourth NMOS field effect transistor, the amplification unit has a first node, a second node, a third node and a fourth node, the first node outputs the first signal, the second node outputs the second signal, and the third node outputs the fourth signal. a third node outputs the third signal, a fourth node outputs the fourth signal, and the fourth node outputs the fourth signal, and is configured to receive the data signal, the first reference signal, and the second reference signal, one end of the first NMOS field effect transistor is connected to the first node, the other end of the first NMOS field effect transistor is connected to one end of the second NMOS field effect transistor, and the other end of the second NMOS field effect transistor is connected to the second node, one gate of the first NMOS field effect transistor and the second NMOS field effect transistor receives a first complementary feedback signal and the other gate of the first NMOS field effect transistor receives the enable signal, the first complementary feedback signal is inverse to a level of the first feedback signal, and the third NMOS field effect transistor one end of the third NMOS field effect transistor is connected to the third node, the other end of the third NMOS field effect transistor is connected to one end of the fourth NMOS field effect transistor, the other end of the fourth NMOS field effect transistor is connected to the fourth node, one gate of the third NMOS field effect transistor and the fourth NMOS field effect transistor receives a second complementary feedback signal, and the other gate receives the enable signal, the second complementary feedback signal is opposite in level to the second feedback signal, and the second amplification module is configured to receive the output signal of the first amplification module as an input signal pair, perform an amplification process on the voltage difference of the input signal pair, and output a first output signal and a second output signal as a result of the amplification process.

In some embodiments, the first amplification module further includes a fifth NMOS field effect transistor and a sixth NMOS field effect transistor, one end of the fifth NMOS field effect transistor is connected to the first node, the other end of the fifth NMOS field effect transistor is connected to one end of the sixth NMOS field effect transistor, and the other end of the sixth NMOS field effect transistor is connected to the second node, and one gate of the fifth NMOS field effect transistor and the sixth NMOS field effect transistor receives the first complementary feedback signal and the other gate receives the enable signal.

In some embodiments, the gate of the first NMOS field effect transistor receives the enable signal, the gate of the second NMOS field effect transistor receives the first complementary feedback signal, the channel width of the first NMOS field effect transistor is greater than the channel width of the second NMOS field effect transistor, the gate of the fifth NMOS field effect transistor receives the first complementary feedback signal, the gate of the sixth NMOS field effect transistor receives the enable signal, and the channel width of the fifth NMOS field effect transistor is smaller than the channel width of the sixth NMOS field effect transistor.

In some embodiments, the channel width of the fifth NMOS field effect transistor is equal to the channel width of the second NMOS field effect transistor, the channel width of the sixth NMOS field effect transistor is equal to the channel width of the first NMOS field effect transistor, and the channel length of the first NMOS field effect transistor, the channel length of the second NMOS field effect transistor, the channel length of the fifth NMOS field effect transistor, and the channel length of the sixth NMOS field effect transistor are all equal.

In some embodiments, the first amplification module further includes a seventh NMOS field effect transistor and an eighth NMOS field effect transistor, one end of the seventh NMOS field effect transistor is connected to the third node, the other end of the seventh NMOS field effect transistor is connected to one end of the eighth NMOS field effect transistor, and the other end of the eighth NMOS field effect transistor is connected to the fourth node, and one of the seventh NMOS field effect transistor and the eighth NMOS field effect transistor receives the second complementary feedback signal and the other gate receives the enable signal.

In some embodiments, the gate of the third NMOS field effect transistor receives the enable signal, the gate of the fourth NMOS field effect transistor receives the second complementary feedback signal, the channel width of the third NMOS field effect transistor is greater than the channel width of the fourth NMOS field effect transistor, the gate of the seventh NMOS field effect transistor receives the second complementary feedback signal, the gate of the eighth NMOS field effect transistor receives the enable signal, and the channel width of the seventh NMOS field effect transistor is smaller than the channel width of the eighth NMOS field effect transistor.

In some embodiments, the channel width of the seventh NMOS field effect transistor is equal to the channel width of the fourth NMOS field effect transistor, the channel width of the eighth NMOS field effect transistor is equal to the channel width of the third NMOS field effect transistor, and the channel length of the third NMOS field effect transistor, the channel length of the fourth NMOS field effect transistor, the channel length of the seventh NMOS field effect transistor, and the channel length of the eighth NMOS field effect transistor are all equal.

In some embodiments, the sampling clock signal includes a first sampling clock signal and a second sampling clock signal, and the amplification unit includes a first comparison circuit having the first node and the second node, configured to receive the data signal and the first reference signal and perform the first comparison in response to the first sampling clock signal; a clock generation circuit configured to receive the enable signal and the original sampling clock signal and output the second sampling clock signal, the phase of the second sampling clock signal being inverse to the phase of the original sampling clock signal while the enable signal has the first level value, and the second sampling clock signal being a logic high level signal while the enable signal has the second level value; and a second comparison circuit having the third node and the fourth node, configured to receive the data signal and the second reference signal, perform the second comparison in response to the second sampling clock signal while the enable signal has the first level value, make a connection path between the third node and a ground terminal conductive while the enable signal has the second level value, and make a connection path between the fourth node and a ground terminal conductive.

In some embodiments, the first comparison circuit includes a first current source connected between a power supply node and a fifth node and configured to supply a current to the fifth node in response to the first sampling clock signal; a first comparison unit connected to the first node, the second node, and the fifth node and configured to receive the data signal and the first reference signal, perform the first comparison when the first current source supplies a current to the fifth node, and output the first signal and the second signal; and a first reset unit connected to the first node and the second node and configured to reset the first node and the second node in response to the first sampling clock signal. The second comparison circuit includes a second current source connected between a power supply node and a sixth node and configured to supply a current to the sixth node in response to the second sampling clock signal, a second comparison unit connected to the third node, the fourth node, and the sixth node and configured to receive the data signal and the second reference signal, perform the second comparison when the second current source supplies a current to the sixth node, and output the third signal and the fourth signal, and a second reset unit connected between the third node and the fourth node and configured to reset the third node and the fourth node in response to the second sampling clock signal.

In some embodiments, the first current source comprises a first PMOS field effect transistor connected between the power supply node and the fifth node, the gate of which receives the first sampling clock signal, and the second current source comprises a second PMOS field effect transistor connected between the power supply node and the sixth node, the gate of which receives the second sampling clock signal.

In some embodiments, the first comparison unit includes a third PMOS field effect transistor connected between the first node and the fifth node, the gate of which receives the data signal, and a fourth PMOS field effect transistor connected between the second node and the fifth node, the gate of which receives the first reference signal, and the second comparison unit includes a fifth PMOS field effect transistor connected between the third node and the sixth node, the gate of which receives the data signal, and a sixth PMOS field effect transistor connected between the fourth node and the sixth node, the gate of which receives the second reference signal.

In some embodiments, the first reset unit includes a ninth NMOS field effect transistor connected between the first node and a ground terminal, the gate of which receives the first sampling clock signal, and a tenth NMOS field effect transistor connected between the second node and the ground terminal, the gate of which receives the first sampling clock signal, and the second reset unit includes an eleventh NMOS field effect transistor connected between the third node and a ground terminal, the gate of which receives the second sampling clock signal, and a twelfth NMOS field effect transistor connected between the fourth node and a ground terminal, the gate of which receives the second sampling clock signal.

In some embodiments, the clock generating circuit includes a first NAND gate circuit having one input terminal that receives the original sampling clock signal, another input terminal that is connected to a power supply node, and an output terminal that outputs the first sampling clock signal.

In some embodiments, the clock generation circuit includes a second NAND gate circuit having one input terminal that receives the original sampling clock signal, another input terminal that receives the enable signal, and an output terminal that outputs the second sampling clock signal.

In some embodiments, the second amplification module comprises: a first input unit connected to the seventh node and the eighth node, configured to receive the first signal pair and perform a third comparison, and provide a signal to the seventh node and the eighth node, respectively, as a result of the third comparison; a second input unit connected to the seventh node and the eighth node, configured to receive the second signal pair and perform a fourth comparison, and provide a signal to the seventh node and the eighth node, respectively, as a result of the fourth comparison; and a latch unit connected to the seventh node and the eighth node, configured to amplify and latch the signal at the seventh node and the signal at the eighth node, and output the first output signal and the second output signal via the first output node and the second output node, respectively.

In some embodiments, the first input unit includes a thirteenth NMOS field effect transistor having a drain electrode connected to the seventh node, a source electrode connected to a ground terminal, and a gate receiving the first signal; a fourteenth NMOS field effect transistor having a drain electrode connected to the eighth node, a source electrode connected to a ground terminal, and a gate receiving the second signal; and the second input unit includes a fifteenth NMOS field effect transistor having a drain electrode connected to the seventh node, a source electrode connected to a ground terminal, and a gate receiving the third signal; and a sixteenth NMOS field effect transistor having a drain electrode connected to the eighth node, a source electrode connected to a ground terminal, and a gate receiving the fourth signal.

In some embodiments, the latch unit includes a 17th NMOS field effect transistor and a 7th PMOS field effect transistor, in which the gate of the 17th NMOS field effect transistor and the gate of the 7th PMOS field effect transistor are both connected to the second output node, the source electrode of the 17th NMOS field effect transistor is connected to the 7th node, the drain electrode of the 17th NMOS field effect transistor and the drain electrode of the 7th PMOS field effect transistor are both connected to the first output node, and the source electrode of the 7th PMOS field effect transistor is connected to a power supply node; and an 18th NMOS field effect transistor and an 8th PMOS field effect transistor, in which the gate of the 18th NMOS field effect transistor and the gate of the 8th PMOS field effect transistor are both connected to the first output node, the source electrode of the 18th NMOS field effect transistor is connected to the 8th node, the drain electrode of the 18th NMOS field effect transistor and the drain electrode of the 8th PMOS field effect transistor are both connected to the second output node, and the source electrode of the 8th PMOS field effect transistor is connected to the power supply node.

In some embodiments, the second amplification module further comprises a third reset unit connected between a power supply node and the output terminal of the latch unit and configured to reset the output terminal of the latch unit.

In some embodiments, the third reset unit includes a 93rd PMOS field effect transistor connected between the first output node and a power supply node, the gate of which receives the original sampling clock signal, and a 14th PMOS field effect transistor connected between the second output node and the power supply node, the gate of which receives the original sampling clock signal.

In some embodiments, the data receiving circuit further comprises a first inversion circuit configured to receive the first feedback signal and output the first complementary feedback signal, and a second inversion circuit configured to receive the second feedback signal and output the second complementary feedback signal.

In some embodiments, the first inversion circuit comprises a first inverter and the second inversion circuit comprises a second inverter.

In some embodiments, the first inverter circuit includes a third NAND gate, two input terminals of which respectively receive the first feedback signal and the enable signal, and an output terminal of which outputs the first complementary feedback signal, and the second inverter circuit includes a fourth NAND gate, two input terminals of which respectively receive the second feedback signal and the enable signal, and an output terminal of which outputs the second complementary feedback signal.

According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a data receiving system, comprising a plurality of data transmission circuits connected in cascade, each of which comprises a data receiving circuit as described in any one of the above and a latch circuit connected to the data receiving circuit, and the output signal of the data transmission circuit of the previous stage is used as the feedback signal of the data transmission circuit of the subsequent stage, and the output signal of the data transmission circuit of the final stage is used as the feedback signal of the data transmission circuit of the first stage.

In some embodiments, the data receiving circuit receives data in response to a sampling clock signal, and the data receiving system includes four of the data transmission circuits cascaded together, and the phase difference between the sampling clock signals of the data receiving circuits of adjacent stages is 90°.

In some embodiments, the first output signal and the second output signal output by the second amplification module of the data receiving circuit in the previous stage are used as the feedback signal of the data receiving circuit in the subsequent stage, or the signal output by the latch circuit in the previous stage is used as the feedback signal of the data receiving circuit in the subsequent stage.

According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a storage device, comprising a plurality of data ports and a plurality of data receiving systems according to any one of the above items, each corresponding to one of the data ports.

The technical solution according to the embodiments of the present disclosure has at least the following advantages:

The first amplification module receives a data signal, a first reference signal, and a second reference signal, and further controls the potentials of the first node and the second node by receiving an enable signal and a first complementary feedback signal using the first NMOS field effect transistor and the second NMOS field effect transistor, and controls the potentials of the third node and the fourth node by receiving an enable signal and a second complementary feedback signal using the third NMOS field effect transistor and the fourth NMOS field effect transistor. Specifically, when the enable signal is in the first level value period, one of the first NMOS field effect transistor and the second NMOS field effect transistor and one of the third NMOS field effect transistor and the fourth NMOS field effect transistor are conductive based on the enable signal, the other of the first NMOS field effect transistor and the second NMOS field effect transistor is conductive or cut off in response to the first complementary feedback signal, and the other of the third NMOS field effect transistor and the fourth NMOS field effect transistor is conductive or cut off in response to the second complementary feedback signal. Since the first feedback signal is inverse to the level of the second feedback signal, the first complementary feedback signal is inverse to the level of the first feedback signal, and the second complementary feedback signal is inverse to the level of the second feedback signal, so that when the enable signal is in the first level value period, one of the other of the first NMOS field effect transistor and the second NMOS field effect transistor and the other of the third NMOS field effect transistor and the fourth NMOS field effect transistor is turned on and the other is cut off, so that the first amplification module can selectively perform the first comparison or the second comparison in response to the sampling clock signal, thereby enabling one of the output first signal pair and the second signal pair and disabling the other, reducing the influence of inter-symbol interference of the received data signal on the data receiving circuit, and only one of the circuit for performing the first comparison and the circuit for performing the second comparison in the first amplification module may be in an operating state, and the other may be in an inoperating state, contributing to reducing the power consumption of the data receiving circuit. Furthermore, since the conduction resistance of the NMOS field effect transistor is much smaller than the conduction resistance of the PMOS field effect transistor under the same conditions, the first NMOS field effect transistor, the second NMOS field effect transistor, the third NMOS field effect transistor, and the fourth NMOS field effect transistor in the first amplification module are turned on or off faster in response to the signal received at their gates than the PMOS field effect transistor, making it easier for the first amplification module to perform only one of the first comparison and the second comparison at the same time, improving the processing efficiency and processing speed of the data signal by the first amplification module. In this way, it contributes to improving the reception performance of the data receiving circuit and improving the processing speed of the data signal.

In addition, when the enable signal is in the second level value period, the first amplification module performs only the first comparison in response to the sampling clock signal and fixes and outputs the valid first signal pair, and at this time, the circuit for outputting the second signal pair in the first amplification module may be in an inoperative state, which contributes to further reducing the power consumption of the data receiving circuit.

One or more embodiments are illustratively described by pictures in corresponding drawings, and these illustrative descriptions are not intended to limit the embodiments, and elements with the same reference numerals in the drawings indicate similar elements, and unless otherwise stated, the figures in the drawings are not limited to the scale, and in order to more clearly describe the embodiments of the present disclosure or the technical solutions of the prior art, the drawings that need to be used in the embodiments are briefly described below, of course, the drawings in the following description are merely some embodiments of the present disclosure, and a person skilled in the art can further obtain other drawings based on these drawings without requiring creative efforts.

FIG. 1 is a functional block diagram of a data receiving circuit according to an embodiment of the present disclosure. FIG. 2 is another functional block diagram of a data receiving circuit according to an embodiment of the present disclosure. FIG. 3 is a functional block diagram of a first amplification module of a data receiving circuit according to an embodiment of the present disclosure. FIG. 4 is another functional block diagram of a data receiving circuit according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram of two circuit structures of a first amplifying module, a first inverter circuit, and a second inverter circuit of a data receiving circuit according to an embodiment of the present disclosure. FIG. 6 is a schematic diagram of two circuit structures of a first amplifying module, a first inverter circuit, and a second inverter circuit of a data receiving circuit according to an embodiment of the present disclosure. FIG. 7 is a schematic diagram of a circuit structure of a second amplifying module of a data receiving circuit according to an embodiment of the present disclosure. FIG. 8 is another schematic diagram of the circuit structure of the second amplifying module, the first inverting circuit and the second inverting circuit of the data receiving circuit according to an embodiment of the present disclosure. FIG. 9 is a functional block diagram of a data receiving system according to another embodiment of the present disclosure.

Embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device, in which the data receiving circuit can achieve further control over the first amplification module using an enable signal, a first feedback signal, and a second feedback signal, thereby selecting whether the data receiving circuit takes into account the effect of inter-symbol interference in the received data on the data receiving circuit. For example, when it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit, that is, when the enable signal is in the first level value period, the first amplification module responds to the sampling clock signal, and uses the first NMOS field effect transistor, the second NMOS field effect transistor, the third NMOS field effect transistor, and the fourth NMOS field effect transistor to selectively perform one of the first comparison and the second comparison, to enable one of the output first signal pair and the second signal pair, disable the other, and increase the difference in the signal level value of the effective signal pair, thereby ensuring that the second amplification module receives a pair of differential signals with a larger difference in signal level value, and further uses the low conductive resistance of the NMOS field effect transistor to prevent the first amplification module from simultaneously performing the first comparison and the second comparison, and improve the processing effect and processing speed of the data signal by the first amplification module; when it is not necessary to consider the influence of inter-symbol interference on the data receiving circuit, the enable signal is in the second level value period, and the first amplification module performs only the first comparison in response to the sampling clock signal, fixes and outputs the effective first signal pair, and reduces the power consumption of the data receiving circuit.

The following describes in detail each embodiment of the present disclosure with reference to the drawings. However, as will be appreciated by those skilled in the art, each embodiment of the present disclosure provides many technical details to allow the reader to better understand the embodiment of the present disclosure. However, the technical solutions claimed in the embodiments of the present disclosure can be realized without these technical details and various changes and modifications based on the following embodiments.

An embodiment of the present disclosure provides a data receiving circuit, and the data receiving circuit according to the embodiment of the present disclosure will be described in detail below with reference to the drawings. FIG. 1 is a functional block diagram of a data receiving circuit according to an embodiment of the present disclosure, FIG. 2 is another functional block diagram of a data receiving circuit according to an embodiment of the present disclosure, FIG. 3 is a functional block diagram of a first amplification module of a data receiving circuit according to an embodiment of the present disclosure, FIG. 4 is another functional block diagram of a data receiving circuit according to an embodiment of the present disclosure, FIG. 5 and FIG. 6 are two types of circuit structure schematic diagrams of a first amplification module, a first inversion circuit, and a second inversion circuit of a data receiving circuit according to an embodiment of the present disclosure, FIG. 7 is a circuit structure schematic diagram of a second amplification module of a data receiving circuit according to an embodiment of the present disclosure, and FIG. 8 is another circuit structure schematic diagram of a second amplification module, a first inversion circuit, and a second inversion circuit of a data receiving circuit according to an embodiment of the present disclosure.

Referring to FIG. 1, the data receiving circuit 100 may include a first amplification module 101, which receives an enable signal EnDfe, a first feedback signal fbp, a second feedback signal fbn, a data signal DQ, a first reference signal VR+ and a second reference signal VR-, and responds to a sampling clock signal clkN while the enable signal EnDfe has a first level value, and selects the data signal DQ and the first reference signal VR+ based on the first feedback signal fbp to perform a first comparison and output a first signal pair as a result of the first comparison, or In response to the ring clock signal clkN, the data signal DQ and the second reference signal VR- are selected based on the second feedback signal fbn to perform a second comparison and output a second signal pair as a result of the second comparison, and while the enable signal EnDfe has a second level value, a first comparison is performed in response to the sampling clock signal clkN to output a first signal pair, the first feedback signal fbp is inverse to the level of the second feedback signal fbn, the first signal pair includes the first signal Sn+ and the second signal Sp+, and the second signal pair includes the third signal Sn- and the fourth signal Sp-.

Continuing to refer to FIG. 1, the first amplification module 101 includes an amplification unit 131, a first NMOS field effect transistor MN1, a second NMOS field effect transistor MN2, a third NMOS field effect transistor MN3, and a fourth NMOS field effect transistor MN4, the amplification unit 131 having a first node net1, a second node net2, a third node net3, and a fourth node net4, the first node net1 outputs a first signal Sn+; The second node net2 outputs a second signal Sp+, the third node net3 outputs a third signal Sn−, and the fourth node net4 outputs a fourth signal Sp−, and is configured to receive a data signal DQ, a first reference signal VR+, and a second reference signal VR−. One end of a first NMOS field effect transistor MN1 is connected to the first node net1, the other end of the first NMOS field effect transistor MN1 is connected to one end of a second NMOS field effect transistor MN2, The other end of the OS field effect transistor MN2 is connected to the second node net2, one gate of the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 receives a first complementary feedback signal fbpN and the other gate receives an enable signal EnDfe, the first complementary feedback signal fbpN is inverse to the level of the first feedback signal fbp, one end of the third NMOS field effect transistor MN3 is connected to the third node net3, the other end of the third NMOS field effect transistor MN3 is connected to one end of the fourth NMOS field effect transistor MN4, the other end of the fourth NMOS field effect transistor MN4 is connected to the fourth node net4, one gate of the third node net3 and the fourth NMOS field effect transistor MN4 receives a second complementary feedback signal fbnN and the other gate receives the enable signal EnDfe, the second complementary feedback signal fbnN is inverse to the level of the second feedback signal fbn. The second amplification module 102 is configured to receive the output signal of the first amplification module 101 as an input signal pair, perform an amplification process on the voltage difference of the input signal pair, and output a first output signal Vout and a second output signal VoutN as the result of the amplification process.

The first level value period of the enable signal EnDfe refers to the first amplification module 101 determining that the enable signal EnDfe is in the level value range of logic level 1, i.e., high level, and the second level value period of the enable signal EnDfe refers to the first amplification module 101 determining that the enable signal EnDfe is in the level value range of logic level 0, i.e., low level. In addition, the first feedback signal fbp being inverse to the level of the second feedback signal fbn refers to the fact that when one of the first feedback signal fbp and the second feedback signal fbn is in a high level, the other is in a low level. The first complementary feedback signal fbpN being inverse to the level of the first feedback signal fbp refers to the fact that when one of the first complementary feedback signal fbpN and the first feedback signal fbp is in a high level, the other is in a low level. The second complementary feedback signal fbnN being inverse to the level of the second feedback signal fbn means that when one of the second complementary feedback signal fbnN and the second feedback signal fbn is at a high level, the other is at a low level. In this way, the first complementary feedback signal fbpN is inverse to the level of the second complementary feedback signal fbnN.

In this way, it is necessary to reduce the effect of inter-symbol interference on the data receiving circuit 100, and when the enable signal EnDfe is in the first level value period, i.e., when the enable signal EnDfe is at logic level 1, one of the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 and one of the third NMOS field effect transistor MN3 and the fourth NMOS field effect transistor MN4 are made conductive based on the enable signal EnDfe, the other of the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 is made conductive or cut off in response to the first complementary feedback signal fbpN, and the other of the third NMOS field effect transistor MN3 and the fourth NMOS field effect transistor MN4 is made conductive or cut off in response to the second complementary feedback signal fbnN. When one of the first complementary feedback signal fbpN and the second complementary feedback signal fbnN is at a high level, the other is at a low level, so that one of the other of the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 and the other of the third NMOS field effect transistor MN3 and the fourth NMOS field effect transistor MN4 is made conductive and the other is cut off, thereby enabling the first amplification module 101 to selectively perform the first comparison or the second comparison in response to the sampling clock signal clkN, thereby enabling one of the output first signal pair and second signal pair and disabling the other, thereby reducing the influence of inter-symbol interference of the received data signal on the data receiving circuit 100, and only one of the circuit for performing the first comparison and the circuit for performing the second comparison in the first amplification module 101 may be in an operating state and the other in an inoperable state, which contributes to reducing the power consumption of the data receiving circuit 100. At this time, based on the enable signal EnDfe, the first feedback signal fbp, and the second feedback signal fbn, the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 conduct the connection path between the first node net1 and the second node net2, or the third NMOS field effect transistor MN3 and the fourth NMOS field effect transistor MN4 conduct the connection path between the third node net3 and the fourth node net4, and the two nodes of the conduction path cannot output a valid signal pair, which causes the amplifier unit 131 to selectively perform the first comparison or the second comparison.

In addition, since the conduction resistance of an NMOS field effect transistor is much smaller than the conduction resistance of a PMOS field effect transistor under the same conditions, the first NMOS field effect transistor MN1, the second NMOS field effect transistor MN2, the third NMOS field effect transistor MN3, and the fourth NMOS field effect transistor MN4 in the first amplification module 101 are turned on or off faster in response to the signals received at their gates than the PMOS field effect transistors, making it easier for the first amplification module 101 to perform only one of the first comparison and the second comparison at the same time, improving the processing efficiency and processing speed of the data signal DQ by the first amplification module 101. In this way, it contributes to improving the reception performance of the data receiving circuit 100 and improving the processing speed of the data signal DQ.

As can be seen, when the enable signal EnDfe is in the first level value period, the first amplification module 101 selectively performs the first comparison or the second comparison, causing the first amplification module 101 to output a valid first signal pair or a valid second signal pair, and the other is an invalid signal pair at this time. Note that the first signal pair being valid refers to the level value of the first signal Sn+ and the level value of the second signal Sp+ in the first signal pair having a relatively large difference, and the second signal pair being valid refers to the level value of the third signal Sn- and the level value of the fourth signal Sp- in the second signal pair having a relatively large difference. In this way, the second amplification module 102 ensures that what is received is a pair of differential signals with a relatively large difference in signal level values, and reduces the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

In addition, there is no need to consider the effect of inter-symbol interference on the data receiving circuit 100. When the enable signal EnDfe is in the second level value period, that is, when the enable signal EnDfe is at logic level 0, one of the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 is cut off based on the enable signal EnDfe at this time, cutting off the connection path between the first node net1 and the second node net2, and one of the third node net3 and the fourth NMOS field effect transistor MN4 is cut off, cutting off the connection path between the third node net3 and the fourth node net4, and the amplification unit 131 performs only the first comparison under its own control. In addition, the first NMOS field effect transistor MN1, the second NMOS field effect transistor MN2, the third NMOS field effect transistor MN3, and the fourth NMOS field effect transistor MN4 are all integrated into the first amplification module 101, which contributes to further reducing the layout area of the entire data receiving circuit 100.

Note that a situation in which inter-symbol interference must be taken into consideration is generally a situation in which the data signal DQ received by the data receiving circuit 100 is high-speed data, i.e., a situation in which the data transmission speed is fast, and a situation in which inter-symbol interference does not need to be taken into consideration is a situation in which the data signal DQ received by the data receiving circuit 100 is generally low-speed data, i.e., a situation in which the data transmission speed is slow.

In some embodiments, when the level value of the first reference signal VR+ and the level value of the second reference signal VR- are different, for the data signal DQ with different level values, it can be satisfied that the difference in the level value of one of the data signal DQ and the first reference signal VR+ or the second reference signal VR- is greater, and when the first amplification module 101 can perform the first comparison and the second comparison simultaneously, the first amplification module 101 can output a set of signal pairs with a greater difference in level values. In one embodiment of the present disclosure, when an inter-symbol interference phenomenon occurs in the data signal DQ received by the data receiving circuit 100, the first amplification module 101 can selectively perform the first comparison or the second comparison based on the first feedback signal fbp and the second feedback signal fbn, and one of the output first signal pair and the second signal pair is valid and the other is invalid, and the valid set of signal pairs refers to a set of signal pairs with a greater difference in level values when the first comparison and the second comparison can be performed simultaneously, reducing the effect of the inter-symbol interference of the received data signal DQ on the data receiving circuit 100. As can be seen, when the enable signal EnDfe is in the first level value period, the first amplification module 101 can selectively perform a comparison of the data signal DQ with a better processing based on the received first feedback signal fbp and second feedback signal fbn, i.e., selectively perform the first comparison or the second comparison, thereby obtaining a better set of signal pairs. In this way, when the enable signal EnDfe is in the first level value period, the first amplification module 101 performs only one of the first comparison and the second comparison with a better processing, and the other is in an inactive state, which contributes to reducing the power consumption of the data receiving circuit.

In addition, when the enable signal EnDfe is in the second level value period, regardless of how the level values of the first feedback signal fbp and the second feedback signal fbn obtained based on the previously received data change, the first amplification module 101 also performs a fixed first comparison based on the enable signal EnDfe at this time, that is, the first amplification module 101 outputs a fixed valid first signal pair at this time, and at this time, the first amplification module 101 does not perform a second comparison, that is, the circuit for outputting the second signal pair in the first amplification module 101 may be in a non-operating state, which contributes to further reducing the power consumption of the data receiving circuit.

The following provides a detailed explanation of how the data receiving circuit 100 reduces the effect of inter-symbol interference in the received data signal DQ on the data receiving circuit 100, using a specific example.

In some embodiments, when the level value of the first reference signal VR+ is higher than the level value of the second reference signal VR-, and the data signal DQ is at a low level and an inter-symbol interference phenomenon occurs in the data signal DQ received by the data receiving circuit 100, the enable signal EnDfe is in a first level value period, and the first amplification module 101 performs a first comparison based on the enable signal EnDfe, the first feedback signal fbp and the second feedback signal fbn at this time, that is, outputs a valid first signal pair. At this time, the data signal DQ and the first reference signal VR+ and The difference in level values is greater than the difference in level values between the data signal DQ and the second reference signal VR-, and thus performing the first comparison at this time generates an output signal pair with a greater difference in level values than performing the second comparison. Therefore, the second amplification module 102 receiving a valid first signal pair contributes to improving the accuracy of the output first output signal Vout and second output signal VoutN, thereby contributing to reducing the effect of inter-symbol interference of the received data signal DQ on the data receiving circuit 100.

In addition, when the data signal DQ is at a high level and an intersymbol interference phenomenon occurs in the data signal DQ received by the data receiving circuit 100, the enable signal EnDfe is in the first level value period, and the first amplification module 101 performs a second comparison based on the enable signal EnDfe, the first feedback signal fbp, and the second feedback signal fbn at this time, that is, outputs a valid second signal pair. At this time, the difference in level value between the data signal DQ and the first reference signal VR+ is smaller than the difference in level value between the data signal DQ and the second reference signal VR-. Therefore, performing the second comparison at this time generates an output signal pair with a larger difference in level value compared to performing the first comparison. Therefore, the second amplification module 102 receiving a valid second signal pair contributes to improving the accuracy of the output first output signal Vout and second output signal VoutN, thereby contributing to reducing the impact of intersymbol interference of the received data signal DQ on the data receiving circuit 100.

As can be understood, in practical applications, the level value of the first reference signal VR+ may be lower than the level value of the second reference signal VR-.

In FIG. 1, the gate of the first NMOS field effect transistor MN1 and the gate of the third NMOS field effect transistor MN3 receive the enable signal EnDfe, the gate of the second NMOS field effect transistor MN2 receives the first complementary feedback signal fbpN, and the gate of the fourth NMOS field effect transistor MN4 receives the second complementary feedback signal fbnN. In actual applications, the gate of the first NMOS field effect transistor MN1 may receive the first complementary feedback signal fbpN, the gate of the third NMOS field effect transistor MN3 may receive the second complementary feedback signal fbnN, and the gates of the second NMOS field effect transistor MN2 and the fourth NMOS field effect transistor MN4 may receive the enable signal EnDfe.

In some embodiments, referring to FIG. 2, the first amplification module 101 includes a first NMOS field effect transistor MN1 and a second NMOS field effect transistor MN2, and may further include a fifth NMOS field effect transistor MN5 and a sixth NMOS field effect transistor MN6, where one end of the fifth NMOS field effect transistor MN5 is connected to the first node net1, the other end of the fifth NMOS field effect transistor MN5 is connected to one end of the sixth NMOS field effect transistor MN6, and the other end of the sixth NMOS field effect transistor MN6 is connected to the second node net2, and one gate of the fifth NMOS field effect transistor MN5 and the sixth NMOS field effect transistor MN6 receives the first complementary feedback signal fbpN, and the other gate receives the enable signal EnDfe.

As can be seen, the branch circuit consisting of the fifth NMOS field effect transistor MN5 and the sixth NMOS field effect transistor MN6 is connected in parallel to the branch circuit consisting of the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2, and thus, when the connection path between the first node net1 and the second node net2 is conductive, it contributes to reducing the total path resistance of the connection path between the first node net1 and the second node net2, and improves the conduction speed of the connection path between the first node net1 and the second node net2 in response to the enable signal EnDfe and the first complementary feedback signal fbpN.

In some embodiments, the ratio of the width to the length of the channel of the first NMOS field effect transistor MN1 or the second NMOS field effect transistor MN2 that receives the enable signal EnDfe is greater than the ratio of the width to the length of the other channel, and the ratio of the width to the length of the channel of the fifth NMOS field effect transistor MN5 or the sixth NMOS field effect transistor MN6 that receives the enable signal EnDfe is greater than the ratio of the width to the length of the other channel.

As will be understood, when the level value of the signal received by the gate of an NMOS field effect transistor changes frequently, the larger the channel width of the NMOS field effect transistor, the larger the capacitance of the gate, and conversely, the lower the sensitivity of the gate to changes in the level value of the signal sensed by the gate; therefore, in the case of an NMOS field effect transistor whose gate receives a level value that changes frequently, reducing the channel width of the NMOS field effect transistor contributes to reducing the effect of the gate capacitance on the NMOS field effect transistor. In this way, when the enable signal EnDfe is in the first level value period, the level value of the enable signal EnDfe is fixed, and in the case of the first NMOS field effect transistor MN1, the second NMOS field effect transistor MN2, the fifth NMOS field effect transistor MN5, and the sixth NMOS field effect transistor MN6, the gate capacitance of the two NMOS field effect transistors that receive the enable signal EnDfe does not have a large effect on the data receiving circuit 100, and at this time, the level value of the first complementary feedback signal fbpN changes much more frequently, which further reduces the channel width of the two NMOS field effect transistors that receive the first complementary feedback signal fbpN, thereby contributing to reducing the effect of the gate capacitance on the NMOS field effect transistors.

In addition, the larger the ratio of the channel width to the channel length of the NMOS field effect transistor, the smaller the on-resistance and the faster the switching speed of the on- or off-state. The channel width of the two NMOS field effect transistors receiving the first complementary feedback signal fbpN is ensured to be relatively small, and the channel width of the two NMOS field effect transistors receiving the enable signal EnDfe is made relatively large relative to the channel length, which contributes to reducing the total on-resistance of the connection path between the first node net1 and the second node net2. Therefore, by considering the two elements of the gate capacitance and on-resistance of the NMOS field effect transistors together, when the enable signal EnDfe is in the first level value period, the two NMOS field effect transistors receiving the first complementary feedback signal fbpN can sensitively detect the change in the level value of the first complementary feedback signal fbpN, and contributes to improving the on- or off-state speed of the connection path between the first node net1 and the second node net2.

2, in one example, the gate of the first NMOS field effect transistor MN1 receives the enable signal EnDfe and the gate of the second NMOS field effect transistor MN2 receives the first complementary feedback signal fbpN. The channel width of the first NMOS field effect transistor MN1 is greater than the channel width of the second NMOS field effect transistor MN2, thus contributing to realizing that the ratio of the width to the channel length of the first NMOS field effect transistor MN1 receiving the enable signal EnDfe is greater than the ratio of the width to the channel length of the second NMOS field effect transistor MN2 receiving the first complementary feedback signal fbpN. Furthermore, the gate of the fifth NMOS field effect transistor MN5 receives the first complementary feedback signal fbpN, the gate of the sixth NMOS field effect transistor MN6 receives the enable signal EnDfe, and the channel width of the fifth NMOS field effect transistor MN5 is smaller than the channel width of the sixth NMOS field effect transistor MN6, thus contributing to realizing that the ratio of the width to the channel length of the sixth NMOS field effect transistor MN6 receiving the enable signal EnDfe is greater than the ratio of the width to the channel length of the fifth NMOS field effect transistor MN5 receiving the first complementary feedback signal fbpN.

In FIG. 2, the gate of the first NMOS field effect transistor MN1 and the gate of the sixth NMOS field effect transistor MN6 receive the enable signal EnDfe, and the gate of the second NMOS field effect transistor MN2 and the gate of the fifth NMOS field effect transistor MN5 receive the first complementary feedback signal fbpN. In actual applications, the gate of the first NMOS field effect transistor MN1 and the gate of the sixth NMOS field effect transistor MN6 may receive the first complementary feedback signal fbpN, and the gate of the second NMOS field effect transistor MN2 and the gate of the fifth NMOS field effect transistor MN5 may receive the enable signal EnDfe.

In some embodiments, the channel width of the fifth NMOS field effect transistor MN5 is equal to the channel width of the second NMOS field effect transistor MN2, the channel width of the sixth NMOS field effect transistor MN6 is equal to the channel width of the first NMOS field effect transistor MN1, and the channel lengths of the first NMOS field effect transistor MN1, the second NMOS field effect transistor MN2, the fifth NMOS field effect transistor MN5, and the sixth NMOS field effect transistor MN6 are all equal. In this way, the total equivalent capacitance of the first NMOS field effect transistor MN1 and the fifth NMOS field effect transistor MN5 at the first node net1 is contributed to be no different from the total equivalent capacitance of the second NMOS field effect transistor MN2 and the sixth NMOS field effect transistor MN6 at the second node net2, thereby matching the load at the first node net1 and the load at the second node net2.

In some embodiments, referring to FIG. 2, the first amplification module 101 includes a third NMOS field effect transistor MN3 and a fourth NMOS field effect transistor MN4, and may further include a seventh NMOS field effect transistor MN7 and an eighth NMOS field effect transistor MN8, where one end of the seventh NMOS field effect transistor MN7 is connected to the third node net3, the other end of the seventh NMOS field effect transistor MN7 is connected to one end of the eighth NMOS field effect transistor MN8, and the other end of the eighth NMOS field effect transistor MN8 is connected to the fourth node net4, and one of the gates of the seventh NMOS field effect transistor MN7 and the eighth NMOS field effect transistor MN8 receives the second complementary feedback signal fbnN, and the other gate receives the enable signal EnDfe.

As can be seen, the branch circuit consisting of the seventh NMOS field effect transistor MN7 and the eighth NMOS field effect transistor MN8 is connected in parallel to the branch circuit consisting of the third NMOS field effect transistor MN3 and the fourth NMOS field effect transistor MN4, and thus, when the connection path between the third node net3 and the fourth node net4 is made conductive, this contributes to reducing the total path resistance of the connection path between the third node net3 and the fourth node net4, and improves the conduction speed of the connection path between the third node net3 and the fourth node net4 in response to the enable signal EnDfe and the second complementary feedback signal fbnN.

In some embodiments, the ratio of the width to the length of the channel of the third NMOS field effect transistor MN3 or the fourth NMOS field effect transistor MN4 that receives the enable signal EnDfe is greater than the ratio of the width to the length of the other channel, and the ratio of the width to the length of the channel of the seventh NMOS field effect transistor MN7 or the eighth NMOS field effect transistor MN8 that receives the enable signal EnDfe is greater than the ratio of the width to the length of the other channel.

As can be seen from the above explanation, when the level value of the signal received by the gate of an NMOS field effect transistor changes frequently, the larger the channel width of the NMOS field effect transistor, the larger the capacitance of the gate, and conversely, the sensitivity of the gate to changes in the level value of the signal sensed by the gate decreases. Therefore, in the case of an NMOS field effect transistor whose gate receives a level value that changes frequently, reducing the channel width of the NMOS field effect transistor contributes to reducing the influence of the gate capacitance on the NMOS field effect transistor. In this way, when the enable signal EnDfe is in the first level value period, the level value of the enable signal EnDfe is fixed, and in the case of the third NMOS field effect transistor MN3, the fourth NMOS field effect transistor MN4, the seventh NMOS field effect transistor MN7, and the eighth NMOS field effect transistor MN8, the gate capacitance of the two NMOS field effect transistors that receive the enable signal EnDfe does not have a large effect on the data receiving circuit 100, and at this time, the level value of the second complementary feedback signal fbnN always changes frequently, which further reduces the channel width of the two NMOS field effect transistors that receive the second complementary feedback signal fbnN, thereby contributing to reducing the effect of the gate capacitance on the NMOS field effect transistors.

In addition, the larger the ratio of the channel width to the channel length of the NMOS field effect transistor, the smaller the on-resistance and the faster the switching speed of the on- or off-state. The channel width of the two NMOS field effect transistors receiving the second complementary feedback signal fbnN is ensured to be relatively small, and the channel width of the two NMOS field effect transistors receiving the enable signal EnDfe is made relatively large relative to the channel length, which contributes to reducing the total on-resistance of the connection path between the third node net3 and the fourth node net4. Therefore, by considering the two elements of the gate capacitance and on-resistance of the NMOS field effect transistors together, when the enable signal EnDfe is in the first level value period, the two NMOS field effect transistors receiving the second complementary feedback signal fbnN can sensitively detect the change in the level value of the second complementary feedback signal fbnN, and contributes to improving the on- or off-state speed of the connection path between the third node net3 and the fourth node net4.

As can be understood, the ratio of the width to the length of the channel of the first NMOS field effect transistor MN1 and the second NMOS field effect transistor MN2 that receives the enable signal EnDfe is greater than the ratio of the width to the length of the other channel, the ratio of the width to the length of the channel of the fifth NMOS field effect transistor MN5 and the sixth NMOS field effect transistor MN6 that receives the enable signal EnDfe is greater than the ratio of the width to the length of the other channel, the ratio of the width to the length of the channel of the third NMOS field effect transistor MN3 and the fourth NMOS field effect transistor MN4 that receives the enable signal EnDfe is greater than the ratio of the width to the length of the other channel, and The ratio of the channel width to length of the transistor MN7 and the eighth NMOS field effect transistor MN8 that receives the enable signal EnDfe is greater than the ratio of the channel width to length of the other, thus improving the speed of conduction or interruption of the connection path between the first node net1 and the second node net2, and improving the speed of conduction or interruption of the connection path between the third node net3 and the fourth node net4, thereby contributing to quickly turning on one of the connection paths between the first node net1 and the second node net2 and the connection path between the third node net3 and the fourth node net4 when the other is quickly turned on, thereby preventing the first amplification module 101 from simultaneously performing the first comparison and the second comparison.

In one example, continuing to refer to FIG. 2, the gate of the third NMOS field effect transistor MN3 receives the enable signal EnDfe, and the gate of the fourth NMOS field effect transistor MN4 receives the second complementary feedback signal fbnN, and in practical application, the channel width of the third NMOS field effect transistor MN3 is larger than the channel width of the fourth NMOS field effect transistor MN4, thus contributing to realizing that the ratio of the width to the channel length of the third NMOS field effect transistor MN3 receiving the enable signal EnDfe is larger than the ratio of the width to the channel length of the fourth NMOS field effect transistor MN4 receiving the second complementary feedback signal fbnN. Furthermore, the gate of the seventh NMOS field effect transistor MN7 receives the second complementary feedback signal fbnN, the gate of the eighth NMOS field effect transistor MN8 receives the enable signal EnDfe, and the channel width of the seventh NMOS field effect transistor MN7 is smaller than the channel width of the eighth NMOS field effect transistor MN8, thus contributing to realizing that the ratio of the width to the channel length of the eighth NMOS field effect transistor MN8 that receives the enable signal EnDfe is greater than the ratio of the width to the channel length of the seventh NMOS field effect transistor MN7 that receives the second complementary feedback signal fbnN.

In FIG. 2, the gate of the third NMOS field effect transistor MN3 and the gate of the eighth NMOS field effect transistor MN8 receive the enable signal EnDfe, and the gate of the fourth NMOS field effect transistor MN4 and the gate of the seventh NMOS field effect transistor MN7 receive the second complementary feedback signal fbnN. In actual applications, the gate of the third NMOS field effect transistor MN3 and the gate of the eighth NMOS field effect transistor MN8 may receive the second complementary feedback signal fbnN, and the gate of the fourth NMOS field effect transistor MN4 and the gate of the seventh NMOS field effect transistor MN7 may receive the enable signal EnDfe.

In some embodiments, the channel width of the seventh NMOS field effect transistor MN7 is equal to the channel width of the fourth NMOS field effect transistor MN4, the channel width of the eighth NMOS field effect transistor MN8 is equal to the channel width of the third NMOS field effect transistor MN3, and the channel lengths of the third NMOS field effect transistor MN3, the fourth NMOS field effect transistor MN4, the seventh NMOS field effect transistor MN7, and the eighth NMOS field effect transistor MN8 are all equal. In this way, the total equivalent capacitance of the third NMOS field effect transistor MN3 and the seventh NMOS field effect transistor MN7 at the third node net3 is contributed to be no different from the total equivalent capacitance of the fourth NMOS field effect transistor MN4 and the eighth NMOS field effect transistor MN8 at the fourth node net4, thereby matching the load at the third node net3 and the load at the fourth node net4.

As can be understood, taking FIG. 2 as an example, the ratio of channel length to width of the first NMOS field effect transistor MN1 and the sixth NMOS field effect transistor MN6 that receive the enable signal EnDfe is greater than the ratio of channel length to width of the second NMOS field effect transistor MN2 and the fifth NMOS field effect transistor MN5 that receive the first complementary feedback signal fbpN, and the ratio of channel length to width of the third NMOS field effect transistor MN3 and the eighth NMOS field effect transistor MN8 that receive the enable signal EnDfe is greater than the ratio of channel length to width of the fourth NMOS field effect transistor MN4 and the seventh NMOS field effect transistor MN7 that receive the second complementary feedback signal fbnN. Then, when the enable signal EnDfe is in the first level value period, the first NMOS field effect transistor MN1, the sixth NMOS field effect transistor MN6, the third NMOS field effect transistor MN3 and the eighth NMOS field effect transistor MN8 are all driven based on the enable signal EnDfe. The second NMOS field effect transistor MN2 and the fifth NMOS field effect transistor MN5 can sensitively detect a change in the level value of the first complementary feedback signal fbpN, and the fourth NMOS field effect transistor MN4 and the seventh NMOS field effect transistor MN7 can sensitively detect a change in the level value of the second complementary feedback signal fbnN. Therefore, the second NMOS field effect transistor MN2 and the fifth NMOS field effect transistor MN5 can quickly respond to the first complementary feedback signal fbpN. When the fourth NMOS field effect transistor MN4 and the seventh NMOS field effect transistor MN7 are quickly turned on in response to the second complementary feedback signal fbnN, or when the second NMOS field effect transistor MN2 and the fifth NMOS field effect transistor MN5 are quickly turned off in response to the first complementary feedback signal fbpN, the fourth NMOS field effect transistor MN4 and the seventh NMOS field effect transistor MN7 can be quickly turned on in response to the second complementary feedback signal fbnN. In this way, when the enable signal EnDfe is in the first level value period, it helps ensure that the first amplification module 101 performs only one of the first comparison and the second comparison.

The following explanations will all be based on the schematic example in Figure 2.

3 and 4, in some embodiments, the sampling clock signal clkN includes a first sampling clock signal clkN1 and a second sampling clock signal clkN2, the amplification unit 131 has a first node net1 and a second node net2, and includes a first comparison circuit 111 configured to receive the data signal DQ and the first reference signal VR+ and perform a first comparison in response to the first sampling clock signal clkN1, and an enable signal EnDfe and the original sampling clock signal clk and output a second sampling clock signal clkN2, and the phase of the second sampling clock signal clkN2 is adjusted while the enable signal EnDfe has a first level value. is opposite in phase to the original sampling clock signal clk, and the second sampling clock signal clkN2 is a logic high level signal while the enable signal EnDfe has a second level value; and a second comparison circuit 121 having a third node net3 and a fourth node net4, receiving the data signal DQ and the second reference signal VR-, and configured to perform a second comparison in response to the second sampling clock signal clkN2 while the enable signal EnDfe has a first level value, to make the connection path between the third node net3 and the ground terminal conductive while the enable signal EnDfe has a second level value, and to make the connection path between the fourth node net4 and the ground terminal conductive.

As can be understood, when the enable signal EnDfe is in a first level value period and the second NMOS field effect transistor MN2 and the fifth NMOS field effect transistor MN5 cut off the connection path between the first node net1 and the second node net2 in response to the first complementary feedback signal fbpN, the first comparison circuit 111 can perform a first comparison in response to the first sampling clock signal clkN1, and when the enable signal EnDfe is in a second level value period, the first NMOS field effect transistor MN1 and the sixth NMOS field effect transistor MN6 cut off the connection path between the first node net1 and the second node net2 based on the enable signal EnDfe at this time, and the first comparison circuit 111 can perform a first comparison in response to the first sampling clock signal clkN1. As can be seen from the above, regardless of whether the enable signal EnDfe is in the first level value period or the second level value period, i.e., regardless of whether the effect of inter-symbol interference on the data receiving circuit 100 needs to be considered or not, the first comparison circuit 111 may also perform the first comparison in response to the first sampling clock signal clkN1. However, the second comparison circuit 121 can perform the second comparison in response to the second sampling clock signal clkN2 whose level value changes only when the enable signal EnDfe is in the first level value period and the fourth NMOS field effect transistor MN4 and the seventh NMOS field effect transistor MN7 cut off the connection path between the third node net3 and the fourth node net4 in response to the second complementary feedback signal fbnN. When the enable signal EnDfe is in the second level value period, the second sampling clock signal clkN2 is a logic high level signal, and the second comparison circuit 121 conducts the connection path between the third node net3 and the ground terminal and the connection path between the fourth node net4 and the ground terminal, and the level value of the third signal Sn- output by the third node net3 and the level value of the fourth signal Sp- output by the fourth node net4 are both pulled down to 0, that is, the second comparison circuit 121 does not perform the second comparison and cannot output a valid second signal pair.

In some embodiments, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk, and when the enable signal EnDfe is in the first level value period, the phase of the second sampling clock signal clkN2 is opposite to the phase of the original sampling clock signal clk, so that the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2 at this time, thereby enabling the first comparison circuit 111 at this time to perform a first comparison in response to the first sampling clock signal clkN1, or the second comparison circuit 121 to perform a second comparison in response to the second sampling clock signal clkN2. At the same time, the first NMOS field effect transistor MN1, the second NMOS field effect transistor MN2, the fifth NMOS field effect transistor MN5 and the sixth NMOS field effect transistor MN6 further control the potentials at the first node net1 and the second node net2 according to the enable signal EnDfe, the first complementary feedback signal fbpN and the second complementary feedback signal fbnN, and the third NMOS field effect transistor MN3, the fourth NMOS field effect transistor MN4, the seventh NMOS field effect transistor MN7 and the eighth NMOS field effect transistor MN8 further control the potentials at the third node net1 and the second node net2 according to the enable signal EnDfe, the first complementary feedback signal fbpN and the second complementary feedback signal fbnN. The potentials at the nodes net3 and net4 are further controlled, for example, by making the potential at the first node net1 and the potential at the second node net2 the same, so that the amplification unit 131 does not actually perform the first comparison and is unable to output a valid first signal pair, or by making the potential at the third node net3 and the potential at the fourth node net4 the same, so that the amplification unit 131 does not actually perform the second comparison and is unable to output a valid second signal pair, thus contributing to allowing the amplification unit 131 to selectively perform the first comparison or the second comparison.

In some embodiments, continuing to refer to FIG. 3 and FIG. 4, the first comparison circuit 111 may include a first current source 1111 connected between the power supply node Vcc (see FIG. 5) and the fifth node net5 and configured to supply a current to the fifth node net5 in response to the first sampling clock signal clkN1; a first comparison unit 1112 connected to the first node net1, the second node net2, and the fifth node net5 and configured to receive the data signal DQ and the first reference signal VR+, perform a first comparison when the first current source 1111 supplies a current to the fifth node net5, and output a first signal Sn+ and a second signal Sp+; and a first reset unit 1113 connected to the first node net1 and the second node net2 and configured to reset the first node net1 and the second node net2 in response to the first sampling clock signal clkN1.

The second comparison circuit 121 may include a second current source 1211 connected between the power supply node Vcc and the sixth node net6 and configured to supply a current to the sixth node net6 in response to the second sampling clock signal clkN2, a second comparison unit 1212 connected to the third node net3, the fourth node net4, and the sixth node net6 and configured to receive the data signal DQ and the second reference signal VR-, perform a second comparison when the second current source 1211 supplies a current to the sixth node net6, and output a third signal Sn- and a fourth signal Sp-, and a second reset unit 1213 connected between the third node net3 and the fourth node net4 and configured to reset the third node net3 and the fourth node net4 in response to the second sampling clock signal clkN2.

As can be seen, the first comparison unit 1112 can output the first signal Sn+ and the second signal Sp+ by controlling the difference between the current supplied to the first node net1 and the current supplied to the second node net2 based on the voltage difference between the data signal DQ and the first reference signal VR+, and the second comparison unit 1212 can output the third signal Sn- and the fourth signal Sp- by controlling the difference between the current supplied to the third node net3 and the current supplied to the fourth node net4 based on the voltage difference between the data signal DQ and the second reference signal VR-. In addition, after the data receiving circuit 100 has completed one round of receiving the data signal DQ, the first reference signal VR+, and the second reference signal VR-, and outputting the first output signal Vout and the second output signal VoutN, the first reset unit 1113 can restore the level values at the first node net1 and the second node net2 to their initial values, and the second reset unit 1213 can restore the level values at the third node net3 and the fourth node net4 to their initial values, making it easier for the subsequent data receiving circuit 100 to receive and process data the next time.

In some embodiments, the circuit structure of the first current source 1111 is the same as the circuit structure of the second current source 1211, and the circuit structure of the first comparison unit 1112 is the same as the circuit structure of the second comparison unit 1212. In this way, the first signal pair output by the first comparison circuit 111 is mainly influenced by the first reference signal VR+, or the difference of the second signal pair output by the second comparison circuit 121 is mainly influenced by the second reference signal VR-, which contributes to reducing the influence of inter-symbol interference of the data signal DQ received by the data receiving circuit 100 based on the first reference signal VR+ and the second reference signal VR- on the data receiving circuit 100, thereby further improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102.

In some embodiments, referring to FIG. 5 and FIG. 6, the first current source 1111 may include a first PMOS field effect transistor MP1 connected between the power supply node Vcc and the fifth node net5 and having a gate receiving the first sampling clock signal clkN1, and the second current source 1112 may include a second PMOS field effect transistor MP2 connected between the power supply node Vcc and the sixth node net6 and having a gate receiving the second sampling clock signal clkN2.

Thus, when the first sampling clock signal clkN1 is at a low level, the gate of the first PMOS field effect transistor MP1 receives the first sampling clock signal clkN1 and is turned on, supplying current to the fifth node net5, and putting the first comparison unit 1112 into an operating state, i.e., performing a first comparison on the received data signal DQ and the first reference signal VR+; at the same time, the enable signal EnDfe is at a high level, the first complementary feedback signal fbpN is at a low level, the second NMOS field effect transistor MN2 and the fifth NMOS field effect transistor MN5 are both cut off, and the connection path between the first node net1 and the second node net2 is cut off. When the second sampling clock signal clkN2 is at a low level, the gate of the second PMOS field effect transistor MP2 receives the second sampling clock signal clkN2 and is turned on to supply current to the sixth node net6, making the second comparison unit 1212 in an operating state and performing a second comparison on the received data signal DQ and the second reference signal VR-; at the same time, the enable signal EnDfe is at a high level, the second complementary feedback signal fbnN is at a low level, the fourth NMOS field effect transistor MN4 and the seventh NMOS field effect transistor MN7 are both cut off, and the connection path between the third node net3 and the fourth node net4 is cut off.

In one example, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk, and when it is necessary to reduce the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is in the first level value period, i.e., high level, and the phase of the second sampling clock signal clkN2 is also opposite to the phase of the original sampling clock signal clk, so that at this time, the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2, and the first current source 1111 supplies current to the fifth node net5 to prepare the first comparison unit 121 to perform the first comparison, and the second current source 1211 supplies current to the sixth node net6 to prepare the second comparison unit 122 to perform the second comparison. At this time, when the enable signal EnDfe is at a high level and the first complementary feedback signal fbpN is at a low level, the connection path between the first node net1 and the second node net2 is cut off, and the first comparison unit 121 performs the first comparison; at this time, when the second complementary feedback signal fbnN is at a high level, the connection path between the third node net3 and the fourth node net4 is conductive, and the second comparison unit 122 cannot perform the second comparison; when the first complementary feedback signal fbpN is at a high level, the connection path between the first node net1 and the second node net2 is conductive, and the first comparison unit 121 cannot perform the first comparison; at this time, when the second complementary feedback signal fbnN is at a low level, the connection path between the third node net3 and the fourth node net4 is cut off, and the second comparison unit 122 performs the second comparison.

Also, when there is no need to consider the effect of intersymbol interference on the data receiving circuit 100, the enable signal EnDfe is in the second level value period, i.e., low level, the second sampling clock signal clkN2 is a logic high level signal, the second PMOS field effect transistor MP2 is always cut off, the current in the second comparison unit 1212 is almost zero, thereby reducing the power consumption of the data receiving circuit 100, and the second comparison unit 1212 at this time cannot perform the second comparison and cannot output a valid second signal pair, and at this time, the first sampling clock signal clkN1 is a clock signal, and the first PMOS field effect transistor MP1 can conduct in response to the clock signal, thereby allowing the first comparison unit 1112 to perform the first comparison, thereby outputting a valid first signal pair, and allowing the entire data receiving circuit 100 to operate normally.

In some embodiments, still referring to FIG. 5 and FIG. 6, the first comparison unit 1112 may include a third PMOS field effect transistor MP3 connected between the first node net1 and the fifth node net5, the gate of which receives the data signal DQ, and a fourth PMOS field effect transistor MP4 connected between the second node net2 and the fifth node net5, the gate of which receives the first reference signal VR+, and the second comparison unit 1212 may include a fifth PMOS field effect transistor MP5 connected between the third node net3 and the sixth node net6, the gate of which receives the data signal DQ, and a sixth PMOS field effect transistor MP6 connected between the fourth node net4 and the sixth node net6, the gate of which receives the second reference signal VR-.

In addition, for the first comparison unit 1112, the changes in the level values of the data signal DQ and the first reference signal VR+ are not synchronized, the conduction time of the third PMOS field effect transistor MP3 receiving the data signal DQ is different from the conduction time of the fourth PMOS field effect transistor MP4 receiving the first reference signal VR+, and the conductance of the third PMOS field effect transistor MP3 is different from the conductance of the fourth PMOS field effect transistor MP4 at the same time. As can be seen, the conductance of the third PMOS field effect transistor MP3 is different from the conductance of the fourth PMOS field effect transistor MP4, and the current shunting capabilities of the third PMOS field effect transistor MP3 and the fourth PMOS field effect transistor MP4 at the fifth node net5 are also different, so that the voltage at the first node net1 is different from the voltage at the second node net2, which contributes to outputting a first signal pair with a relatively large difference in the signal level values of the first signal Sn+ and the second signal Sp+.

For the second comparison unit 1212, the changes in the level values of the data signal DQ and the second reference signal VR- are not synchronized, the conduction time of the fifth PMOS field effect transistor MP5 receiving the data signal DQ is different from the conduction time of the sixth PMOS field effect transistor MP6 receiving the second reference signal VR-, and at the same time, the conduction degree of the fifth PMOS field effect transistor MP5 is different from the conduction degree of the sixth PMOS field effect transistor MP6. As can be seen, the conduction degree of the fifth PMOS field effect transistor MP5 is different from the conduction degree of the sixth PMOS field effect transistor MP6, and the current shunting ability of the fifth PMOS field effect transistor MP5 and the sixth PMOS field effect transistor MP6 at the sixth node net6 is also different, so that the voltage at the third node net3 is different from the voltage at the fourth node net4, which contributes to outputting a second signal pair with a relatively large difference in the signal level values of the third signal Sn- and the fourth signal Sp-.

In one example, the first amplification module 101 performs a first comparison, and when the level value of the data signal DQ is lower than the level value of the first reference signal VR+, the conductivity of the third PMOS field effect transistor MP3 is greater than the conductivity of the fourth PMOS field effect transistor MP4, and thus the current at the fifth node net5 flows more through the path in which the third PMOS field effect transistor MP3 is located, and the current at the first node net1 is greater than the current at the second node net2, which in turn causes the level value of the first signal Sn+ output by the first node net1 to be higher and the level value of the second signal Sp+ output by the second node net2 to be lower, and so on. In this example, the first amplification module 101 performs a second comparison, and when the level value of the data signal DQ is lower than the level value of the second reference signal VR-, the conductivity of the fifth PMOS field effect transistor MP5 is greater than the conductivity of the sixth PMOS field effect transistor MP6, and thus the current at the sixth node net6 flows more through the path in which the fifth PMOS field effect transistor MP5 is located, and the current at the third node net3 is greater than the current at the fourth node net4, which further increases the level value of the third signal Sn- output by the third node net3 and decreases the level value of the fourth signal Sp- output by the fourth node net4.

Similarly, when the level value of the data signal DQ is higher than the level value of the first reference signal VR+, the conductivity of the third PMOS field effect transistor MP3 is lower than the conductivity of the fourth PMOS field effect transistor MP4, the level value of the first signal Sn+ output by the first node net1 is low, and the level value of the second signal Sp+ output by the second node net2 is high; when the level value of the data signal DQ is higher than the level value of the second reference signal VR-, the conductivity of the fifth PMOS field effect transistor MP5 is lower than the conductivity of the sixth PMOS field effect transistor MP6, the level value of the third signal Sn- output by the third node net3 is low, and the level value of the fourth signal Sp- output by the fourth node net4 is high.

In some embodiments, continuing to refer to FIG. 5 and FIG. 6, the first reset unit 1113 may include a ninth NMOS field effect transistor MN9 connected between the first node net1 and the ground terminal, the gate of which receives the first sampling clock signal clkN1, and a tenth NMOS field effect transistor MN10 connected between the second node net2 and the ground terminal, the gate of which receives the first sampling clock signal clkN1, and the second reset unit 1213 may include an eleventh NMOS field effect transistor MN11 connected between the third node net3 and the ground terminal, the gate of which receives the second sampling clock signal clkN2, and a twelfth NMOS field effect transistor MN12 connected between the fourth node net4 and the ground terminal, the gate of which receives the second sampling clock signal clkN2.

In one example, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk, and when it is necessary to reduce the effect of inter-symbol interference on the data receiving circuit, the enable signal EnDfe is in the first level value period, and the phase of the second sampling clock signal clkN2 is also opposite to the phase of the original sampling clock signal clk. At this time, the phase of the first sampling clock signal clkN1 is synchronized with the phase of the second sampling clock signal clkN2, and when the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are both at a low level and the first PMOS field effect transistor MP1 and the second PMOS field effect transistor MP2 are both conductive, the ninth NMOS field effect transistor MN9, the tenth NMOS field effect transistor MN10, the eleventh NMOS field effect transistor MN11, the ninth NMOS field effect transistor MN12, the eleventh NMOS field effect transistor MN13, the eleventh NMOS field effect transistor MN14, the eleventh NMOS field effect transistor MN15, the eleventh NMOS field effect transistor MN16, the eleventh NMOS field effect transistor MN17, the eleventh NMOS field effect transistor MN18, the eleventh NMOS field effect transistor MN19, the eleventh NMOS field effect transistor MN20, the eleventh NMOS field effect transistor MN21, the eleventh NMOS field effect transistor MN22, the eleventh NMOS field effect transistor MN23, the eleventh NMOS field effect transistor MN24, the eleventh NMOS field effect transistor MN25, the eleventh NMOS field effect transistor MN26, the eleventh NMOS field effect transistor MN27, the eleventh NMOS field effect transistor MN28, the eleventh NMOS field effect transistor MN29, the eleventh NMOS field effect transistor MN30, the eleventh NMOS field effect At this time, the ninth NMOS field effect transistor MN9 and the tenth NMOS field effect transistor MN10 may be used as a load for the first comparison unit 1112, thereby increasing the amplification gain of the first comparison unit 1112; and the eleventh NMOS field effect transistor MN11 and the twelfth NMOS field effect transistor MN12 may be used as a load for the second comparison unit 1212, thereby increasing the amplification gain of the second comparison unit 1212.

When the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are both at a high level, the first PMOS field effect transistor MP1 and the second PMOS field effect transistor MP2 are both cut off, and no current flows through the first comparison unit 1112 and the second comparison unit 1212. At this time, the ninth NMOS field effect transistor MN9, the tenth NMOS field effect transistor MN10, the eleventh NMOS field effect transistor MN11, and the twelfth NMOS field effect transistor MN12 are all conductive, thereby pulling down the voltage at the first node net1, the voltage at the second node net2, the voltage at the third node net3, and the voltage at the fourth node net4 to reset the first node net1, the second node net2, the third node net3, and the fourth node net4, making it easier for the data receiving circuit 100 to receive and process data the next time.

In addition, when there is no need to consider the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is in the second level value period, the second sampling clock signal clkN2 is a logic high level signal, and the second PMOS field effect transistor MP2 is always cut off; at this time, the eleventh NMOS field effect transistor MN11 and the twelfth NMOS field effect transistor MN12 are both conductive, thereby conducting the connection path between the third node net3 and the ground terminal, and conducting the connection path between the fourth node net4 and the ground terminal, thereby realizing the resetting of the third node net3 and the fourth node net4; at this time, the current in the second comparison unit 1212 is almost zero, which contributes to reducing the power consumption of the data receiving circuit 100. At this time, when the first sampling clock signal clkN1 is at a low level, the first PMOS field effect transistor MP1 is turned on, and the ninth NMOS field effect transistor MN9 and the tenth NMOS field effect transistor MN10 are both turned off, thereby ensuring that the first comparison circuit 111 performs a first comparison and outputs a valid first signal pair, so that the second amplification module 102 can receive the first signal pair in a fixed manner; or when the first sampling clock signal clkN1 is at a high level, the first PMOS field effect transistor MP1 is turned off, and the ninth NMOS field effect transistor MN9 and the tenth NMOS field effect transistor MN10 are both turned on, thereby pulling down the voltage at the first node net1 and the voltage at the second node net2 to reset the first node net1 and the second node net2, and facilitating the data receiving circuit 100 to receive and process data the next time.

In some embodiments, and continuing to refer to Figures 5 and 6, the clock generation circuit 151 may include a first NAND gate circuit 1511 having one input terminal receiving the original sampling clock signal clk, another input terminal connected to the power supply node Vcc, and an output terminal outputting the first sampling clock signal clkN1.

As can be seen, the input terminal connected to the power supply node Vcc of the first NAND gate circuit 1511 receives a high level. At this time, when the original sampling clock signal clk received by the other input terminal of the first NAND gate circuit 1511 is at a high level, the first sampling clock signal clkN1 is at a low level, and when the original sampling clock signal clk received by the other input terminal of the first NAND gate circuit 1511 is at a low level, the first sampling clock signal clkN1 is at a high level. Thus, when it is necessary to reverse the phase of the first sampling clock signal clkN1 to the phase of the original sampling clock signal clk, and thus reduce the influence of inter-symbol interference on the data receiving circuit, the phase of the first sampling clock signal clkN1 can be synchronized with the phase of the second sampling clock signal clkN2, and the first amplification module 101 can selectively perform the first comparison or the second comparison.

In some embodiments, and continuing to refer to Figures 5 and 6, the clock generation circuit 151 may include a second NAND gate circuit 1512 having one input terminal receiving the original sampling clock signal clk, another input terminal receiving the enable signal EnDfe, and an output terminal outputting the second sampling clock signal clkN2.

As can be seen, the phase of the first sampling clock signal clkN1 is opposite to that of the original sampling clock signal clk. When it is necessary to reduce the influence of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at a high level, and when the original sampling clock signal clk is at a high level, the second sampling clock signal clkN2 output by the second NAND gate circuit 1512 is at a low level. At this time, the first sampling clock signal clkN1 is also at a low level, and the first amplification module 101 selectively performs the first comparison or the second comparison, whichever is more excellent in processing, based on the first complementary feedback signal fbpN and the second complementary feedback signal fbnN. The latter second amplification module 102 receives the valid first signal pair or the valid second signal pair, and the other set of signal pairs is invalid. This reduces the effect of inter-symbol interference of the received data signal DQ on the data receiving circuit 100. When the original sampling clock signal clk is at a low level, the second sampling clock signal clkN2 output by the second NAND gate circuit 1512 is at a high level, and the first sampling clock signal clkN1 is also at a high level at this time. Then, the first comparison unit 1112 and the second comparison unit 1212 are both in an inactive state, and the first reset unit 1113 can restore the level values at the first node net1 and the second node net2 to their initial values, and the second reset unit 1213 can restore the level values at the third node net3 and the fourth node net4 to their initial values, which makes it easier for the subsequent data receiving circuit 100 to receive and process data the next time.

When there is no need to consider the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at a low level. At this time, regardless of whether the original sampling clock signal clk is at a high level or a low level, the second sampling clock signal clkN2 output by the second NAND gate circuit 1512 is also at a high level. Therefore, regardless of whether the first sampling clock signal clkN1 is at a high level or a low level, that is, regardless of whether the first comparison unit 1112 performs a first comparison or not, the connection path between the third node net3 and the earth terminal in the second comparison circuit 121 and the connection path between the fourth node net4 and the earth terminal are also conductive, making the current in the second comparison circuit 121 at this time almost zero, and neither of them performs a second comparison.

In some embodiments, referring to FIG. 4, the second amplification module 102 includes a first input unit 112 connected to the seventh node net7 and the eighth node net8 and configured to receive the first signal pair, perform a third comparison, and provide a signal as a result of the third comparison to the seventh node net7 and the eighth node net8, respectively; a second input unit 122 connected to the seventh node net7 and the eighth node net8 and configured to receive the second signal pair, perform a fourth comparison, and provide a signal as a result of the fourth comparison to the seventh node net7 and the eighth node net8, respectively; and a latch unit 132 connected to the seventh node net7 and the eighth node net8 and configured to amplify and latch the signal at the seventh node net7 and the signal at the eighth node net8, and output the first output signal Vout and the second output signal VoutN via the first output node net9 and the second output node net10, respectively.

As can be understood, when it is necessary to reduce the effect of inter-symbol interference on the data receiving circuit, the enable signal EnDfe is in a first level value period, and the first amplification module 101 selectively performs a first comparison and a second comparison based on the first complementary feedback signal fbpN and the second complementary feedback signal fbnN, one of the output first signal pair and the second signal pair is valid and the other is invalid, and at this time, what is received by the conductive input unit is a valid signal pair, and a valid signal pair refers to a set of signal pairs with a larger difference in the outputtable level values when the first comparison and the second comparison can be performed simultaneously, thereby improving the accuracy of the first output signal Vout and the second output signal VoutN output by the second amplification module 102. When there is no need to consider the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is in the second level value period, the first amplification module 101 fixes and outputs the valid first signal pair, the first input unit 112 is conductive or cut off in response to the valid first signal pair, and the signal pair received by the second input unit 122 is invalid and in a cut-off state, thereby reducing the power consumption of the data receiving circuit.

The latch unit 132 outputs a high-level signal to the first output node net9 and a low-level signal to the second output node net10 based on the signal of the seventh node net7 and the signal of the eighth node net8, or outputs a low-level signal to the first output node net9 and a high-level signal to the second output node net10.

In some embodiments, referring to FIG. 7 and FIG. 8, the first input unit 112 may include a thirteenth NMOS field effect transistor MN13 having a drain electrode connected to the seventh node net7, a source electrode connected to the ground terminal, and a gate receiving the first signal Sn+, and a fourteenth NMOS field effect transistor MN14 having a drain electrode connected to the eighth node net8, a source electrode connected to the ground terminal, and a gate receiving the second signal Sp+, and the second input unit 122 may include a fifteenth NMOS field effect transistor MN15 having a drain electrode connected to the seventh node net7, a source electrode connected to the ground terminal, and a gate receiving the third signal Sn-, and a sixteenth NMOS field effect transistor MN16 having a drain electrode connected to the eighth node net8, a source electrode connected to the ground terminal, and a gate receiving the fourth signal Sp-.

In one example, when the first amplification module 101 performs the first comparison, if the level value of the data signal DQ is higher than the level value of the first reference signal VR+, the level value of the first signal Sn+ is low and the level value of the second signal Sp+ is high, so that the conductivity of the 14th NMOS field effect transistor MN14 is greater than the conductivity of the 13th NMOS field effect transistor MN13, making the voltage at the 8th node net8 smaller than the voltage at the 7th node net7. Similarly, if the level value of the data signal DQ is lower than the level value of the first reference signal VR+, the level value of the first signal Sn+ is high and the level value of the second signal Sp+ is low, so that the conductivity of the 13th NMOS field effect transistor MN13 is greater than the conductivity of the 14th NMOS field effect transistor MN14, making the voltage at the 7th node net7 smaller than the voltage at the 8th node net8.

In another example, when the first amplification module 101 performs the second comparison, if the level value of the data signal DQ is higher than the level value of the second reference signal VR-, the level value of the third signal Sn- is low and the level value of the fourth signal Sp- is high, so that the conductivity of the 16th NMOS field effect transistor MN16 is greater than the conductivity of the 15th NMOS field effect transistor MN15, making the voltage at the 8th node net8 smaller than the voltage at the 7th node net7. Similarly, if the level value of the data signal DQ is lower than the level value of the second reference signal VR-, the level value of the third signal Sn- is high and the level value of the fourth signal Sp- is low, so that the conductivity of the 15th NMOS field effect transistor MN15 is greater than the conductivity of the 16th NMOS field effect transistor MN16, making the voltage at the 7th node net7 smaller than the voltage at the 8th node net8.

7 and 8, in some embodiments, the latch unit 132 includes a 17th NMOS field effect transistor MN17 and a 7th PMOS field effect transistor MP7, each having a gate connected to the second output node net10, a source electrode of the 17th NMOS field effect transistor MN17 connected to the 7th node net7, a drain electrode of the 17th NMOS field effect transistor MN17 and a drain electrode of the 7th PMOS field effect transistor MP7 connected to the first output node net9, and a source electrode of the 7th PMOS field effect transistor MP7 connected to the power supply node Vcc. The output terminal may include an 18th NMOS field effect transistor MN18 and an 8th PMOS field effect transistor MP8, in which the gate of the 18th NMOS field effect transistor MN18 and the gate of the 8th PMOS field effect transistor MP8 are both connected to the first output node net9, the source electrode of the 18th NMOS field effect transistor MN18 is connected to the 8th node net8, the drain electrode of the 18th NMOS field effect transistor MN18 and the drain electrode of the 8th PMOS field effect transistor MP8 are both connected to the second output node net10, and the source electrode of the 8th PMOS field effect transistor MP8 is connected to the power supply node Vcc.

In one example, when the first amplification module 101 performs a first comparison, if the level value of the data signal DQ is higher than the level value of the first reference signal VR+, the level value of the first signal Sn+ is low and the level value of the second signal Sp+ is high, so that the voltage at the eighth node net8 is smaller than the voltage at the seventh node net7, thereby making the conductivity of the eighth NMOS field effect transistor MN18 greater than the conductivity of the seventeenth NMOS field effect transistor MN17 and making the voltage at the second output node net10 smaller than the voltage at the first output node net9, so that the conductivity of the eighth PMOS field effect transistor MP8 is smaller than the conductivity of the seventh PMOS field effect transistor MP7, and the latch unit 132 forms a positive feedback amplification, further making the first output signal Vout output by the first output node net9 high and the second output signal VoutN output by the second output node net10 low. Similarly, when the level value of the data signal DQ is lower than the level value of the first reference signal VR+, the voltage at the seventh node net7 is smaller than the voltage at the eighth node net8, the first output signal Vout output by the first output node net9 is at a low level, and the second output signal VoutN output by the second output node net10 is at a high level.

In another example, when the first amplification module 101 performs the second comparison, if the level value of the data signal DQ is higher than the level value of the second reference signal VR-, the level value of the third signal Sn- is low and the level value of the fourth signal Sp- is high, so that the conductivity of the 16th NMOS field effect transistor MN16 is greater than the conductivity of the 15th NMOS field effect transistor MN15, making the voltage at the 8th node net8 smaller than the voltage at the 7th node net7, thereby making the first output signal Vout output by the first output node net9 a high level and the second output signal VoutN output by the second output node net10 a low level. Similarly, when the level value of the data signal DQ is lower than the level value of the second reference signal VR-, the level value of the third signal Sn- is high and the level value of the fourth signal Sp- is low, and at this time, the first output signal Vout output by the first output node net9 is at a low level, and the second output signal VoutN output by the second output node net10 is at a high level.

In some embodiments, referring to FIG. 4, the second amplification module 102 may further include a third reset unit 142 connected between the power supply node Vcc and the output terminal of the latch unit 132 and configured to reset the output terminal of the latch unit 132. In this way, after the data receiving circuit 100 completes one reception of the data signal DQ, the first reference signal VR+, and the second reference signal VR-, and one output of the first output signal Vout and the second output signal VoutN, the third reset unit 142 can restore the level values at the first output node net9 and the second output node net10 to their initial values, facilitating the subsequent data receiving circuit 100 to receive and process data.

In some embodiments, referring to FIG. 7 and FIG. 8, the third reset unit 142 may include a ninth PMOS field effect transistor MP9 connected between the first output node net9 and the power supply node Vcc and having a gate receiving the original sampling clock signal clk, and a tenth PMOS field effect transistor MP10 connected between the second output node net10 and the power supply node Vcc and having a gate receiving the original sampling clock signal clk.

In one example, the phase of the first sampling clock signal clkN1 is opposite to the phase of the original sampling clock signal clk. When it is necessary to reduce the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at logic level 1, the phase of the second sampling clock signal clkN2 is opposite to the phase of the original sampling clock signal clk, and when the original sampling clock signal clk is at a high level, the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are both at a low level, so that the first PM The OS field effect transistor MP1 and the second PMOS field effect transistor MP2 are both conductive, and at this time, the first amplification module 101 selectively performs one of the first comparison or the second comparison based on the first complementary feedback signal fbpN and the second complementary feedback signal fbnN, so that the first amplification module 101 can output only one of the valid first signal pair and the valid second signal pair. For example, when the first complementary feedback signal fbpN is at a low level and the second complementary feedback signal fbnN is at a high level, the first comparison unit 121 performs the first comparison, and the second comparison unit 122 cannot perform the second comparison. At this time, the ninth NMOS field effect transistor MN9, the tenth NMOS field effect transistor MN10, the eleventh NMOS field effect transistor MN11, the twelfth NMOS field effect transistor MN12, the ninth PMOS field effect transistor MP9, and the tenth PMOS field effect transistor MP10 are all cut off.

When the original sampling clock signal clk is at a low level, the first sampling clock signal clkN1 and the second sampling clock signal clkN2 are both at a high level, and then the first PMOS field effect transistor MP1 and the second PMOS field effect transistor MP2 are both cut off, and at this time, the ninth NMOS field effect transistor MN9, the tenth NMOS field effect transistor MN10, the eleventh NMOS field effect transistor MN11 and the twelfth NMOS field effect transistor MN12 are all conductive, so that The voltage at the first node net1, the voltage at the second node net2, the voltage at the third node net3, and the voltage at the fourth node net4 are pulled down to reset the first node net1, the second node net2, the third node net3, and the fourth node net4, and the ninth PMOS field effect transistor MP9 and the tenth PMOS field effect transistor MP10 are also turned on, thereby pulling up the voltage at the first output node net9 and the voltage at the second output node net10 to reset the first output node net9 and the second output node net10.

When there is no need to consider the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at logic level 0, and at this time, regardless of whether the original sampling clock signal clk is at high level or low level, the second sampling clock signal clkN2 is also always at high level, and then the second PMOS field effect transistor MP2 is always cut off, thereby reducing the current in the second comparison circuit 121, and thereby reducing the power consumption of the data receiving circuit 100.

In some embodiments, referring to FIG. 4, the data receiving circuit 100 may further include a first inverter circuit 114 configured to receive the first feedback signal fbp and output a first complementary feedback signal fbpN, and a second inverter circuit 124 configured to receive the second feedback signal fbn and output a second complementary feedback signal fbnN. In this manner, the first inverter circuit 114 converts the first feedback signal fbp into a first complementary feedback signal fbpN and supplies it to the gate of the second NMOS field effect transistor MN2 and the gate of the fifth NMOS field effect transistor MN5, and the second inverter circuit 124 converts the second feedback signal fbn into a second complementary feedback signal fbnN and supplies it to the gate of the fourth NMOS field effect transistor MN4 and the gate of the seventh NMOS field effect transistor MN7.

In some embodiments, referring to Figures 4-6, the first inversion circuit 114 may include a first inverter 1141 and the second inversion circuit 124 includes a second inverter 1241.

Referring to FIG. 9, the data receiving circuit 100 and the latch circuit 110 connected to the data receiving circuit 100 can form a plurality of data transmission circuits 120, and the plurality of cascaded data transmission circuits 120 form a data receiving system, in which the output signal of the data transmission circuit 120 in the previous stage is used as the feedback signal fb of the data transmission circuit 120 in the next stage, and the output signal of the data transmission circuit 120 in the final stage is used as the feedback signal fb of the data transmission circuit 120 in the first stage. The feedback signal fb includes a first feedback signal fbp and a second feedback signal fbn.

As will be understood, when multiple data receiving circuits 100 are cascaded, the first output signal Vout and the second output signal VoutN output by the data receiving circuit 100 of the previous stage are respectively set as the first feedback signal fbp and the second feedback signal fbn of the data receiving circuit 100 of the subsequent stage, and the data receiving circuit 100 of the subsequent stage selectively performs the first comparison or the second comparison based on the received first feedback signal fbp and the second feedback signal fbn, and the first output signal Vout and the second output signal VoutN output by the data receiving circuit 100 of the final stage are respectively set as the first feedback signal fbp and the second feedback signal fbn of the data receiving circuit 100 of the first stage, and the data receiving circuit 100 of the first stage selectively performs the first comparison or the second comparison based on the received first feedback signal fbp and the second feedback signal fbn.

Specifically, the first output signal Vout output from the first output node net9 of the data receiving circuit 100 of the previous stage is used as the first feedback signal fbp of the data receiving circuit 100 of the next stage, and the second output signal VoutN output from the second output node net10 of the data receiving circuit 100 of the previous stage is used as the second feedback signal fbn of the data receiving circuit 100 of the next stage. Next, the first inverter 1141 in the data receiving circuit 100 of the next stage converts the first feedback signal fbp into a first complementary feedback signal fbpN and supplies it to the gate of the second NMOS field effect transistor MN2 and the gate of the fifth NMOS field effect transistor MN5 of the current stage, and the second inverter 1241 in the data receiving circuit 100 of the next stage converts the second feedback signal fbn into a second complementary feedback signal fbnN and supplies it to the gate of the fourth NMOS field effect transistor MN4 and the gate of the seventh NMOS field effect transistor MN7 of the current stage.

As can be seen, when the first output signal Vout output by the first output node net9 of the data receiving circuit 100 in the preceding stage is at a high level and the second output signal VoutN output by the second output node net10 is at a low level, the first feedback signal fbp received by the data receiving circuit 100 in the succeeding stage is at a high level and the second feedback signal fbn is at a low level, and then the first complementary feedback signal fbpN is at a low level and the second complementary feedback signal fbnN is at a high level.

In some embodiments, referring to FIG. 4 and FIG. 8, the first inverter circuit 114 may include a third NAND gate 1142, two input terminals of which respectively receive the first feedback signal fbp and the enable signal EnDfe, and an output terminal of which outputs the first complementary feedback signal fbpN, and the second inverter circuit 124 may include a fourth NAND gate 1242, two input terminals of which respectively receive the second feedback signal fbn and the enable signal EnDfe, and an output terminal of which outputs the second complementary feedback signal fbnN.

When the enable signal EnDfe is in the first level value period, i.e., logic level 1, the change in the level value of the first feedback signal fbp received by the third NAND gate 1142 is the opposite of the change in the level value of the first complementary feedback signal fbpN output, i.e., the first complementary feedback signal fbpN is the opposite of the level of the first feedback signal fbp, and the change in the level value of the second feedback signal fbn received by the fourth NAND gate 1242 is the opposite of the change in the level value of the second complementary feedback signal fbnN output, i.e., the second complementary feedback signal fbnN is the opposite of the level of the second feedback signal fbn.

In one example, referring to Figures 4 and 8, when multiple data receiving circuits 100 are cascade-connected, the first output signal Vout output by the first output node net9 of the preceding data receiving circuit 100 is set as the first feedback signal fbp, and the third NAND gate 1142 in the preceding data receiving circuit 100 receives the first feedback signal fbp and the enable signal EnDfe, and outputs a first complementary feedback signal fbpN to the subsequent data receiving circuit 100, the second output signal VoutN output by the second output node net10 of the preceding data receiving circuit 100 is set as the second feedback signal fbn, and the fourth NAND gate 1242 in the preceding data receiving circuit 100 receives the second feedback signal fbn and the enable signal EnDfe, and outputs a second complementary feedback signal fbnN to the subsequent data receiving circuit 100. Next, the data receiving circuit 100 at the subsequent stage selectively performs a first comparison or a second comparison based on the received first complementary feedback signal fbpN and second complementary feedback signal fbnN. As can be seen, the first complementary feedback signal fbpN is obtained by processing it through the third NAND gate 1142, and the third NAND gate 1142 is used to enhance the driving capability of the first complementary feedback signal fbpN. The second complementary feedback signal fbnN is obtained by processing it through the fourth NAND gate 1242, and the fourth NAND gate 1242 is used to enhance the driving capability of the second complementary feedback signal fbnN. In this way, when the transmission path through which the first complementary feedback signal fbpN and the second complementary feedback signal fbnN are transmitted from the previous stage to the subsequent stage is relatively long, the third NAND gate 1142 and the fourth NAND gate 1242 contribute to enhancing the driving capability of the subsequent stage data transmission circuit 100 by the first complementary feedback signal fbpN and the second complementary feedback signal fbnN.

In another example, when multiple data receiving circuits 100 are cascaded, the first output signal Vout and the second output signal VoutN output by the data receiving circuit 100 in the previous stage are respectively used as the first feedback signal fbp and the second feedback signal fbn of the data receiving circuit 100 in the subsequent stage, the third NAND gate 1142 in the data receiving circuit 100 in the subsequent stage converts the first feedback signal fbp into a first complementary feedback signal fbpN and supplies it to the gate of the second NMOS field effect transistor MN2 and the gate of the fifth NMOS field effect transistor MN5 of the current stage, and the fourth NAND gate 1242 in the data receiving circuit 100 in the subsequent stage converts the second feedback signal fbn into a second complementary feedback signal fbnN and supplies it to the gate of the fourth NMOS field effect transistor MN4 and the gate of the seventh NMOS field effect transistor MN7 of the current stage. In addition, the third NAND gate 1142 may be provided adjacent to the gate of the second NMOS field effect transistor MN2 and the gate of the fifth NMOS field effect transistor MN5, and the fourth NAND gate 1242 may be provided adjacent to the gate of the fourth NMOS field effect transistor MN4 and the gate of the seventh NMOS field effect transistor MN7.

Below, the specific operating principle of the data receiving circuit 100 according to one embodiment of the present disclosure will be described in detail with reference to Figures 5, 7, and Table 1.

In one example, when multiple data receiving circuits 100 are cascaded, the first output signal Vout output from the first output node net9 of the preceding data receiving circuit 100 is used as the first feedback signal fbp of the succeeding data receiving circuit 100, and the second output signal VoutN output from the second output node net10 of the preceding data receiving circuit 100 is used as the second feedback signal fbn of the succeeding data receiving circuit 100.

The following describes an example in which the level value of the received first reference signal VR+ is greater than the level value of the second reference signal VR-. When the data signal DQ is at logic level 1, it indicates that the level value of the data signal DQ is greater than the level value of the first reference signal VR+, and when the data signal DQ is at logic level 0, it indicates that the level value of the data signal DQ is smaller than the level value of the second reference signal VR-. In Table 1, 1 indicates a high level and 0 indicates a low level.

When it is necessary to consider the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at a high level, at which time the first NMOS field effect transistor MN1 and the third NMOS field effect transistor MN3 are conductive, the second NMOS field effect transistor MN2 is conductive or cut off in response to the first complementary feedback signal fbpN, and the fourth NMOS field effect transistor MN4 is conductive or cut off in response to the second complementary feedback signal fbnN.

Referring to Table 1, when the data signal DQ1 received by the data receiving circuit 100 at the front stage is at logic level 1, the first output signal Vout output by the data receiving circuit 100 at the front stage, i.e., the first feedback signal fbp of the data receiving circuit 100 at the rear stage, is at a high level, and the second output signal VoutN output by the data receiving circuit 100 at the front stage, i.e., the second feedback signal fbn of the data receiving circuit 100 at the rear stage, is at a low level. At this time, the first complementary feedback signal fbpN is at a low level, and the second complementary feedback signal fbnN is at a high level. The second NMOS field effect transistor MN2 is cut off, the fourth NMOS field effect transistor MN4 is conductive, the first amplification module 101 performs a first comparison and outputs the first signal Sn+ and the second signal Sp+ via the first node net1 and the second node net2, the first input unit 112 is for providing signals to the seventh node net7 and the eighth node net8 by performing a third comparison on the first signal Sn+ and the second signal Sp+, and there is no current flowing through the second input unit 122.

When the data signal DQ1 received by the data receiving circuit 100 in the previous stage is at logic level 1, the data signal DQ2 received by the data receiving circuit 100 in the next stage has the following two states:

Situation 1
Referring to Table 1, when the data signal DQ2 received by the downstream data receiving circuit 100 is at logic level 0, the difference with the level value of the data signal DQ1 received by the upstream data receiving circuit 100 is relatively large, and relatively large inter-symbol interference occurs. At this time, the first amplification module 101 in the downstream data receiving circuit 100 performs a first comparison, outputs a first signal Sn+ and a second signal Sp+, and makes the first input unit 112 conductive, that is, what is received by the second amplification module 102 in the downstream data receiving circuit 100 is the first signal Sn+ and the second signal Sp+. At this time, in the downstream data receiving circuit 100, the data signal DQ2 is at logic level 0, the voltage difference between the data signal DQ2 and the first reference signal VR+ is greater than the voltage difference between the data signal DQ2 and the second reference signal VR-, if the second comparison can be performed at this time, the difference in the signal level values of the valid first signal pair obtained by performing the first comparison is greater than the difference in the signal level values of the valid second signal pair obtained by performing the second comparison, at this time, the second amplification module 102 receiving the valid first signal pair contributes to outputting the first output signal Vout and the second output signal VoutN with higher accuracy, thereby achieving the purpose of reducing the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100, and not performing the second comparison at this time contributes to reducing the power consumption of the data receiving circuit 100.

Situation 2
Referring to Table 1, when the data signal DQ2 received by the downstream data receiving circuit 100 is at logic level 1, the difference with the level value of the data signal DQ1 received by the upstream data receiving circuit 100 is relatively small, and relatively small inter-symbol interference occurs, or no inter-symbol interference occurs. At this time, the first amplification module 101 in the downstream data receiving circuit 100 performs a first comparison, outputs a first signal Sn+ and a second signal Sp+, and makes the first input unit 112 conductive, that is, what is received by the second amplification module 102 in the downstream data receiving circuit 100 is the first signal Sn+ and the second signal Sp+.

Referring to Table 1, when the data signal DQ1 received by the data receiving circuit 100 at the front stage is at logic level 0, the first output signal Vout output by the data receiving circuit 100 at the front stage, i.e., the first feedback signal fbp of the data receiving circuit 100 at the rear stage, is at a low level, and the second output signal VoutN output by the data receiving circuit 100 at the front stage, i.e., the second feedback signal fbn of the data receiving circuit 100 at the rear stage, is at a high level. At this time, the first complementary feedback signal fbpN is at a high level, and the second complementary feedback signal fbnN is at a low level. The second NMOS field effect transistor MN2 is turned on, the fourth NMOS field effect transistor MN4 is turned off, the first amplification module 101 performs a second comparison and outputs the third signal Sn- and the fourth signal Sp- via the third node net3 and the fourth node net4, the second input unit 122 is for providing signals to the seventh node net7 and the eighth node net8 by performing a fourth comparison on the third signal Sn- and the fourth signal Sp-, and there is no current flowing through the first input unit 112.

When the data signal DQ1 received by the data receiving circuit 100 in the previous stage is at logic level 0, the data signal DQ2 received by the data receiving circuit 100 in the next stage has the following two states:

Situation 3
Referring to Table 1, when the data signal DQ2 received by the downstream data receiving circuit 100 is at logic level 0, the difference with the level value of the data signal DQ1 received by the upstream data receiving circuit 100 is relatively small, and relatively small inter-symbol interference occurs, or no inter-symbol interference occurs. At this time, the first amplification module 101 in the downstream data receiving circuit 100 performs a second comparison, outputs a third signal Sn- and a fourth signal Sp-, and makes the second input unit 122 conductive, that is, what is received by the second amplification module 102 in the downstream data receiving circuit 100 is the third signal Sn- and the fourth signal Sp-.

Situation 4
Referring to Table 1, when the data signal DQ2 received by the downstream data receiving circuit 100 is at logic level 1, the difference with the level value of the data signal DQ1 received by the upstream data receiving circuit 100 is relatively large, and relatively large inter-symbol interference occurs. At this time, the first amplification module 101 in the downstream data receiving circuit 100 performs a second comparison, outputs a third signal Sn- and a fourth signal Sp-, and makes the second input unit 122 conductive, that is, what is received by the second amplification module 102 in the downstream data receiving circuit 100 is the third signal Sn- and the fourth signal Sp-. At this time, in the downstream data receiving circuit 100, the data signal DQ2 is at logic level 1, the voltage difference between the data signal DQ2 and the second reference signal VR- is greater than the voltage difference between the data signal DQ2 and the first reference signal VR+, if the first comparison can be performed at this time, the difference in the signal level values of the valid second signal pair obtained by performing the second comparison is greater than the difference in the signal level values of the valid first signal pair obtained by performing the first comparison, at this time, the second amplification module 102 receiving the valid second signal pair contributes to outputting the first output signal Vout and the second output signal VoutN with higher accuracy, thereby achieving the purpose of reducing the impact of inter-symbol interference of the received data signal DQ on the data receiving circuit 100, and not performing the first comparison at this time contributes to reducing the power consumption of the data receiving circuit 100.

When there is no need to consider the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is at a low level, at this time the first NMOS field effect transistor MN1 and the third NMOS field effect transistor MN3 are both cut off, the first amplification module 101 performs a fixed first comparison and outputs the first signal Sn+ and the second signal Sp+, the first input unit 112 is turned on or off in response to the first signal pair, at this time the third signal Sn- and the fourth signal Sp- output by the second comparison circuit 121 are both logical low level signals, and the second input unit 122 in response to the third signal Sn- and the fourth signal Sp- is cut off.

In the above description of the high level and low level, the high level may be a level value equal to or higher than the power supply voltage, and the low level may be a level value equal to or lower than the ground voltage. In addition, the high level and the low level are relative terms, and the specific level value ranges included in the high level and the low level may be determined based on a specific device. For example, in the case of an NMOS field effect transistor, the high level refers to the level value range of the gate voltage that can make the NMOS field effect transistor conductive, and the low level refers to the level value range of the gate voltage that can cut off the NMOS field effect transistor. In the case of a PMOS field effect transistor, the low level refers to the level value range of the gate voltage that can make the PMOS field effect transistor conductive, and the high level refers to the level value range of the gate voltage that can cut off the PMOS field effect transistor. In addition, the high level may be the logic level 1 in the above description, and the low level may be the logic level 0 in the above description.

In short, the enable signal EnDfe, the first feedback signal fbp, and the second feedback signal fbn are used to realize further control over the first amplification module 101, thereby selecting whether or not to consider the effect of inter-symbol interference of the data received by the data receiving circuit 100 on the data receiving circuit 100. For example, when it is necessary to reduce the effect of inter-symbol interference on the data receiving circuit 100, that is, when the enable signal EnDfe is in the first level value period, the first amplification module 101 responds to the sampling clock signal clkN, and selectively performs one of the first comparison and the second comparison using the first NMOS field effect transistor MN1, the second NMOS field effect transistor MN2, the third NMOS field effect transistor MN3, and the fourth NMOS field effect transistor MN4, enabling one of the output first and second signal pairs and disabling the other, and further increasing the difference in the signal level values of the enabled signal pairs, thereby controlling the second amplification module 101 to perform the first comparison and the second comparison. 02 receives a pair of differential signals with a larger difference in signal level value, and further uses the low conductive resistance of the NMOS field effect transistor to prevent the first amplification module 101 from simultaneously performing the first comparison and the second comparison, and improves the processing efficiency and processing speed of the data signal DQ by the first amplification module 101, and when there is no need to consider the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is in the second level value period, and the first amplification module 101 performs only the first comparison in response to the sampling clock signal clkN, and fixes and outputs the valid first signal pair, thereby reducing the power consumption of the data receiving circuit 100.

Another embodiment of the present disclosure further provides a data receiving system, which will be described in detail below with reference to the drawings. FIG. 9 is a functional block diagram of a data receiving system according to another embodiment of the present disclosure.

Referring to FIG. 9, the data receiving system includes a plurality of data transmission circuits 120 connected in cascade, each of which includes a data receiving circuit 100 according to one embodiment of the present disclosure and a latch circuit 110 connected to the data receiving circuit 100, and the output signal of the data transmission circuit 120 in the preceding stage is used as a feedback signal fb for the data transmission circuit 120 in the succeeding stage, and the output signal of the data transmission circuit 120 in the final stage is used as a feedback signal fb for the data transmission circuit 120 in the first stage. The latch circuits 110 are provided in one-to-one correspondence with the data receiving circuits 100, and the latch circuits 110 are intended to latch and output the signal output by the data receiving circuit 100 corresponding to the latch circuit 110.

In some embodiments, the data receiving circuit 100 receives data in response to a sampling clock signal, and the data receiving system includes four data receiving circuits 100 connected in cascade, where the phase difference between the sampling clock signals clkN of the data receiving circuits 100 of adjacent stages is 90°. In this way, the period of the sampling clock signal clkN is twice the period of the data signal DQ received by the data port, which contributes to saving clock wiring and power consumption.

In FIG. 9, the data receiving system has four data receiving circuits 100 connected in cascade, and the phase difference between the sampling clock signals of the data receiving circuits 100 of adjacent stages is taken as an example. In actual applications, the number of cascaded data receiving circuits 100 included in the data receiving system may not be limited, and the phase difference between the sampling clock signals of the data receiving circuits 100 of adjacent stages may be set rationally based on the number of cascaded data receiving circuits 100.

In some embodiments, the first output signal Vout and the second output signal VoutN output by the second amplification module 102 of the data receiving circuit 100 in the preceding stage are used as the feedback signal fb of the data receiving circuit 100 in the succeeding stage. In this way, the output of the data receiving circuit 100 is directly transmitted to the data transmission circuit 120 in the succeeding stage, and does not need to pass through the latch circuit 110, which contributes to reducing the data transmission delay, or the signal output by the latch circuit 110 in the preceding stage is used as the feedback signal fb of the data receiving circuit 100 in the succeeding stage.

In short, the data receiving system according to another embodiment of the present disclosure can use the enable signal EnDfe, the first feedback signal fbp, and the second feedback signal fbn to realize further control over the first amplification module 101, thereby selecting whether the data receiving circuit 100 should consider the effect of inter-symbol interference of the received data on the data receiving circuit 100. For example, when it is necessary to reduce the effect of inter-symbol interference on the data receiving circuit 100, that is, when the enable signal EnDfe is in the first level value period, the first amplification module 101 selects whether to perform the first comparison or the second comparison based on the first feedback signal fbp and the second feedback signal fbn in response to the sampling clock signal clkN, enables one of the output first and second signal pairs, disables the other, and further increases the difference in the signal level values of the enabled signal pair, so that the second amplification module 102 receives a pair of differential signals with a larger difference in signal level values. In addition, the low conductive resistance of the NMOS field effect transistor is used to prevent the first amplification module 101 from simultaneously performing the first comparison and the second comparison, and the processing efficiency and processing speed of the data signal DQ by the first amplification module 101 is improved. When there is no need to consider the effect of inter-symbol interference on the data receiving circuit 100, the enable signal EnDfe is in the second level value period, and the first amplification module 101 performs only the first comparison in response to the sampling clock signal clkN, and fixes and outputs the effective first signal pair, thereby reducing the power consumption of the data receiving circuit 100.

Another embodiment of the present disclosure further provides a storage device, comprising a plurality of data ports and a plurality of data receiving systems according to any one of the above, each of which corresponds to one of the data ports. In this way, when it is necessary to reduce the influence of inter-symbol interference on the storage device, each data port in the storage device can flexibly adjust the data signal DQ received by the data receiving system, and improve the adjustment ability of the first output signal Vout and the second output signal VoutN, thereby improving the reception performance of the storage device; when it is not necessary to consider the influence of inter-symbol interference on the storage device, the enable signal EnDfe is in the second level value period, and the first amplification module 101 only performs the first comparison in response to the sampling clock signal clkN, and fixes and outputs the effective first signal pair, thereby reducing the power consumption of the storage device.

As will be understood by those skilled in the art, the above embodiments are specific examples of realizing the present disclosure, but in actual applications, various changes in form and details can be made without departing from the spirit and scope of the embodiments of the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the patent scope of the embodiments of the present disclosure should conform to the scope limited by the claims.

Claims (16)

A data receiving circuit, comprising a first amplification module and a second amplification module;
the first amplification module is configured to receive an enable signal, a first feedback signal, a second feedback signal, a data signal, a first reference signal, and a second reference signal; and while the enable signal has a first level value, to: respond to a sampling clock signal, and select the data signal and the first reference signal based on the first feedback signal to perform a first comparison and output a first signal pair as a result of the first comparison; or respond to the sampling clock signal, and select the data signal and the second reference signal based on the second feedback signal to perform a second comparison and output a second signal pair as a result of the second comparison; and while the enable signal has a second level value, to perform the first comparison in response to the sampling clock signal to output the first signal pair, the first feedback signal is inverse to a level of the second feedback signal, the first signal pair includes a first signal and a second signal, and the second signal pair includes a third signal and a fourth signal;
The first amplification module comprises an amplification unit, a first NMOS field effect transistor, a second NMOS field effect transistor, a third NMOS field effect transistor, and a fourth NMOS field effect transistor, the amplification unit has a first node, a second node, a third node, and a fourth node, the first node outputs the first signal, the second node outputs the second signal, the third node outputs the third signal, the fourth node outputs the fourth signal, and is configured to receive the data signal, the first reference signal, and the second reference signal, one end of the first NMOS field effect transistor is connected to the first node, the other end of the first NMOS field effect transistor is connected to one end of the second NMOS field effect transistor, and the other end of the second NMOS field effect transistor is a third NMOS field effect transistor connected to the third node, one of the gates of the first NMOS field effect transistor and the second NMOS field effect transistor receiving a first complementary feedback signal and the other gate receiving the enable signal, the first complementary feedback signal being inverse in level to the first feedback signal; one end of the third NMOS field effect transistor connected to the third node, the other end of the third NMOS field effect transistor connected to one end of the fourth NMOS field effect transistor, the other end of the fourth NMOS field effect transistor connected to the fourth node, one of the gates of the third NMOS field effect transistor and the fourth NMOS field effect transistor receiving a second complementary feedback signal and the other gate receiving the enable signal, the second complementary feedback signal being inverse in level to the second feedback signal;
The data receiving circuit is characterized in that the second amplification module is configured to receive the output signals of the first amplification module as an input signal pair, perform an amplification process on the voltage difference of the input signal pair, and output a first output signal and a second output signal as a result of the amplification process. The first amplification module further comprises:
a fifth NMOS field effect transistor and a sixth NMOS field effect transistor, one end of the fifth NMOS field effect transistor being connected to the first node, the other end of the fifth NMOS field effect transistor being connected to one end of the sixth NMOS field effect transistor, and the other end of the sixth NMOS field effect transistor being connected to the second node, one gate of the fifth NMOS field effect transistor and the sixth NMOS field effect transistor receiving the first complementary feedback signal and the other gate receiving the enable signal ;
2. The data receiving circuit according to claim 1, comprising a seventh NMOS field effect transistor and an eighth NMOS field effect transistor, one end of the seventh NMOS field effect transistor is connected to the third node, the other end of the seventh NMOS field effect transistor is connected to one end of the eighth NMOS field effect transistor, and the other end of the eighth NMOS field effect transistor is connected to the fourth node, one gate of the seventh NMOS field effect transistor and the eighth NMOS field effect transistor receives the second complementary feedback signal, and the other gate of the seventh NMOS field effect transistor receives the enable signal. a gate of the first NMOS field effect transistor receives the enable signal, a gate of the second NMOS field effect transistor receives the first complementary feedback signal, a channel width of the first NMOS field effect transistor is larger than a channel width of the second NMOS field effect transistor, a gate of the fifth NMOS field effect transistor receives the first complementary feedback signal, a gate of the sixth NMOS field effect transistor receives the enable signal, and a channel width of the fifth NMOS field effect transistor is smaller than a channel width of the sixth NMOS field effect transistor;
3. The data receiving circuit according to claim 2, wherein a gate of the third NMOS field effect transistor receives the enable signal, a gate of the fourth NMOS field effect transistor receives the second complementary feedback signal, a channel width of the third NMOS field effect transistor is larger than a channel width of the fourth NMOS field effect transistor, a gate of the seventh NMOS field effect transistor receives the second complementary feedback signal, a gate of the eighth NMOS field effect transistor receives the enable signal, and a channel width of the seventh NMOS field effect transistor is smaller than a channel width of the eighth NMOS field effect transistor . a channel width of the fifth NMOS field effect transistor is equal to a channel width of the second NMOS field effect transistor, a channel width of the sixth NMOS field effect transistor is equal to a channel width of the first NMOS field effect transistor, and the channel lengths of the first NMOS field effect transistor, the second NMOS field effect transistor, the fifth NMOS field effect transistor, and the sixth NMOS field effect transistor are all equal;
3. The data receiving circuit according to claim 2, wherein a channel width of the seventh NMOS field effect transistor is equal to a channel width of the fourth NMOS field effect transistor, a channel width of the eighth NMOS field effect transistor is equal to a channel width of the third NMOS field effect transistor, and a channel length of the third NMOS field effect transistor, a channel length of the fourth NMOS field effect transistor, a channel length of the seventh NMOS field effect transistor, and a channel length of the eighth NMOS field effect transistor are all equal . The sampling clock signal includes a first sampling clock signal and a second sampling clock signal, and the amplifying unit:
a first comparison circuit having the first node and the second node, the first comparison circuit configured to receive the data signal and the first reference signal and to perform the first comparison in response to the first sampling clock signal;
a clock generating circuit configured to receive the enable signal and the original sampling clock signal and to output the second sampling clock signal, wherein while the enable signal has the first level value, the phase of the second sampling clock signal is opposite to that of the original sampling clock signal, and while the enable signal has the second level value, the second sampling clock signal is a logic high level signal;
a second comparison circuit having the third node and the fourth node, configured to receive the data signal and the second reference signal, and to perform the second comparison in response to the second sampling clock signal while the enable signal has the first level value, to make a connection path between the third node and a ground terminal conductive while the enable signal has the second level value, and to make a connection path between the fourth node and a ground terminal conductive while the enable signal has the second level value. The first comparison circuit is
a first current source connected between a power supply node and a fifth node and configured to supply a current to the fifth node in response to the first sampling clock signal;
a first comparison unit coupled to the first node, the second node, and the fifth node, configured to receive the data signal and the first reference signal, perform the first comparison when the first current source supplies a current to the fifth node, and output the first signal and the second signal;
a first reset unit coupled to the first node and the second node and configured to reset the first node and the second node in response to the first sampling clock signal;
The second comparison circuit is
a second current source connected between a power supply node and a sixth node and configured to supply a current to the sixth node in response to the second sampling clock signal;
a second comparison unit coupled to the third node, the fourth node, and the sixth node, configured to receive the data signal and the second reference signal, perform the second comparison when the second current source supplies a current to the sixth node, and output the third signal and the fourth signal;
6. The data receiving circuit of claim 5, further comprising: a second reset unit connected between the third node and the fourth node and configured to reset the third node and the fourth node in response to the second sampling clock signal. The first current source is
a first PMOS field effect transistor connected between the power supply node and the fifth node, the gate of the first PMOS field effect transistor receiving the first sampling clock signal;
The second current source is
a second PMOS field effect transistor connected between the power supply node and the sixth node, the gate of the second PMOS field effect transistor receiving the second sampling clock signal ;
The first comparison unit is
a third PMOS field effect transistor connected between the first node and the fifth node, the gate of which receives the data signal;
a fourth PMOS field effect transistor connected between the second node and the fifth node, the gate of the fourth PMOS field effect transistor receiving the first reference signal;
The second comparison unit is
a fifth PMOS field effect transistor connected between the third node and the sixth node, the fifth PMOS field effect transistor having a gate receiving the data signal;
a sixth PMOS field effect transistor connected between the fourth node and the sixth node, the gate of which receives the second reference signal;
The first reset unit is
a ninth NMOS field effect transistor connected between the first node and a ground terminal, the gate of which receives the first sampling clock signal;
a tenth NMOS field effect transistor connected between the second node and the ground terminal, the tenth NMOS field effect transistor having a gate receiving the first sampling clock signal;
The second reset unit is
an eleventh NMOS field effect transistor connected between the third node and a ground terminal, the gate of which receives the second sampling clock signal;
7. The data receiving circuit of claim 6 , further comprising: a twelfth NMOS field effect transistor connected between the fourth node and a ground terminal, the gate of which receives the second sampling clock signal . The clock generating circuit includes:
a first NAND gate circuit having one input terminal for receiving the original sampling clock signal, another input terminal connected to a power supply node, and an output terminal for outputting the first sampling clock signal;
6. The data receiving circuit according to claim 5, further comprising: a second NAND gate circuit having one input terminal for receiving the original sampling clock signal, another input terminal for receiving the enable signal, and an output terminal for outputting the second sampling clock signal . The second amplification module includes:
a first input unit connected to a seventh node and an eighth node, configured to receive the first pair of signals, perform a third comparison, and provide a signal to the seventh node and the eighth node, respectively, as a result of the third comparison;
a second input unit connected to the seventh node and the eighth node and configured to receive the second pair of signals, perform a fourth comparison, and provide a signal to the seventh node and the eighth node, respectively, as a result of the fourth comparison;
a latch unit connected to the seventh node and the eighth node, configured to amplify and latch a signal at the seventh node and a signal at the eighth node, and output the first output signal and the second output signal via a first output node and a second output node, respectively;
2. The data receiving circuit according to claim 1, further comprising : a third reset unit connected between a power supply node and the output terminal of the latch unit and configured to reset the output terminal of the latch unit . The first input unit is
a thirteenth NMOS field effect transistor having a drain electrode connected to the seventh node, a source electrode connected to a ground terminal, and a gate receiving the first signal;
a fourteenth NMOS field effect transistor having a drain electrode connected to the eighth node, a source electrode connected to a ground terminal, and a gate receiving the second signal;
The second input unit is
a fifteenth NMOS field effect transistor having a drain electrode connected to the seventh node, a source electrode connected to a ground terminal, and a gate for receiving the third signal;
a sixteenth NMOS field effect transistor having a drain electrode connected to the eighth node, a source electrode connected to a ground terminal, and a gate receiving the fourth signal ;
The latch unit includes:
a 17th NMOS field effect transistor and a 7th PMOS field effect transistor, a gate of the 17th NMOS field effect transistor and a gate of the 7th PMOS field effect transistor are both connected to the second output node, a source electrode of the 17th NMOS field effect transistor is connected to the 7th node, a drain electrode of the 17th NMOS field effect transistor and a drain electrode of the 7th PMOS field effect transistor are both connected to the first output node, and a source electrode of the 7th PMOS field effect transistor is connected to a power supply node;
an 18th NMOS field effect transistor and an 8th PMOS field effect transistor, a gate of the 18th NMOS field effect transistor and a gate of the 8th PMOS field effect transistor are both connected to the first output node, a source electrode of the 18th NMOS field effect transistor is connected to the 8th node, a drain electrode of the 18th NMOS field effect transistor and a drain electrode of the 8th PMOS field effect transistor are both connected to the second output node, and a source electrode of the 8th PMOS field effect transistor is connected to the power supply node;
The third reset unit is
a ninth PMOS field effect transistor connected between the first output node and a power supply node, the gate of which receives the original sampling clock signal;
10. The data receiving circuit of claim 9 , further comprising : a tenth PMOS field effect transistor connected between the second output node and the power supply node, the gate of which receives the original sampling clock signal . a first inverter circuit configured to receive the first feedback signal and to output the first complementary feedback signal;
2. The data receiving circuit of claim 1, further comprising: a second inverting circuit configured to receive the second feedback signal and output the second complementary feedback signal. 12. The data receiving circuit of claim 11, wherein the first inverter circuit comprises a third NAND gate, two input terminals of which respectively receive the first feedback signal and the enable signal, and an output terminal of which outputs the first complementary feedback signal; and the second inverter circuit comprises a fourth NAND gate, two input terminals of which respectively receive the second feedback signal and the enable signal, and an output terminal of which outputs the second complementary feedback signal. 1. A data receiving system, comprising:
a plurality of data transmission circuits connected in cascade, each of the data transmission circuits comprising the data receiving circuit according to any one of claims 1 to 12 and a latch circuit connected to the data receiving circuit;
the output signal of the data transmission circuit at the front stage is used as the feedback signal of the data transmission circuit at the rear stage;
1. A data receiving system, comprising: a data transmission circuit in a first stage, and an output signal of the data transmission circuit in a final stage is used as the feedback signal of the data transmission circuit in a first stage. The data receiving system according to claim 13, characterized in that the data receiving circuit receives data in response to a sampling clock signal, and the data receiving system comprises four data transmission circuits connected in cascade, and the phase difference of the sampling clock signals of the data receiving circuits of adjacent stages is 90°. The data receiving system according to claim 13, characterized in that the first output signal and the second output signal output by the second amplification module of the data receiving circuit of the previous stage are used as the feedback signal of the data receiving circuit of the subsequent stage, or the signal output by the latch circuit of the previous stage is used as the feedback signal of the data receiving circuit of the subsequent stage. 1. A storage device comprising:
Multiple data ports and
A storage device comprising: a plurality of data receiving systems according to claim 13 , each of the data receiving systems corresponding to one of the data ports.

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