JP7267089B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7267089B2 JP7267089B2 JP2019091286A JP2019091286A JP7267089B2 JP 7267089 B2 JP7267089 B2 JP 7267089B2 JP 2019091286 A JP2019091286 A JP 2019091286A JP 2019091286 A JP2019091286 A JP 2019091286A JP 7267089 B2 JP7267089 B2 JP 7267089B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q21/00—Antenna arrays or systems
- H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
- H01Q21/061—Two dimensional planar arrays
- H01Q21/065—Patch antenna array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
- H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
- H05K7/023—Stackable modules
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
- H01Q9/0414—Substantially flat resonant element parallel to ground plane, e.g. patch antenna in a stacked or folded configuration
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
[第1実施形態に係る半導体装置の構造]
図1は、第1実施形態に係る半導体装置を例示する図であり、図1(a)は断面図、図1(b)は絶縁層51のみを示す平面図である。
次に、第1実施形態に係る半導体装置の製造方法について説明する。図2は、第1実施形態に係る半導体装置の製造工程を例示する図である。
ここで、半導体装置1における1次放射器12及び2次放射器72のアンテナ特性について説明する。
又、半導体装置1Xでは、アンテナ特性を考慮して1次放射器12と2次放射器72との距離を適正化するためには、絶縁層75をある程度厚くする必要がある。又、アンテナ特性を向上するために、絶縁層75の材料として絶縁層11よりも低誘電率かつ低誘電正接の材料を用いる場合が多い。
第1実施形態の変形例1では、基板接続用パッドを枠状の基板接続用パターンとする例を示す。なお、第1実施形態の変形例1において、既に説明した実施形態と同一構成部についての説明は省略する場合がある。
第1実施形態の変形例2では、基板間接続部材のバリエーションの例を示す。なお、第1実施形態の変形例2において、既に説明した実施形態と同一構成部についての説明は省略する場合がある。
10、50、70 配線基板
11、51、71 絶縁層
11a、51a、71a 一方の面
11b、51b、71b 他方の面
12 1次放射器
13、52、53、73 基板接続用パッド
14 チップ接続用パッド
20 半導体チップ
21 本体
21a 回路形成面
22 電極パッド
30、31、32 バンプ
33、34、35、36 金属ポスト
40 アンダーフィル樹脂
52A 基板接続用パターン
72 2次放射器
Claims (5)
- 一方の面に1次放射器が形成され、他方の面に半導体チップが実装された第1配線基板と、
2次放射器を備えた第2配線基板と、
前記第1配線基板の一方の面と前記第2配線基板との間に、前記第1配線基板及び前記第2配線基板と所定の間隔で配置された第3配線基板と、を有し、
前記1次放射器と前記2次放射器に挟まれた領域に前記第3配線基板が存在し、
前記1次放射器及び前記2次放射器は、アンテナを構成し、
前記第1配線基板と前記第3配線基板との間には、前記第1配線基板と前記第3配線基板との間に空間を形成すると共に、前記第1配線基板と前記第3配線基板との間隔を規定する第1基板間接続部材が配置され、
前記第2配線基板と前記第3配線基板との間には、前記第2配線基板と前記第3配線基板との間に空間を形成すると共に、前記第2配線基板と前記第3配線基板との間隔を規定する第2基板間接続部材が配置されている半導体装置。 - 前記第1配線基板は第1絶縁層を有し、
前記第2配線基板は第2絶縁層を有し、
前記第3配線基板は第3絶縁層を有し、
前記第1絶縁層と、前記第2絶縁層と、前記第3絶縁層とは、互いに熱膨張係数が異なる請求項1に記載の半導体装置。 - 前記第3絶縁層の熱膨張係数は、前記第1絶縁層の熱膨張係数と前記第2絶縁層の熱膨張係数の間である請求項2に記載の半導体装置。
- 前記第2絶縁層及び前記第3絶縁層は、前記第1絶縁層よりも誘電率及び誘電正接が低い請求項2又は3に記載の半導体装置。
- 前記第2絶縁層及び/又は前記第3絶縁層は、フッ素系樹脂を含む請求項2乃至4の何れか一項に記載の半導体装置。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019091286A JP7267089B2 (ja) | 2019-05-14 | 2019-05-14 | 半導体装置 |
| US16/869,995 US11343915B2 (en) | 2019-05-14 | 2020-05-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019091286A JP7267089B2 (ja) | 2019-05-14 | 2019-05-14 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2020188355A JP2020188355A (ja) | 2020-11-19 |
| JP7267089B2 true JP7267089B2 (ja) | 2023-05-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019091286A Active JP7267089B2 (ja) | 2019-05-14 | 2019-05-14 | 半導体装置 |
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| Country | Link |
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| US (1) | US11343915B2 (ja) |
| JP (1) | JP7267089B2 (ja) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230019616A (ko) * | 2021-08-02 | 2023-02-09 | 삼성전자주식회사 | 칩 연결 구조체를 포함하는 반도체 패키지 |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010507929A (ja) | 2006-09-21 | 2010-03-11 | レイセオン カンパニー | タイルサブアレイ並びに関連する回路及び技法 |
| JP2014514801A (ja) | 2011-03-11 | 2014-06-19 | オートリブ エー・エス・ピー・インク | 超広帯域レーダ用アンテナアレイ |
| JP2015216577A (ja) | 2014-05-13 | 2015-12-03 | 富士通株式会社 | アンテナ装置 |
| US20170125895A1 (en) | 2014-08-13 | 2017-05-04 | International Business Machines Corporation | Wireless communications package with integrated antennas and air cavity |
| JP2018093491A (ja) | 2016-12-03 | 2018-06-14 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | 集積アンテナ・アレーを有するワイヤレス通信パッケージ |
| WO2019064683A1 (ja) | 2017-09-28 | 2019-04-04 | 三菱電機株式会社 | アレーアンテナ装置 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5976118U (ja) * | 1982-11-12 | 1984-05-23 | 宇宙開発事業団 | マイクロストリツプアレ−アンテナ |
| US9941226B2 (en) * | 2014-12-15 | 2018-04-10 | Industrial Technology Research Institute | Integrated millimeter-wave chip package |
| US11509038B2 (en) * | 2017-06-07 | 2022-11-22 | Mediatek Inc. | Semiconductor package having discrete antenna device |
| TWI693679B (zh) * | 2018-08-07 | 2020-05-11 | 矽品精密工業股份有限公司 | 電子封裝件 |
-
2019
- 2019-05-14 JP JP2019091286A patent/JP7267089B2/ja active Active
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2020
- 2020-05-08 US US16/869,995 patent/US11343915B2/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010507929A (ja) | 2006-09-21 | 2010-03-11 | レイセオン カンパニー | タイルサブアレイ並びに関連する回路及び技法 |
| JP2014514801A (ja) | 2011-03-11 | 2014-06-19 | オートリブ エー・エス・ピー・インク | 超広帯域レーダ用アンテナアレイ |
| JP2015216577A (ja) | 2014-05-13 | 2015-12-03 | 富士通株式会社 | アンテナ装置 |
| US20170125895A1 (en) | 2014-08-13 | 2017-05-04 | International Business Machines Corporation | Wireless communications package with integrated antennas and air cavity |
| JP2018093491A (ja) | 2016-12-03 | 2018-06-14 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | 集積アンテナ・アレーを有するワイヤレス通信パッケージ |
| WO2019064683A1 (ja) | 2017-09-28 | 2019-04-04 | 三菱電機株式会社 | アレーアンテナ装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US11343915B2 (en) | 2022-05-24 |
| JP2020188355A (ja) | 2020-11-19 |
| US20200367361A1 (en) | 2020-11-19 |
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