JP6929171B2 - Non-volatile semiconductor storage device - Google Patents

Description

The invention disclosed herein relates to a non-volatile semiconductor storage device.

Non-volatile semiconductor storage devices (for example, EEPROM [electrically erasable and programmable read only memory]) capable of arbitrarily rewriting data in memory cells are used in various applications.

In addition, as an example of the prior art related to the above, Patent Document 1 and Patent Document 2 can be mentioned.

Japanese Unexamined Patent Publication No. 2-244500 Japanese Unexamined Patent Publication No. 6-84400

However, in the above-mentioned conventional non-volatile semiconductor storage device, there is room for further improvement in the maximum number of times of rewriting of memory cells.

The invention disclosed in the present specification provides a non-volatile semiconductor storage device capable of improving the maximum number of times of rewriting of a memory cell in view of the above-mentioned problems found by the inventors of the present application. The purpose.

The non-volatile semiconductor storage device disclosed in the present specification includes a first memory in which data can be arbitrarily rewritten, a second memory for storing a set value of a read voltage applied to the first memory, and a second memory. A sense amplifier for reading data from both the first memory and the second memory, and a logic unit for reading the set value from the second memory and generating a control signal before reading the data from the first memory. It has a configuration (first configuration) including a read-out voltage setting unit that sets the read-out voltage according to the control signal.

In the non-volatile semiconductor storage device having the first configuration, the read voltage is the threshold voltage when the data "1" is written in the memory cell of the first memory and the data in the memory cell. It is preferable to use a configuration (second configuration) in which the value is set to an intermediate value with the threshold voltage when "0" is written.

Further, in the non-volatile semiconductor storage device having the first or second configuration, the second memory may be a dummy memory formed adjacent to the first memory (third configuration). ..

Further, in the non-volatile semiconductor storage device having any of the first to third configurations, the logic unit is configured to complete the reading operation of the set value during the input period of the operation code (fourth configuration). good.

Further, in the non-volatile semiconductor storage device having any of the first to fourth configurations, the set value is a correction value for correcting the read voltage from a predetermined reference value (fifth configuration). It is good to set it to.

Further, in the non-volatile semiconductor storage device having any of the first to fifth configurations, the read voltage applied to the second memory may be a fixed value (sixth configuration).

Further, in the non-volatile semiconductor storage device having any of the first to sixth configurations, the plurality of memory cells forming the first memory are a memory transistor having a control gate, a floating gate, a source and a drain, respectively. With the first choice transistor where the source is connected to the drain of the memory transistor, the drain is connected to the bit line and the gate is connected to the word line; the drain is connected to the source of the memory transistor and the source is The control gate of the memory transistor is connected to the first pad via the third selection transistor, including a second selection transistor whose gate is connected to the first gate control means, which is connected to the ground potential. The source of the memory transistor may be connected to the second pad via the fourth selection transistor (seventh configuration).

Further, in the non-volatile semiconductor storage device having the seventh configuration, the source is connected to the input stage of the sense amplifier, the drain is connected to the second pad, and the gate is connected to the second gate control means. It is preferable to have a configuration (eighth configuration) further including a 5-select transistor.

Further, in the non-volatile semiconductor storage device having the eighth configuration, in the test mode for measuring the threshold voltage of the memory transistor, the first supply potential applied to the first pad is set to a variable value. It is preferable to have a configuration (9th configuration) in which the second supply potential applied to the second pad has an indefinite value or a fixed value.

Further, in the initial setting method of the non-volatile semiconductor storage device having the ninth configuration, the first selection transistor, the second selection transistor, and the third selection transistor are turned on, and the fourth selection transistor and the fourth selection transistor are turned on. The fifth selection transistor is turned off, the second pad is not used, and the transition of the memory transistor on / off state is detected by the sense amplifier while changing the first supply potential. The step of measuring the positive threshold voltage of the memory transistor; the first selection transistor, the third selection transistor, the fourth selection transistor, and the fifth selection transistor are turned on, and the second selection transistor is turned on. Is turned off, the second supply potential is fixed, and the transition of the on / off state of the memory transistor is detected by the sense amplifier while changing the first supply potential in a range lower than this. The step of measuring the negative threshold voltage of the memory transistor; the set value is calculated so that the read voltage is set to an intermediate value between the positive threshold voltage and the negative threshold voltage. It is preferable to have a configuration (10th configuration) having a step and a step of storing the set value in the second memory.

According to the non-volatile semiconductor storage device disclosed in the present specification, it is possible to improve the maximum number of times of rewriting of a memory cell.

It is a figure which shows the basic structure of the non-volatile semiconductor storage device. It is a figure which shows the correlation between the number of times of rewriting of a memory cell, and the threshold voltage. It is a timing chart which shows the measurement operation of a negative threshold voltage. It is a figure which shows the measurement input potential applied at the time of the measurement of a negative threshold voltage. It is a figure which shows the node potential and the on / off state of a transistor in each mode. The figure which shows the maximum number of times of rewriting when the threshold voltage is a typical value. The figure which shows how the threshold voltage shifts upward and the maximum number of rewrites decreases. The figure which shows how the threshold voltage shifts downward and the maximum number of rewrites decreases. The figure which shows one configuration example of the non-volatile semiconductor storage device which provided the read-out voltage correction function. The figure which shows one configuration example of a read-out voltage setting part. The flowchart which shows an example of the read-out voltage correction operation. The figure which shows how the read-out voltage is corrected at the time of the upper shift of a threshold voltage. The figure which shows how the read-out voltage is corrected at the time of the lower shift of a threshold voltage.

<Basic configuration>
FIG. 1 is a diagram showing a basic configuration of a non-volatile semiconductor storage device.

The non-volatile semiconductor storage device NVM1 in this figure can be roughly divided into a memory cell MC1 having a sense amplifier SA1, a first potential supply means PAD1 (hereinafter referred to as a pad PAD1), a fourth selection transistor M12, and a fifth selection transistor M13. , And a second potential supply means PAD2 (hereinafter, referred to as pad PAD2).

The sense amplifier SA1 is composed of transistors M1, M2, M3, M4, a first transistor M6, a second transistor M14, a third transistor M5, an inverter INV1, and a resistor R1.

The two transistors M1 and M2 are of the p-channel MOS type, and these two transistors form a part of the well-known current mirror circuit CUM. The output current Im2 of the current mirror circuit CUM is determined by a transistor M3 made of a depletion type and a resistor R1. The sources of the transistors M1 and M2 are both connected to the power supply potential VCS. The gate of the transistor M3 is connected to the ground potential GND. The drain of the transistor M3 is connected to the common gate of the transistors M1 and M2. The gate and drain of the transistor M1 are commonly connected. The source of the transistor M3 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the ground potential GND. The output current Im2 of the current mirror circuit CUM composed of the transistors M1 and M2 is supplied to the drain of the third transistor M5.

The first transistor M6 constitutes an input stage of the sense amplifier SA1 and plays a role of coupling the sense amplifier SA1 and the memory cell MC1 and also plays a role of a first amplification means of the sense amplifier SA1. The drain of the first transistor M6 and the gate of the third transistor M5 are commonly connected to the fifth gate control means VC5.

One amplification means is composed of three transistors M2, M4, and a third transistor M5. The transistor M4 is a p-channel MOS type, the source is connected to the power supply potential VCS, the gate is connected to the fourth gate control means VC4, and the drain is connected to the drain of the third transistor M5. Both the transistors M2 and M4 are the loads of the third transistor M5, but the channel width of the transistor M4 is set to be larger than that of the transistor M2 in order to quickly set the potential of the node A to the threshold voltage Vth. ing. After the node A reaches the threshold voltage Vth, the transistor M4 is turned off by the fourth gate control means VC4. After that, only the transistor M2 becomes the load of the third transistor M5.

The third transistor M5 is an n-channel MOS type. As described above, the gate of the third transistor M5 is connected to the fifth gate control means VC5 together with the drain of the first transistor M6. The on / off of the sense amplifier SA1 is controlled by the fifth gate control means VC5. The source of the third transistor M5 is connected to the gate of the first transistor M6 and is coupled to the node A (that is, the first conductive path). Such a circuit connection between the third transistor M5 and the first transistor M6 forms a well-known negative feedback. As a result, the amplification degree of the sense amplifier SA1 is set to a predetermined magnitude, and the potential of the first conductive path is stabilized.

The transistors M2 and the third transistor M5 play the role of the second amplification means of the sense amplifier SA1 and are connected in series with the first amplification means. The common connection points of the transistors M2 and the third transistor M5, that is, the drains of these transistors are connected to the input end of the inverter INV1. The output OUT of the sense amplifier SA1 is taken out via the inverter INV1. The inverter INV1 also serves as a third amplification means including, for example, a CMOS inverter.

The second transistor M14 is also one of the features of the sense amplifier SA1 and is prepared for measuring a negative threshold voltage in the test mode of the non-volatile semiconductor storage device NVM1. The drain of the second transistor M14 is connected to the source of the first transistor M6. The source of the second transistor M14 is connected to the ground potential GND. The gate of the second transistor M14 is connected to the third gate control means VC3. In the normal mode of the non-volatile semiconductor storage device NVM1, the source of the first transistor M6 is always coupled to the ground potential GND via the second transistor M14. As a result, in the normal mode, data is written, read, and erased in the memory cell MC1, and the sense amplifier SA1 amplifies the data signals. On the other hand, in the test mode, the second transistor M14 is always set to off.

The memory cell MC1 includes a column selection transistor M7, a bit selection transistor M8, a memory transistor M9, a second selection transistor M10, and a third selection transistor M11.

The column selection transistor M7 and the bit selection transistor M8 are connected in series to form a composite transistor. In the present specification, such a composite transistor is referred to as a first-choice transistor.

The bit selection transistor M8 selects one bit line from a plurality of memory cells. The drain of the bit selection transistor M8 is connected to the source of the column selection transistor M7. The source of the bit selection transistor M8 is connected to the drain of the memory transistor M9. The gate of the bit selection transistor M8 is connected to the word line WL. Although FIG. 1 shows only one memory cell MC1, that is, one bit, the actual non-volatile semiconductor storage device NVM1 includes, for example, 128 bits, that is, 128 memory cells.

The column selection transistor M7 selects a plurality of bit lines together, that is, a bit line of a predetermined bit (for example, 8 bits) as one unit. The drain of the column selection transistor M7 is connected to the node A (that is, the first conductive path). The source of the column selection transistor M7 is connected to the drain of the bit selection transistor M8. The gate of the column selection transistor M7 is connected to the column selection gate CG1.

The bit selection transistor M8 is indispensable in this type of non-volatile semiconductor storage device, but the column selection transistor M7 is not always indispensable. Therefore, whether or not to prepare the column selection transistor M7 is one of the selective items.

The pad PAD1 is prepared to apply a predetermined potential, that is, a first supply potential Vpad1, to the control gate CG9 of the memory transistor M9 when measuring the threshold voltage of the memory transistor M9. The first supply potential Vpad1 is set to a variable potential. The memory transistor M9 is a non-volatile memory transistor and is a storage element that is the main body of the EEPROM.

The second selection transistor M10 plays a role as a so-called ground selection transistor for coupling the source of the memory transistor M9 to the ground potential GND. The drain of the second selection transistor M10 is connected to the source of the memory transistor M9. The source of the second selection transistor M10 is connected to the ground potential GND. The gate of the second selection transistor M10 is connected to the first gate control means VC1.

When the second selection transistor M10 is placed in the ON state, the first selection transistor (column selection transistor M7, bit selection transistor M8), the memory transistor M9, and the memory transistor M9 are placed between the bit line BL of the memory cell MC1 and the ground potential GND. A series conductive path composed of the second selection transistor M10 is formed. When the second selection transistor M10 is placed in the off state, the formation of the conductive path in series is cut off.

The third selection transistor M11 is an n-channel type MOS transistor, the drain is connected to the pad PAD1, the source S is connected to the control gate CG9 of the memory transistor M9, and the gate is the node D, that is, the word. It is connected to the line WL. The third selection transistor M11 is generally referred to as a byte selection transistor. Since the byte selection transistor can collectively select 8 bits of a 1-bit memory cell, it is used, for example, when erasing data in 1-byte units.

When the non-volatile semiconductor storage device NVM1 is placed in the normal mode, a voltage suitable for writing, reading, and erasing data to the memory transistor M9 is applied to the pad PAD1 from a circuit (not shown). ..

On the other hand, when measuring the negative threshold voltage Vth2 of the memory transistor M9 in the test mode of the non-volatile semiconductor storage device NVM1, the pad PAD1 is stepped, for example, in the range of 2V to 0V, for example, 0.1V. Potential is applied. Details will be described later.

The fourth selection transistor M12, the fifth selection transistor M13, and the pad PAD2 are prepared for measuring the negative threshold voltage Vth2 of the memory transistor M9 of the non-volatile semiconductor storage device NVM1. In the test mode of the non-volatile semiconductor storage device NVM1, that is, when measuring the threshold voltage of the memory transistor M9, the fourth selection transistor M12 maintains the source of the memory transistor M9, that is, the node C at a predetermined potential. It is prepared in. Further, the fifth selection transistor M13 is prepared to increase the potential of the first conductive path, that is, the node A in the test mode of the non-volatile semiconductor storage device NVM1 within a range that does not affect the dynamic range of the sense amplifier SA1. There is.

When the fifth selection transistor M13 is placed in the ON state in the test mode, the potential of the node A becomes (Vpad2 + Vth). Here, Vth is the threshold voltage of the first transistor M6, and the second supply potential Vpad2 is applied to the pad PAD2. Since the second transistor M14 is placed in the ON state, the potential of the node A in the normal mode is substantially the same as the threshold voltage Vth of the first transistor M6. Therefore, the potential of the node A in the test mode is increased by the second supply potential Vpad2 as compared with the normal mode. The potential thus increased is applied to the drain of the memory transistor M9 via the first selection transistor (column selection transistor M7 and bit selection transistor M8). As a result, a potential sufficient to normally measure the negative threshold voltage Vth2 is provided between the drain and the source of the memory transistor M9.

Both the fourth selection transistor M12 and the fifth selection transistor M13 are composed of an n-channel type MOS transistor. In this way, the fourth selection transistor M12 is selected so as to be of the same conductive type as the third selection transistor M11, and the physical sizes such as the channel length and channel width of both transistors M11 and M12 are also selected. It has been. As a result, the threshold voltage between the gate and source of both transistors M11 and M12 becomes almost equal, and the on-resistance becomes almost equal. Therefore, when the same gate voltage is applied to both transistors M11 and M12, the respective drain voltages are used. The voltage drops that occur between the sources are equal.

It is extremely important to set the voltage drop (threshold value) between the gate and source of the third selection transistor M11 and the fourth selection transistor M12 to be equal in the measurement of the negative threshold voltage Vth2. This is because, when measuring the negative threshold voltage Vth2 of the memory transistor M9, the control gate CG9 of the memory transistor M9 is first supplied from the pad PAD1 via the conductive path of the drain source of the third selection transistor M11. This is because the potential Vpad1 is applied and the second supply potential Vpad2 is applied to the source of the memory transistor M9 from the pad PAD2 via the conductive path of the drain source of the fourth selection transistor M12, respectively. This is because if the voltage drops (threshold values) in the conduction path of the gate and source are equal, the difference between the first supply potential Vpad1 and the second supply potential Vpad2 can be regarded as the negative threshold voltage Vth2.

When, for example, a 2V second supply potential Vpad2 is applied to the pad PAD2, 2V is supplied to the drains of the fourth selection transistor M12 and the fifth selection transistor M13. At this time, when a high potential is applied to the second gate control means VC2 connected to the gates of both transistors M12 and M13, both transistors M12 and M13 are turned on.

The pad PAD2 and the drains of the fourth selection transistor M12 and the fifth selection transistor M13 are commonly connected. The source of the fourth selection transistor M12, the source of the memory transistor M9 (node C), and the drain of the second selection transistor M10 are commonly connected. The source of the second selection transistor M10 is connected to the ground potential GND. The source of the fifth selection transistor M13, the source of the first transistor M6, and the drain of the second transistor M14 are commonly connected.

In the test mode of the non-volatile semiconductor storage device NVM1, the pad PAD2 determines the source potential of the memory transistor M9, and also determines the drain voltage of the memory cell MC1, that is, the node A (first conductive path), and thus the sense amplifier SA1. It is also the reference voltage that determines the bias voltage of.

When a voltage is applied to the drain of a miniaturized n-channel MOS transistor, a high electric field region is formed in the vicinity of the drain. When carriers flow into this region, the carriers obtain high energy due to the electric field and become hot carriers. Some of them scatter phonons, and some lose energy due to impact ionization. However, hot carriers with enough energy to overcome the silicon-silicon oxide potential barrier are injected into the gate oxide film, causing fluctuations in the threshold voltage and transconductance of MOS transistors. ..

It is known that when rewriting to a memory cell, that is, writing and erasing data is repeated, the above phenomenon gradually progresses, and the threshold voltage of the memory cell gradually fluctuates. Further, it is known that when a memory cell is manufactured on a semiconductor substrate, the gate oxide film pressure and the like vary due to variations in the manufacturing process, and the threshold value of the memory cell also varies to some extent. ..

FIG. 2 is a diagram schematically showing a change in the threshold voltage of the memory cell depending on the number of times the memory cell is rewritten. The horizontal axis (logarithmic axis) indicates the number of times the memory cell is rewritten Nw, and the vertical axis indicates the change in the positive threshold voltage Vth1 and the negative threshold voltage Vth2 of the memory cell.

Normally, there is a difference between the threshold voltage when the data "1" is written in the memory cell and the threshold voltage when the data "0" is written in the memory cell. Since the threshold voltage when the data "0" is written is usually 0 V or less, it is also generally referred to as "negative threshold voltage". Further, since the threshold voltage when the data "1" is written usually exceeds 0V, it is generally called "positive threshold voltage".

In FIG. 2, the positive threshold voltage Vth1 indicates the threshold voltage when the data “1” is written to the memory transistor M9 constituting the memory cell MC1. On the other hand, the negative threshold voltage Vth2 indicates the threshold voltage when the data “0” is written to the memory transistor M9.

It is known that the positive threshold voltage Vth1 gradually decreases as the number of rewrites Nw increases. Here, the number of rewrites Nw is the total number of times data is written (written) and erased in the memory cell MC1. The minimum value Vth1 (min) and the maximum value Vth1 (max) of the positive threshold voltage Vth1 also naturally decrease as the number of rewrites Nw increases. However, it is known that the distribution Dth1 of the threshold voltage Vth1 is almost the same as the initial distribution even if the number of writes Nw increases. Therefore, as shown in FIG. 2, the minimum value Vth1 (min) and the maximum value Vth1 (max) of the positive threshold voltage Vth1 also decrease with the same distribution width as the number of rewrites Nw increases. As a matter of course, the same thing can be seen from the median value Vth1 (cent) and the average value Vth1 (ave) of the distribution Dth1.

On the other hand, it is known that the negative threshold voltage Vth2 gradually increases as the number of rewrites Nw increases. As a matter of course, the maximum value Vth2 (max) and the minimum value Vth2 (min) of the negative threshold voltage Vth2 also increase as the number of rewrites Nw increases. However, it is known that the distribution Dth2 of the threshold voltage Vth2 is almost the same as the initial distribution even if the number of rewrites Nw increases. Therefore, as shown in FIG. 2, the maximum value Vth2 (max) and the minimum value Vth2 (min) of the negative threshold voltage Vth2 also increase with the same distribution width as the number of rewrites Nw increases. As a matter of course, the same thing can be seen from the median value Vth2 (cent) and the average value Vth2 (ave) of the distribution Dth2.

The read voltage Vw shown in FIG. 2 indicates a voltage at which the data stored in the memory cell MC1 of the non-volatile semiconductor storage device NVM1 is read. Since the read voltage Vw reads two data of data "0" and data "1", both are based on the distribution Dth1 of the positive threshold voltage Vth1 and the distribution Dth2 of the negative threshold voltage Vth2. It will be set to a value almost in the middle of the distribution of. When the read voltage Vw is biased to either the positive threshold voltage distribution Dth1 or the negative threshold voltage distribution Dth2, the maximum number of rewrites Nw (max) decreases and is non-volatile. The life of the sex semiconductor storage device NVM1 is shortened.

In setting the read voltage Vw, the minimum value Vth1 (min) of the positive threshold voltage is obtained based on the distribution Dth1 of the positive threshold voltage, and based on the distribution Dth2 of the negative threshold voltage. , The maximum value Vth2 (max) of the negative threshold voltage may be obtained, and the read voltage Vw may be set as Vw = (Vth1 (min) + Vth2 (max)) / 2 from each value.

As another setting method, the average value Vth1 (ave) of the positive threshold voltage is obtained based on the distribution Dth1 of the positive threshold voltage, and the distribution Dth2 of the negative threshold voltage is used as the basis. It is also possible to obtain the average value Vth2 (ave) of the negative threshold voltage and set the read voltage Vw from each value as Vw = (Vth1 (ave) + Vth2 (ave)) / 2. Is.

As yet another setting method, the median value Vth1 (cent) of the positive threshold voltage is obtained based on the distribution Dth1 of the positive threshold voltage, and the distribution Dth2 of the negative threshold voltage is set. Based on this, the median value Vth2 (ce n) of the negative threshold voltage can be obtained, and the read voltage Vw can be set as Vw = (Vth1 (cen) + Vth2 (cen)) / 2 from each value. It is possible.

The method for setting the read voltage Vw is not limited to the above three methods. For example, it may be a combination of the above three. For example, it can be set with reference to the minimum value Vth1 (min) of the positive threshold voltage and the average value Vth2 (ave) of the negative threshold voltage. In any case, the read voltage Vw is set in consideration of the distribution states Dth1 and Dth2 of the positive and negative threshold voltages, respectively.

FIG. 3 is a timing chart of the main nodes at the time of measuring the negative threshold voltage Vth2 of the memory cell MC1. Hereinafter, FIG. 3 will be described with reference to FIG.

The stage (a) of FIG. 3 shows the temporal transition of the first supply potential Vpad1 applied to the pad PAD1. The first supply potential Vpad1 plays the role of a measurement input potential for measuring the negative threshold voltage Vth2 of the memory cell MC1. The first supply potential Vpad1 is maintained in a period from time t0 to time t4, for example, 2V. After that, the voltage is adjusted to 1.9 V at time t4 and 1.8 V at time t5 so as to gradually decrease in 0.1 V steps. The section from time t6 to time t7 is omitted for convenience of explanation and drawing. When the time t7 is reached, the first potential supply potential Vpad1 is adjusted to 0.3V, 0.2V at the time t8, 0.1V at the time t9, and 0V at the time t10.

The stage (b) of FIG. 3 shows the temporal transition of the second supply potential Vpad2 applied to the pad PAD2. The second supply potential Vpad2 serves as a reference potential for measuring the negative threshold voltage Vth2 of the memory cell MC1. When the time t1 is reached, the second supply potential Vpad2 is maintained at a fixed potential of, for example, 2 V in the section up to the time t10 when the measurement of the negative threshold voltage Vth2 is completed.

Stage (c) of FIG. 3 shows the potential of node A. The magnitude and timing of the potential generated at the node A follows the second supply potential Vpad2 applied to the pad PAD2. Therefore, when the second supply potential Vpad2 reaches the time t2 shortly after the rising time t1, the potential of the node A is fixed at (Vpad2 + Vth). Here, Vth is the threshold voltage between the gate and source of the first transistor M6.

The stage (d) of FIG. 3 shows the potential of the node B (= the gate of the memory transistor M9). The magnitude and timing of the potential generated in the node B follow the magnitude and timing of the potential applied to the first supply potential Vpad1 applied to the pad PAD1 and the wordline WL (= node D). Therefore, it becomes 2V at time t3, 1.9V at time t4, and 1.8V at time t5. Even at the subsequent time, the potential follows the potential applied to the pad PAD1, and its magnitude becomes the same as that of the first supply potential Vpad1.

The stage (e) in FIG. 3 shows the potential of the node C. The magnitude and timing of the potential generated in the node C follow the magnitude and rising timing of the second supply potential Vpad2 applied to the pad PAD2. Therefore, when the time t2 is reached, the potential of the node C becomes 2V, and this potential is maintained in the subsequent sections.

Stage (f) of FIG. 3 shows the high potential VPP of node D. The potential applied to the node D, that is, the word line WL is set to a potential sufficient to sufficiently turn on the third selection transistor M11. The high potential VPP of node D is, for example, 15V to 17V.

The stage (g) of FIG. 3 is based on the premise that the memory transistor M9 has transitioned from the off state to the on state or from the on state to the off state depending on the potential of the node B shown in the stage (d) of FIG. It shows a negative threshold voltage Vth2. That is, in the section from time t3 to t4, when the potential of the node B is 2V, the negative threshold voltage Vth2 when the memory transistor M9 transitions from the off state to the on state is 0V. ing. Similarly, at time t4 to t5, time t5 to t6, time t7 to t8, time t8 to t9, and time t9 to t10, the negative value when the memory transistor M9 transitions from the off state to the on state. The threshold voltage Vth2 is measured as −0.1V, −0.2V, -1.7V, -1.8V, and -1.9V, respectively. Since the negative threshold voltage Vth2 cannot be measured at times t0 to t3 until the potential of the node B rises, it is undefined.

On the other hand, when measuring the positive threshold voltage Vth1 of the memory transistor M9 of the memory cell MC1, the first selection transistor (column selection transistor M7, bit selection transistor M8), the second selection transistor M10, and the third selection transistor M11 are used. Turn on. Further, the 4th selection transistor 12 and the 5th selection transistor M13 are set to the off state, respectively. That is, the potential supply to the pad PAD2 is cut off, the first supply potential Vpad1 is variablely applied to the pad PAD1, and the transition of the on / off state of the memory transistor M9 is detected and measured by the sense amplifier SA1.

FIG. 4 shows the first supply potential Vpad1 as a so-called measurement input potential applied to the pad PAD1 shown in FIG. 3 not on the time axis but on the number of measurements. In FIG. 3, the horizontal axis is the time axis. For example, in the stage (d) of FIG. 3, the potential of the node B transitions to 2V at time t3, and the potential of node B is 2. It showed a state of rapid transition from 0V to 1.9V. However, in the actual measurement, after applying the first supply potential Vpad1V of 2.0 V to the memory transistor M9, the negative threshold voltage Vth2 is once measured, and after the measurement is completed, the first supply potential Vpad1 is set to 1. It is variable to 9V. These measurements are performed with the first measurement at a potential of 2.0 V, the second measurement at a potential of 1.9 V, the third measurement at a potential of 1.8 V, and thereafter, the first supply potential Vpad1 is 0.3 V, 0. The measurements at .2V, 0.1V, and 0V can be seen as the 18th, 19th, 20th, and 21st measurements, respectively. FIG. 4 shows the variable state of the first supply potential Vpad1 from such a viewpoint.

What is shown in FIG. 4 shows a state in which the potential applied to the pad PAD1 is changed from 2.0 V to 0 V in 0.1 V steps when measuring the negative threshold voltage Vth2. Therefore, the number of measurements is 21 from 1 to 21. The 21 measurements are the maximum number of measurements for one chip. In the first measurement, that is, in the first measurement, the first supply potential Vpad1 is set to 2.0 V. At this time, the transition of the memory transistor M9 in the on / off state is measured on the sense amplifier SA1 side. If the on / off transition of the memory transistor M9 is measured at a potential of 2.0 V, the negative threshold voltage Vth2 becomes 0 V. If the reversal of the operation at the potential of 2.0 V is not detected, the potential is lowered to 1.9 V, the reversal state of the operation of the memory transistor M9 is confirmed again, and this operation is continued. If the 18th measurement, that is, when the inversion of the operation of the memory transistor M9 is confirmed at the first supply potential Vpad1 = 0.3V, the negative threshold voltage Vth2 becomes -1.7V. Similarly, the negative threshold voltage Vth2 when the inverted state of the operation of the memory transistor M9 is detected in the 21st inning, which is the final inning, becomes −2.0V. As described above, the number of times the negative threshold voltage Vth2 is measured is at least once and at most 21 times.

In order to accurately know the distribution state of the negative threshold voltage Vth2, it is conceivable to widen the range of the first supply potential Vpad1 applied to the pad PAD1 and to reduce the measurement step potential. Be done. In any case, these choices will be determined with an acceptable measurement time in mind.

FIG. 5 shows the potential states of the main nodes and the on / off states of the main transistors when the non-volatile semiconductor storage device NVM1 shown in FIG. 1 is used in the test mode and the normal mode.

First, in the test mode, that is, in the operating state of measuring the threshold voltage of the memory transistor M9 constituting the memory cell MC1, it depends on whether the positive threshold voltage Vth1 or the negative threshold voltage Vth2 is measured. , The potential of the main node and the on / off state of the main transistor are different.

When measuring the positive threshold voltage Vth1 in the test mode, the pad PAD1 has, for example, a first supply potential Vpad1 of 2V to 4V, for example, 2V, 2.1V, 2.2V, ..., 3.8V. , 3.9V, 4.0V, etc. are applied in 0.1V steps. At this time, the pad PAD2 is not intended for use, and is placed in an open state, for example.

At this time, the potential of the node A is substantially equal to the threshold voltage Vth of the first transistor M6. To be precise, the voltage on the drain side of the second transistor M14 is added, but such a voltage is considered to be negligible as compared with the threshold voltage Vth.

Further, the potential of the node B, that is, the potential of the control gate CG9 of the memory transistor M9 becomes substantially equal to the first supply potential Vpad1 applied to the pad PAD1. To be precise, the voltage between the drain and the source of the third selection transistor M11 (byte selection transistor) is lower than that of the first supply potential Vpad1, but the magnitude of such a voltage is also ignored.

Further, the potential of the node C, that is, the source potential of the memory transistor M9 becomes 0V, which is substantially equal to the ground potential GND. This is because the second selection transistor M10 is placed in the ON state.

Further, the potential of the node D, that is, the potential of each gate (= wordline WL) of the first selection transistor M8 and the third selection transistor M11 (byte selection transistor) is placed in the high potential VPP.

When measuring the positive threshold voltage Vth1 in the test mode, the fourth selection transistor M12, the fifth selection transistor M13, the first selection transistor M7 (column selection transistor), the second selection transistor M10, and the second selection transistor M10. Transistors M14 are turned off, off, on, on, and on, respectively, as shown in FIG. Further, both the first-selection transistor M8 and the third-selection transistor M11 are turned on.

On the other hand, when measuring the negative threshold voltage Vth2 in the test mode, the pad PAD1 has, for example, a first supply potential Vpad1 of 2V to 0V, for example, 2V, 1.9V, 1.8V, ..., 0. It is applied in 0.1V steps such as .2V, 0.1V, 0V.

At this time, a fixed potential of 2V is given as the second supply potential Vpad2 applied to the pad PAD2. That is, the first supply potential Vpad1 applied to the pad PAD1 is selected to be lower than the second supply potential Vpad2 applied to the pad PAD2. By having a potential relationship of such a magnitude, it is possible to measure the negative threshold voltage Vth2 of the memory transistor M9 without using the negative potential supply means.

At this time, the potential of the node A is obtained by adding the second supply potential Vpad2 applied to the pad PAD2 to the threshold voltage Vth of the first transistor M6 (Vpad2 + Vth). The increased potential of the node A (= first conductive path) is applied to the drain D of the memory transistor M9 via the first selection transistor (column selection transistor M7, bit selection transistor M8). This makes it possible to measure the negative threshold voltage Vth2 of the memory transistor M9. If the potential of the node A is lower than the source potential of the memory transistor M9 (= second supply potential Vpad2), the measurement of the negative threshold voltage Vth2 of the memory transistor M9 becomes insufficient.

Further, the potential of the node B, that is, the potential of the control gate CG9 of the memory transistor M9 becomes equal to the first supply potential Vpad1, and the potential is changed in the range of 2V to 0V.

Further, the potential of the node C, that is, the source potential of the memory transistor M9 is placed at 2V, which is substantially equal to the potential of the pad PAD2.

Further, as the potential of the node D, that is, the potential of the gate (= wordline WL) of the third selection transistor M11 (byte selection transistor), a high potential VPP is given as in the measurement of the positive threshold voltage Vth1. Has been done.

When measuring the negative threshold voltage Vth2 in the test mode, the fourth selection transistor M12, the fifth selection transistor M13, the first selection transistor M7 (column selection transistor), the second selection transistor M10, and the second selection transistor M10. As shown in FIG. 5, the transistor M14 (second transistor) is turned on, on, on, off, and off, respectively. Further, both the first-selection transistor M8 and the third-selection transistor M11 are turned on. Therefore, when the negative threshold voltage Vth2 is measured, the positive threshold voltage Vth1 is measured with the exception of the first-selection transistors M7 and M8 and the third-selection transistor M11. The on / off states are reversed from each other.

When the non-volatile semiconductor storage device NVM1 shown in FIG. 1 is used in the normal mode, the conditions are different from those in the test mode. In the normal mode, the memory cell MC1 is subjected to three operations of reading, writing (writing), or erasing (erasing) data. In any case, the pad PAD1 and the pad PAD2 are used. Not subject to use (not used). Therefore, the 4th selection transistor M12 and the 5th selection transistor M13 are always in the off state. Looking at each one in a little more detail, it is as follows.

In reading in the normal mode, the potential of the node A, that is, the gate potential of the first transistor M6 constituting the input stage of the operational amplifier SA1, is substantially equal to the threshold voltage Vth between the gate and the source. To be precise, the voltage on the drain side of the second transistor M14 is added to the potential of the node A, but such a voltage is considered to be negligible as compared with the threshold voltage Vth.

The potential of the node B, that is, the potential of the control gate CG9 of the memory transistor M9 is given a predetermined potential determined from the distribution of the positive threshold voltage Vth1 and the distribution of the negative threshold voltage Vth2. Here, the predetermined potential corresponds to the read-out voltage Vw shown in FIG. The read voltage Vw is set for each chip. For example, as shown in FIG. 2, the read voltage Vw is a value set to the magnitude of Vw = (Vth1 (min) + Vth2 (max)) / 2. be.

The potential of the node C, that is, the source potential of the memory transistor M9 becomes 0V, which is substantially equal to the ground potential GND. This is because the second selection transistor M10 is placed in the ON state.

The power supply potential VCS is given as the potential of the node D, that is, the potential of the gate (= wordline WL) of each of the first selection transistor M8 (bit selection transistor) and the third selection transistor M11 (byte selection transistor). ..

The operating states of the 4th selection transistor M12, the 5th selection transistor M13, the 1st selection transistor M7 (column selection transistor), the 2nd selection transistor M10, and the 2nd selection transistor M14 at the time of reading in the normal mode are shown in FIG. As shown, they will be placed off, off, on, on, and on, respectively.

In writing (writing) in the normal mode, the potential of the node A, that is, the gate potential of the first transistor M6 constituting the input stage of the operational amplifier SA1 is set to 0V, which is substantially equal to the ground potential GND. The potential of the node B, that is, the potential of the control gate CG9 of the memory transistor M9 is also set to approximately 0V. The potential of the node C, that is, the source potential of the memory transistor M9 is placed in the open state. A high potential VPP is given as the potential of the node D, that is, as the gate potential of each of the gates (= wordline WL) of the first selection transistor M8 and the third selection transistor M11 (byte selection transistor).

At the time of writing (writing) in the normal mode, the operating states of the 4th selection transistor M12, the 5th selection transistor M13, the 1st selection transistor M7 (column selection transistor), the 2nd selection transistor M10, and the 2nd selection transistor M14 are As shown in FIG. 5, they will be placed off, off, off, off, and on, respectively.

In the erasure (erase) in the normal mode, the potential of the node A, that is, the gate potential of the first transistor M6 (first transistor) constituting the input stage of the sense amplifier SA1 becomes approximately 0V. The potential of the node B, that is, the potential of the control gate CG9 of the memory transistor M9 is placed in the high potential VPP in order to pull out the electrons accumulated in the floating gate FG to the ground potential GND side. The potential of the node C, that is, the source potential of the memory transistor M9 is naturally set to about 0 V in order to guide the electrons accumulated in the floating gate FG9 of the memory transistor M9 to the ground potential GND side. A high potential VPP is given as the potential of the node D, that is, the potential of each gate (= wordline WL) of the first selection transistor M8 (bit selection transistor) and the third selection transistor M11 (byte selection transistor). ..

At the time of erasing (erasing) in the normal mode, the operating states of the 4th selection transistor M12, the 5th selection transistor M13, the 1st selection transistor M7 (column selection transistor), the 2nd selection transistor M10, and the 2nd selection transistor M14 are As shown in FIG. 5, they will be placed off, off, off, on, and on, respectively.

Although FIG. 1 illustrates a memory cell MC1 including one non-volatile memory transistor M9, a configuration in which a plurality of non-volatile memory transistors M9 are connected in series, for example, a NAND flash memory It can also be applied to the measurement of positive and negative threshold voltages.

As described above, the non-volatile semiconductor storage device NVM1 has an extremely small number of additional elements (fourth selection transistor M12 of memory cell MC1, fifth selection transistor M13, pad PAD2, and sense amplifier SA1) as compared with the conventional configuration. The second transistor M14) makes it possible to measure the positive and negative threshold voltages of the memory cell MC1.

<Consideration on read voltage>
In order to maximize the number of rewrites Nw of the memory cell MC1, a positive threshold voltage Vth1 (= threshold voltage when data "1" is written in the memory cell MC1) and a negative threshold are used. It is essential to set the read voltage Vw to an intermediate value (= average value) with the value voltage Vth2 (= threshold voltage when data “0” is written in the memory cell MC1).

However, when the threshold voltages Vth1 and Vth2 are shifted from their respective representative values due to manufacturing variations of the memory cell MC1, an intermediate value between the two is set in advance as the read voltage Vw (= fixed value). Therefore, the maximum number of rewrites Nw (max) of the memory cell MC1 is reduced. Hereinafter, a specific description will be given with reference to FIGS. 6A to 6C.

FIG. 6A is a diagram showing the maximum number of rewrites Nw (max) when the threshold voltages Vth1 and Vth2 are both representative values (= when not shifted). In the case of this figure, the intermediate value (= (Vth1 + Vth2) / 2) of the threshold voltage Vth1 and Vth2 and the preset read-out voltage Vw match. Therefore, the maximum number of rewrites Nw (max) does not fall below the intended number of times.

FIG. 6B is a diagram showing how the maximum number of rewrites Nw (max) decreases when the threshold voltages Vth1 and Vth2 are shifted upward from their respective representative values. As shown in this figure, when the intermediate value of the threshold voltages Vth1 and Vth2 becomes higher than the read voltage Vw, the negative threshold voltage Vth2 exceeds the read voltage Vw with a smaller number of rewrites Nw than in the case of FIG. 6A. Will be. Therefore, the maximum number of rewrites Nw (max) is reduced by that amount.

FIG. 6C is a diagram showing how the maximum number of rewrites Nw (max) decreases when the threshold voltages Vth1 and Vth2 are shifted downward from their respective representative values. As shown in this figure, when the intermediate value of the threshold voltages Vth1 and Vth2 becomes lower than the read voltage Vw, the positive threshold voltage Vth1 falls below the read voltage Vw with a smaller number of rewrites Nw than in the case of FIG. 6A. Will be. Therefore, the maximum number of rewrites Nw (max) is reduced by that amount.

<Non-volatile semiconductor storage device with read voltage correction function>
In order to improve the decrease in the maximum number of rewrites Nw (max) as described above, the non-volatile semiconductor storage device provided with the read voltage correction function will be proposed below.

FIG. 7 is a diagram showing a configuration example of a non-volatile semiconductor storage device having a read voltage correction function. The non-volatile semiconductor storage device 1 in this figure includes a normal memory 10, a dummy memory 20, a sense amplifier 30, a logic unit 40, and a read voltage setting unit 50.

The normal memory 10 is a non-volatile storage block (= corresponding to the first memory) in which data can be arbitrarily rewritten, and is formed by a plurality of memory cells 11 (*) (however, * = 0, 1, ...). ing. Since the internal configuration and operation of the memory cell 11 (*) are the same as those of the memory cell MC1 in FIG. 1, duplicated description is omitted.

The dummy memory 20 has a memory cell 11 (*) at the outer edge so that the characteristics of the memory cell 11 (*) do not vary between the central portion and the outer edge of the area where the normal memory 10 is formed (this figure). In the example of, the dummy memory cell 21 formed adjacent to the memory cell 11 (0)) is included. Since the internal configuration and operation of the dummy memory cell 21 are the same as those of the memory cell MC1 in FIG. 1, duplicated description is omitted.

In general, a dummy memory whose characteristics tend to vary is often not used, but in the non-volatile semiconductor storage device 1 of this configuration example, a set value of a read voltage Vw usually applied to the memory 10 is stored. The dummy memory 20 is actively used as the non-volatile storage block (= corresponding to the second memory). By adopting such a configuration, it is possible to introduce the read voltage correction function without unnecessarily increasing the chip area of the non-volatile semiconductor storage device 1. However, as a means for storing the set value of the read voltage Vw, it is also possible to separately incorporate an OTPROM [one time programmable read only memory] or the like.

The work of calculating the set value of the read voltage Vw and writing it to the dummy memory 20 may be performed in advance at the time of product shipment or the like as the initial setting work of the non-volatile semiconductor storage device 1. This will be described later.

The input node A (see FIG. 1) of the sense amplifier 30 is connected to the memory cell 11 (*) and the dummy memory cell 21 (particularly the drain of each bit selection transistor M8) via the column selection transistor M7 and the bit line BL. It is connected and functions as a means for selectively reading data from both the normal memory 10 and the dummy memory 20. The data read by the sense amplifier 30 is output as a read signal S1 from the output node OUT of the sense amplifier 30 to the logic unit 40. Since the internal configuration and operation of the sense amplifier 30 are the same as those of the sense amplifier SA1 of FIG. 1, duplicated description is omitted.

The logic unit 40 is a means for controlling the overall operation of the non-volatile semiconductor storage device 1. In particular, as an operation related to the read voltage correction function, the read voltage Vw from the dummy memory 20 is set before the data is read from the normal memory 10. The set value is read, and the control signal S2 is generated according to the read signal S1 (= set value of the read voltage Vw) input from the sense amplifier 30 at that time. The operation will be described in detail later.

The read voltage setting unit 50 sets the read voltage Vw according to the control signal S2 input from the logic unit 40. The configuration and operation of the read voltage setting unit 50 will be described below.

<Read voltage setting unit>
FIG. 8 is a diagram showing a configuration example of the read voltage setting unit 50. The read-out voltage setting unit 50 of this configuration example includes an MOSFET [N-channel type metal oxide semiconductor field effect transistor] 51 to 55, current sources 56 and 57, and a variable resistor 58. NMOSFETs 51, 52 and 55 are all enhancement types, and NMOSFETs 53 and 54 are depletion types.

The first end of the current source 56 is connected to the power supply potential. The second end of the current source 56 is connected to the drain of the NMOSFET 51. The gates of the NMOSFETs 51 and 52 are connected to the drain of the NMOSFET 51. The sources of NMOSFETs 51 and 52 are connected to the ground potential, respectively.

The first end of the current source 57 is connected to the power supply potential. The second end of the current source 57 is connected to the gate of the NMOSFET 53 and the first end of the variable resistor 58. The second end of the variable resistor 58 is connected to the ground potential. The control end of the variable resistor 58 is connected to the input node of the control signal S2.

The drain of the NMOSFET 53 is connected to the power supply potential. The drain of the NMOSFET 52 and the source of the NMOSFET 53 are connected to the drain of the NMOSFET 54. The source of the NMOSFET 54 and the drain of the NMOSFET 55 are connected to the output node of the read voltage Vw. The source of the NMOS ET55 is connected to the ground potential. The gate of the NMOSFET 54 is connected to the input node of the control voltage Va. The gate of the NMOSFET 55 is connected to the input node of the control voltage Vb.

In the read voltage setting unit 50 having the above configuration, the resistance value of the variable resistor 58 is variably controlled according to the control signal S2. When the resistance value of the variable resistor 58 is raised, the node voltage V51 appearing at the first end of the variable resistor 58 becomes high, so that the node voltage V52 appearing at the drain of the NMOSFET 54 also becomes high. On the contrary, when the resistance value of the variable resistor 58 is lowered, the node voltage V51 becomes low, so that the node voltage V52 also becomes low.

When the control voltage Va is set to a high level and the control voltage Vb is set to a low level, the NMOSFET 54 is turned on and the NMOSFET 55 is turned off. Therefore, the node voltage V52 is output as the read voltage Vw. On the other hand, when the control voltage Va is set to a low level and the control voltage Vb is set to a high level, the NMOSFET 54 is turned off and the NMOSFET 55 is turned on. Therefore, the read voltage Vw is fixed to the ground potential without depending on the node voltage V52. In this way, the read voltage setting unit 50 switches whether or not to output the read voltage Vw according to the control voltages Va and Vb.

<Initial setting work>
In the initial setting work of the non-volatile semiconductor storage device 1, it is necessary to calculate the set value of the read voltage Vw and store it in the dummy memory 20 in advance. Hereinafter, a series of initial setting operations will be specifically described.

First, with a plurality of memory cells 11 (*) as measurement targets, the positive threshold voltage Vth1 and the negative threshold voltage Vth2 are measured, and the respective distributions Dth1 and Dth2 are acquired. Since this measurement work has been described so far with reference to FIGS. 1 to 5, duplicate explanations will be omitted.

Next, the set value of the read voltage Vw is calculated so that the read voltage Vw is set to an intermediate value (= (Vth1 + Vth2) / 2) between the positive threshold voltage Vth1 and the negative threshold voltage Vth2. .. For example, the above set value may be calculated as a correction value (offset value or correction coefficient) for shifting the read voltage Vw up and down from a predetermined reference value (for example, 1 V).

Finally, the set value of the read voltage Vw calculated above is stored in the dummy memory 20. The above set value is common to all the memory cells 1 (*) forming the normal memory 10. Therefore, the dummy memory cell 21 for storing this needs only a few bits.

<Read voltage correction operation>
FIG. 9 is a flowchart showing an example of the read voltage correction operation in the non-volatile semiconductor storage device 1. On the left side of the alternate long and short dash line, the operation of the non-volatile semiconductor storage device 1 seen from the user side (outside the device) is shown with step numbers (S11 and S12) in the 10s. On the other hand, on the right side of the alternate long and short dash line, the operations automatically performed inside the non-volatile semiconductor storage device 1 are indicated by step numbers (S21 to S24) in the 20s. Further, in this figure, the solid line arrow indicates the new flow (= with the read voltage correction function), and the broken line arrow indicates the conventional flow (= without the read voltage correction function).

When the read operation code is input from the outside of the non-volatile semiconductor storage device 1 in step S11, the flow shifts to step S21, and the data of the dummy memory 20 (= the set value of the read voltage Vw) is read by the sense amplifier 30. .. As described above with reference to FIG. 7, in step S21, the dummy word line WLd connected to the dummy memory 20 is set to a high level, and all the word lines WL * connected to the normal memory 10 are low. It is considered to be a level. As a result, the data in the dummy memory 20 is read out by the sense amplifier 30.

Since data is not basically rewritten for the dummy memory 20, it is not necessary to consider deterioration due to repeated rewriting operations. Therefore, it is sufficient to set the read voltage Vd of the dummy memory 20 to a predetermined fixed value (for example, 1 V).

Next, in step S22, the read voltage Vw is corrected via the logic unit 40. At this time, it is desirable that the logic unit 40 completes the data reading operation from the dummy memory 20 and the correction operation of the reading voltage Vw during the input period of the read operation code. For that purpose, regardless of the content of the operation code input from the outside of the device, the flow may shift to step S21 when the chip select signal is input from the outside of the device. Since the operation of setting the read voltage Vw according to the control signal S2 has already been explained with reference to FIG. 8, duplicated explanations will be omitted.

Next, in step S23, the data in the normal memory 10 is read out by the sense amplifier 30. For example, a case where data is read from the memory cell 11 (0) will be described with reference to FIG. 7 above. In this case, in step S23, the word line WL0 connected to the memory cell 11 (0) is set to the high level, and the remaining word lines WL1, WL2 ... Are all set to the low level. Further, as the read voltage V0 of the memory cell 11 (0), the read voltage Vw corrected in step S22 is applied. On the other hand, the dummy word line WLd connected to the dummy memory 20 is set to a low level. As a result, the data stored in the memory cell 11 (0) is read out by the sense amplifier 30.

Finally, in step S24, the data of the normal memory 10 is output via the logic unit 40, and then in step S12, the data is output to the outside of the device, so that the series of operations is completed.

In this way, the read voltage correction operation is performed every time the read operation code is input. Therefore, the set value of the read voltage Vw can be refreshed one by one every time the opportunity to read the data from the normal memory 10 occurs, so that it is not necessary to worry about unintended data garbled of the set value due to noise or the like.

However, the execution timing of the read voltage correction operation is not limited to this. For example, when the non-volatile semiconductor storage device 1 is started for the first time, the set value of the read voltage Vw is stored in the register, and thereafter. , The data read operation of the normal memory 10 may be performed by continuously using the read voltage Vw corrected based on the register value.

10A and 10B are diagrams showing how the read voltage Vw is appropriately corrected when the threshold voltages Vth1 and Vth2 are shifted upward and downward, respectively. The left half of each figure shows the state when the read voltage Vw is a fixed value (= no read voltage correction function, corresponding to FIGS. 6B and 6C above), and the right half of each figure. Describes the state when the read voltage Vsw is a variable value (= with the read voltage correction function).

As shown in FIG. 10A, when the threshold voltages Vth1 and Vth2 are shifted upward, the read voltage Vw is also shifted upward from the reference value. Therefore, since the intermediate value (= (Vth1 + Vth2) / 2) of the threshold voltages Vth1 and Vth2 and the corrected read voltage Vw match, the maximum number of rewrites Nw (max) can be maintained at the intended number. can.

Further, as shown in FIG. 10B, when the threshold voltages Vth1 and Vth2 are shifted downward, the read voltage Vw is also shifted downward from the reference value. Therefore, since the intermediate values of the threshold voltages Vth1 and Vth2 and the corrected read voltage Vw match, the maximum number of rewrites Nw (max) can be maintained at the intended number as in FIG. 10A.

As described above, in the non-volatile semiconductor storage device 1 provided with the read voltage correction function, even when the threshold voltages Vth1 and Vth2 are shifted from their respective representative values due to manufacturing variations of the normal memory 10 and the like. , The number of rewrites Nw can be maximized. Therefore, it is possible to extend the life of the non-volatile semiconductor storage device 1 (for example, guarantee 1 million times → guarantee 4 million times).

<Other variants>
In addition to the above-described embodiment, the various technical features disclosed in the present specification can be modified in various ways without departing from the spirit of the technical creation. That is, it should be considered that the above-described embodiment is exemplary in all respects and is not restrictive, and the technical scope of the present invention is not limited to the above-described embodiment, and claims for a patent. It should be understood that the meaning equal to the scope and all changes belonging to the scope are included.

According to the invention disclosed in the present specification, the life of the non-volatile semiconductor storage device can be extended, so that the industrial applicability is extremely high.

BL Bitline CG1 Column Selection Gate CUM Karen Mirror Circuit Dth1 Positive Threshold Voltage Distribution Dth2 Negative Threshold Voltage Distribution Im2 Output Current INV1 Inverter M1 to M4 Transistor M5 Third Transistor M6 First Transistor M7 First Selection Transistor (column selection transistor)
M8 1st selection transistor (bit selection transistor)
M9 Memory Transistor M10 Second Selection Transistor M11 Third Selection Transistor (Byte Selection Transistor)
M12 4th selection transistor M13 5th selection transistor M14 2nd transistor NVM1 Non-volatile semiconductor storage device Nw Number of rewrites Nw (max) Maximum number of rewrites MC1 Memory cell OUT output PAD1 1st potential supply means PAD2 2nd potential supply means R1 Resistance SA1 Sense amplifier VC1 1st gate control means VC2 2nd gate control means VC3 3rd gate control means VC4 4th gate control means VC5 5th gate control means VCC power supply potential Vpad1 1st supply potential Vpad2 2nd supply potential VPP high potential Vth Threshold voltage Vth1 Positive threshold voltage Vth1 (ave) Average value of positive threshold voltage Vth1 (cent) Median value of positive threshold voltage Vth1 (max) Maximum value of positive threshold voltage Vth1 (Min) Minimum value of positive threshold voltage Vth2 Negative threshold voltage Vth2 (ave) Average value of negative threshold voltage Vth2 (cent) Median value of negative threshold voltage Vth2 (max) Negative Maximum value of threshold voltage Vth2 (min) Minimum value of negative threshold voltage Vw Read voltage WL Wordline 1 Non-volatile semiconductor storage device 10 Normal memory 11 (0), 11 (1) Memory cell 20 Dummy memory 21 Dummy memory cell 30 Sense amplifier 40 Logic unit 50 Read voltage setting unit 51-55 NMOSFET
56, 57 Current source 58 Variable resistor

Claims (9)

The first memory that can rewrite the data arbitrarily,
A second memory that stores the set value of the read voltage applied to the first memory, and
A sense amplifier for reading data from both the first memory and the second memory, and
A logic unit that reads the set value from the second memory and generates a control signal before reading the data from the first memory.
A read voltage setting unit that sets the read voltage according to the control signal, and a read voltage setting unit.
Have a,
The plurality of memory cells forming the first memory are each
Memory transistors with control gates, floating gates, sources, and drains,
A first-choice transistor with a source connected to the drain of the memory transistor, a drain connected to the bitline, and a gate connected to the wordline.
A second-select transistor in which the drain is connected to the source of the memory transistor, the source is connected to the ground potential, and the gate is connected to the first gate control means.
Including
The control gate of the memory transistor is connected to the first pad via the third selection transistor, and the source of the memory transistor is connected to the second pad via the fourth selection transistor.
A non-volatile semiconductor storage device in which the voltage drop generated between the drain and source of the third selection transistor is equal to the voltage drop generated between the drain and source of the fourth selection transistor. The read voltage is intermediate between the threshold voltage when data "1" is written to the memory cell of the first memory and the threshold voltage when data "0" is written to the memory cell. The non-volatile semiconductor storage device according to claim 1 , which is set to a value. It said second memory is a dummy memory formed adjacent to the first memory, a nonvolatile semiconductor memory device according to claim 1 or claim 2. The logic unit completes the read operation of the set value during the input period of the opcode, the nonvolatile semiconductor memory device according to any one of claims 1 to 3. The set value, the read voltage is a correction value for correcting the predetermined reference value, the nonvolatile semiconductor memory device according to any one of claims 1 to 4. It said second read voltage applied to the memory is a fixed value, the nonvolatile semiconductor memory device according to any one of claims 1 to 5. Claims 1 to 6 further include a fifth selection transistor in which the source is connected to the input stage of the sense amplifier, the drain is connected to the second pad, and the gate is connected to the second gate control means. The non-volatile semiconductor storage device according to any one of the above. In the test mode for measuring the threshold voltage of the memory transistor, the first supply potential applied to the first pad is a variable value, and the second supply potential applied to the second pad is an indefinite value or fixed. The non-volatile semiconductor storage device according to claim 7, which is a value. The initial setting method for the non-volatile semiconductor storage device according to claim 8.
The first selection transistor, the second selection transistor, and the third selection transistor are turned on, the fourth selection transistor and the fifth selection transistor are turned off, and the second pad is not used. The step of measuring the positive threshold voltage of the memory transistor by detecting the transition of the on / off state of the memory transistor with the sense amplifier while changing the first supply potential;
The first selection transistor, the third selection transistor, the fourth selection transistor, and the fifth selection transistor are turned on, the second selection transistor is turned off, the second supply potential is fixed, and the second supply potential is fixed. A step of measuring the negative threshold voltage of the memory transistor by detecting the transition of the on / off state of the memory transistor with the sense amplifier while changing the first supply potential in a range lower than this. ;
With the step of calculating the set value so that the read voltage is set to an intermediate value between the positive threshold voltage and the negative threshold voltage;
With the step of storing the set value in the second memory;
The a, initial setting method of a nonvolatile semiconductor memory device.

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