JP6978669B2 - Compound semiconductor equipment and its manufacturing method, as well as receiving equipment and power generation equipment - Google Patents

Description

The present invention relates to a compound semiconductor device, a method for manufacturing the same, a receiving device, and a power generation device.

Schottky diodes are active elements used in wireless communication receivers and power generators. As an active element having higher detection sensitivity and conversion efficiency, a backward diode utilizing the interband tunnel phenomenon is suitable. In order to improve the efficiency of the diode, it is effective to reduce the area of the junction to suppress the junction capacitance. In a normal mesa type diode, there is a limit to the reduction of the junction, so a method of making an active element into nanowires is used. For example, a nanowired tunnel diode formed by bonding n-InAs and p-GaAsSb to a GaAs (111) B substrate is formed. According to this diode, it is possible to reduce the area of the pn junction.

Japanese Unexamined Patent Publication No. 2011-233714 Japanese Patent Publication No. 2008-505476

In nanowire tunnel diodes, InAs-based nanowires grow on a GaAs substrate, so it is necessary to make ohmic contact with GaAs to form electrodes. As a metal that makes ohmic contact with GaAs, there are AuGe (lower layer) / Ni (intermediate layer) / Au (upper layer) using AuGe.

In order to diffuse AuGe's Ge into GaAs and form ohmic contact, it is necessary to perform heat treatment. Normally, AuGe can be brought into ohmic contact with GaAs by performing a heat treatment at 350 ° C to 450 ° C.

However, this heat treatment can be problematic for active elements. When forming a nanowire tunnel diode as an active element, an InAs-based nanowire is grown by, for example, the Vapor-Liquid-Solid method (VLS method) using, for example, an Au catalyst. Therefore, the Au catalyst remains at the tip of the nanowire. When heat treatment for forming ohmic contact is performed in this state, there is a concern that the Au catalyst reacts with the nanowires and causes destabilization of the operation of the nanowire tunnel diode.

The present invention is a compound semiconductor device that does not require heat treatment to obtain ohmic contact between nanowires and a metal layer, reliably forms ohmic contact without burdening the active element, and contributes to stable operation of the active element. It is an object of the present invention to provide the manufacturing method.

In one embodiment, the compound semiconductor device comprises an active element and a nanowire assembly comprising a plurality of nanowires having an In-containing compound semiconductor that is ohmically contacted with a metal, electrically connected to the active element. It is provided with a metal layer that covers the upper surface and the side surface of the nanowire assembly with the metal.

In one embodiment, a method of manufacturing a compound semiconductor device includes the steps of forming an active element, said being active element electrically connected, the plurality of nanowires with a compound semiconductor containing In contact metal ohmic It includes a step of forming the provided nanowire aggregate and a step of forming a metal layer covering the upper surface and the side surface of the nanowire aggregate with the metal.

On one aspect, a compound semiconductor device that does not require heat treatment to obtain ohmic contact between the nanowire and the metal layer, reliably forms ohmic contact without burdening the active element, and contributes to stable operation of the active element. Will be realized.

It is the schematic sectional drawing which shows the manufacturing method of the compound semiconductor apparatus by 1st Embodiment in the order of a process. Continuing from FIG. 1, it is a schematic cross-sectional view which shows the manufacturing method of the compound semiconductor apparatus by 1st Embodiment in process order. Continuing from FIG. 2, it is a schematic cross-sectional view which shows the manufacturing method of the compound semiconductor apparatus by 1st Embodiment in process order. Continuing from FIG. 3, it is a schematic cross-sectional view which shows the manufacturing method of the compound semiconductor apparatus by 1st Embodiment in process order. It is a schematic sectional drawing which shows the main process of the manufacturing method of the compound semiconductor apparatus by the modification of 1st Embodiment. It is the schematic sectional drawing which shows the main process of the manufacturing method of the compound semiconductor apparatus by 2nd Embodiment. Continuing from FIG. 6, it is a schematic cross-sectional view which shows the main process of the manufacturing method of the compound semiconductor apparatus by 2nd Embodiment. Continuing from FIG. 7, it is a schematic cross-sectional view which shows the main process of the manufacturing method of the compound semiconductor apparatus by 2nd Embodiment. It is a schematic sectional drawing which shows the main process of the manufacturing method of the compound semiconductor apparatus by the modification of 2nd Embodiment. It is a schematic sectional drawing which shows the main process of the manufacturing method of the compound semiconductor apparatus by 3rd Embodiment. Continuing from FIG. 10, it is a schematic cross-sectional view which shows the main process of the manufacturing method of the compound semiconductor apparatus by 3rd Embodiment. It is a schematic sectional drawing which shows the main process of the manufacturing method of the compound semiconductor apparatus by 4th Embodiment. Continuing from FIG. 12, it is a schematic cross-sectional view which shows the main process of the manufacturing method of the compound semiconductor apparatus by 4th Embodiment. Continuing from FIG. 13, it is a schematic cross-sectional view which shows the main process of the manufacturing method of the compound semiconductor apparatus by 4th Embodiment. It is a schematic diagram which shows the schematic structure of the radio wave receiving device by 5th Embodiment. It is a schematic diagram which shows the schematic structure of the power conversion module by 6th Embodiment.

[First Embodiment]
Hereinafter, the first embodiment will be described. In this embodiment, a compound semiconductor device including a nanowire tunnel diode as an active element is exemplified, and its configuration and manufacturing method will be described in detail with reference to the drawings.
1 to 4 are schematic cross-sectional views showing the manufacturing method of the compound semiconductor device according to the first embodiment in the order of processes.

First, as shown in FIG. 1A, the conductive layer 2 and the insulating film 3 are sequentially formed on the substrate 1.
Specifically, for example, a semi-insulating GaAs (111) B substrate is prepared as the substrate 1. ^{N +} −GaAs is grown on the substrate 1 to form the conductive layer 2. The conductive layer 2 is formed to have an impurity concentration of n-type impurities (Si, Ge, etc.) of ^{about 5 × 10 18} / cm ² and a thickness of about 200 nm.
Next, for example, a silicon oxide film is formed on the conductive layer 2 to a thickness of about 50 nm to form the insulating film 3.

Subsequently, as shown in FIG. 1B, openings 3a and 3b are formed in the insulating film 3.
Specifically, a resist is applied onto the insulating film 3 to form an opening that exposes the nanowire forming region of the insulating film 3, for example, by electron beam (EB) lithography. Using this resist as a mask, openings 3a and 3b that expose a part of the surface of the conductive layer 2 are formed in a plurality of nanowire forming regions of the insulating film 3 by dry etching. The openings 3a and 3b are formed to have a predetermined size of about 100 nm or less. The opening 3a is formed in the element forming region 10a, which is the forming region of the nanowire tunnel diode which is an active element. The openings 3b, in this case the plurality of openings 3b, are formed side by side with the ohmic forming region 10b, which is a nanowire forming region for forming ohmic contact of the electrodes. The resist is removed by a wet treatment or an ashing treatment.

Subsequently, as shown in FIG. 1 (c), the Au catalyst 4 is formed.
Specifically, in order to grow nanowires described later, an Au catalyst 4 having a thickness of about 30 nm is formed in the openings 3a and 3b by vapor deposition and lift-off.

Subsequently, as shown in FIG. 2A, various nanowires are grown.
Specifically, first, for example, using the Vapor-Liquid-Solid method (VLS method), n-InAs having a predetermined diameter of 100 nm or less is placed in the openings 3a and 3b of the insulating film 3 with a length of about 0.5 μm. It grows only in the vertical direction. The growing material contains In and is a compound semiconductor that makes ohmic contact with a metal, and for example, n-InGaAs may be used instead of n-InAs. As a result, the n-type compound semiconductor nanowires 5a are formed in the device forming region 10a, and a plurality of n-type compound semiconductor nanowires 6 are formed in the ohmic forming region 10b in the same step. Since n-InAs and the like have different lattice constants from n-GaAs, it is difficult to grow by normal thin film growth, but they can grow into n-GaAs by nanowire formation.

Following the growth of n-InAs, p-GaAsSb having a predetermined diameter of 100 nm or less is grown only in the vertical direction to a length of about 0.5 μm. As the growing material, for example, p-GaSb or p-AlGaSb may be used instead of p-GaAsSb. As a result, the p-type compound semiconductor nanowire 5b bonded to the n-type compound semiconductor nanowire 5a is formed in the device forming region 10a. Similarly, the p-type compound semiconductor nanowire 5b is formed on each n-type compound semiconductor nanowire 6 in the ohmic formation region 10b. At the junction between the n-type compound semiconductor nanowire 5a and the p-type compound semiconductor nanowire 5b, the doping concentration is adjusted so that the nanowire tunnel diode operates as a backward diode.

Subsequently, as shown in FIG. 2B, the resist mask 20 is formed.
Specifically, two layers of resists having different sensitivities are applied. The lower layer resist 20a is applied so as to cover only the n-type compound semiconductor nanowires 5a and 6. The upper layer resist 20b is a resist having a higher sensitivity than the lower layer resist 20a, and is applied so as to cover only the p-type compound semiconductor nanowire 5b. Only the ohmic forming region 10b side of the upper resist 20b is removed by lithography to form an opening 20A that exposes the p-type compound semiconductor nanowire 5b on the ohmic forming region 10b side. As a result, the resist mask 20 having the opening 20A is formed.

Subsequently, as shown in FIG. 2C, the p-type compound semiconductor nanowire 5b on the ohmic formation region 10b side is removed.
Specifically, the resist mask 20 is used to etch and remove the p-type compound semiconductor nanowires 5b on the ohmic forming region 10b side exposed from the opening 20A. The resist mask 20 is removed by a wet treatment or an ashing treatment. As described above, the nanowire tunnel diode 5 in which the n-type compound semiconductor nanowire 5a and the p-type compound semiconductor nanowire 5b are pn-junctioned to stand on the conductive layer 2 is formed in the element forming region 10a. In the ohmic forming region 10b, a plurality of n-type compound semiconductor nanowires 6 standing side by side on the conductive layer 2 are formed. The n-type compound semiconductor nanowire 6 is electrically connected to the nanowire tunnel diode 5 via the conductive layer 2.

Subsequently, as shown in FIG. 3A, the metal layer 7 is formed.
Specifically, first, a resist mask (not shown) is formed by covering the nanowire tunnel diode 5 in the device forming region 10a and exposing the n-type compound semiconductor nanowire 6 in the ohmic forming region 10b.
Next, for example, Ti (lower layer) / Pt (intermediate layer) / Au (upper layer) is deposited on the entire surface as a metal to a thickness of about 10 nm / about 30 nm / about 300 nm. By lift-off, the resist mask and Ti / Pt / Au on it are removed. As a result, a metal layer 7 is formed in the ohmic forming region 10b by covering the upper surface and the side surface of each n-type compound semiconductor nanowire 6 with Ti / Pt / Au.

Here, since n-InAs of the n-type compound semiconductor nanowire 6 has a low work function with respect to the metal and the difference between the work functions of the two is small, the metal in contact with the n-type compound semiconductor nanowire 6 is automatically applied without heat treatment. Ohmic contact is formed. In this embodiment, ohmic contact is formed between the metal layer 7 and the n-type compound semiconductor nanowire 6 without heat treatment. Where the Au catalyst 4 remains on the crown of the nanowire tunnel diode 5, heat treatment for ohmic contact is not required. Therefore, the reaction between the Au catalyst 4 and the nanowire tunnel diode 5 due to the heat treatment is prevented, which contributes to the stable operation of the nanowire tunnel diode 5.

Further, the n-type compound semiconductor nanowire 6 is an ultrafine structure, and the contact area is insufficient only by covering the upper surface of the metal layer, and ohmic contact is insufficient. In the present embodiment, the metal layer 7 covers the upper surface and the side surface of the n-type compound semiconductor nanowire 6 to the lower portion of the side surface very close to the conductive layer 2. Therefore, a contact area as large as possible is secured, and sufficient ohmic contact can be obtained.

Subsequently, as shown in FIG. 3 (b), the passivation film 8 is formed.
Specifically, for example, using a resin such as BCB, the nanowire tunnel diode 5 and the n-type compound semiconductor nanowire 6 are deposited to a thickness to be embedded to form the passivation film 8.

Subsequently, as shown in FIG. 3C, the surface of the passivation film 8 is etched back.
Specifically, a gas containing F is used to etch back the surface of the passivation film 8 until the Au catalyst 4 on the crown of the nanowire tunnel diode 5 is exposed. As a result, the surface of the passivation film 8 is flattened, and the Au catalyst 4 is exposed from the flat surface.

Subsequently, as shown in FIG. 4A, a contact hole 8a is formed in the passivation membrane 8.
Specifically, a resist mask (not shown) is formed by photolithography to open a portion located above the metal layer 7 which is a contact hole forming region of the passivation film 8. Using this resist mask, the passivation film 8 is etched with a gas containing F and O until the surface of the metal layer 7 under the opening of the resist mask is exposed. The resist mask is removed by wet treatment or ashing treatment. As a result, the contact hole 8a is formed in the passivation film 8.

Subsequently, as shown in FIG. 4B, the anode electrode 9 and the cathode electrode 11 are formed.
Specifically, first, a resist that opens an anode electrode forming region (a region above the nanowire tunnel diode 5 including the Au catalyst 4) and a cathode electrode forming region (a region including the contact hole 8a) on the surface of the passivation film 8. Form a mask (not shown).

Next, using this resist mask, for example, Au is formed as an electrode material in the opening of the resist mask by a plating method, for example. By removing the resist mask, the anode electrode 9 is electrically connected to the nanowire tunnel diode 5 via the Au catalyst 4, and the cathode electrode is electrically connected to the metal layer 7 by embedding the contact hole 8a with Au. 11 and are formed. As described above, the compound semiconductor device according to the present embodiment is formed.

As described above, according to the present embodiment, no heat treatment is required to obtain ohmic contact between the n-type compound semiconductor nanowire 6 and the metal film 7. Therefore, ohmic contact is surely formed on the nanowire tunnel diode 5 without burden, and a compound semiconductor device that contributes to the stable operation of the nanowire tunnel diode 5 is realized.

(Modification example)
Hereinafter, a modified example of the first embodiment will be described. In this example, a compound semiconductor device including a nanowire tunnel diode as an active element is exemplified as in the first embodiment, but it differs from the first embodiment in that the formation mode of ohmic contact is different.
FIG. 5 is a schematic cross-sectional view showing a main step of a method for manufacturing a compound semiconductor device according to a modified example of the first embodiment.

First, the same steps as those in FIGS. 1 (a) to 1 (c) of the first embodiment are performed to form the Au catalyst 4 in the openings 3a and 3b of the insulating film 3.
Subsequently, as shown in FIG. 5A, various nanowires are grown.
Specifically, first, for example, using the Vapor-Liquid-Solid method (VLS method), n-InAs having a predetermined diameter of 100 nm or less is placed in the openings 3a and 3b of the insulating film 3 with a length of about 0.5 μm. It grows only in the vertical direction. The growing material contains In and is a compound semiconductor that makes ohmic contact with a metal, and for example, n-InGaAs may be used instead of n-InAs. As a result, the n-type compound semiconductor nanowires 5a are formed in the device forming region 10a, and a plurality of n-type compound semiconductor nanowires 5a are formed in the ohmic forming region 10b in the same step.

Following the growth of n-InAs, p-GaAsSb having a predetermined diameter of 100 nm or less is grown only in the vertical direction to a length of about 0.5 μm. As the growing material, for example, p-GaSb or p-AlGaSb may be used instead of p-GaAsSb. As a result, the p-type compound semiconductor nanowire 5b bonded to the n-type compound semiconductor nanowire 5a is formed in the device forming region 10a. Similarly, the p-type compound semiconductor nanowire 5b is formed on each n-type compound semiconductor nanowire 5a in the ohmic formation region 10b. At the junction between the n-type compound semiconductor nanowire 5a and the p-type compound semiconductor nanowire 5b, the doping concentration is adjusted so that the nanowire tunnel diode operates as a backward diode.

As described above, the nanowire tunnel diode 5 in which the n-type compound semiconductor nanowire 5a and the p-type compound semiconductor nanowire 5b are pn-junctioned is formed in the device forming region 10a. In the ohmic formation region 10b, a plurality of compound semiconductor nanowires 21 formed by joining n-type compound semiconductor nanowires 5a and p-type compound semiconductor nanowires 5b are formed. The compound semiconductor nanowire 21 is electrically connected to the nanowire tunnel diode 5 via the conductive layer 2.

Subsequently, as shown in FIG. 5B, the metal layer 22 is formed.
Specifically, first, a resist mask (not shown) that covers the nanowire tunnel diode 5 in the device forming region 10a and exposes the compound semiconductor nanowire 21 in the ohmic forming region 10b is formed.
Next, for example, Ti (lower layer) / Pt (intermediate layer) / Au (upper layer) is deposited on the entire surface as a metal to a thickness of about 10 nm / about 30 nm / about 300 nm. By lift-off, the resist mask and Ti / Pt / Au on it are removed. As a result, the metal layer 22 covering the upper surface and the side surface of the compound semiconductor nanowire 21 with Ti / Pt / Au is formed in the ohmic forming region 10b.

Here, the work function of n-InAs of the n-type compound semiconductor nanowire 5a of the compound semiconductor nanowire 21 is lower than that of the metal, and the difference between the work functions of the two is small. Therefore, ohmic contact is automatically formed with the metal in contact with the n-type compound semiconductor nanowire 5a without heat treatment. In this example, ohmic contact is formed between the metal layer 22 and the n-type compound semiconductor nanowire 5a of the compound semiconductor nanowire 21 without heat treatment. On the other hand, the metal layer 22 and the p-type compound semiconductor nanowire 5b of the compound semiconductor nanowire 21 are in a shotky-like state, but the current mainly flows through ohmic contact on the n-type compound semiconductor nanowire 5a side.

Where the Au catalyst 4 remains on the crown of the nanowire tunnel diode 5, heat treatment for ohmic contact is not required. Therefore, the reaction between the Au catalyst 4 and the nanowire tunnel diode 5 due to the heat treatment is prevented, which contributes to the stable operation of the nanowire tunnel diode 5.

Further, the n-type compound semiconductor nanowire 5a is an ultrafine structure, and the contact area is insufficient only by covering the upper surface of the metal layer, and ohmic contact is insufficient. In this example, the metal layer 22 covers the upper surface and the side surface of the compound semiconductor nanowire 21 to the lower portion of the side surface of the n-type compound semiconductor nanowire 5a very close to the conductive layer 2. Therefore, a contact area as large as possible is secured, and sufficient ohmic contact can be obtained.

In this example, in the ohmic forming region 10b, ohmic contact with the metal layer 22 is ensured by the n-type compound semiconductor nanowire 5a without removing the p-type compound semiconductor nanowire 5b formed on the n-type compound semiconductor nanowire 5a. Therefore, the lithography process and the etching process for removing the p-type compound semiconductor nanowire 5b become unnecessary, and the process can be reduced.

Subsequently, various steps similar to those in FIGS. 3 (b) to 4 (b) of the first embodiment are performed, and as shown in FIG. 5 (c), the compound semiconductor device according to this example is formed.

As described above, according to this example, the cathode electrode of the nanowire tunnel diode 5 between the n-type compound semiconductor nanowire 5a of the compound semiconductor nanowire 21 and the metal film 7 does not require heat treatment for obtaining ohmic contact. be. Therefore, ohmic contact is surely formed on the nanowire tunnel diode 5 without burden, and a compound semiconductor device that contributes to the stable operation of the nanowire tunnel diode 5 is realized.

[Second Embodiment]
Hereinafter, the second embodiment will be described. In this embodiment, a compound semiconductor device including a nanowire tunnel diode as an active element is exemplified as in the first embodiment, but it differs from the first embodiment in that the formation mode of ohmic contact is different.
6 to 8 are schematic cross-sectional views showing the main steps of the method for manufacturing the compound semiconductor device according to the second embodiment.

First, the conductive layer 2 and the insulating film 3 are sequentially formed on the substrate 1 in the same manner as in FIG. 1 (a) of the first embodiment.
Subsequently, as shown in FIG. 6A, openings 3a and 3c are formed in the insulating film 3.
Specifically, a resist is applied onto the insulating film 3 to form an opening that exposes the nanowire forming region of the insulating film 3, for example, by electron beam (EB) lithography. Using this resist as a mask, openings 3a and 3c that expose a part of the surface of the conductive substrate 1 are formed in a plurality of nanowire forming regions of the insulating film 3 by dry etching. The opening 3a is formed in the element forming region 10a, which is the forming region of the nanowire tunnel diode which is an active element, in a predetermined size having a diameter of about 100 nm or less. The opening 3c is formed over the ohmic forming region 10b, which is a nanowire forming region for forming ohmic contact of the electrodes. The resist is removed by a wet treatment or an ashing treatment.

Subsequently, as shown in FIG. 6 (b), the Au catalyst 4 is formed.
Specifically, in order to grow nanowires to be described later, an Au catalyst 4 having a thickness of about 30 nm is formed in the openings 3a and 3c by vapor deposition and lift-off. The opening 3c is formed so that a plurality of Au catalysts 4 come into contact with each other side by side in the opening 3c.

Subsequently, as shown in FIG. 6 (c), various nanowires are grown.
Specifically, first, for example, using the VLS method, n-InAs having a predetermined diameter of 100 nm or less is grown in the openings 3a and 3c of the insulating film 3 only in the vertical direction to a length of about 0.5 μm. The growing material contains In and is a compound semiconductor that makes ohmic contact with a metal, and for example, n-InGaAs may be used instead of n-InAs. As a result, the n-type compound semiconductor nanowires 5a are formed in the device forming region 10a, and a plurality of n-type compound semiconductor nanowires 12 are formed in the ohmic forming region 10b in the same step. In the ohmic formation region 10b, adjacent n-type compound semiconductor nanowires 12 are formed in contact with each other on the side surface.

Following the growth of n-InAs, p-GaAsSb having a predetermined diameter of 100 nm or less is grown only in the vertical direction to a length of about 0.5 μm. As the growing material, for example, p-GaSb or p-AlGaSb may be used instead of p-GaAsSb. As a result, the p-type compound semiconductor nanowire 5b bonded to the n-type compound semiconductor nanowire 5a is formed in the device forming region 10a. Similarly, the p-type compound semiconductor nanowire 5b is formed on each n-type compound semiconductor nanowire 12 in the ohmic formation region 10b. In the ohmic formation region 10b, adjacent p-type compound semiconductor nanowires 5b are formed in contact with each other on the side surfaces, similarly to the n-type compound semiconductor nanowires 12. At the junction between the n-type compound semiconductor nanowire 5a and the p-type compound semiconductor nanowire 5b, the doping concentration is adjusted so that the nanowire tunnel diode operates as a backward diode.

Subsequently, as shown in FIG. 7A, the resist mask 20 is formed.
Specifically, two layers of resists having different sensitivities are applied. The lower layer resist 20a is applied so as to cover only the n-type compound semiconductor nanowires 5a and 12. The upper layer resist 20b is a resist having a higher sensitivity than the lower layer resist 20a, and is applied so as to cover only the p-type compound semiconductor nanowire 5b. Only the ohmic forming region 10b side of the upper resist 20b is removed by lithography to form an opening 20A that exposes the p-type compound semiconductor nanowire 5b on the ohmic forming region 10b side. As a result, the resist mask 20 having the opening 20A is formed.

Subsequently, as shown in FIG. 7B, the p-type compound semiconductor nanowire 5b on the ohmic formation region 10b side is removed.
Specifically, the resist mask 20 is used to etch and remove the p-type compound semiconductor nanowires 5b on the ohmic forming region 10b side exposed from the opening 20A. The resist mask 20 is removed by a wet treatment or an ashing treatment. As described above, the nanowire tunnel diode 5 in which the n-type compound semiconductor nanowire 5a and the p-type compound semiconductor nanowire 5b are pn-junctioned to stand on the conductive layer 2 is formed in the element forming region 10a. In the ohmic forming region 10b, a plurality of n-type compound semiconductor nanowires 12 standing side by side on the conductive layer 2 are formed. The plurality of n-type compound semiconductor nanowires 12 are in contact with adjacent objects on the side surfaces to form a nanowire aggregate 31, and are electrically connected to the nanowire tunnel diode 5 via the conductive layer 2.

Subsequently, as shown in FIG. 8A, the metal layer 32 is formed.
Specifically, first, a resist mask (not shown) that covers the nanowire tunnel diode 5 in the device forming region 10a and exposes the nanowire aggregate 31 in the ohmic forming region 10b is formed.

Next, for example, Ti (lower layer) / Pt (intermediate layer) / Au (upper layer) is deposited on the entire surface as a metal to a thickness of about 10 nm / about 30 nm / about 300 nm. By lift-off, the resist mask and Ti / Pt / Au on it are removed. As a result, the metal layer 32 that covers the upper surface and the side surface of the nanowire assembly 31 with Ti / Pt / Au is formed in the ohmic forming region 10b.

Here, since n-InAs of the n-type compound semiconductor nanowire 12 has a low work function with respect to the metal and the difference between the work functions of the two is small, the metal in contact with the n-type compound semiconductor nanowire 12 is automatically applied without heat treatment. Ohmic contact is formed. In this embodiment, ohmic contact is formed between the metal layer 32 and the nanowire assembly 31 without heat treatment. Where the Au catalyst 4 remains on the crown of the nanowire tunnel diode 5, heat treatment for ohmic contact is not required. Therefore, the reaction between the Au catalyst 4 and the nanowire tunnel diode 5 due to the heat treatment is prevented, which contributes to the stable operation of the nanowire tunnel diode 5.

Further, the n-type compound semiconductor nanowire 12 is an ultrafine structure, and the contact area is insufficient only by covering the upper surface of the metal layer, and ohmic contact is insufficient. In the present embodiment, the metal layer 32 covers the upper surface and the side surface of the nanowire assembly 31 in which a plurality of n-type compound semiconductor nanowires 12 are assembled to the lower portion of the side surface extremely close to the conductive layer 2. Therefore, a contact area as large as possible is secured, and sufficient ohmic contact can be obtained.

Subsequently, various steps similar to those in FIGS. 3 (b) to 4 (b) of the first embodiment are performed, and as shown in FIG. 8 (b), the compound semiconductor device according to the present embodiment is formed.

In this embodiment, the case where adjacent n-type compound semiconductor nanowires 6 are in contact with each other to form a nanowire aggregate 31 is illustrated, but the following (1) or (2) may be used, for example.
(1) Adjacent Au catalysts 4 are formed slightly apart in the opening 3c, and nanowire aggregates are established with adjacent n-type compound semiconductor nanowires 12 slightly separated (there may be a portion in contact with each other). Form like this.
(2) When forming openings in the element forming region 10a of the insulating film 3, a plurality of fine openings are formed so as to be densely formed, and the nanowire aggregates are slightly separated from each other by the adjacent n-type compound semiconductor nanowires 12 (2). (There may be some parts that come into contact with each other).

As described above, according to the present embodiment, no heat treatment is required to obtain ohmic contact between the n-type compound semiconductor nanowire 12 of the nanowire assembly 31 and the metal layer 32. Therefore, ohmic contact is surely formed on the nanowire tunnel diode 5 without burden, and a compound semiconductor device that contributes to the stable operation of the nanowire tunnel diode 5 is realized.

(Modification example)
Hereinafter, a modified example of the second embodiment will be described. In this example, a compound semiconductor device including a nanowire tunnel diode as an active element is exemplified as in the second embodiment, but it differs from the second embodiment in that the formation mode of ohmic contact is different.
FIG. 9 is a schematic cross-sectional view showing a main step of a method for manufacturing a compound semiconductor device according to a modified example of the second embodiment.

First, the same steps as in FIGS. 1 (a) of the first embodiment and FIGS. 6 (a) to 6 (b) of the second embodiment are performed in the openings 3a and 3c of the insulating film 3. The Au catalyst 4 is formed.

Subsequently, as shown in FIG. 9A, various nanowires are grown.
Specifically, first, for example, using the VLS method, n-InAs having a predetermined diameter of 100 nm or less is grown in the openings 3a and 3c of the insulating film 3 only in the vertical direction to a length of about 0.5 μm. The growing material contains In and is a compound semiconductor that makes ohmic contact with a metal, and for example, n-InGaAs may be used instead of n-InAs. As a result, the n-type compound semiconductor nanowires 5a are formed in the device forming region 10a, and a plurality of n-type compound semiconductor nanowires 13 are formed in the ohmic forming region 10b in the same step. In the ohmic formation region 10b, adjacent n-type compound semiconductor nanowires 13 are formed in contact with each other on the side surface.

Following the growth of n-InAs, p-GaAsSb having a predetermined diameter of 100 nm or less is grown only in the vertical direction to a length of about 0.5 μm. As the growing material, for example, p-GaSb or p-AlGaSb may be used instead of p-GaAsSb. As a result, the p-type compound semiconductor nanowire 5b bonded to the n-type compound semiconductor nanowire 5a is formed in the device forming region 10a. Similarly, the p-type compound semiconductor nanowire 14 is formed on each n-type compound semiconductor nanowire 13 in the ohmic formation region 10b. In the ohmic formation region 10b, adjacent p-type compound semiconductor nanowires 5b are formed in contact with each other on the side surfaces, similarly to the n-type compound semiconductor nanowires 5a. At the junction between the n-type compound semiconductor nanowire 5a and the p-type compound semiconductor nanowire 5b, the doping concentration is adjusted so that the nanowire tunnel diode operates as a backward diode.

As described above, the nanowire tunnel diode 5 in which the n-type compound semiconductor nanowire 5a and the p-type compound semiconductor nanowire 5b are pn-junctioned is formed in the device forming region 10a. In the ohmic formation region 10b, a plurality of compound semiconductor nanowires 21 formed by joining n-type compound semiconductor nanowires 13 and p-type compound semiconductor nanowires 14 are formed. The plurality of compound semiconductor nanowires 21 are in contact with adjacent objects on the side surfaces to form nanowire aggregates 41, and are electrically connected to the nanowire tunnel diode 5 via the conductive layer 2.

Subsequently, as shown in FIG. 9B, the metal layer 42 is formed.
Specifically, first, a resist mask (not shown) that covers the nanowire tunnel diode 5 in the device forming region 10a and exposes the nanowire aggregate 41 in the ohmic forming region 10b is formed.
Next, for example, Ti (lower layer) / Pt (intermediate layer) / Au (upper layer) is deposited on the entire surface as a metal to a thickness of about 10 nm / about 30 nm / about 300 nm. By lift-off, the resist mask and Ti / Pt / Au on it are removed. As a result, the metal layer 42 that covers the upper surface and the side surface of the nanowire assembly 41 with Ti / Pt / Au is formed in the ohmic forming region 10b.

Here, the work function of n-InAs of the n-type compound semiconductor nanowire 21 of the compound semiconductor nanowire 21 is lower than that of the metal, and the difference between the work functions of the two is small. Therefore, ohmic contact is automatically formed with the metal in contact with the n-type compound semiconductor nanowire 13 without heat treatment. In this example, ohmic contact is formed between the metal layer 42 and the n-type compound semiconductor nanowire 13 of the nanowire assembly 41 without heat treatment. On the other hand, the metal layer 42 and the p-type compound semiconductor nanowire 13 of the nanowire assembly 41 are in a shotky-like state, but the current mainly flows through ohmic contact on the n-type compound semiconductor nanowire 13 side.

Where the Au catalyst 4 remains on the crown of the nanowire tunnel diode 5, heat treatment for ohmic contact is not required. Therefore, the reaction between the Au catalyst 4 and the nanowire tunnel diode 5 due to the heat treatment is prevented, which contributes to the stable operation of the nanowire tunnel diode 5.

Further, the n-type compound semiconductor nanowire 5a is an ultrafine structure, and the contact area is insufficient only by covering the upper surface of the metal layer, and ohmic contact is insufficient. In this example, the metal layer 42 covers the upper surface and the side surface of the nanowire assembly 41 to the lower portion of the side surface of the n-type compound semiconductor nanowire 13 which is extremely close to the conductive layer 2. Therefore, a contact area as large as possible is secured, and sufficient ohmic contact can be obtained.

In this example, in the compound semiconductor nanowire 21, the n-type compound semiconductor nanowire 13 secures ohmic contact with the metal layer 42 without removing the p-type compound semiconductor nanowire 5b formed on the n-type compound semiconductor nanowire 5a. Therefore, the lithography step and the etching step for removing the p-type compound semiconductor nanowire 14 are not required, and the number of steps can be reduced.

Subsequently, various steps similar to those in FIGS. 3 (b) to 4 (b) of the first embodiment are performed, and as shown in FIG. 9 (c), the compound semiconductor device according to this example is formed.

As described above, according to this example, heat treatment for obtaining ohmic contact between the n-type compound semiconductor nanowire 13 of the nanowire assembly 41 and the metal layer 42 is not required. Therefore, ohmic contact is surely formed on the nanowire tunnel diode 5 without burden, and a compound semiconductor device that contributes to the stable operation of the nanowire tunnel diode 5 is realized.

In the first and second embodiments and modifications thereof, the nanowire tunnel diode may be covered with an insulating film such _{as SiN, SiO 2} , Al ₂ O _3. In a plurality of standing nanowires, the doping concentration can be changed depending on the coarse density. The state of ohmic contact between the n-type compound semiconductor nanowire and the metal layer may be controlled by the coarse density of the n-type compound semiconductor nanowire.

[Third Embodiment]
Hereinafter, the third embodiment will be described. In this embodiment, a compound semiconductor device including a mesa-type diode as an active element is exemplified.
10 to 11 are schematic cross-sectional views showing a main step of a method for manufacturing a compound semiconductor device according to a third embodiment.

First, as shown in FIG. 10A, the conductive layer 2, the n-GaAs layer 51, and the p-GaAs layer 52 are sequentially formed on the substrate 1.
Specifically, for example, a semi-insulating GaAs (111) B substrate is prepared as the substrate 1. ^{N +} -GaAs, n-GaAs, and p-GaAs are sequentially grown on the substrate 1. As a result, the conductive layer 2, the n-GaAs layer 51, and the p-GaAs layer 52 are formed on the substrate 1. The conductive layer 2 is formed to have an impurity concentration of n-type impurities (Si, Ge, etc.) of ^{about 5 × 10 18} / cm ² and a thickness of about 200 nm.

Subsequently, as shown in FIG. 10B, the n-GaAs layer 51 and the p-GaAs layer 52 are processed.
Specifically, the n-GaAs layer 51 and the p-GaAs layer 52 are processed by lithography and etching, and the n-GaAs layer 51 and the p-GaAs layer 52 are left in the element forming region 10a which is the forming region of the mesa type diode.

Subsequently, as shown in FIG. 10 (c), the first metal layer 53 is formed.
Specifically, first, a silicon oxide film having a thickness of, for example, about 50 nm is formed on the conductive layer 2 so as to cover the element forming region 10a, and the insulating film 54 is formed.
Next, the insulating film 54 is processed by lithography and etching to form an opening 54a that exposes a part of the surface of the p-GaAs layer 52.

Next, a resist mask (not shown) that covers the insulating film 54 and exposes the opening 54a is formed.
Next, for example, Ti (lower layer) / Pt (intermediate layer) / Au (upper layer) is deposited on the entire surface as a metal to a thickness of about 10 nm / about 30 nm / about 200 nm. By lift-off, the resist mask and Ti / Pt / Au on it are removed. As a result, the first metal layer 53 to be embedded in the opening 54a is formed. p-GaAs has a low Schottky barrier height with metal. Therefore, by adjusting the doping concentration of the p-type impurities in the p-GaAs layer 52 to a high level, ohmic contact is formed between the first metal layer 53 and the p-GaAs layer 52 without heat treatment. As described above, the main configuration of the mesa-type diode having the n-GaAs layer 51, the p-GaAs layer 52, and the first metal layer 53 is formed in the element forming region 10a.

Subsequently, as shown in FIG. 11A, the n-type compound semiconductor nanowire 55 and the second metal layer 56 are formed.
Specifically, first, a resist is applied on the insulating film 54, and a plurality of openings are formed in the ohmic forming region 10b of the insulating film 54 by, for example, electron beam (EB) lithography. Using this resist as a mask, a plurality of openings 54b that expose a part of the surface of the conductive layer 2 are formed in the plurality of nanowire forming regions of the insulating film 54 by dry etching. The resist is removed by a wet treatment or an ashing treatment.

Next, an Au catalyst 4 having a thickness of about 30 nm is formed in the opening 54b by vapor deposition and lift-off.
Next, a resist mask having an opening that covers the device forming region 10a including the first metal layer 53 and exposes the ohmic forming region 10b is formed. For example, using the VLS method, n-InAs having a predetermined diameter of 100 nm or less is grown in the opening 54b of the insulating film 54 to a length of about 0.5 μm only in the vertical direction. The growing material contains In and is a compound semiconductor that makes ohmic contact with a metal, and for example, n-InGaAs may be used instead of n-InAs. As a result, a plurality of n-type compound semiconductor nanowires 55 are formed in the ohmic forming region 10b.

Next, for example, Ti (lower layer) / Pt (intermediate layer) / Au (upper layer) is deposited on the entire surface as a metal to a thickness of about 10 nm / about 30 nm / about 300 nm. By lift-off, the resist mask and Ti / Pt / Au on it are removed. As a result, the second metal layer 56 is formed in the ohmic forming region 10b by covering the upper surface and the side surface of each n-type compound semiconductor nanowire 55 with Ti / Pt / Au.

Here, since n-InAs of the n-type compound semiconductor nanowire 55 has a low work function with respect to the metal and the difference between the work functions of the two is small, the metal in contact with the n-type compound semiconductor nanowire 55 is automatically applied without heat treatment. Ohmic contact is formed. In this embodiment, ohmic contact is formed between the second metal layer 56 and the n-type compound semiconductor nanowire 55 without heat treatment. In the device forming region 10a, where the first metal layer 53 is formed on the p-GaAs layer 52, heat treatment for ohmic contact of the second metal layer 56 is unnecessary. Therefore, the reaction between the first metal layer 53 and the p-GaAs layer 52 due to the heat treatment is prevented, which contributes to the stable operation of the mesa type diode.

Further, the n-type compound semiconductor nanowire 55 is an ultrafine structure, and the contact area is insufficient only by covering the upper surface of the metal layer, and ohmic contact is insufficient. In the present embodiment, the second metal layer 56 covers the upper surface and the side surface of the n-type compound semiconductor nanowire 55 to the lower portion of the side surface very close to the conductive layer 2. Therefore, a contact area as large as possible is secured, and sufficient ohmic contact can be obtained.

Subsequently, as shown in FIG. 11B, the passivation film 57, the anode electrode 58, and the cathode electrode 59 are formed.
Specifically, first, using a resin such as BCB, the first metal layer 53 and the second metal layer 56 are deposited to a thickness to be embedded to form the passivation film 57.
Next, the surface of the passivation film 57 is etched back using a gas containing F. As a result, the surface of the passivation film 57 is flattened.

Next, a resist mask (not shown) is formed by photolithography to open a portion located above the first metal layer 53 and the second metal layer 56, which are regions for forming contact holes of the passivation film 57. Using this resist mask, the passivation film 57 is etched with a gas containing F and O until the surfaces of the first metal layer 53 and the second metal layer 56 under the opening of the resist mask are exposed. The resist mask is removed by wet treatment or ashing treatment. As a result, the contact holes 57a and 57b are formed in the passivation film 57.

Next, a resist mask (not shown) that opens the anode electrode forming region (the region including the contact hole 57a) and the cathode electrode forming region (the region including the contact hole 57b) on the surface of the passivation film 57 is formed.

Next, using this resist mask, for example, Au is formed as an electrode material in the opening of the resist mask by a plating method, for example. By removing the resist mask, the contact hole 57a is embedded with Au and the anode electrode 58 is electrically connected to the first metal layer 53, and the contact hole 57b is embedded with Au and electrically connected to the second metal layer 56. A connected cathode electrode 59 is formed. As described above, the compound semiconductor device according to the present embodiment is formed.

In this embodiment, the case where the p-GaAs layer 52 is formed on the n-GaAs layer 51 as the mesa type diode is exemplified, but the p-GaAs layer 52 may not be formed. In this case, the first metal layer 56 is provided on the n-GaAs layer 51 to form a Schottky contact, and the Schottky diode operates.

Further, also in the present embodiment, similarly to the second embodiment, a plurality of n-type compound semiconductor nanowires 55 are densely formed (for example, adjacent n-type compound semiconductor nanowires 55 are in contact with each other on the side surface). May be.

As described above, according to the present embodiment, no heat treatment is required to obtain ohmic contact between the n-type compound semiconductor nanowire 55 and the second metal layer 56. Therefore, ohmic contact is surely formed on the mesa-type diode without burden, and a compound semiconductor device that contributes to the stable operation of the mesa-type diode is realized.

[Fourth Embodiment]
Hereinafter, the fourth embodiment will be described. In this embodiment, a compound semiconductor device including a heterojunction Bipolar Transistor (HBT) as an active element is exemplified.
12 to 14 are schematic cross-sectional views showing the main steps of the method for manufacturing the compound semiconductor device according to the fourth embodiment.

First, as shown in FIG. 12A, the conductive layer 2, the n-GaAs layer 61, the p-GaAs layer 62, the n-InGaP layer 63, and the n-GaAs layer 64 are sequentially formed on the substrate 1.
Specifically, for example, a semi-insulating GaAs (111) B substrate is prepared as the substrate 1. ^{N +} -GaAs, n-GaAs, p-GaAs, n-InGaP, and n-GaAs are sequentially grown on the substrate 1. As a result, the conductive layer 2, the n-GaAs layer 61, the p-GaAs layer 62, the n-InGaP layer 63, and the n-GaAs layer 64 are formed on the substrate 1. The conductive layer 2 is formed to have an impurity concentration of n-type impurities (Si, Ge, etc.) of ^{about 5 × 10 18} / cm ² and a thickness of about 200 nm.

Subsequently, as shown in FIG. 12B, the n-GaAs layer 61, the p-GaAs layer 62, the n-InGaP layer 63, and the n-GaAs layer 64 are processed.
Specifically, the n-GaAs layer 61, the p-GaAs layer 62, the n-InGaP layer 63, and the n-GaAs layer 64 are processed by lithography and etching, and these are left in the device forming region 10a, which is an HBT forming region. .. The n-GaAs layer 61 and the p-GaAs layer 62 are processed to have the same width, and the n-InGaP layer 63 and the n-GaAs layer 64 are processed to have the same width narrower than the n-GaAs layer 61 and the p-GaAs layer 62.

Subsequently, as shown in FIG. 12 (c), the first metal layer 65 is formed.
Specifically, first, a resist mask (not shown) that covers the entire surface and exposes a part of the surface of the n-GaAs layer 64 is formed.
Next, AuGe (lower layer) / Au (upper layer) as a metal is deposited on the entire surface to a thickness of about 20 nm / 300 nm by a vapor deposition method. Lift-off removes the resist mask and AuGe / Au on it. As a result, the first metal layer 65 to be the emitter electrode layer is formed on the n-GaAs layer 64.

Subsequently, as shown in FIG. 13A, the second metal layer 66 is formed.
Specifically, first, a resist mask (not shown) that covers the entire surface and exposes a part of the surface of the p-GaAs layer 62 on both sides of the n-InGaP layer 63 is formed.
Next, for example, Ti (lower layer) / Pt (intermediate layer) / Au (upper layer) is deposited on the entire surface as a metal to a thickness of about 10 nm / about 30 nm / about 150 nm. By lift-off, the resist mask and Ti / Pt / Au on it are removed. As a result, each second metal layer 66 to be a base electrode layer is formed on the p-GaAs layer 62 on both sides of the n-InGaP layer 63. As described above, the main HBT having the n-GaAs layer 61, the p-GaAs layer 62, the n-InGaP layer 63, the n-GaAs layer 64, the first metal layer 65, and the second metal layer 66 in the element forming region 10a. The composition is formed.

Subsequently, as shown in FIG. 13B, the insulating film 67 is formed.
Specifically, a silicon oxide film having a thickness of, for example, about 50 nm is formed on the conductive layer 2 so as to cover the element forming region 10a, and the insulating film 67 is formed.

Subsequently, as shown in FIG. 14A, the n-type compound semiconductor nanowire 68 and the third metal layer 69 are formed.
Specifically, first, a resist is applied on the insulating film 67, and a plurality of openings are formed in the ohmic forming region 10b of the insulating film 67 by, for example, electron beam (EB) lithography. Using this resist as a mask, a plurality of openings 67a that expose a part of the surface of the conductive layer 2 are formed in the plurality of nanowire forming regions of the insulating film 67 by dry etching. The resist is removed by a wet treatment or an ashing treatment.

Next, an Au catalyst 4 having a thickness of about 30 nm is formed in the opening 67a by vapor deposition and lift-off.
Next, a resist mask having an opening that covers the device forming region 10a and exposes the ohmic forming region 10b is formed. For example, using the VLS method, n-InAs having a predetermined diameter of 100 nm or less is grown in the opening 67a of the insulating film 67 to a length of about 0.5 μm only in the vertical direction. The growing material contains In and is a compound semiconductor that makes ohmic contact with a metal, and for example, n-InGaAs may be used instead of n-InAs. As a result, a plurality of n-type compound semiconductor nanowires 68 are formed in the ohmic forming region 10b.

Next, for example, Ti (lower layer) / Pt (intermediate layer) / Au (upper layer) is deposited on the entire surface as a metal to a thickness of about 10 nm / about 30 nm / about 300 nm. By lift-off, the resist mask and Ti / Pt / Au on it are removed. As a result, the third metal layer 69 is formed in the ohmic forming region 10b by covering the upper surface and the side surface of each n-type compound semiconductor nanowire 68 with Ti / Pt / Au.

Here, since n-InAs of the n-type compound semiconductor nanowire 68 has a low work function with respect to the metal and the difference between the work functions of the two is small, the metal in contact with the n-type compound semiconductor nanowire 68 is automatically applied without heat treatment. Ohmic contact is formed. In this embodiment, ohmic contact is formed between the third metal layer 69 and the n-type compound semiconductor nanowire 68 without heat treatment. In the device forming region 10a, where the second metal layer 66 is formed on the p-GaAs layer 62, heat treatment for ohmic contact of the third metal layer 69 is unnecessary. Therefore, the reaction between the second metal layer 66 and the p-GaAs layer 62 due to the heat treatment is prevented, which contributes to the stable operation of the HBT.

Further, the n-type compound semiconductor nanowire 68 is an ultrafine structure, and the contact area is insufficient only by covering the upper surface of the metal layer, and ohmic contact is insufficient. In the present embodiment, the third metal layer 69 covers the upper surface and the side surface of the n-type compound semiconductor nanowire 68 to the lower portion of the side surface very close to the conductive layer 2. Therefore, a contact area as large as possible is secured, and sufficient ohmic contact can be obtained.

Subsequently, as shown in FIG. 14B, the passivation film 71, the emitter electrode 72, and the collector electrode 73 are formed.
Specifically, first, using a resin such as BCB, the first metal layer 65 and the third metal layer 69 are deposited to a thickness to be embedded to form the passivation film 71.
Next, the surface of the passivation film 71 is etched back using a gas containing F. As a result, the surface of the passivation film 71 is flattened.

Next, a resist mask (not shown) is formed by photolithography to open the portions located above the first metal layer 65 and the third metal layer 69, which are the contact hole forming regions of the passivation film 71. Using this resist mask, the passivation film 71 is etched with a gas containing F and O until the surfaces of the first metal layer 65 and the third metal layer 69 under the opening of the resist mask are exposed. The resist mask is removed by wet treatment or ashing treatment. As a result, the contact holes 71a and 71b are formed in the passivation film 71.

Next, a resist mask (not shown) that opens the emitter electrode forming region (region including the contact hole 71a) and the collector electrode forming region (region including the contact hole 71b) on the surface of the passivation film 71 is formed.

Next, using this resist mask, for example, Au is formed as an electrode material in the opening of the resist mask by a plating method, for example. By removing the resist mask, the contact hole 71a is embedded with Au and the emitter electrode 72 is electrically connected to the first metal layer 65, and the contact hole 71b is embedded with Au and electrically connected to the third metal layer 69. A connected collector electrode 73 is formed. As described above, the compound semiconductor device according to the present embodiment is formed.

In this embodiment as well, as in the second embodiment, a plurality of n-type compound semiconductor nanowires 68 are densely formed (for example, adjacent n-type compound semiconductor nanowires 68 are in contact with each other on the side surface). May be.

As described above, according to the present embodiment, no heat treatment is required to obtain ohmic contact between the n-type compound semiconductor nanowire 68 and the third metal layer 69. Therefore, ohmic contact is surely formed without burdening the HBT, and a compound semiconductor device that contributes to the stable operation of the HBT is realized.

[Fifth Embodiment]
Hereinafter, the fifth embodiment will be described. In this embodiment, a radio wave receiving device of a so-called ultra-large capacity wireless communication system including the first to third embodiments and one kind of diode selected from these modifications will be exemplified. FIG. 15 is a schematic diagram showing a schematic configuration of the radio wave receiving device according to the fifth embodiment.

This radio wave receiving device includes a receiving antenna 81, a low noise amplifier 82, a diode 83 which is a detector, a low-pass filter 84 which is an inductor, and an output terminal 85. The diode 83 is a kind of diode selected from the first to third embodiments and modifications thereof.

The strength of the RF signal input from the receiving antenna 81 is amplified by the low noise amplifier 82. After that, the RF signal is converted into a DC signal by passing through the diode 83 and the low-pass filter 84, and is output from the output terminal 85.

In the present embodiment, the electrode does not require heat treatment for obtaining ohmic contact, and a diode that reliably obtains ohmic contact without burden and contributes to stable operation is applied. With this configuration, a highly reliable ultra-large capacity wireless communication network system is realized.

[Sixth Embodiment]
Hereinafter, the sixth embodiment will be described. In this embodiment, a power generation device of a power conversion module including one kind of diode selected from the first to third embodiments and modifications thereof will be exemplified. FIG. 16 is a schematic diagram showing a schematic configuration of the power conversion module according to the sixth embodiment.

This power generation device includes a receiving antenna 91, a matching circuit 92, a diode 93, a booster circuit 94, a capacitor 95, and an IoT (Internet of Things) sensor 96. The diode 93 is a kind of diode selected from the first to third embodiments and modifications thereof.

When the RF signal input from the receiving antenna 91 is input to the diode 93 through the matching circuit 92, the diode 93 performs power conversion from the RF signal to the DC signal. The voltage of the DC signal is increased by the booster circuit 94, and then the power of the DC signal is temporarily stored in the capacitor 95. When power is stored to some extent, the capacitor 95 functions as a power source for driving, for example, a low power consumption IoT sensor 96.

In the present embodiment, the electrode does not require heat treatment for obtaining ohmic contact, and a diode that reliably obtains ohmic contact without burden and contributes to stable operation is applied. With this configuration, the IoT sensor 96 that can operate with low power can be driven with high efficiency without using a battery or the like.

Hereinafter, the compound semiconductor device, its manufacturing method, and various aspects of the radio wave receiving device and the power generation device will be collectively described as an appendix.

(Appendix 1) Conductive layer and
The active element provided on the conductive layer and
Nanowires having a compound semiconductor containing In and making ohmic contact with a metal, which stands on the conductive layer and is electrically connected to the active element.
A compound semiconductor device comprising a metal layer that covers the upper surface and the side surface of the nanowire with the metal.

(Appendix 2) A plurality of the nanowires stand side by side on the conductive layer.
The compound semiconductor device according to Appendix 1, wherein the metal layer covers the upper surface and the side surface of the nanowire for each nanowire.

(Appendix 3) A nanowire aggregate having a plurality of the nanowires is formed on the conductive layer.
The compound semiconductor device according to Appendix 1, wherein the metal layer covers the upper surface and the side surface of the nanowire aggregate.

(Supplementary Note 4) The compound semiconductor device according to any one of Supplementary note 1 to 3, wherein the active element is a nanowire diode having the same structure as the nanowire in the lower portion.

(Appendix 5) The compound semiconductor device according to Appendix 4, wherein the nanowire and the lower portion are both composed of n-type InAs or n-type InGaAs.

(Appendix 6) The active element is a nanowire diode.
The compound semiconductor device according to any one of Supplementary note 1 to 3, wherein the nanowire has the same structure as the active element.

(Appendix 7) The active element and the nanowire are both composed of n-type InAs or n-type InGaAs in the lower portion, and the upper portion is selected from p-type GaSb, p-type GaAsSb, and p-type AlGaSb. The compound semiconductor device according to Appendix 6, wherein the compound semiconductor device comprises one type.

(Appendix 8) A step of forming an active element on the conductive layer and
A step of forming nanowires having a compound semiconductor containing In and making ohmic contact with a metal, which stands on the conductive layer and is electrically connected to the active element.
A method for manufacturing a compound semiconductor device, which comprises a step of forming a metal layer in which the upper surface and the side surface of the nanowire are covered with the metal.

(Appendix 9) A plurality of the nanowires standing side by side on the conductive layer are formed.
The method for manufacturing a compound semiconductor device according to Appendix 8, wherein the metal layer is formed so as to cover the upper surface and the side surface of the nanowire for each nanowire.

(Appendix 10) A nanowire aggregate having a plurality of the nanowires is formed on the conductive layer, and the nanowire aggregate is formed.
The method for manufacturing a compound semiconductor device according to Appendix 8, wherein the metal layer is formed so as to cover the upper surface and the side surface of the nanowire aggregate.

(Appendix 11) The active element is a nanowire diode whose lower portion has the same structure as the nanowire.
The method for manufacturing a compound semiconductor device according to any one of Supplementary note 8 to 10, wherein the lower portion is formed at the same time as the nanowire.

(Appendix 12) The method for manufacturing a compound semiconductor device according to Appendix 11, wherein the nanowire and the lower portion are both composed of n-type InAs or n-type InGaAs.

(Appendix 13) The active element is a nanowire diode, and the nanowire has the same structure as the active element.
The method for manufacturing a compound semiconductor device according to any one of Supplementary note 8 to 10, wherein the active element and the nanowire are simultaneously formed.

(Appendix 14) The active element and the nanowire are both composed of n-type InAs or n-type InGaAs in the lower portion, and the upper portion is selected from p-type GaSb, p-type GaAsSb, and p-type AlGaSb. The method for manufacturing a compound semiconductor device according to Appendix 13, which comprises one type.

(Appendix 15) Receiving antenna and
The amplifier connected to the receiving antenna and
The diode connected to the amplifier and
Including the above amplifier and the connected inductor.
The diode is
With a conductive layer
The active element provided on the conductive layer and
Nanowires having a compound semiconductor containing In and making ohmic contact with a metal, which stands on the conductive layer and is electrically connected to the active element.
A receiving device including a metal layer that covers the upper surface and the side surface of the nanowire with the metal.

(Appendix 16) Receiving antenna and
The diode connected to the receiving antenna and
A smoothing capacitor connected to the diode,
The voltage constant circuit connected to the diode and
Including
The diode is
With a conductive layer
The active element provided on the conductive layer and
Nanowires having a compound semiconductor containing In and making ohmic contact with a metal, which stands on the conductive layer and is electrically connected to the active element.
A power generation device including a metal layer that covers the upper surface and the side surface of the nanowire with the metal.

1 Substrate 2 Conductive layer 3,54,67 Insulation film 3a, 3b, 20A, 54a, 54b, 67a Opening 4 Au catalyst 5 Nanowire tunnel diode 5a, 6,12,13,55,68 n-type compound semiconductor nanowire 5b, 14 p-type compound semiconductor nanowire 7,22,32,42 Metal layer 8,57,71 Passion film 8a, 57a, 57b, 71a, 71b Contact hole 9,58 Anode electrode 10a Element formation region 10b Ohmic formation region 11,59 Cathode electrode 20 Resistor mask 20a Lower layer resist 20b Upper layer resist 21 Compound semiconductor nanowire 31,41 Nanowire assembly 51,61,64 n-GaAs layer 52,62 p-GaAs layer 53,65 First metal layer 56,66 Second metal layer 63 n-InGaP layer 69 Third metal layer 72 Emitter electrode 73 Collector electrode 81, 91 Receiving antenna 82 Low noise amplifier 83, 93 Diode 84 Low pass filter 85 Output terminal 92 Matching circuit 94 Boost circuit 95 Condenser 96 IoT sensor

Claims (8)

With active elements
An aggregate of nanowires comprising a plurality of nanowires electrically connected to the active element and having a compound semiconductor containing In and having ohmic contact with a metal.
A compound semiconductor device including a metal layer that covers the upper surface and side surfaces of the nanowire assembly with the metal. The compound semiconductor device according to claim 1, wherein the active element is a nanowire diode having the same structure as the nanowire in the lower portion. The active element is a nanowire diode and is
The compound semiconductor device according to claim 1, wherein the nanowire has the same structure as the active element. The process of forming an active element and
A step of forming an aggregate of nanowires including a plurality of nanowires having a compound semiconductor containing In and making ohmic contact with a metal, which is electrically connected to the active element.
A method for manufacturing a compound semiconductor device, which comprises a step of forming a metal layer in which an upper surface and a side surface of the nanowire aggregate are covered with the metal. The active element is a nanowire diode whose lower portion has the same structure as the nanowire.
The method for manufacturing a compound semiconductor device according to claim 4, wherein the lower portion is formed at the same time as the nanowires. The active element is a nanowire diode, and the nanowire has the same structure as the active element.
The method for manufacturing a compound semiconductor device according to claim 4, wherein the active element and the nanowire are simultaneously formed. With the receiving antenna
The amplifier connected to the receiving antenna and
The diode connected to the amplifier and
Including the above amplifier and the connected inductor.
The diode is
With active elements
An aggregate of nanowires comprising a plurality of nanowires electrically connected to the active element and having a compound semiconductor containing In and having ohmic contact with a metal.
A receiving device including a metal layer that covers the upper surface and the side surface of the nanowire assembly with the metal. With the receiving antenna
The diode connected to the receiving antenna and
A smoothing capacitor connected to the diode,
The voltage constant circuit connected to the diode and
Including
The diode is
With active elements
An aggregate of nanowires comprising a plurality of nanowires electrically connected to the active element and having a compound semiconductor containing In and having ohmic contact with a metal.
A power generation device including a metal layer that covers the upper surface and side surfaces of the nanowire assembly with the metal.

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