JP6965721B2 - Circuit element and how to use the circuit element - Google Patents

Description

The present invention relates to a circuit element and a method of using the circuit element.

A technique for forming a bypass capacitor using a epitope (P-channel Metal Oxide Semiconductor) transistor and an NMOS (N-channel Metal Oxide Semiconductor) transistor that are not used for forming a logic circuit is known (for example, patent documents). See 1 and 2). For example, the gate of the NMOS transistor is connected to the ground potential and the source and drain are connected to the power potential, the gate of the NMOS transistor is connected to the power potential and the source and drain are connected to the ground potential. As a result, a bypass capacitor is formed between the power supply potential and the ground potential. The bypass capacitor formed between the power supply potential and the ground potential is also called a decoupling capacitor.

Further, in order to change the filler cell functioning as such a decoupling capacitor to a logic cell such as an inverter cell, a technique for modifying the wiring of the metal wiring layer is known (see, for example, Patent Document 3). A large number of filler cells are arranged in the free area where the logical cells are not arranged. As a result, even if a logical correction is required after the layout is completed, the logical correction can be dealt with by changing the filler cell to a desired logical cell.

Japanese Unexamined Patent Publication No. 2-241061 Japanese Unexamined Patent Publication No. 10-107235 Japanese Unexamined Patent Publication No. 2008-263185

By the way, in order to enhance the effect of suppressing power supply noise, it may be desired to further increase the decoupling capacity of the filler cell that functions as the decoupling capacitor. Since the size of the decoupling capacitance is determined by the width of the diffusion layer of the transistor included in the filler cell, it is conceivable to increase the width of the diffusion layer in order to increase the decoupling capacitance. On the other hand, the gate of the transistor and the LIC (Local Inter Connect) are required to protrude from the diffusion layer in the plan view of the semiconductor integrated circuit according to the manufacturing rules. Therefore, when increasing the width of the diffusion layer, the gate and the LIC are extended in the width direction of the diffusion layer so as to protrude from the diffusion layer in the plan view of the semiconductor integrated circuit.

However, a large number of filler cells are pre-arranged by the automatic arrangement tool in the empty area where the logical cells are not arranged. Therefore, if the gate or LIC is extended too much until the gate or LIC is connected between the filler cells arranged adjacent to each other in the width direction of the diffusion layer, those filler cells will be unnecessary after the change to the logical cell. There is a risk of short-circuit defects.

Therefore, the present disclosure provides a circuit element and a method of using the circuit element that realizes an increase in the decoupling capacity while preventing a short-circuit defect after the change to the logic cell.

This disclosure is
It has a multi-site structure in which three or more sites each including a MOSFET transistor and an NMOS transistor are arranged adjacent to each other in the width direction of the diffusion layer.
The multi-site structure includes a logical cell changeable portion that can be changed into a logical cell and a pair of decoupling cell portions that sandwich the logical cell changeable portion in the width direction.
The logic cell changeable portion includes a first site boundary connecting the gates of the epitaxial transistors provided by the adjacent sites in the width direction and the gates of the NMOS transistors provided by the adjacent sites in the width direction. Has a second site boundary to connect with
The boundary between the logic cell changeable portion and each of the pair of decoupling cell portions provides a circuit element located between the NMOS transistor and the NMOS transistor.

In addition, this disclosure is
A method of using a circuit element having a multi-site structure in which three or more sites including a MOSFET transistor and an NMOS transistor are arranged adjacent to each other in the width direction of the diffusion layer.
The multi-site structure includes a logical cell changeable portion that can be changed into a logical cell and a pair of decoupling cell portions that sandwich the logical cell changeable portion in the width direction.
The logic cell changeable portion includes a first site boundary connecting the gates of the epitaxial transistors provided by the adjacent sites in the width direction and the gates of the NMOS transistors provided by the adjacent sites in the width direction. Has a second site boundary to connect with
The boundary between the logic cell changeable portion and the pair of decoupling cell portions is located between the MOSFET transistor and the NMOS transistor.
The design apparatus provides a method of using a circuit element that changes at least a part of the logic cell changeable part into a logic cell by changing the wiring of the metal wiring layer of the logic cell changeable part.

According to the present disclosure, it is possible to provide a circuit element and a method of using a circuit element that realizes an increase in decoupling capacity while preventing a short-circuit defect after a change to a logic cell.

It is a figure which shows an example of the design flow when the decoupling cell and the EC cell are used. It is a figure which shows an example of the structure of a decoupling cell. It is a figure which shows an example of the structure of an EC cell. It is a figure which shows an example of the structure of an EC decoupling cell. It is a figure which shows an example of the structure of the inverter cell which is one of the logical cells. It is a figure which shows an example of the state after changing the EC decoupling cell into an inverter cell. FIG. 5 is a plan view schematically showing an example of a layout in which a logical cell and an EC decoupling cell are adjacent to each other. It is a top view which shows typically an example of the layout in which a logical cell and a decoupling cell are adjacent to each other. It is a top view which shows typically an example of the layout in which decoupling cells are adjacent to each other. It is a top view which shows typically an example of the layout in which EC decoupling cells are adjacent to each other. FIG. 10 is a plan view schematically showing an example of a layout when the width of the diffusion layer is tentatively maximized in the configuration of FIG. 10. It is a figure which shows the arrangement example when the decoupling cell and EC cell are used. It is a figure which shows an example of the state in which an EC cell is changed to a logical cell when a logical failure occurs in the arrangement layout of FIG. It is a top view which shows an example of the layout of a multi-site EC decoupling cell schematically. It is a figure which shows an example of the circuit of a multi-site EC decoupling cell. FIG. 5 is a plan view schematically showing an example of a layout in which three EC decoupling cells are adjacent to each other. It is a figure which shows the arrangement example when the multi-site EC decoupling cell is used. It is a figure which shows an example of the state in which a multi-site EC decoupling cell is changed to a logical cell when a logical failure occurs in the arrangement layout of FIG. It is a figure which shows an example of the design flow when the multi-site EC decoupling cell is used. It is a top view which shows typically an example of the layout of the multi-site EC decoupling cell of 5 single sites before the logical cell change. It is a top view which shows typically an example of the layout of the multi-site EC decoupling cell of 4 single sites before the logical cell change. It is a top view which shows typically an example of the layout of the multi-site EC decoupling cell of 5 single sites after the logical cell change. It is a figure which shows an example of the circuit of the multi-site EC decoupling cell of 5 single sites after the logical cell change. It is a figure which shows the arrangement example of the multi-site EC decoupling cell with a large number of sites. It is a figure which shows the location of the logical cell changeable part in the structure of FIG.

Hereinafter, modes for carrying out the present invention will be described.

First, before explaining the embodiment of the present invention, the decoupling cell and the EC (Engineering Change) cell, which are related technologies of the present invention, will be described.

The semiconductor integrated circuit is designed so that a decoupling cell for suppressing power supply noise and an EC cell for dealing with failures after the semiconductor integrated circuit is manufactured are arranged on a semiconductor substrate. The EC cell is also called a spare cell, a repair cell, an ECO (Engineering Change Order) cell, or the like.

The decoupling cell and the EC cell are formed by using a layer (bulk layer) on which transistors such as a substrate, a diffusion layer and a polygate are formed, and a wiring layer (metal wiring layer) connected to the bulk layer. Generally, the manufacturing cost of the bulk layer is higher than the manufacturing cost of the metal wiring layer.

The decoupling cell suppresses transient fluctuations in the power supply voltage (power supply noise) caused by the current flowing during circuit operation. As the speed and functionality of LSIs (Large Scale Integrated circuits) increase, the number of transistors increases and the density increases, so power supply noise tends to increase. Therefore, in order to suppress power supply noise, it is required to mount more decoupling cells and increase the decoupling capacity.

On the other hand, EC cells have a wide variety of logical operations such as negative logical product (NAND), NOR, and inversion (inverter) by changing the wiring of the metal wiring layer without changing the bulk layer. Can be changed to a logical cell. Therefore, the manufacturing cost due to the design change can be suppressed. Further, in order to deal with an unpredictable location failure, a plurality of EC cells are evenly arranged in advance in an empty space where no logical cell is arranged.

FIG. 1 is a diagram showing an example of a design flow when a decoupling cell and an EC cell are used.

In step S10, the design apparatus determines the ratio of the EC cell and the decoupling cell to be arranged in the empty space and the arrangement position thereof. In steps S20 and S30, the design apparatus arranges the EC cell and the decoupling cell at the determined arrangement position at the determined ratio. In step S40, the semiconductor manufacturing apparatus manufactures a semiconductor integrated circuit in which an EC cell and a decoupling cell are arranged. In step S50, the design apparatus inspects whether or not a logic failure has occurred in the manufactured semiconductor integrated circuit in the inspection step of the manufactured semiconductor integrated circuit. In step S60, when it is detected that a logical failure has occurred, the design device identifies an EC cell arranged in an area relatively close to the logical cell in which the logical failure is detected. In step S70, the design apparatus changes the specified EC cell into a logical cell by performing a metal revision that changes the wiring of the metal wiring layer, and deals with the detected logical failure.

FIG. 2 is a diagram showing an example of the configuration of the decoupling cell. FIG. 2A is a plan view schematically showing an example of the layout of the decoupling cell. FIG. 2B is a circuit diagram of the decoupling cell.

In addition, "Pch" represents a NMOS transistor, and "Nch" represents an NMOS transistor.

In the decoupling cell, the drain 27 and the source 28 formed in the P-type diffusion layer 20 are connected to the power rail VDD via the LIC 34 and the via 29 and the metal wiring 35. The gate 23 formed on the P-type diffusion layer 20 is connected to the power rail VSS via the via 29 and the metal wiring 35. On the other hand, the drain 31 and the source 32 formed in the N-type diffusion layer 30 are connected to the power rail VSS via the LIC 34 and the via 29 and the metal wiring 35. The gate 24 formed on the N-type diffusion layer 30 is connected to the power rail VDD via the via 29 and the metal wiring 35.

The metal wiring 35 is formed in the metal wiring layer formed above the P-type diffusion layer 20 and the N-type diffusion layer 30, respectively.

The LIC 34 is a wiring for connecting between the impurity diffusion regions formed on the semiconductor substrate, or a lead-out wiring from the impurity diffusion region, respectively. The P-type diffusion layer 20 and the N-type diffusion layer 30 are impurity diffusion regions. The LIC 34 is, for example, a local wiring formed in a conductive layer below the metal wiring layer on which the power rail VDD or the power rail VSS is formed.

The power rail VDD is an example of the first power rail, and is, for example, a power wiring connected to the positive electrode side of the power supply. The power rail VSS is an example of a second power rail whose potential is lower than that of the first rail, and is, for example, a ground wire connected to the negative electrode side of the power supply.

One cell formed between the power rail VDD and the power rail VSS adjacent to each other in the direction of the width W of the diffusion layer is called a cell having a single site structure. The decoupling cell is a cell having a single site structure. Further, the size of the capacity of the decoupling cell is determined by the size of the width W of the diffusion layer. Therefore, in order to enhance the effect of suppressing power supply noise, it is preferable to make the width W of the diffusion layer as large as possible.

The gate 23 and the LIC 34 of the epitaxial transistor are formed so as to protrude from the P-type diffusion layer 20 in the plan view of the semiconductor integrated circuit according to the manufacturing rules. Similarly, the gate 24 and the LIC 34 of the NMOS transistor are formed so as to protrude from the N-type diffusion layer 30 in the plan view of the semiconductor integrated circuit according to the manufacturing rules.

FIG. 3 is a diagram showing an example of the configuration of the EC cell. FIG. 3A is a plan view schematically showing an example of the layout of the EC cell. FIG. 3B is a circuit diagram of an EC cell.

In the EC cell, the gate 23 formed on the P-type diffusion layer 20 is connected to the power rail VDD via the via 29 and the metal wiring 35, and is formed on the N-type diffusion layer 30. 24 is connected to the power rail VSS via the via 29 and the metal wiring 35. The circuit configuration other than this is the same as that of the decoupling cell shown in FIG.

In addition to the above-mentioned EC cell and decoupling cell, there is a cell called an EC decoupling cell that combines the functions of both the EC cell and the decoupling cell. The EC decoupling cell is a decoupling cell that can be changed into a logical cell by changing the wiring of the metal wiring layer. By using the EC decoupling cell, it is possible to deal with failures after manufacturing the semiconductor integrated circuit.

FIG. 4 is a diagram showing an example of the configuration of the EC decoupling cell. FIG. 4A is a plan view schematically showing an example of the layout of the EC decoupling cell. FIG. 4B is a circuit diagram of an EC decoupling cell.

The width W of the diffusion layer of the EC decoupling cell is shorter than that of the decoupling cell shown in FIG. 2 in order to prevent a short-circuit defect (details will be described later) after the change to the logical cell. The circuit configuration other than this is the same as that of the decoupling cell shown in FIG.

FIG. 5 is a diagram showing an example of the configuration of an inverter cell which is one of the logical cells. FIG. 5A is a plan view schematically showing an example of the layout of the inverter cell. FIG. 5B is a circuit diagram of the inverter cell.

In the inverter cell, the source 28 formed in the P-type diffusion layer 20 is connected to the power rail VDD via the LIC 34 and the via 29 and the metal wiring 35. The source 32 formed in the N-type diffusion layer 30 is connected to the power rail VSS via the metal wiring 35 via the LIC 34 and the via 29. The gate 23 formed on the P-type diffusion layer 20 and the gate 24 formed on the N-type diffusion layer 30 are connected to each other by a polysilicon layer, pass through a via 29, and are an input portion of an inverter cell. It is connected to the metal wiring 35 corresponding to IN. The drain 27 formed in the P-type diffusion layer 20 is connected to the metal wiring 35 corresponding to the output unit OUT of the inverter cell via the LIC 34 and the via 29. The drain 31 formed in the N-type diffusion layer 30 is connected to the metal wiring 35 corresponding to the output unit OUT of the inverter cell via the LIC 34 and the via 29.

FIG. 6 shows an example of the state after the EC decoupling cell of FIG. 4 is changed to the inverter cell, that is, an example of the configuration of the EC decoupling cell after being changed to the inverter cell having the same circuit configuration as that of FIG. Is shown. FIG. 6A is a plan view schematically showing an example of the layout of the EC decoupling cell after being changed to the inverter cell. FIG. 6B is a circuit diagram of the EC decoupling cell after being changed to the inverter cell.

In the EC decoupling cell of FIG. 4, the metal wiring 35 connecting the source 28 of the NMOS transistor and the gate 24 of the NMOS transistor is deleted. Further, the metal wiring 35 connecting the gate 23 of the NMOS transistor and the drain 31 of the NMOS transistor is deleted. Then, by forming the metal wiring 35 connecting the gate 23 of the NMOS transistor and the gate 24 of the NMOS transistor as shown in FIG. 6, the input portion IN as shown in FIG. 6 is formed in the metal wiring 35. .. Further, by forming the metal wiring 35 connecting the drain 27 of the NMOS transistor and the drain 31 of the NMOS transistor, the output unit OUT as shown in FIG. 6 is formed in the metal wiring 35.

Here, since the EC decoupling cell is required to prevent a short-circuit defect after the change to the logical cell, it is difficult to maximize the decoupling capacity. Next, this point will be described.

In EC cells, EC decoupling cells, and logical cells, the protrusion of the gate or LIC is to some extent from the site boundary with other sites so that short-circuit defects do not occur between itself and other adjacent sites. It is located with a space (see, for example, FIG. 7). The protrusion of the gate or LIC is a portion where the gate or LIC protrudes from the diffusion layer in a plan view. In this way, in order to prevent the occurrence of short-circuit defects, the protrusion of the gate or LIC is located with a certain space from the site boundary with other sites, so that the maximization of the width W of the diffusion layer is limited. NS. However, since the protrusions of the gate and the LIC are separated from the site boundary, short-circuit defects do not occur in any combination of adjacent cells among the EC cell, the EC decoupling cell, and the logical cell.

For example, FIG. 7 is a plan view schematically showing an example of a layout in which a logical cell and an EC decoupling cell are adjacent to each other. The portion where the gates 23a and LIC34a1, 34a2 of the logic cell protrude from the P-type diffusion layer 20 and the portion where the gates 23b and LIC34b1, 34b2 of the EC decoupling cell protrude from the P-type diffusion layer 20 are separated from the site boundary.

FIG. 8 is a plan view schematically showing an example of a layout in which a logical cell and a decoupling cell are adjacent to each other. In order to maximize the capacity of the decoupling cell, as described above, the protrusions of the gate 23b and the LICs 34b1 and 34b2 extend to the site boundary due to the large width W of the diffusion layer. However, even if the decoupling cell is adjacent to the logical cell, the protrusions of the gates 23a and LIC34a1 and 34a2 of the logical cell are located away from the site boundary, so that a short circuit defect does not occur.

FIG. 9 is a plan view schematically showing an example of a layout in which decoupling cells are adjacent to each other. When the decoupling cells are adjacent to each other, the gate 23a and the gate 23b, the LIC34a1 and the LIC34b1, and the LIC34a2 and the LIC34b2 are connected to each other at the site boundary. However, the decoupling cell is a cell in which the metal wiring is not changed, and the gate and the LIC have the same potential between the adjacent decoupling cells, so that a short circuit failure does not occur.

In contrast to FIGS. 7, 8 and 9, FIG. 10 is a diagram showing an example of a layout in which EC decoupling cells are adjacent to each other. FIG. 10 shows an example of the state after changing each of the adjacent EC decoupling cells to an inverter cell. FIG. 10A is a plan view schematically showing an example of the layout of adjacent EC decoupling cells after being changed to an inverter cell. FIG. 10B is a circuit diagram of adjacent EC decoupling cells after being changed to an inverter cell.

In the configuration of FIG. 10, in order to maximize the capacity of the EC decoupling cell, it is conceivable to increase the width W of the diffusion layer. When increasing the width W of the diffusion layer, the gate or LIC is extended in the width direction of the diffusion layer so as to protrude from the diffusion layer in the plan view of the semiconductor integrated circuit according to the manufacturing rule. However, if the gates 23a, 23b and the LICs 34a1, 34a2, 34b1, 34b2 are extended too much, the gates and the LICs will be connected as shown in FIG. 11 between the EC decoupling cells arranged adjacent to each other in the width direction of the diffusion layer. Become. If the adjacent EC decoupling cells are changed to logical cells in this connected state, a short-circuit defect may occur in which a short-circuit is unnecessary.

FIG. 11 is a plan view schematically showing an example of a layout when the width W of the diffusion layer is tentatively maximized in the configuration of FIG. FIG. 11A is a plan view schematically showing an example of the layout of adjacent EC decoupling cells after being changed to an inverter cell. FIG. 11B is a circuit diagram of adjacent EC decoupling cells after being changed to an inverter cell.

In FIG. 10, since the gate and the LIC are separated from each other between the adjacent EC decoupling cells, even if at least one of the adjacent EC decoupling cells is changed to the inverter cell, a short circuit failure does not occur. However, in FIG. 11, for example, when both adjacent EC decoupling cells are changed to inverter cells, the input unit IN1 is short-circuited to the input unit IN2, the output unit OUT1 is short-circuited to the power rail VDD, and the output unit OUT2 Shorts to the power rail VDD. Therefore, the logic change as shown in the circuit diagram of FIG. 10B cannot be made.

Further, if the EC decoupling cell is not used, in the conventional technique, many EC cells must be arranged in order to deal with the circuit change when an unpredictable logic failure occurs. As more EC cells are arranged, the number of decoupling cells that can be arranged decreases, and the decoupling capacity cannot be increased.

For example, FIG. 12 is a diagram showing an arrangement example when a decoupling cell and an EC cell are used. In FIG. 12, “EC” indicates an EC cell, “CAP” indicates a decoupling cell, and “logic” indicates a logic cell forming a logic circuit.

FIG. 13 is a diagram showing an example of a state in which an EC cell is changed to a logical cell when a logical failure occurs in the layout of FIG. 12. As shown in FIG. 13, only a small number of EC cells are changed to logical cells, and all EC cells that are not changed to logical cells and are not used are wasted. The “x” part in FIG. 13 indicates a wasted EC cell.

Therefore, the present disclosure provides a circuit element and a method of using the circuit element that can maximize the mounting amount and the decoupling capacity of the decoupling cell while making it possible to change the circuit when a logic failure occurs by metal modification.

Specifically, a decoupling cell (hereinafter, referred to as "multisite EC decoupling cell"), which is a circuit element having a multisite structure that can be changed to a logic cell by metal modification, is provided.

FIG. 14 is a plan view schematically showing an example of the layout of the multi-site EC decoupling cell. FIG. 15 is a diagram showing an example of a circuit of a multi-site EC decoupling cell.

The multi-site EC decoupling cell 10 is an example of a circuit element having a multi-site structure in which three or more sites including a MOSFET transistor and an NMOS transistor are arranged adjacent to each other in the width direction of the diffusion layer. The multi-site structure includes a logical cell changeable unit 50 that can be changed into a logical cell, and a pair of decoupling cell units 41 and 42 that sandwich the logical cell changeable unit 50 in the width direction of the diffusion layer. The power rail VDD and the power rail VSS are arranged alternately in the width direction of the diffusion layer.

The logical cell changeable unit 50 has a first site boundary 63 and a second site boundary 62. The first site boundary 63 is a portion where the gates of the epitaxial transistors provided by the adjacent sites in the width direction of the diffusion layer are connected to each other. The second site boundary 62 is a portion where the gates of the NMOS transistors provided by the adjacent sites in the width direction of the diffusion layer are connected to each other.

For example, at the first site boundary 63, the gate 23a of one adjacent epitaxial transistor and the gate 23b of the other epitaxial transistor are connected to each other by a polysilicon layer 23ab. The gates 23a and 23b are connected to the common power rail VSS located at the second site boundary 62 via the common via 29 and the common metal wiring 35. On the other hand, at the second site boundary 62, the gate 24a of one adjacent NMOS transistor and the gate 24b of the other NMOS transistor are connected to each other by a polysilicon layer 24ab. The gates 24a and 24b are connected to the common power rail VDD located at the first site boundary 63 via the common via 29 and the common metal wiring 35.

In this way, the gates of the adjacent MOSFET transistors are fixed at the same potential by being connected to each other, and the gates of the adjacent NMOS transistors are fixed at the same potential by being connected to each other. Short-circuit defects at the site boundary do not occur.

Further, the boundary between the logic cell changeable unit 50 and the pair of decoupling cell units 41 and 42 is a PN boundary located between the MOSFET transistor and the NMOS transistor.

For example, the gate 23 and LIC34 of the NMOS transistor included in one of the decoupling cell units 41 are not connected to the gates 24a and LIC34 of the NMOS transistor included in the logic cell changeable unit 50 at the PN boundary 71. The PN boundary 71 is an example of the first boundary. The gate 24 and LIC34 of the NMOS transistor included in the other decoupling cell unit 42 are not connected to the gates 23b and LIC34 of the NMOS transistor included in the logic cell changeable unit 50 at the PN boundary 72. The PN boundary 72 is an example of the second boundary. Due to the presence of the PN boundaries 71 and 72, it is possible to secure a space for arranging the respective gates and LICs between the MOSFET transistors and the NMOS transistors adjacent to each other at the PN boundaries 71 and 72. Therefore, a short-circuit defect at the PN boundary after the change to the logical cell does not occur.

Therefore, since short-circuit defects do not occur at either the site boundary or the PN boundary, the multi-site EC decoupling cell 10 in FIG. 14 can maximize the width W1 of each of the P-type diffusion layer 20 and the N-type diffusion layer 30. Therefore, the width W1 can be made larger than the width W2 of the diffusion layer in the configuration of FIG. 16 in which three EC decoupling cells shown in FIG. 4 are adjacent to each other, and the decoupling capacity can be increased. can. That is, it is possible to increase the decoupling capacity by maximizing the width of the diffusion layer while preventing a short circuit after changing to a logical cell.

As shown in FIG. 14, in the logic cell changeable unit 50, the LIC34s of the SiO transistors provided by the adjacent sites in the width direction of the diffusion layer are connected by the first site boundary 63. Each of the VDD transistors provided by the adjacent sites in the width direction of the diffusion layer has a P-type diffusion layer 20 connected to the power rail VDD via the LIC 34 connected at the first site boundary 63. A drain 27 and a source 28 are formed in each P-type diffusion layer 20. Similarly, in the logic cell changeable unit 50, the LIC34s of the NMOS transistors provided by the adjacent sites in the width direction of the diffusion layer are connected by the second site boundary 62. Each of the NMOS transistors provided by the adjacent sites in the width direction of the diffusion layer has an N-type diffusion layer 30 connected to the power rail VSS via the LIC 34 connected at the second site boundary 62. A drain 31 and a source 32 are formed in each N-type diffusion layer 30.

Further, in order to prevent the occurrence of a short-circuit defect with other adjacent cells when the logical cell changeable unit 50 changes to a logical cell, both ends of the multi-site EC decoupling cell 10 in the width direction of the diffusion layer are set. It has a decoupling cell structure. In the configuration of FIG. 14, the pair of decoupling cell portions 41, 42 are located at both ends of the diffusion layer of the multisite structure in the width direction.

One site boundary 61 located on one end side of the multi-site EC decoupling cell 10 represents a boundary with another single site adjacent to the decoupling cell portion 41 in the width direction of the diffusion layer. The gate 23 and LIC34 of the epitaxial transistor of the decoupling cell portion 41 may each extend to the site boundary 61.

When the cell of the other single site adjacent to the one end side is a cell other than the decoupling cell, the gate and LIC of the epitaxial transistor formed in the cell are separated from the site boundary as shown in FIG. Since it is located, short-circuit defects do not occur. Further, when the cell of the other single site adjacent to the one end side is a decoupling cell, the cell is a cell in which the metal wiring is not changed. Therefore, since the potentials of the gate and the LIC are originally the same between the adjacent decoupling cells as shown in FIG. 9, short-circuit defects do not occur.

The decoupling cell section 41 includes a MPa transistor forming a decoupling capacitor. In the polyclonal transistor, the drain 27 and the source 28 formed in the P-type diffusion layer 20 are connected to the power rail VDD located at the site boundary 61 via the LIC 34 and the via 29 and the metal wiring 35. The gate 23 formed on the P-type diffusion layer 20 is connected to the power rail VSS located at the second site boundary 62 via the via 29 and the metal wiring 35.

On the other hand, the other site boundary 64 located on the other end side of the multi-site EC decoupling cell 10 represents a boundary with another single site adjacent to the decoupling cell portion 42 in the width direction of the diffusion layer. The gate 24 and LIC34 of the NMOS transistor of the decoupling cell portion 42 may extend to the site boundary 64, respectively.

When the other single-site cell adjacent to the one end side is a cell other than the decoupling cell, the gate and LIC of the NMOS transistor formed in the cell are from the site boundary as in the epitaxial transistor of FIG. Located away from each other. Therefore, a short circuit defect does not occur. Further, when the cell of the other single site adjacent to the one end side is a decoupling cell, the cell is a cell in which the metal wiring is not changed. Therefore, the gate and the LIC do not have a short-circuit defect because the potentials of the gate and the LIC are originally the same between the adjacent decoupling cells as in the epitaxial transistor of FIG.

The decoupling cell section 42 includes an NMOS transistor that forms a decoupling capacitor. In the NMOS transistor, the drain 31 and the source 32 formed in the N-type diffusion layer 30 are connected to the power supply rail VSS located at the site boundary 64 via the LIC 34 and the via 29 and the metal wiring 35. The gate 24 formed on the N-type diffusion layer 30 is connected to the power rail VDD located at the first site boundary 63 via the via 29 and the metal wiring 35.

FIG. 17 is a diagram showing an arrangement example when a multi-site EC decoupling cell is used. In FIG. 17, “EC CAP” indicates a multi-site EC decoupling cell, and “logic” indicates a logic cell forming a logic circuit. The design device 100 uniformly arranges the multi-site EC decoupling cells in all the free areas where the logical cells are not arranged. By using the multi-site EC decoupling cell having a relatively small number of sites, as shown in FIG. 17, it is possible to arrange a plurality of multi-site EC decoupling cells in a relatively narrow empty space without waste.

FIG. 18 is a diagram showing an example of a state in which a multi-site EC decoupling cell is changed to a logical cell when a logical failure occurs in the layout of FIG. The design device 100 changes the metal wiring layer of the logic cell changeable portion in at least one multi-site EC decoupling cell adjacent to at least one logic cell in which a logic failure is detected. By changing the metal wiring layer of the logic cell changeable part, the design apparatus 100 changes at least a part of the cells of the logic cell changeable part to a desired logic cell capable of compensating for the detected logic failure. do.

The design device 100 is, for example, a computer including a memory and a CPU (Central Processing Unit). Each function of the design device 100 is realized by a process of causing the CPU to execute a program stored in the memory.

FIG. 19 is a diagram showing an example of a design flow when a multi-site EC decoupling cell is used.

In step S130, the design device 100 uniformly arranges the plurality of multi-site EC decoupling cells in the empty space where the logical cells are not arranged. In step S140, the semiconductor manufacturing apparatus manufactures a semiconductor integrated circuit in which a multi-site EC decoupling cell is arranged. In step S150, the design apparatus 100 inspects whether or not a logic failure has occurred in the manufactured semiconductor integrated circuit in the inspection step of the manufactured semiconductor integrated circuit. In step S160, when it is detected that a logical failure has occurred, the design device 100 is arranged in an area (preferably an adjacent area) relatively close to the logical cell in which the logical failure is detected. Identify the multi-site EC decoupling cell. In step S170, the design apparatus 100 deals with the detected logic failure by performing a metal modification to change the wiring of the metal wiring layer of the logic cell changeable portion of the specified multi-site EC decoupling cell. Specifically, the design device 100 changes at least a part of the cells in the logic cell changeable part to a desired logic cell capable of compensating for the detected logic failure.

Therefore, by using the multi-site EC decoupling cell in the present embodiment, the multi-site EC decoupling cell can be changed to a logical cell by metal revision. Further, a multi-site EC decoupling cell other than the multi-site EC decoupling cell changed to a logical cell can be used as a decoupling cell. As a result, it is possible to increase the loading amount of the decoupling cell. Further, as compared with the EC decoupling cell as shown in FIGS. 10 and 11, the multisite EC decoupling cell can increase the width W of the diffusion layer, so that the decoupling capacity can be increased.

FIG. 20 is a plan view schematically showing an example of the layout of the multi-site EC decoupling cell 11 of 5 single sites (odd sites) before the logical cell change. The multi-site EC decoupling cell 11 is a modification of the multi-site EC decoupling cell 10 of FIG. In the multi-site EC decoupling cell 11 of FIG. 20, each single site includes four MOSFET transistors having gates connected to each other and four NMOS transistors having gates connected to each other. The multi-site EC decoupling cell 11 includes a logical cell changeable unit 51 that can be changed into a logical cell, and a pair of decoupling cell units 43 and 44 that sandwich the logical cell changeable unit 51 in the width direction of the diffusion layer. In the logic cell changeable unit 51, there are two pairs of a MOSFET transistor and an NMOS transistor (a pair of Pch1 and Nch1 and a pair of Pch2 and Nch2). The two pairs allow for changes to multiple complex logic circuits.

FIG. 21 is a plan view schematically showing an example of the layout of the multi-site EC decoupling cell 12 of 4 single sites (even sites) before the logical cell change. The multi-site EC decoupling cell 12 is a modification of the multi-site EC decoupling cell 10 of FIG. The multi-site EC decoupling cell 12 of FIG. 21 includes four MOSFET transistors having gates connected to each other and four NMOS transistors having gates connected to each other per single site. The multi-site EC decoupling cell 12 includes a logical cell changeable unit 52 that can be changed into a logical cell, and a pair of decoupling cell units 45 and 46 that sandwich the logical cell changeable unit 51 in the width direction of the diffusion layer. In the logic cell changeable unit 52, there is one pair of a MOSFET transistor and an NMOS transistor (a pair of Pch1 and Nch1 or a pair of Pch2 and Nch1). This pair allows changes to complex logic circuits.

FIG. 22 is a plan view schematically showing an example of the layout of the multi-site EC decoupling cell 11 of 5 single sites after the logical cell change. FIG. 23 is a diagram showing an example of a circuit of a 5-single-site multi-site EC decoupling cell 11 after changing the logic cell. 22 and 23 show an example in which a part of the logical cell changeable part is changed to a 4-input NAND cell. In FIG. 22, the portion surrounded by the dotted square shows the portion changed to the 4-input NAND cell. “Pch *” represents a NMOS transistor, and “Nch *” represents an NMOS transistor. * Represents a number. A1 to A4 represent the input unit of the NAND cell, and X represents the output unit of the NAND cell.

FIG. 24 shows an arrangement example of a multi-site EC decoupling cell having a large number of sites. FIG. 25 is a diagram showing the location of the logical cell changeable portion in the configuration of FIG. 24. By using a multi-site EC decoupling cell having a relatively large number of sites that fits in the free space, it is possible to secure a large number of changeable parts in the logical cell included in the logical cell changeable part. As a result, the area closest to the failed logical cell can be used for troubleshooting.

Further, by arranging the multi-site EC decoupling cells of the odd-numbered site and the even-numbered site in a mixed manner, it becomes easier to arrange the multi-site EC decoupling cells in the empty space without any gap.

Although the circuit element and the method of using the circuit element have been described above by the embodiment, the present invention is not limited to the above embodiment. Various modifications and improvements, such as combinations and substitutions with some or all of the other embodiments, are possible within the scope of the present invention.

Regarding the above embodiments, the following additional notes will be further disclosed.
(Appendix 1)
It has a multi-site structure in which three or more sites each including a MOSFET transistor and an NMOS transistor are arranged adjacent to each other in the width direction of the diffusion layer.
The multi-site structure includes a logical cell changeable portion that can be changed into a logical cell and a pair of decoupling cell portions that sandwich the logical cell changeable portion in the width direction.
The logic cell changeable portion includes a first site boundary connecting the gates of the epitaxial transistors provided by the adjacent sites in the width direction and the gates of the NMOS transistors provided by the adjacent sites in the width direction. Has a second site boundary to connect with
The boundary between the logic cell changeable portion and the pair of decoupling cell portions is a circuit element located between the NMOS transistor and the NMOS transistor.
(Appendix 2)
The local interconnects of the SiO transistors, which are provided by the adjacent sites in the width direction, are connected at the first site boundary.
The circuit element according to Appendix 1, wherein the local interconnects of the NMOS transistors provided by the adjacent sites in the width direction are connected at the second site boundary.
(Appendix 3)
Each of the epitaxial transistors provided by the adjacent sites in the width direction has a P-type diffusion layer connected to the first power rail via the local interconnect connected at the first site boundary.
Each of the NMOS transistors provided by the adjacent sites in the width direction is connected to a second power rail having a potential lower than that of the first power rail via a local interconnect connected at the second site boundary. The circuit element according to Appendix 2, which has an N-type diffusion layer.
(Appendix 4)
The circuit element according to any one of Appendix 1 to 3, wherein the pair of decoupling cell portions are located at both ends of the multisite structure in the width direction.
(Appendix 5)
Of the pair of decoupling cell portions, one decoupling cell portion includes a MOSFET transistor forming a decoupling capacitor, and the other decoupling cell portion includes an NMOS transistor forming a decoupling capacitor. 4. The circuit element according to any one of 4.
(Appendix 6)
The boundary is located between the first boundary located between the logical cell changeable portion and the one decoupling cell portion, and between the logical cell changeable portion and the other decoupling cell portion. Including the second boundary
The gate and local interconnect of the NMOS transistor included in the one decoupling cell portion are disconnected from the gate and local interconnect of the NMOS transistor included in the logic cell changeable portion at the first boundary.
The gate and the local interconnect of the NMOS transistor included in the other decoupling cell portion are not connected to the gate and the local interconnect of the NMOS transistor included in the logic cell changeable portion at the second boundary, according to Appendix 5. Circuit element.
(Appendix 7)
The circuit element according to any one of Supplementary note 1 to 6, wherein the transistor gate and the local interconnect provided in each of the pair of decoupling cell portions extend to a boundary with another site adjacent in the width direction. ..
(Appendix 8)
A method of using a circuit element having a multi-site structure in which three or more sites including a MOSFET transistor and an NMOS transistor are arranged adjacent to each other in the width direction of the diffusion layer.
The multi-site structure includes a logical cell changeable portion that can be changed into a logical cell and a pair of decoupling cell portions that sandwich the logical cell changeable portion in the width direction.
The logic cell changeable portion includes a first site boundary connecting the gates of the epitaxial transistors provided by the adjacent sites in the width direction and the gates of the NMOS transistors provided by the adjacent sites in the width direction. Has a second site boundary to connect with
The boundary between the logic cell changeable portion and the pair of decoupling cell portions is located between the MOSFET transistor and the NMOS transistor.
A method of using a circuit element, wherein the design apparatus changes at least a part of the logic cell changeable part into a logic cell by changing the wiring of the metal wiring layer of the logic cell changeable part.

10,11,12 Multi-site EC decoupling cell 20 P-type diffusion layer 23,24 Gate 27,31 Drain 28,32 Source 29 Via 30 N-type diffusion layer 34 LIC
35 Metal wiring 41-46 Decoupling cell part 50-52 Logical cell changeable part 61, 62, 63, 64 Site boundary 71, 72 PN boundary 100 Design device

Claims (8)

It has a multi-site structure in which three or more sites each including a MOSFET transistor and an NMOS transistor are arranged adjacent to each other in the width direction of the diffusion layer.
The multi-site structure includes a logical cell changeable portion that can be changed into a logical cell and a pair of decoupling cell portions that sandwich the logical cell changeable portion in the width direction.
The logic cell changeable portion includes a first site boundary connecting the gates of the epitaxial transistors provided by the adjacent sites in the width direction and the gates of the NMOS transistors provided by the adjacent sites in the width direction. Has a second site boundary to connect with
The boundary between the logic cell changeable portion and the pair of decoupling cell portions is a circuit element located between the NMOS transistor and the NMOS transistor. The local interconnects of the SiO transistors, which are provided by the adjacent sites in the width direction, are connected at the first site boundary.
The circuit element according to claim 1, wherein the local interconnects of the NMOS transistors provided by the adjacent sites in the width direction are connected at the second site boundary. Each of the epitaxial transistors provided by the adjacent sites in the width direction has a P-type diffusion layer connected to the first power rail via the local interconnect connected at the first site boundary.
Each of the NMOS transistors provided by the adjacent sites in the width direction is connected to a second power rail having a potential lower than that of the first power rail via a local interconnect connected at the second site boundary. The circuit element according to claim 2, which has an N-type diffusion layer. The circuit element according to any one of claims 1 to 3, wherein the pair of decoupling cell portions are located at both ends of the multisite structure in the width direction. The claim that one of the pair of decoupling cell portions includes a MOSFET transistor forming a decoupling capacitor, and the other decoupling cell portion includes an NMOS transistor forming a decoupling capacitor. The circuit element according to any one of 1 to 4. The boundary is located between the first boundary located between the logical cell changeable portion and the one decoupling cell portion, and between the logical cell changeable portion and the other decoupling cell portion. Including the second boundary
The gate and local interconnect of the NMOS transistor included in the one decoupling cell portion are disconnected from the gate and local interconnect of the NMOS transistor included in the logic cell changeable portion at the first boundary.
The fifth aspect of the present invention, wherein the gate and the local interconnect of the NMOS transistor included in the other decoupling cell portion are disconnected from the gate and the local interconnect of the NMOS transistor included in the logic cell changeable portion at the second boundary. Circuit element. The circuit according to any one of claims 1 to 6, wherein the transistor gate and the local interconnect provided in each of the pair of decoupling cell portions extend to a boundary with another site adjacent in the width direction. element. A method of using a circuit element having a multi-site structure in which three or more sites including a MOSFET transistor and an NMOS transistor are arranged adjacent to each other in the width direction of the diffusion layer.
The multi-site structure includes a logical cell changeable portion that can be changed into a logical cell and a pair of decoupling cell portions that sandwich the logical cell changeable portion in the width direction.
The logic cell changeable portion includes a first site boundary connecting the gates of the epitaxial transistors provided by the adjacent sites in the width direction and the gates of the NMOS transistors provided by the adjacent sites in the width direction. Has a second site boundary to connect with
The boundary between the logic cell changeable portion and the pair of decoupling cell portions is located between the MOSFET transistor and the NMOS transistor.
A method of using a circuit element, wherein the design apparatus changes at least a part of the logic cell changeable part into a logic cell by changing the wiring of the metal wiring layer of the logic cell changeable part.

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