JP6817168B2 - 被処理体を処理する方法 - Google Patents
被処理体を処理する方法 Download PDFInfo
- Publication number
- JP6817168B2 JP6817168B2 JP2017162602A JP2017162602A JP6817168B2 JP 6817168 B2 JP6817168 B2 JP 6817168B2 JP 2017162602 A JP2017162602 A JP 2017162602A JP 2017162602 A JP2017162602 A JP 2017162602A JP 6817168 B2 JP6817168 B2 JP 6817168B2
- Authority
- JP
- Japan
- Prior art keywords
- trench
- gas
- wafer
- film
- trench width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3244—Gas supply means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32715—Workpiece holder
- H01J37/32724—Temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67103—Apparatus for thermal treatment mainly by conduction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/332—Coating
- H01J2237/3321—CVD [Chemical Vapor Deposition]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
- H01J2237/3343—Problems associated with etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
- H01J2237/3343—Problems associated with etching
- H01J2237/3344—Problems associated with etching isotropy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Analytical Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
長方形GCb1は、方法MTの実行前におけるトレンチTR2のトレンチ幅WW1bであってウエハWの表面のうち当該表面の中心部のトレンチ幅WW1bの値(WW1bC)を表している。WW1bC>WW1aC、および、WW1bC−WW1aC=Δ1の関係が満たされる。
Claims (15)
- 被処理体を処理する方法であって、該被処理体には複数のトレンチが該被処理体の表面に設けられており、該方法は、
複数の前記トレンチのトレンチ幅を測定する第1工程と、
前記第1工程において測定した前記トレンチ幅の前記表面におけるバラツキが予め設定された基準範囲内にない場合に該トレンチ幅を調節する第2工程と、
前記バラツキが前記基準範囲内にあり且つ前記第1工程において測定した前記トレンチ幅が予め設定された基準幅よりも狭い場合に該トレンチ幅を広げるエッチング処理を行う第3工程と、
を含む基本工程を備え、
前記表面は、当該方法において複数の領域に区分けされており、
前記第2工程は、
前記表面の温度を複数の前記領域ごとに調節する第4工程と、
前記トレンチの内面に膜を形成する膜形成処理を行う第5工程と、
を備え、
前記第4工程は、前記膜形成処理における前記表面の温度と前記トレンチの内面に堆積する膜の膜厚との対応を示す予め取得された対応データを用いて、該膜の形成によって前記バラツキを低減するように該表面の温度を調節し、
前記膜形成処理は、
前記被処理体が収容されたプラズマ処理装置の処理容器内に第1のガスを供給する第6工程と、
前記第6工程の実行後に、前記処理容器内の空間をパージする第7工程と、
前記第7工程の実行後に、前記処理容器内で第2のガスのプラズマを生成する第8工程と、
前記第8工程の実行後に、前記処理容器内の空間をパージする第9工程と、
を含む第1シーケンスを繰り返し実行し、
前記エッチング処理は、
前記処理容器内に第3のガスのプラズマを生成し該第3のガスのプラズマに含まれるイオンを含む混合層を前記トレンチの内面の原子層に等方的に形成する第10工程と、
前記第10工程の実行後に、前記処理容器内の空間をパージする第11工程と、
前記第11工程の実行後に、前記処理容器内において第4のガスのプラズマを生成し該第4のガスのプラズマに含まれるラジカルによって前記混合層を除去する第12工程と、
前記第12工程の実行後に、前記処理容器内の空間をパージする第13工程と、
を含む第2シーケンスを繰り返し実行し前記膜を原子層ごとに除去することによって該膜を等方的にエッチングし、
前記膜は、シリコンを含み、
前記第1のガスは、アミノシラン系ガスを含み、
前記第2のガスは、酸素原子を含有するガスを含み、
前記第3のガスは、窒素を含み、
前記第4のガスは、フッ素を含み、
前記第12工程において生成される前記第4のガスのプラズマは、シリコンの窒化物を含む前記混合層を除去する前記ラジカルを含み、
前記第6工程は、前記第1のガスのプラズマを生成しない、
方法。 - 前記基本工程は、前記第2工程の実行後および前記第3工程の実行後に前記第1工程に戻る、
請求項1に記載の方法。 - 前記基本工程は、繰り返し実行され、
前記基準範囲は、前記基本工程の実行が繰り返されるごとに段階的に狭くなる、
請求項1または請求項2に記載の方法。 - 前記第1のガスは、モノアミノシランを含む、
請求項1〜3の何れか一項に記載の方法。 - 前記第1のガスのアミノシラン系ガスは、1〜3個のケイ素原子を有するアミノシランを含む、
請求項1〜3の何れか一項に記載の方法。 - 前記第1のガスのアミノシラン系ガスは、1〜3個のアミノ基を有するアミノシランを含む、
請求項1〜3,5の何れか一項に記載の方法。 - 前記第4のガスは、NF3ガスおよびO2ガスを含む混合ガスである、
請求項1〜6の何れか一項に記載の方法。 - 前記第4のガスは、NF3ガス、O2ガス、H2ガスおよびArガスを含む混合ガスである、
請求項1〜6の何れか一項に記載の方法。 - 前記第4のガスは、CH3Fガス、O2ガスおよびArガスを含む混合ガスである、
請求項1〜6の何れか一項に記載の方法。 - 被処理体を処理する方法であって、
(a)複数の領域に区分けされた表面に複数のトレンチが設けられた被処理体を提供し、
(b)前記複数のトレンチの各々のトレンチ幅を測定し、
(c)前記(b)の後に、前記トレンチ幅のバラツキが予め設定された基準範囲内となるように行う膜形成処理によって該トレンチ幅の該バラツキを調節し、該膜形成処理は、
(i)前記(b)において測定された前記複数のトレンチの各々の前記トレンチ幅に基づいて、前記複数の領域ごとに前記被処理体の表面の温度を調節し、
(ii)第1のガスを前記被処理体の表面に付着させることによって、該被処理体の表面に反応前駆体を形成し、
(iii)第2のガスのプラズマによって、前記反応前駆体から前記被処理体の表面に層を形成し、
(iV)前記(ii)及び前記(iii)を繰り返して、前記トレンチの内面に膜を形成する、
方法。 - (d)前記(c)の後に、前記複数のトレンチの各々の内面に形成された前記膜を等方的にエッチングする、
請求項10に記載の方法。 - 前記(c)及び(d)を繰り返す、
請求項11に記載の方法。 - 前記(d)では、原子層エッチングが用いられる、
請求項11に記載の方法。 - 前記原子層エッチングは、
前記トレンチの内面に形成された膜を表面改質するために、プラズマを用いて該膜の表面に混合層を形成する、
請求項13に記載の方法。 - 被処理体を処理する方法であって、
(a)複数のトレンチが設けられた被処理体を提供し、
(b)前記被処理体の表面の複数の領域ごとに、前記複数のトレンチの各々のトレンチ幅を測定し、
(c)前記(b)の後に、前記トレンチ幅のバラツキが予め設定された基準範囲内となるように行う膜形成処理によって該トレンチ幅の該バラツキを調節し、該膜形成処理は、
(i)前記複数の領域ごとに前記被処理体の表面の温度を調節し、
(ii)第1のガスを前記被処理体の表面に付着させることによって、該被処理体の表面に反応前駆体を形成し、
(iii)第2のガスのプラズマによって、前記反応前駆体から前記被処理体の表面に層を形成し、
(iV)前記(ii)及び前記(iii)を繰り返して、前記トレンチの内面に膜を形成し、
前記(i)は、前記被処理体の表面の温度と前記トレンチの内面に形成された前記膜の膜厚との対応を示す予め取得された対応データを用いて、該被処理体の表面の温度を調節する、
方法。
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017162602A JP6817168B2 (ja) | 2017-08-25 | 2017-08-25 | 被処理体を処理する方法 |
| TW111103533A TWI801113B (zh) | 2017-08-25 | 2018-08-16 | 被處理體之處理方法及電漿處理裝置 |
| TW107128531A TW201921432A (zh) | 2017-08-25 | 2018-08-16 | 被處理體之處理方法 |
| KR1020180098685A KR102632154B1 (ko) | 2017-08-25 | 2018-08-23 | 피처리체를 처리하는 방법 |
| US16/111,789 US10748766B2 (en) | 2017-08-25 | 2018-08-24 | Workpiece processing method |
| CN202211541768.0A CN115732351A (zh) | 2017-08-25 | 2018-08-24 | 处理被处理体的方法 |
| CN201810971368.0A CN109427607B (zh) | 2017-08-25 | 2018-08-24 | 处理被处理体的方法 |
| US16/925,934 US11322354B2 (en) | 2017-08-25 | 2020-07-10 | Workpiece processing method |
| US17/728,618 US11735423B2 (en) | 2017-08-25 | 2022-04-25 | Workpiece processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017162602A JP6817168B2 (ja) | 2017-08-25 | 2017-08-25 | 被処理体を処理する方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019041021A JP2019041021A (ja) | 2019-03-14 |
| JP2019041021A5 JP2019041021A5 (ja) | 2020-06-18 |
| JP6817168B2 true JP6817168B2 (ja) | 2021-01-20 |
Family
ID=65437918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017162602A Active JP6817168B2 (ja) | 2017-08-25 | 2017-08-25 | 被処理体を処理する方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US10748766B2 (ja) |
| JP (1) | JP6817168B2 (ja) |
| KR (1) | KR102632154B1 (ja) |
| CN (2) | CN109427607B (ja) |
| TW (2) | TWI801113B (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7066565B2 (ja) * | 2018-07-27 | 2022-05-13 | 東京エレクトロン株式会社 | プラズマ処理方法およびプラズマ処理装置 |
| US10950428B1 (en) * | 2019-08-30 | 2021-03-16 | Mattson Technology, Inc. | Method for processing a workpiece |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3267199B2 (ja) * | 1996-07-11 | 2002-03-18 | 株式会社デンソー | 半導体装置の製造方法 |
| US6620741B1 (en) * | 2002-06-10 | 2003-09-16 | Intel Corporation | Method for controlling etch bias of carbon doped oxide films |
| KR100480610B1 (ko) | 2002-08-09 | 2005-03-31 | 삼성전자주식회사 | 실리콘 산화막을 이용한 미세 패턴 형성방법 |
| US6770852B1 (en) * | 2003-02-27 | 2004-08-03 | Lam Research Corporation | Critical dimension variation compensation across a wafer by means of local wafer temperature control |
| JP2005064324A (ja) * | 2003-08-18 | 2005-03-10 | Konica Minolta Holdings Inc | 微細形状の加工方法及び光学素子 |
| JP4727171B2 (ja) * | 2003-09-29 | 2011-07-20 | 東京エレクトロン株式会社 | エッチング方法 |
| US7416676B2 (en) * | 2005-02-16 | 2008-08-26 | Tokyo Electron Limited | Plasma etching method and apparatus, control program for performing the etching method, and storage medium storing the control program |
| JP2007035777A (ja) * | 2005-07-25 | 2007-02-08 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及び半導体製造装置 |
| JP4722725B2 (ja) * | 2006-02-17 | 2011-07-13 | 東京エレクトロン株式会社 | 処理方法およびプラズマエッチング方法 |
| JP4877747B2 (ja) * | 2006-03-23 | 2012-02-15 | 東京エレクトロン株式会社 | プラズマエッチング方法 |
| TWI424498B (zh) * | 2006-03-31 | 2014-01-21 | Applied Materials Inc | 用以改良介電薄膜之階梯覆蓋與圖案負載的方法 |
| US7780865B2 (en) * | 2006-03-31 | 2010-08-24 | Applied Materials, Inc. | Method to improve the step coverage and pattern loading for dielectric films |
| JP4790649B2 (ja) * | 2007-03-16 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| KR101217778B1 (ko) * | 2007-06-08 | 2013-01-02 | 도쿄엘렉트론가부시키가이샤 | 패터닝 방법 |
| JP2009295729A (ja) * | 2008-06-04 | 2009-12-17 | Hitachi Kokusai Electric Inc | 基板処理装置 |
| US20100227059A1 (en) * | 2009-03-04 | 2010-09-09 | Tokyo Electron Limited | Film deposition apparatus, film deposition method, and computer readable storage medium |
| JP5181100B2 (ja) * | 2009-04-09 | 2013-04-10 | 東京エレクトロン株式会社 | 基板処理装置、基板処理方法及び記憶媒体 |
| US20130187159A1 (en) * | 2012-01-23 | 2013-07-25 | Infineon Technologies Ag | Integrated circuit and method of forming an integrated circuit |
| KR101909091B1 (ko) * | 2012-05-11 | 2018-10-17 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| US8852964B2 (en) * | 2013-02-04 | 2014-10-07 | Lam Research Corporation | Controlling CD and CD uniformity with trim time and temperature on a wafer by wafer basis |
| US9768220B2 (en) * | 2014-04-15 | 2017-09-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Deep trench isolation structure for image sensors |
| JP2016031962A (ja) * | 2014-07-28 | 2016-03-07 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
| JP2016058590A (ja) * | 2014-09-11 | 2016-04-21 | 株式会社日立ハイテクノロジーズ | プラズマ処理方法 |
| US9576811B2 (en) * | 2015-01-12 | 2017-02-21 | Lam Research Corporation | Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch) |
| KR102442309B1 (ko) * | 2015-07-09 | 2022-09-13 | 삼성전자주식회사 | 소자 분리 구조의 형성 방법 |
| US9640423B2 (en) * | 2015-07-30 | 2017-05-02 | GlobalFoundries, Inc. | Integrated circuits and methods for their fabrication |
| US10211051B2 (en) * | 2015-11-13 | 2019-02-19 | Canon Kabushiki Kaisha | Method of reverse tone patterning |
| TWI733850B (zh) * | 2016-07-27 | 2021-07-21 | 美商應用材料股份有限公司 | 使用沉積/蝕刻技術之無接縫溝道填充 |
-
2017
- 2017-08-25 JP JP2017162602A patent/JP6817168B2/ja active Active
-
2018
- 2018-08-16 TW TW111103533A patent/TWI801113B/zh active
- 2018-08-16 TW TW107128531A patent/TW201921432A/zh unknown
- 2018-08-23 KR KR1020180098685A patent/KR102632154B1/ko active Active
- 2018-08-24 US US16/111,789 patent/US10748766B2/en active Active
- 2018-08-24 CN CN201810971368.0A patent/CN109427607B/zh active Active
- 2018-08-24 CN CN202211541768.0A patent/CN115732351A/zh active Pending
-
2020
- 2020-07-10 US US16/925,934 patent/US11322354B2/en active Active
-
2022
- 2022-04-25 US US17/728,618 patent/US11735423B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR102632154B1 (ko) | 2024-01-31 |
| TW202220030A (zh) | 2022-05-16 |
| CN115732351A (zh) | 2023-03-03 |
| TWI801113B (zh) | 2023-05-01 |
| JP2019041021A (ja) | 2019-03-14 |
| US20220254635A1 (en) | 2022-08-11 |
| US11322354B2 (en) | 2022-05-03 |
| TW201921432A (zh) | 2019-06-01 |
| CN109427607A (zh) | 2019-03-05 |
| US20200343091A1 (en) | 2020-10-29 |
| US11735423B2 (en) | 2023-08-22 |
| US20190067009A1 (en) | 2019-02-28 |
| US10748766B2 (en) | 2020-08-18 |
| KR20190022394A (ko) | 2019-03-06 |
| CN109427607B (zh) | 2022-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20210140044A1 (en) | Film forming method and film forming apparatus | |
| US10777422B2 (en) | Method for processing target object | |
| KR102735966B1 (ko) | 피처리체를 처리하는 방법 | |
| KR102626138B1 (ko) | 피처리체의 처리 방법 | |
| US10483118B2 (en) | Etching method | |
| TWI757483B (zh) | 蝕刻方法 | |
| US11735423B2 (en) | Workpiece processing method | |
| US12476115B2 (en) | Method for processing workpiece |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200323 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20200323 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200508 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20201030 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20201201 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20201224 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6817168 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |