JP6723175B2 - Gate drive device and gate drive method for power semiconductor - Google Patents

Description

The present invention relates to a gate driving device and a gate driving method for a power semiconductor used in a power conversion device such as an inverter, a converter or a DC chopper circuit.

In a power converter such as an inverter that converts DC power into AC power, a converter that converts AC power into DC power, or a DC chopper circuit that boosts or lowers DC voltage, power semiconductor elements such as IGBTs are widely used. .. This power semiconductor element is driven by an on/off signal from the gate driving device. The gate drive device is controlled by a signal from a control logic unit that is a controller of the power conversion device.

As an example of using the gate drive device, FIG. 2 shows the overall configuration of a two-level inverter used as a power conversion device for a railway vehicle.
The power conversion device 4 includes a control logic unit 11, gate drive devices 21 to 26, a signal line 12 connecting the control logic unit 11 and the gate drive devices 21 to 26, and power semiconductors 31 to 36. The positive power supply line is connected to the overhead wire via the pantograph 1, and the negative power supply line is connected to the rail via the wheels 6. The filter reactor 2 and the filter capacitor 3 are provided so that a track circuit (not shown) that operates at several tens of Hz does not malfunction due to inductive interference due to the operation of the power conversion device 4. The circuit breaker 7 is provided to protect the power conversion device 4 by cutting off the power supply when overcurrent and overvoltage occur.

Next, the operation of the power conversion device 4 will be described. The gate driving devices 21 to 26, on the basis of the ON/OFF command of the power semiconductors 31 to 36 transmitted from the control logic unit 11, in the case of the ON command, supply a positive voltage to the gate with respect to the source, and in the case of the OFF command. Outputs a negative voltage to the gate with respect to the source. The power semiconductors 31 to 36 repeat conduction/non-conduction according to the voltage output from the gate drive devices 21 to 26, thereby converting the DC power supplied from the overhead wire into the AC power of the pulse train, and the AC motor. Drive 5

2. Description of the Related Art In recent years, in a great social trend of reducing environmental load, demands for higher efficiency and lower loss of power conversion devices are increasing. As a method for responding to this demand, a power converter using a power semiconductor made of silicon carbide (SiC) or gallium nitride (GaN) having a large band cap is becoming popular in place of the conventional silicon power semiconductor element. .. Since these power semiconductors having a large band gap have a withstand voltage of about 10 times that of a silicon power semiconductor, the thickness of the semiconductor chip can be reduced to about 1/10. Therefore, the resistance at the time of conduction is reduced to about 1/10, and the characteristic is that conduction loss can be reduced.

JP, 2013-219874, A

In order to meet the demands for higher efficiency and lower loss of the power conversion device, when using the above-mentioned power semiconductor made of SiC, the SiC MOS-gated power semiconductor is in the off state in which a negative voltage is output to the gate. When a voltage lower than the predetermined voltage is applied for a long time, there is a problem that the threshold value shifts to the negative side. For example, in the case of a SiC MOSFET having a threshold value of 4V, the threshold value decreases by 1V to 3V due to a long-time negative bias. When the threshold value shifts to the negative side, the diode of the arm that forms a pair with the inverter also changes the gate voltage due to the abrupt change of the drain voltage during reverse recovery, and the MOSFET is erroneously turned on. The elements may cause arm short circuit (a phenomenon in which they are turned on at the same time). Since the shift of the gate voltage increases depending on the magnitude of the negative bias of the gate, it is desirable to use the negative bias as small as possible. However, if the negative bias is small, the risk of erroneous turn-on is increased if the gate voltage fluctuates during the recovery described above, so it cannot be simply reduced. As a countermeasure against this, for example, Japanese Patent Laid-Open No. 2013-219874 discloses a technique of reducing the negative bias voltage only during recovery to solve the above-mentioned problem of threshold shift.

Further, when the voltage to be converted is as high as 600 to 3000 V, like a power converter for railways, in order to ensure the reliability of the device, it is operated by connecting to a control logic unit operating at a low voltage and a main circuit at a high voltage. Signal transmission between the gate driving devices to be driven and between the gate driving devices paired with the upper and lower arms needs to be performed through an insulating element such as an optical fiber or a photocoupler.

In the technique disclosed in Patent Document 1 described above, the negative bias voltage is made lower than usual by using the ON command of one of the upper and lower arms as a trigger. However, in this method, in addition to the ON/OFF command transmitted between the control logic unit and the gate drive unit, the gate drive of the arm paired between the control logic unit and the gate drive unit or one of the gate drive units is used. A means for newly transmitting an on/off command between the devices is required. Therefore, it is necessary to newly provide a signal transmission/reception circuit including a signal line and an insulating element, which causes a problem that the device becomes large.

The gate output circuit controls the gate voltage applied to the gate of the power semiconductor to the first voltage when the gate on command is received, and controls the gate voltage to the second voltage when the gate off command is received. Monitors the gate voltage to determine the on/off state of the power semiconductor, and the timer circuit detects the off state determination output from the on/off state determination circuit to output a signal for a fixed time to the gate output circuit. The gate output circuit controls the gate voltage to the third voltage, which is lower than the second voltage, while inputting the signal for a certain period of time.

According to the present invention, a negative bias is provided only during recovery without newly adding a signal transmission path between the control logic unit and the gate driver and between the gate driver of the arm paired with the gate driver through an insulating element. It is possible to reduce the power consumption, and to provide a highly reliable and compact power conversion device that suppresses deterioration of power semiconductor elements and does not increase the size of the device.

1 is a block diagram showing a configuration of a first embodiment of a gate driving device according to the present invention. FIG. 2 is a diagram showing an overall configuration diagram of a two-level inverter used as a power conversion device for a railway vehicle. FIG. 3 is a diagram illustrating a specific configuration example of the gate output circuit according to the first embodiment. FIG. 4 is a time chart showing an operation mode at the time of recovery according to the first embodiment. FIG. 5 is a diagram showing a configuration of a second embodiment of the gate driving device according to the present invention. FIG. 6 is a time chart showing an operation mode during recovery according to the second embodiment. FIG. 7 is a diagram showing a configuration of a third embodiment of the gate drive device according to the present invention. FIG. 8 is a diagram showing a time chart when the gate voltage is lowered to Vss2b after turn-off in the third embodiment. FIG. 9 is a diagram showing a time chart in the case where the gate voltage is not lowered to Vss2b after turn-off in the third embodiment. FIG. 10 is a diagram showing the configuration of a fourth embodiment of the gate drive device according to the present invention. FIG. 11 is a diagram illustrating a current detection circuit that is a component of the fourth embodiment. FIG. 12 is a diagram showing a time chart when the gate voltage is lowered to Vss2b after turn-off in the fourth embodiment. FIG. 13 is a diagram showing a time chart when the gate voltage is not lowered to Vss2b after turn-off in the fourth embodiment. FIG. 14 is a diagram showing a time chart in the case where the turn-on time of the anti-arm is predicted after turn-off and the gate voltage is lowered to Vss2b only for the necessary minimum time.

As modes for carrying out the present invention, Examples 1 to 4 of a gate driving device according to the present invention will be described below with reference to the drawings.

1 is a block diagram showing a configuration of a first embodiment of a gate driving device according to the present invention. The first embodiment has a function of lowering the negative bias voltage only at the time of recovery.
The gate drive device 22 receives the output of the gate command level conversion circuit 101 for converting the level of the gate on/off command 111, the gate on/off command LIN (112) level-converted by the gate command level conversion circuit 101, and the timer circuit 104. A gate output circuit 102 that outputs a gate output voltage LO1 (113) to the gate of the power semiconductor element, an on/off state determination circuit 103 that determines the state of the gate of the power semiconductor element from a gate voltage monitoring signal 114 by the gate output circuit 102, and The timer circuit 104 is configured to drive the timer circuit output N1 (117) for a certain time by the feedback signal LFB (115) which is the output of the on/off state determination circuit 103.

In the gate drive device 22, the gate on/off command 111 output from the control logic unit 11 is input to the gate command level conversion circuit 101 via an insulating element (not shown). This on/off command 111 becomes a gate on/off command LIN (112) whose level is converted to an amplitude level capable of driving the SiC power semiconductor 32 by the gate command level conversion circuit 101. The gate output circuit (102) outputs the gate voltage LO1 (113) based on the received gate on/off command LIN (112) to the base of the SiC power semiconductor 32.

Further, the gate voltage monitoring signal 114 output from the gate output circuit 102 is compared with the reference voltage in the on/off state determination circuit (103), and if it is equal to or higher than the reference voltage, the feedback signal LFB (115) is output as an on signal. If it is less than the reference voltage, the feedback signal LFB (115) is output as an off signal. The feedback signal 116 level-converted by the gate command level conversion circuit (101) is transmitted to the control logic unit (11).

When the control logic unit 11 and the gate drive device 22 are connected by an optical fiber, the gate command level conversion circuit 101 only converts the amplitudes of the gate command 111 and the feedback signal 115. On the other hand, when the control logic unit 11 and the gate drive device 22 are connected by an electric wire, a function of insulating the control logic unit 11 driven at a low voltage from the SiC power semiconductor 32 and the gate output circuit 102 driven at a high voltage is provided. It is provided in the gate command level conversion circuit 101.

The feature of the first embodiment is that the feedback signal LFB (115) is used as a trigger to lower the negative bias voltage at the time of recovery from the off-voltage at the normal time, and return the negative bias voltage to the off-voltage at the normal time after completion of the recovery. It is in. This makes it possible to pull down the negative bias of the gate only during recovery without the on/off information from the anti-arm.

FIG. 3 is a diagram illustrating a specific configuration example of the gate voltage output circuit 102 according to the first embodiment. The gate voltage output circuit 102 includes three MOS transistors 121, 122 and 123, gate resistors 131 and 132 for controlling the switching characteristics of the SiC power semiconductor 32, bias resistors 133 and 134 for turning on the MOS transistor 123, and In addition, it is composed of a negative bias switching comparator 141 that compares the output N1 (117) of the timer circuit 104 with the reference voltage Vref.

When the gate command 112 is on, the MOS transistor 121 is on and the gate output voltage LO1 (113) becomes the positive bias voltage VDD2. When the gate command 112 is off, the MOS transistor 122 is on and the gate output is The voltage LO1 (113) becomes the negative bias voltage VSS2a. Although the transistors 121 to 123 are MOS transistors in FIG. 3, it is clear that the same effect can be obtained even when the transistors 121 to 123 are bipolar transistors.

Next, the operation mode at the time of recovery will be described using the time chart of FIG. FIG. 4 is a diagram showing operation waveforms of respective parts in a state where current is flowing from the inverter side to the load side. As signals first shown in FIG. 4, HIN is an upper arm gate on/off command, VgsH is an upper arm gate voltage, HFB is an upper arm feedback signal, VdsL is a lower arm drain-source voltage, and IdL is a lower arm voltage. The drain current is shown, and the case where the current flows from the drain to the source is positive.

When the gate on/off command LIN (112) of the lower arm becomes L level by the gate off command, the gate voltage VgsL (113) changes from the positive bias voltage VDD2 to the negative bias voltage VSS2a, but constitutes a power semiconductor. Since the current flows through the free wheel diode connected in anti-parallel with the MOSFET, the drain voltage VdsL and drain current IdL of the lower arm do not change. In this state, a motor current flows from the power converter 4 toward the AC motor 5, and in the SiC power semiconductor 32 of the lower arm, a current flows in a freewheel diode which is not parallel but a MOSFET that constitutes the power semiconductor. Is. However, when the gate voltage VgsL (113) becomes the negative bias voltage VSS2a, the on/off state determination circuit 103 in the gate drive device 22 determines that it is turned off, and the feedback signal LFB (115) is at the H level of the turn-off state. Signal changes to. When the feedback signal LFB (115) changes to the H level, the timer circuit 104 operates and outputs the signal N1 (117) which becomes the H level for the fixed time Td.

When the H level of the signal N1 (117) becomes higher than Vref, the output of the comparator 141 (FIG. 3) changes from the L level to the H level, and the MOS transistor 123 turns on. As a result, the negative bias voltage of the gate output voltage LO1 (113) drops from VSS2a to VSS2b. When the SiC power semiconductor 31 of the upper arm is turned on, the SiC power semiconductor 32 of the lower arm is reverse-recovered, and the gate voltage VgsL (113) of the lower arm is momentarily increased due to the abrupt change of the drain voltage VdsL. However, since the gate voltage VgsL is lowered to VSS2b, it does not reach the threshold of the MOSFET forming the power semiconductor, and the MOSFET forming the power semiconductor does not turn on erroneously. When the recovery operation ends and the time Td during which the output N1 (117) of the timer circuit 104 is at the H level elapses, the output of N1 (117) becomes the L level and becomes lower than Vref. As a result, the comparator 141 is turned off, and the negative bias voltage of the gate output voltage LO1 (113) returns to VSS2a.

According to the first embodiment, as described above, the simple system configuration prevents false ignition at the time of recovery, prevents the threshold Vth from shifting, suppresses the deterioration of the power semiconductor element, and shortens the life of the element. Makes it possible to prolong. As a result, it is possible to prevent the gate drive device from increasing in size while maintaining reliability.

In the above configuration, for example, the normal off-time voltage VSS2a is set to -5V, and the time Td when the timer circuit 104 outputs the H level is the output of the gate output circuit 102 of the paired arm after the output of the gate output circuit 102 changes. Is about 5 .mu.s to 10 .mu.s, which is determined by the total of the dead time and the recovery time until .DELTA. Only during this period, the negative bias voltage VSS2b is lowered to −10V. However, in an environment where the influence of noise is extremely small, the deterioration of the SiC power semiconductor element can be further suppressed by setting VSS2a to 0V and VSS2b to -3V.

In the above description, the SiC power semiconductor has been described as an example. However, when a negative bias is applied for a long time, the threshold voltage Vth of the power semiconductor element shifts to the negative side, which is effective for all the power semiconductor elements that deteriorate.

FIG. 5 is a diagram showing a configuration of a second embodiment of the gate driving device according to the present invention. The difference from the configuration of the first embodiment shown in FIG. 1 is that the gate drive device 22 is not provided with the on/off state determination circuit 103, and the control logic unit 11 does not have the function of transmitting the feedback signal 116 of the on/off state. is there. Therefore, as shown in the time chart of FIG. 6, when the OFF of the gate ON/OFF command LIN (112) of the lower arm is detected, the timer circuit 104 unconditionally sets the signal N1 (117) to the H level for the fixed time Td. ) Is output.

The feature of the second embodiment is that the negative bias voltage is lowered only at the time of recovery only by the signal of the gate drive device 22 even in a simple system configuration in which the feedback signal 116 is not transmitted to the control logic unit 11 which is a higher-level controller. Is possible.

FIG. 7 is a diagram showing a configuration of a third embodiment of the gate drive device according to the present invention. The difference from the configuration of the first embodiment shown in FIG. 1 is that a function of monitoring the drain voltage is added to the gate drive device 22, and a drain voltage determination circuit 105 and a timer measurement start circuit 106 by an AND function are added as components. That is the point. The operation mode of the third embodiment will be described below with reference to the time charts of FIGS. 8 and 9.

FIG. 8 is a diagram showing a time chart when the SiC power semiconductor 32 of the lower arm recovers. When the lower arm gate on/off command LIN (112) from the control logic unit 11 is turned off, the gate output voltage LO1 (113) drops to VSS2a, but the drain-source voltage VdsL and the drain current IdL do not change. In this state, the motor current flows from the power converter 4 toward the AC motor 5, and in the SiC power semiconductor 32 of the lower arm, the current flows through the anti-freewheel diode which is not parallel but the MOSFET forming the power semiconductor. Is. Therefore, even if the gate output voltage changes from the positive bias voltage VDD2 to the negative bias voltage VSS2a, the operation mode (drain-source voltage VdsL or drain current IdL) does not change.

In this mode, the drain voltage determination circuit 105 detects that the drain-source voltage VdsL (118) does not change even if the feedback signal LFB (115) detects the turn-off state. As a result, the drain voltage determination circuit 105 outputs the H level drain voltage Low level detection signal 119, the timer measurement start circuit 106 ANDs the feedback signal LFB (115), and the AND signal is input to the timer circuit 104. An H level signal is output from the timer circuit 104 for a predetermined time Td, and the negative bias voltage of the gate output voltage LO1 (113) is lowered to VSS2b.

Next, FIG. 9 is a diagram showing a time chart when the SiC power semiconductor 32 of the lower arm is not recovered. The difference from the time chart in FIG. 8 is that the motor current flows from the AC motor 5 to the power converter 4 in FIG. 2 (regeneration mode). In this mode, when the lower arm gate command is turned off, the gate output voltage LO1 (113) decreases to VSS2a, the drain-source voltage VdsL increases, and the drain current IdL decreases. At this time, the drain voltage determination circuit 105 detects the rise in VdsL, outputs the L level drain voltage Low level detection signal 119, and does not operate the timer circuit 104. Therefore, the gate output voltage LO1 (113) remains VSS2a.

As described above, the feature of the third embodiment is that the negative bias voltage that causes the shift of the threshold value is not lowered to VSS2b in the mode in which the recovery operation is not performed, so that the deterioration of the power semiconductor element can be further prevented.

In the above-mentioned time chart, the change of the feedback signal LFB (115) is assumed to be slower than the change of VdsL, but the reverse case is also possible. In this case, the drain voltage determination circuit 105 determines the state of the drain-source voltage VdsL after a lapse of a certain time from the change of the feedback signal LFB (115), and outputs the drain voltage Low level detection signal 119, and the timer circuit The operation of 104 will be decided. As a result, even when the change in the feedback signal LFB (115) is faster than the change in VdsL, the gate output voltage LO1 (113) can be controlled in the same manner as described above, and the deterioration of the power semiconductor element can be further prevented. it can.

FIG. 10 is a diagram showing the configuration of a fourth embodiment of the gate drive device according to the present invention. The difference from the configuration of the first embodiment shown in FIG. 1 is that a function of monitoring an electromotive voltage generated in a source parasitic inductance 151 when a current flows through a SiC power semiconductor is added to a gate drive device 22, and as a component, The point is that the current detection circuit 150 and the timer measurement start circuit 106 by the AND function are added.

In the fourth embodiment, the source current IsL of the SiC power semiconductor 32 can be monitored by detecting the electromotive voltage generated in the source parasitic inductance 151 by the current detection circuit 150. When the current detection circuit 150 detects a change in the source current IsL, the current detection circuit 150 outputs a turn-off detection signal 153, the timer measurement start circuit 106 performs an AND operation with the feedback signal LFB (115), and outputs the negative bias voltage switching command 120 to the timer circuit 104. To enter.

As shown in the time chart of FIG. 12, after the SiC power semiconductor 32 of the lower arm receives a turn-off command in response to a gate-off command from the control logic unit 11, it is determined that recovery occurs if the source current IsL does not change. , A negative bias VSS2b is applied for a certain period. This prevents the gate voltage of the SiC power semiconductor 32 from rising and erroneously firing.

On the other hand, as shown in the time chart of FIG. 13, after the SiC power semiconductor 32 of the lower arm receives the turn-off command by the gate-off command from the control logic unit 11, there is a change in the source current IsL (AC motor 5 in FIG. 2). In the mode in which the motor current flows from the power converter 4 to the power converter 4 (regeneration mode), it is determined that recovery does not occur, and the SiC power semiconductor 32 functions so as not to apply the negative bias VSS2b. Thereby, the deterioration of the SiC power semiconductor 32 can be suppressed.

FIG. 11 is a diagram showing a basic configuration example of the current detection circuit 150. The current detection circuit 150 detects a current by utilizing the fact that an electromotive voltage of V=Ldi/dt (V is a voltage, L is an inductance, and i is a current) is generated due to a change in the current. The circuit configuration shown in FIG. 11 suppresses the influence of noise and prevents malfunction.

As described above, in the fourth embodiment, when the electromotive voltage generated in the source parasitic inductance is used, the negative bias time can be controlled by the same mechanism by using the electromotive voltage generated in the drain parasitic inductance.
Further, the negative bias time can be controlled by the same mechanism by a method of capturing a current change of the SiC power semiconductor 32 by using an insulated current/voltage conversion component such as a current transformer or a Rogowski coil. Since the current transformer, the Rogowski coil, etc. are insulated, they do not significantly affect the size of the gate drive device.

Next, a method for further suppressing the deterioration of the SiC power semiconductor will be described with reference to FIG. The shorter the time for applying the negative bias VSS2b to the gate voltage, the more the change in the threshold voltage that leads to the deterioration of the SiC power semiconductor can be suppressed. Therefore, it is desirable to shorten the negative bias time as much as possible. In order to realize this, the time (dead time) at which the on/off command HIN to the gate of the upper arm changes after the on/off command LIN (102) to the gate of the lower arm changes is set to be constant. By doing so, the gate drive device 22 can predict the timing at which recovery occurs. That is, instead of applying the negative bias after the feedback signal LFB (115) has changed, the timing is adjusted by the timer circuit 104 so as to focus on the timing at which the recovery occurs and apply the negative bias for a shorter time. To This method can be applied to all of the first to fourth embodiments shown above.

1... Pantograph, 2... Filter reactor, 3... Filter capacitor,
4... Power converter, 5... AC motor, 6... Wheel,
11... Control logic unit, 12... Control command signal line,
21... U layer upper arm gate driver, 22... U layer lower arm gate driver,
23... V layer upper arm gate driver, 24... V layer lower arm gate driver,
25... W layer upper arm gate driver, 26... W layer lower arm gate driver,
31... U layer upper arm SiC power semiconductor, 32... U layer lower arm SiC power semiconductor,
33... V layer upper arm SiC power semiconductor, 34... V layer lower arm SiC power semiconductor,
35... W layer upper arm SiC power semiconductor, 36... W layer lower arm SiC power semiconductor,
101... Gate command level conversion circuit, 102... Gate voltage output circuit,
103... ON/OFF state determination circuit, 104... Timer circuit,
105... Drain voltage determination circuit, 106... Timer measurement start circuit,
111... ON/OFF command received from the control logic unit,
112... Level-converted gate on/off command LIN,
113... Gate output voltage LO1, 114... Gate voltage monitoring signal,
115... Feedback signal LFB, 116... Feedback signal transmitted to control logic unit,
117... Timer circuit output N1, 118... Drain-source voltage detection signal,
119... Drain voltage low level detection signal, 120... Negative bias voltage switching command,
121, 122, 123... MOS transistors, 131, 132... Gate resistors,
133, 134... Bias resistance, 141 Negative bias switching comparator 150... Current detection circuit, 151... Source parasitic inductance,
152... electromotive voltage detection signal due to source parasitic inductance, 153... turn-off detection signal

Claims (10)

A gate drive device for controlling a gate voltage applied to a gate of a power semiconductor in response to a gate on command or a gate off command from a control logic unit,
An on/off state determination circuit that determines the on/off state of the power semiconductor by monitoring the gate voltage,
The pre Kige over G Voltage controls the turn on receiving the first voltage command, a gate output circuit for controlling the second voltage when receiving the OFF command,
A timer circuit that outputs a signal for a certain period of time to the gate output circuit by detecting a determination of an off state output from the on/off state determination circuit ,
The gate driving device controls the gate voltage to a third voltage lower than the second voltage while inputting the signal for the fixed time. The gate drive device according to claim 1, wherein
Detecting a voltage of one main terminal from a pair of main terminals of the power semiconductor, further comprising a main terminal voltage determination circuit for determining whether the detected voltage changes after the power semiconductor is turned off ,
The timer circuit, by the detected voltage determines that the main terminal voltage judging circuit in the OFF state previous SL on / off state determination circuit outputs to the output detects the determination that does not change, the predetermined time The signal of the above is output to the gate output circuit. The gate drive device according to claim 1 , wherein
The power semiconductor to detect an electromotive voltage generated in the inductance parasitic on one of the main terminals of the pair of main terminals having further comprises a current determination circuit for determining the presence or absence of a change in the main current of the power semiconductor,
The timer circuit detects the determination of the off state output by the on/off state determination circuit and the determination that the main current output by the current determination circuit does not change, thereby outputting the signal of the fixed time. A gate driving device characterized by outputting to a gate output circuit. A gate drive apparatus according to any one of claims 1 to 3,
The gate drive device drives a power conversion device including the power semiconductor in an upper arm and a lower arm,
The timer circuit adjusts the timing of outputting the signal of the constant time to the gate output circuit in a state in which the dead time due to on/off of each of the power semiconductors included in the upper arm and the lower arm is constant. <br/> A gate drive device characterized by the above. The gate drive device according to claim 1, wherein
The gate driving device , wherein the power semiconductor is a semiconductor composed of silicon carbide . A gate driving method for controlling a gate voltage of a power semiconductor, comprising:
When an ON command is applied to the gate of the power semiconductor, the gate voltage of the power semiconductor is controlled to a first voltage,
Monitoring the gate voltage to determine the on/off state of the power semiconductor,
When an off command is applied to the gate of the power semiconductor, the gate voltage is controlled to a second voltage, and when the on/off off state is determined, the gate voltage is changed to the second voltage for a certain period of time. Control to a lower third voltage than
A gate driving method characterized by the above. The gate driving method according to claim 6, wherein
By detecting the voltage of one main terminal from the pair of main terminals of the power semiconductor, to determine whether the detected voltage changes after the power semiconductor is turned off,
By determining the OFF state and determining that the detected voltage does not change, the gate voltage is controlled to the third voltage lower than the second voltage during the certain period of time. And the gate driving method. The gate driving method according to claim 6 , wherein
By detecting an electromotive voltage generated in the inductance parasitic on any one of the main terminals of the pair of main terminals of the power semiconductor, to determine whether the main current of the power semiconductor changes,
By determining the off state and determining that the main current does not change, the gate voltage is controlled to the third voltage lower than the second voltage during the certain period of time. Gate driving method. The gate driving method according to any one of claims 6 to 8 ,
The gate driving method drives a power conversion device including the power semiconductor in an upper arm and a lower arm,
A gate driving method comprising adjusting a timing for setting the constant time in a state where a dead time accompanying turning on/off of each of the power semiconductors included in the upper arm and the lower arm is constant. .. The gate driving method according to any one of claims 6 to 9 ,
A gate driving method , wherein the power semiconductor is a semiconductor composed of silicon carbide .

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