JP6762656B2 - CPU standby return structure - Google Patents

Description

The present invention relates to a CPU standby return structure that returns a sleeping CPU, and more particularly to a CPU standby return structure that enables recovery even when an external interrupt is not inserted.

It is known that a CPU resets hardware when a WDT (Watchdog Timer) or the like overflows in order to prevent a freeze due to a runaway of software (for example, Patent Document 1). On the other hand, for example, in a CPU with a large circuit scale, a sleep state (ultra-low power consumption mode) in which only a specific interrupt terminal is left depending on the setting and the other external input blocks are stopped (power is cut off) to reduce power consumption. ) Can be migrated. In such an ultra-low power consumption mode, the reset terminal is also stopped and hardware reset cannot be performed based on the idea that software runaway does not occur during sleep.

Then, in the normal state, as shown in FIG. 4, when the external interrupt IR1 is input to the WKUP terminal of the CPU during the ultra-low power consumption mode, the CPU start WU1 is generated, and the WDT counter is reset by the CPU. To. Therefore, the WDT reset RS1 does not occur, and the hardware reset is not performed.

Japanese Unexamined Patent Publication No. 07-129413

By the way, as shown in FIG. 4, when the periodic external interrupt IR2 does not enter the WKUP terminal for some reason (when it freezes), the CPU startup WU2 does not occur, so the WDT counter is not reset and the WDT Overflows and WDT reset RS2 occurs. However, at this time, since the CPU is not started and the reset terminal is not functioning, the hardware is not reset and the product freezes.

Then, when the frozen state is reached, it has conventionally been necessary to restart by turning on the power again. That is, as shown in FIG. 5, in the state of shifting to the ultra-low power consumption mode (step S11), when the software cannot be controlled and freezes (step S12), the hardware is reset by WDT or the like (step S12). In step S13), since the hardware cannot be reset and the frozen state continues, it is necessary to turn on the power again (step S14) and restart (step S15).

However, for restarting, dedicated hardware such as a power supply circuit configuration that can be turned on again separately from normal operation and a backup power supply for the control circuit is required, which increases the component mounting area and component cost. There was a problem.

Therefore, an object of the present invention is to provide a CPU standby return structure that enables return even when an external interrupt is not inserted.

In order to solve the above problem, in the invention according to claim 1, an external interrupt unit that inserts an external interrupt into a sleeping CPU at a predetermined cycle to activate the CPU, and an external timer are the first. An external reset unit that resets the CPU when a predetermined time elapses, and an internal interrupt built into the CPU, when a second predetermined time elapses, inserts an internal interruption into the CPU to start the CPU. The CPU includes an internal interrupting unit, and when the CPU is activated by the external interruption, the external timer and the internal timer are reset, and the first predetermined time is set longer than the second predetermined time. The second predetermined time is set longer than the predetermined cycle , and in a normal state, the CPU activated by the external interruption resets the external timer and the internal timer, and the external allocation to the CPU. If there is no insertion, the CPU is started by the internal interruption when the second predetermined time elapses, and then the external reset unit resets the CPU when the first predetermined time elapses. It is a featured CPU standby return structure.

According to the present invention, in a normal state, an external interrupt unit inserts an external interrupt into a sleeping CPU at a predetermined cycle to start the CPU, and the external timer and the internal timer are reset. As a result, CPU reset and internal interrupt do not occur.

On the other hand, when the external interrupt by the external interrupt unit is not inserted for some reason, the internal timer enters the CPU by the internal interrupt unit after the second predetermined time elapses, and the CPU is started. After that, the external timer elapses for the first predetermined time, and the CPU is reset / restored by the external reset unit.

According to the invention of claim 1 , even if the CPU is not interrupted externally for some reason, the internal interrupt is inserted into the CPU and the CPU is started, so that the CPU is surely reset / restored. It becomes possible. As a result, since it is not necessary to turn on the power of the CPU again, it is possible to prevent or suppress an increase in the component mounting area and the component cost.

It is a timing chart which shows the operation of the CPU standby return structure which concerns on embodiment of this invention. It is a schematic block diagram which shows the CPU standby return structure of FIG. It is a flowchart which shows the operation of the CPU standby return structure of FIG. It is a timing chart which shows the operation of the conventional CPU standby return structure. It is a flowchart which shows the operation of the conventional CPU standby return structure.

Hereinafter, the present invention will be described based on the illustrated embodiment.

1 to 3 show an embodiment of the present invention, and FIG. 2 is a schematic block diagram showing a CPU standby return structure according to the embodiment of the present invention. This CPU standby return structure is a structure for returning the sleeping CPU 1, and as shown in FIG. 2, an external interrupt unit 2 and an external reset unit 3 provided outside the CPU 1 and an internal interrupt unit built in the CPU 1 are used. It is provided with an interrupt portion 4.

The external interrupt unit 2 inserts an external interrupt into the sleep state CPU 1 at a predetermined cycle to start the CPU 1, and is connected to the WKUP terminal 11 of the CPU 1.

The external reset unit 3 includes an external timer, which resets the CPU 1 when the first predetermined time elapses, and is connected to the reset terminal 12 of the CPU 1. Here, in this embodiment, the external timer is the WDT, and the CPU 1 is hardware reset by inputting the WDT reset to the reset terminal 12 when the first predetermined time has elapsed.

The internal interrupt unit 4 is a software control unit that can operate even in the ultra-low power consumption mode (sleep) of the CPU 1. It includes an internal timer, and when the internal timer elapses for a second predetermined time, the internal interrupt unit 4 is internally interrupted to the CPU 1. This is to start the CPU 1 with an interrupt.

Here, the first predetermined time is set longer than the second predetermined time, and the second predetermined time is set longer than the predetermined cycle. That is, it is set so that the external interrupt occurs first, the internal interrupt occurs next, and then the CPU reset occurs. Specifically, in this embodiment, the predetermined cycle is set to 30 seconds, the second predetermined time is set to 31 seconds, and the first predetermined time is set to 32 seconds.

Further, when the CPU 1 is started by an external interrupt from the external interrupt unit 2, it resets the external timer of the external reset unit 3 and the internal timer of the internal interrupt unit 4.

Next, the operation of the CPU standby return structure having such a configuration and the CPU standby return method will be described. Here, the power consumption is reduced by stopping (cutting off the power supply) other external input blocks such as the reset terminal 12 while leaving the specific interrupt terminal including the WKUP terminal 11 and the internal interrupt portion 4. It is assumed that the CPU 1 has shifted to the power consumption mode (one of the sleep states). Further, at the time of shifting to the ultra-low power consumption mode, the external interrupt unit 2 (predetermined cycle), the external reset unit 3 (external timer), and the internal interrupt unit 4 (internal timer) are set. Further, when the CPU 1 is started in the ultra-low power consumption mode, all the external input blocks function.

As shown in FIG. 1, first, in a normal state, when the external interrupt IR1 is input from the external interrupt unit 2 to the WKUP terminal 11 in a predetermined cycle (30 second cycle), the CPU1 start WU1 is generated and the external reset unit 3 is generated. The external timer and the internal timer of the internal interrupt unit 4 are reset. As a result, the WDT reset RS1 and the internal interrupt IR11 do not occur. Normally, such processing is repeated.

On the other hand, if the external interrupt IR2 by the external interrupt unit 2 does not enter due to some reason such as software runaway, the startup WU2 of the CPU 1 by the external interrupt IR2 does not occur, so that the external timer and the internal of the external reset unit 3 do not occur. The internal timer of the interrupt unit 4 is not reset. After that, when the second predetermined time (31 seconds) elapses in the internal timer, the internal interrupt unit 4 enters the internal interrupt IR12 into the CPU 1, and the start WU3 of the CPU 1 is generated. As a result, the CPU 1 shifts from the ultra-low power consumption mode to the normal mode, and the function of the reset terminal 12 becomes effective.

Subsequently, when the first predetermined time (32 seconds) elapses in the external timer, the WDT reset RS2 is input to the reset terminal 12 by the external reset unit 3, and the CPU 1 is reset / restored. Here, the startup time of the CPU 1 and the first predetermined time are set so that the WDT reset RS2 occurs during the startup WU3 of the CPU 1. For example, when the CPU 1 is started by the internal interrupt (IR12), the start of the CPU 1 (WU3) is continued.

In this way, even if a freeze occurs due to a runaway of software or the like during the ultra-low power consumption mode, the freeze is eliminated. That is, as shown in FIG. 3, when the mode shifts to the ultra-low power consumption mode and the internal timer is set (step S1) and the software cannot be controlled and freezes (step S2), the internal interrupt unit 4 causes an internal interrupt in the CPU 1 and releases the ultra-low power consumption mode (step S3). Subsequently, the CPU 1 is hardware reset by the external reset unit 3 (step S4) and restarted (step S5).

As described above, according to this CPU standby reset structure, even if the CPU 1 is not interrupted externally for some reason during the ultra-low power consumption mode, the internal interrupt unit 4 interrupts the CPU 1 internally and the CPU 1 Is activated, so that the CPU 1 can be reliably reset and restored. As a result, since it is not necessary to turn on the power of the CPU 1 again, it is possible to prevent or suppress an increase in the component mounting area and the component cost.

Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above-described embodiment, and even if there is a design change or the like within a range that does not deviate from the gist of the present invention. Included in the invention. For example, in the above embodiment, the predetermined cycle is set to 30 seconds, the second predetermined time is set to 31 seconds, and the first predetermined time is set to 32 seconds, but other cycles and times may be set. Good.

1 CPU
11 WKUP terminal 12 Reset terminal 2 External interrupt part 3 External reset part 4 Internal interrupt part

Claims (1)

An external interrupt unit that activates the CPU by inserting an external interrupt into the sleeping CPU at a predetermined cycle.
An external reset unit that resets the CPU when the first predetermined time elapses with the external timer.
An internal interrupt unit built into the CPU that activates the CPU by inserting an internal interrupt into the CPU when the second predetermined time elapses.
When the CPU is activated by the external interrupt, the external timer and the internal timer are reset, the first predetermined time is set longer than the second predetermined time, and the second predetermined time is set. The time is set longer than the predetermined cycle ,
Normally, the CPU activated by the external interrupt resets the external timer and the internal timer, and if the external interrupt does not enter the CPU, the internal interrupt occurs after the second predetermined time elapses. The CPU is started by the interrupt, and then the external reset unit resets the CPU when the first predetermined time elapses.
A CPU standby return structure characterized by this.

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