JP6757610B2 - Semiconductor device - Google Patents

Description

One aspect of the present invention relates to semiconductor devices, electronic components, and electronic devices.

A programmable logic device (PLD: Programmable Logic Device) has a plurality of programmable logic elements (PLE: Programmable Logic Element). In PLE, the configuration data is stored in the configuration memory.

A multi-context PLD has been proposed (for example, Non-Patent Document 1). The multi-context method is a method in which a plurality of configuration data corresponding to a plurality of functions are stored in the PLD, and the functions of the PLD are switched by switching the configuration data to be used.

H. M. Waidya sooriya et al. , "Implementation of a partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture", IEICE TRANSACTIONS on Electronics. E92-C, pp. 539-549, 2009

There is a demand for semiconductor devices that can supply image-processed image data to displays in response to changes in the environment immediately. In this case, it is necessary to change the parameters for image processing the image data in response to changes in the environment immediately.

When changing the parameters for image processing of image data, it is necessary to calculate the parameters according to the changes in the environment. It takes time to calculate this parameter, and it also takes time to update the parameter obtained by the calculation, so that it is difficult to change the parameter immediately in response to a change in the environment.

One aspect of the present invention is to provide a semiconductor device capable of changing parameters for image processing of image data in response to changes in the environment immediately. One aspect of the present invention is to provide a semiconductor device capable of realizing low power consumption.

One aspect of the present invention includes a sensor, an application processor, a configuration controller, a configuration memory array, and an image processor, the sensor has a function of detecting illuminance, and the application processor has an illuminance. The configuration controller has a function of generating arithmetic parameters for changing the display according to the arithmetic parameters and a function of generating a context switching signal, and the configuration controller has a function of generating first configuration data according to the arithmetic parameters. And has the function of generating multiple second configuration data according to the tentative parameters, and the configuration memory array responds to any one of the plurality of second configuration data by controlling the context switching signal. A semiconductor having a function of outputting a first output signal to the image processor and a function of outputting a second output signal corresponding to the first configuration data updated by the control of the configuration controller to the image processor. It is a device.

In one aspect of the present invention, the configuration memory array has a plurality of configuration memories, and the configuration memory includes a first charge holding circuit, a second charge holding circuit, a first switch, and a first. It has two switches and a buffer circuit, and the first charge holding circuit and the second charge holding circuit have a first transistor and a second transistor, respectively, and have a first transistor and a second transistor. Each of the second transistors has an oxide semiconductor in a semiconductor layer serving as a channel forming region, and one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, so that the second transistor has a second transistor. One of the source or drain of the transistor is electrically connected to one terminal of the first switch or one terminal of the second switch, and the other terminal of the first switch is the other terminal of the second switch. Electrically connected to a terminal, the other terminal of the first switch and the other terminal of the second switch are electrically connected to the input terminal of the buffer circuit, electrostatically connected to one terminal of the first switch. It is preferable that the capacitance is larger than the capacitance of the input terminal of the buffer circuit, and the capacitance of one terminal of the second switch is larger than the capacitance of the input terminal of the buffer circuit.

In one aspect of the present invention, a semiconductor device in which the on or off of the first switch and the second switch is controlled by a context switching signal is preferable.

In one aspect of the present invention, the first switch and the second switch each have a third transistor, and the third transistor is preferably a semiconductor device having silicon in the semiconductor layer serving as a channel forming region.

In one aspect of the present invention, the first transistor and the second transistor are preferably semiconductor devices provided on the upper layer of the third transistor.

In one aspect of the present invention, the semiconductor device has a first capacitive element and a second capacitive element, and the capacitance of the first capacitive element is the capacitance of one terminal of the first switch. Yes, the capacitance of the second capacitive element is the capacitance of one terminal of the second switch, and the first capacitive element and the second capacitive element are the first transistor and the second transistor. It is preferable that it is provided on the upper layer.

Further, another aspect of the present invention is described in the description and drawings of the embodiments described below.

One aspect of the present invention can provide a semiconductor device capable of changing parameters for image processing image data in response to changes in the environment immediately. One aspect of the present invention can provide a semiconductor device capable of realizing low power consumption.

The block diagram explaining one aspect of this invention. The block diagram explaining one aspect of this invention. The circuit diagram explaining one aspect of this invention. A graph explaining the characteristics of a transistor. A graph explaining the characteristics of a transistor. A graph explaining the characteristics of a transistor. The circuit diagram explaining one aspect of this invention. A timing chart for explaining one aspect of the present invention. The flowchart explaining one aspect of this invention. A timing chart for explaining one aspect of the present invention. The schematic diagram explaining one aspect of this invention. The cross-sectional schematic diagram explaining one aspect of this invention. The cross-sectional schematic diagram explaining one aspect of this invention. The block diagram explaining one aspect of this invention. A schematic cross-sectional view, a circuit diagram, and a schematic view illustrating one aspect of the present invention. Schematic diagram and state transition diagram illustrating one aspect of the present invention. A flowchart for explaining an example of a method for manufacturing an electronic component and a schematic perspective view for explaining a configuration example of the electronic component. The figure explaining the electronic device.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different embodiments, and that the embodiments and details can be variously changed without departing from the spirit and scope thereof. .. Therefore, one aspect of the present invention is not construed as being limited to the description of the following embodiments.

<Semiconductor device configuration example>
The configuration of the semiconductor device according to one aspect of the present invention will be described. The semiconductor device according to one aspect of the present invention has a function of switching parameters used for image processing stored as configuration data according to a change in the output of the sensor.

FIG. 1 shows a block diagram of a semiconductor device. The block diagram of FIG. 1 illustrates a sensor 101, an application processor 102, a configuration controller 103, a configuration memory array 104, and an image processor 105.

The sensor 101 is connected to an application processor (Application Processor).

Although one sensor is shown in FIG. 1, a plurality of sensors may be provided. Examples of the sensor 101 include a sensor capable of detecting changes in the environment in which the sensor is used, an illuminance sensor, and the like. In addition, various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, and a strain sensor can be used.

The sensor 101 has a function of outputting a data _sensor regarding changes in the environment in which it is used to the application processor 102. For data transfer from the sensor 101 to the application processor 102, for example, an I2C (Inter Integrated Circuit) communication standard can be used.

The application processor 102 is connected to the configuration controller 103 and the configuration memory array 104 in addition to the sensor 101.

The application processor 102 has a function of determining a change in the environment in which the application processor 102 is used by using the data _sensor from the sensor 101.

Application processor 102, when it is determined that there has been a change in the environment to be used, has the function of calculating the parameter (P _s) used for the image processing of the dimming or toning or the like according to the use environment after the change. This appropriate parameter (P _s ) is a parameter obtained with high accuracy by calculation, and is also referred to as a calculation parameter or parameter P _s .

Application processor 102, the parameter _{P s} was converted into a data format conforming to the communication standard used between the configuration controller 103 (data _{D Comp),} configuration controller 103 that data _{D Comp} with timing information configuration Has a function to output to.

Here, it is assumed that the I2C communication standard is used for the output of the data D _Comp from the application processor 102 to the configuration controller 103.

Application processor 102, in parallel with the calculation of the parameter P _s, has a function of selecting the closest match to the parameter P _s from prewritten parameters in the configuration memory array 104 (P _t). Application processor 102 has a function of outputting context switch signal ctx corresponding to the selected parameter _{(P t),} a ctxb the configuration memory array 104. As will be described later, this parameter (P _t ) is a parameter obtained only by a simple magnitude comparison operation, and is also referred to as a tentative parameter or a parameter P _t .

The parameter P _t can be obtained only by a simple magnitude comparison operation. Therefore, the time required for selecting the parameter P _t is very short as compared with the calculation time of the parameter P _s obtained by calculation.

The configuration controller 103 is connected to the application processor 102 and the configuration memory array 104.

Configuration controller 103, parameters _{P s} data and configuration data signal line in accordance with timing information data output from the application processor 102, the complementary signal lines datab configuration data signal line data, and the write control signal line wl Has a function of giving a signal to. Then, the configuration controller 103 has a function of executing the configuration operation of the configuration memory array 104 at the timing specified by the application processor 102.

The bit widths of the configuration data signal line data, the complementary signal line data of the configuration data signal line data, and the write control signal line wl are appropriately changed according to the number of configuration memories or the number of contexts of the configuration memory array 104. can do.

The configuration memory array 104 is connected to the configuration controller 103 and the image processor 105.

The configuration memory array 104 has a function of outputting the parameter P _x [N: 0] used in image processing to the image processor 105 based on the configuration data written in the configuration memory of the configuration memory array 104. ..

The bit width of the parameter P _x is N + 1 from 0 to N. N is a natural number.

The configuration memory array 104 has a function of switching the context based on the context switching signals ctx and ctxb from the application processor 102.

The image processor 105 is connected to the configuration memory.

Image processor 105 has a function of executing image processing such as dimming-toning based on parameters P _x which is output from the configuration memory array 104.

The semiconductor device of FIG. 1 executes image processing with the parameter P _t closest to the parameter P _s as the parameter P _x while detecting the change in the environment in which it is used and calculating the parameter P _s with the application processor 102. Can be done. Therefore, it is possible to change the parameters for image processing the image data in response to changes in the environment immediately.

<Configuration memory array configuration>
FIG. 2 is a block diagram for explaining the configuration memory array 104 shown in FIG. The configuration memory array has, for example, configuration memories MEM_0 to MEM_3.

Although the memory cells are arranged one-dimensionally in FIG. 2, other arrangements may be used. For example, a configuration in which memory cells are arranged two-dimensionally by arranging them in a matrix, or a configuration in which memory cells are arranged three-dimensionally by arranging memory cells arranged in a matrix in multiple layers can be used. ..

As shown in FIG. 2, the configuration memories MEM_0 to MEM_3 are configured data signal lines data [0] to [3], complementary signal lines data [0] to [3] of the configuration data signal line data, and write control. Signal lines wl [0] to [3], context selection signal lines ctx [0] to [3], complementary signal lines ctxb [0] to [3] and parameters of context selection signal lines ctx [0] to [3] It is connected to the data signal line P _x [0] to [3].

For example, the configuration memory MEM_0 is configured by a signal transferred using the configuration data signal line data [0], the complementary signal line data [0] of the data [0], and the write control signal line wl [0]. To. The description of the configuration memories MEM_1 to MEM_3 is the same as that of the configuration memory MEM_0.

The configuration memories MEM_0 to MEM_3 can write, for example, four contexts.

For example, the configuration memory MEM_0 is transferred using the complementary signal lines ctxb [0] to [3] of the context selection signal lines ctx [0] to [3] and the context selection signal lines ctx [0] to [3]. The context can be switched by the signal. The description of the configuration memories MEM_1 to MEM_3 is the same as that of the configuration memory MEM_0.

For example, the parameter P _t3 [0] used in a relatively bright situation is held in the context 1 of the configuration memory MEM_0. Further, in the context 3 of the configuration memory MEM_0, the parameter P _t1 [0] used in a relatively dark situation is held. Further, in the context 2 of the configuration memory MEM_0, for example, the parameter P _t2 [0] used in a brightness situation between a relatively bright situation and a relatively dark situation is held. Also in the context 4 configuration memory MEM_0, parameters P _s obtained by the arithmetic processing to acquire the information of the brightness _[0] is updated from time to time. The description of the configuration memories MEM_1 to MEM_3 is the same as that of the configuration memory MEM_0.

The configuration memory MEM_0 has parameters P _t3 [0], parameter P _t1 [0], parameter P _{t 2} [0], and parameter P _s [0] held internally using the parameter data signal line P _x [0]. One of the parameters of [0] is selected by the context selection signal lines ctx [0] to [3] and ctxb [0] to [3], and is output as parameter data. The description of the configuration memories MEM_1 to MEM_3 is the same as that of the configuration memory MEM_0.

FIG. 3 describes the configuration of the configuration memory MEM_A applicable to the configuration memories MEM_0 to MEM_3 of FIG. Note that FIG. 3 illustrates a configuration for holding the charge holding circuits M _s and M _t corresponding to two contexts, for example. For example, the charge holding circuit M _s can hold data corresponding to the parameter P _s . For example, the charge holding circuit M _t can hold data corresponding to the parameter P _{t 1} . When the configuration memory MEM_A further holds a plurality of parameters such as the parameter P _t2 and the parameter P _{t 3} , a plurality of charge holding circuits M _t may be additionally provided.

The configuration memory MEM_A is composed of a charge holding circuit M _s , a charge holding circuit M _t , a switch CS0, a switch CS1, a capacitor 207, a capacitor 214, and an inverter circuit 216. In the configuration memory MEM_A, when a plurality of charge holding circuits M _t are additionally provided in order to further hold a plurality of parameters such as the parameter P _t2 and the parameter P _t3 , a configuration corresponding to the switch CS0 and the capacitor 207 is additionally provided. Just do it.

The charge holding circuit _Ms includes a transistor 201, a transistor 202, a transistor 203, and a transistor 204.

The gate of the transistor 201 is connected to the write control signal line wl0. One of the source and drain of transistor 201 is connected to the data line data. The other of the source or drain of transistor 201 is connected to the gate of transistor 202. The back gate of the transistor 201 is connected to the threshold control line MG. The node to which the other of the source or drain of the transistor 201 and the gate of the transistor 202 are connected is called a node m0.

One of the source and drain of the transistor 202 is connected to the high potential power line VDD. The other of the source or drain of the transistor 202 is connected to the context switch input signal line swing [0]. The back gate of the transistor 202 is connected to the threshold control line PG. The context switch input signal line swing [0] is connected to one terminal of the switch CS0.

The gate of the transistor 203 is connected to the write control signal line wl0. One of the source and drain of transistor 203 is connected to the data line datab. The other of the source or drain of transistor 203 is connected to the gate of transistor 204. The back gate of the transistor 203 is connected to the threshold control line MG. The node to which the other of the source or drain of the transistor 203 and the gate of the transistor 204 are connected is called a node mb0.

One of the source and drain of transistor 204 is connected to the low potential power line VSS. The other of the source or drain of transistor 204 is connected to the context switch input signal line swing [1]. The back gate of the transistor 204 is connected to the threshold control line PG.

In the transistor 201, the potential of the data line data is written to the node m0 at a high level of the potential of the write control signal line wl0. Further, the transistor 201 has a function of holding a charge corresponding to the potential of the node m0 at a low level of the potential of the write control signal line wl0. The threshold voltage of the transistor 201 is controlled by the potential of the threshold control signal line MG connected to the back gate, and the leakage current (off current) in the non-conducting state is controlled to be extremely small.

The transistor 202 has a function of controlling whether or not the high potential power supply line VDD is given to the context switch input signal line swing [0] depending on the potential of the node m0. The transistor 202 is controlled by the potential of the threshold control signal line PG connected to the back gate so that the drain current (on current) in the conduction state is large.

In the transistor 203, the potential of the data line data is written to the node mb0 at a high level of the potential of the write control signal line wl0. Further, the transistor 203 has a function of holding a charge corresponding to the potential of the node mb0 at a low level of the potential of the write control signal line wl0. The threshold voltage of the transistor 203 is controlled by the potential of the threshold control signal line MG connected to the back gate, and the off current is controlled to be extremely small.

The transistor 204 has a function of controlling whether or not the low potential power supply line VSS is given to the context switch input signal line win [0] depending on the potential of the node mb0. The transistor 204 is controlled in a state where the on-current is large by the potential of the threshold control signal line PG connected to the back gate.

The transistor 201 and the transistor 203 are configured to use a transistor having an extremely small off-current, such as an OS transistor. With this configuration, when the transistor 201 and the transistor 203 are brought into a non-conducting state, data corresponding to the potentials held in the nodes m0 and the node mb0 can be continuously held.

The OS transistor can be used at a higher temperature than the Si transistor. Further, the withstand voltage of the OS transistor with respect to the voltage is higher than the withstand voltage of the Si transistor with respect to the voltage. Therefore, the circuit can be made highly reliable against changes in the environment. The electrical characteristics of the OS transistor will be described later.

The transistor 202 and the transistor 204 are configured to use, for example, an OS transistor having a thicker gate insulating film than a Si transistor. With this configuration, it is possible to suppress the leakage current flowing between the gate and the semiconductor layer due to the generation of the tunnel current due to the thin gate insulating film of the transistor 202 and the transistor 204. Therefore, it is possible to continue to hold the data corresponding to the potential held in the node m0 and the node mb0.

The node m0 and the node mb0 may have a capacitor in order to enhance the function of holding the electric charge.

The charge holding circuit _Mt includes a transistor 208, a transistor 209, a transistor 210, and a transistor 211.

The gate of the transistor 208 is connected to the write control signal line wl1. One of the source and drain of transistor 208 is connected to the data line data. The other of the source or drain of transistor 208 is connected to the gate of transistor 209. The back gate of transistor 208 is connected to the threshold control line MG. The node to which the other of the source or drain of the transistor 208 and the gate of the transistor 209 are connected is referred to as a node m1.

One of the source or drain of transistor 209 is connected to the high potential power line VDD. The other of the source or drain of the transistor 209 is connected to the context switch input signal line swing [1]. The back gate of the transistor 209 is connected to the threshold control line PG. The context switch input signal line swing [1] is connected to one terminal of the switch CS1.

The gate of the transistor 210 is connected to the write control signal line wl1. One of the source and drain of the transistor 210 is connected to the data line datab. The other of the source or drain of transistor 210 is connected to the gate of transistor 211. The back gate of the transistor 210 is connected to the threshold control line MG. The node to which the other of the source or drain of the transistor 210 and the gate of the transistor 211 are connected is called a node mb1.

One of the source and drain of the transistor 211 is connected to the low potential power line VSS. The other of the source or drain of the transistor 211 is connected to the context switch input signal line swing [1]. The back gate of the transistor 211 is connected to the threshold control line PG.

In the transistor 208, the potential of the data line data is written to the node m1 at a high level of the potential of the write control signal line wl1. Further, the transistor 208 has a function of holding a charge corresponding to the potential of the node m1 at a low level of the potential of the write control signal line wl1. The threshold voltage of the transistor 208 is controlled by the potential of the threshold control signal line MG connected to the back gate, and the off current is controlled to be extremely small.

The transistor 209 has a function of controlling whether or not the high potential power supply line VDD is given to the context switch input signal line swing [1] depending on the potential of the node m1. The transistor 209 is controlled in a state where the on-current is large by the potential of the threshold control signal line PG connected to the back gate.

In the transistor 210, the potential of the data line data is written to the node mb1 at a high level of the potential of the write control signal line wl1. Further, the transistor 210 has a function of holding a charge corresponding to the potential of the node mb1 at a low level of the potential of the write control signal line wl1. The threshold voltage of the transistor 210 is controlled by the potential of the threshold control signal line MG connected to the back gate, and the off current is controlled to be extremely small.

The transistor 211 has a function of controlling whether or not the low potential power supply line VSS is given to the context switch input signal line win [1] depending on the potential of the node mb0. The transistor 211 is controlled so that the on-current is large by the potential of the threshold control signal line PG connected to the back gate.

The transistor 208 and the transistor 210 are configured to use a transistor having an extremely small off-current, such as an OS transistor. With this configuration, when the transistor 208 and the transistor 210 are brought into a non-conducting state, data corresponding to the potentials held in the nodes m1 and the node mb1 can be continuously held.

The transistor 209 and the transistor 211 are configured to use, for example, an OS transistor having a thicker gate insulating film than a Si transistor. With this configuration, it is possible to suppress the leakage current flowing between the gate and the semiconductor layer due to the generation of the tunnel current due to the thin gate insulating film of the transistor 209 and the transistor 211. Therefore, it is possible to continue to hold the data corresponding to the potential held in the node m1 and the node mb1.

The node m1 and the node mb1 may have a capacitor in order to enhance the function of holding the electric charge.

The switch CS0 has a function of making the potential of the context selection signal ctx [0] high and making the context switch input signal line swing [0] and the context switch output signal line swout conductive. Further, the switch CS0 has a function of making the potential of the context selection signal ctx [0] low and making the context switch input signal line swing [0] and the context switch output signal line swout non-conducting.

The switch CS1 has a function of making the potential of the context selection signal ctx [1] high and making the context switch input signal line swing [1] and the context switch output signal line swout conductive. Further, the switch CS1 has a function that the potential of the context selection signal ctx [1] is low and the context switch input signal line swing [1] and the context switch output signal line swout are in a non-conducting state.

Further, in FIG. 3, the capacitor 207 is illustrated. One electrode of the capacitor 207 is connected to the context switch input signal line win [0], and the other electrode is connected to the low potential power line VSS. The capacitor 207 can be omitted by increasing the parasitic capacitance of the context switch input signal line swing [0].

Further, in FIG. 3, the capacitor 214 is shown. One electrode of the capacitor 214 is connected to the context switch input signal line win [1], and the other electrode is connected to the low potential power line VSS. The capacitor 214 can be omitted by increasing the parasitic capacitance of the context switch input signal line swing [1].

The buffer circuit 216 is composed of complementary Si transistors. The input terminal of the buffer circuit 216 is connected to the context switch output signal line swout. The output terminal of the buffer circuit 216 is connected to the parameter data signal line P _x out of the configuration memory MEM_A.

The switch CS0 is composed of the transistor 205 and the transistor 206 as in the configuration memory MEM_B shown in FIG. 7 as an example. The transistor 205 is an n-channel type, and the transistor 206 is a p-channel type. The gate of the transistor 205 is given a context selection signal ctx [0], and the gate of the transistor 206 is given a context selection signal ctxb [0] which is an inverted signal of the context selection signal ctx [0]. The conduction state can be controlled.

Further, the switch CS1 is composed of the transistor 212 and the transistor 213 as in the configuration memory MEM_B shown in FIG. 7 as an example. The transistor 212 is an n-channel type, and the transistor 213 is a p-channel type. The gate of the transistor 212 is given a context selection signal ctx [1], and the gate of the transistor 213 is given a context selection signal ctxb [1] which is an inverted signal of the context selection signal ctx [1]. The conduction state can be controlled.

The transistor 205 and the transistor 206, and the transistor 212 and the transistor 213 are configured to use a transistor having a large on-current such as a Si transistor. With this configuration, when the switch CS0 or the switch CS1 is put into the conductive state (ON), the electric charge can be distributed at high speed.

The OS transistor can be used at a higher temperature than the Si transistor. Further, the withstand voltage of the OS transistor with respect to the voltage is higher than the withstand voltage of the Si transistor with respect to the voltage. Therefore, the circuit can be made highly reliable against changes in the environment. The electrical characteristics of the OS transistor will be described later.

Further, the context switch output signal line swout may have a transistor 217 for pulling down the context switch output signal line swout, as in the configuration memory MEM_B shown in FIG. 7 as an example. The transistor 217 is, for example, an n-channel type. The gate of transistor 217 is connected to a wire that gives the pull-down enable signal cfg. One of the source and drain of transistor 217 is connected to the context switch output signal line swout. The other of the source or drain of transistor 217 is connected to the low potential power line VSS. By having the transistor 217 and setting the potential of the pull-down enable signal cfg to a high level, it is possible to fix the potential of the parameter data signal line P _x out of the configuration memory MEM_B to a high level.

The configuration memory MEM_A and the configuration memory MEM_B shown in FIGS. 3 and 7 described above are the context selection signal ctx [0] (and the context selection signal ctxb [0]) and the context selection signal ctx [1] (and context selection). The signal ctxb [1]) has a function of outputting a logic (potential) depending on the data held in the charge holding circuit M _s or the charge holding circuit M _t .

Charge holding circuit M _s and each node having charge holding circuit M _t is m0, mb0, m1, capacitance to be added to the mb1 is sufficient value at which the charge can hold a charge as the value of the capacitance is small The time required to write the configuration data to the holding circuit M _s and the charge holding circuit M _t can be reduced.

In the configuration memory MEM_A and the configuration memory MEM_B shown in FIGS. 3 and 7 described above, the context switch input signal line swin [0] and the context switch are used with respect to the capacitance added to the context switch output signal line swout node. In order to increase the capacitance applied to the node of the input signal line swing [1], the capacitor 207 and the capacitor 214 are provided. With this configuration, the electric charge held in the nodes of the context switch input signal lines win [0] to win [1] at the time of context switching is the node of the context switch output signal line swout via the switch CS0 or the switch CS1. Can be distributed to.

Capacitor 207 and the capacitor 207 and so as to be higher than the threshold of the inverter circuit, which is the buffer circuit 216, when the potential of the node of the context switch output signal line swout changes from low potential to high potential due to the distribution of charge to the context switch output signal line swout. Adjust the capacitance of capacitor 214. In addition, when the potential of the node of the context switch output signal line swout changes from high potential to low potential due to the distribution of electric charge to the context switch output signal line swout, it is made lower than the threshold value of the inverter circuit which is the buffer circuit 216. Adjust the capacitance of capacitors 207 and 214. That is, the capacitance added to the nodes of the context switch input signal line swing [0] and the context switch input signal line swing [1] is made larger than the capacitance added to the node of the context switch output signal line swout.

The transistors 202 and 204 shown in FIGS. 3 and 7 and the transistors 209 and 211 described above use OS transistors having a thicker gate insulating film than Si transistors. Since the OS transistor has a smaller field effect mobility than the Si transistor using a single crystal in the semiconductor layer, the on-current is smaller than that of the Si transistor.

Therefore, in the configurations shown in FIGS. 3 and 7, the logical transition of the inverter circuit, which is the buffer circuit 216, can be realized even if the on-currents of the transistors 202, 204, 209, and 211 are small by the above-mentioned configuration of distributing electric charges. Therefore, the context can be switched at the same speed as when the transistors 202, 204, 209 and 211 are composed of Si transistors.

In the case of the configurations shown in FIGS. 3 and 7, the capacitors 207 and 214 are preferably capacitors having a large capacitance. In this configuration, it is preferable to form a layer for providing the OS transistor on the upper layer of the layer for providing the Si transistor, and to provide the capacitor 207 and the capacitor 214 on the upper layer of the layer for providing the OS transistor. With this configuration, a capacitor having a large capacitance can be formed in the uppermost layer of the device, and connection with the transistors 202, 204, 209 and 211 can be easily realized.

<Electrical characteristics of OS transistor>
The OS transistor can be used at a higher temperature than the Si transistor. To illustrate a specific example, the drain current I _D of the OS transistor in FIG. 4 (A) - the gate voltage V _G characteristics, and the gate voltage V _G - the temperature dependence of the field-effect mobility mu _FE characteristic, FIG. 4 (B) the gate voltage of the Si transistor _{V G} - drain current _{I D} characteristics, and the gate voltage _{V G} - the temperature dependence of the field-effect mobility _{mu FE} characteristics shown. Note that FIGS. 4 (A) and 4 (B) show the measurement results of each electrical characteristic at temperatures of −25 ° C., 50 ° C., and 150 ° C. The drain voltage V _D is 1 V.

The electrical characteristics of the OS transistor shown in FIG. 4A are graphs with a channel length L = 0.45 μm, a channel width W = 10 μm, and a thickness of the oxide film of the gate insulating layer Tox = 20 nm. The electrical characteristics of the Si transistor shown in FIG. 4B are graphs at L = 0.35 μm, W = 10 μm, and Tox = 20 nm.

The oxide semiconductor layer of the OS transistor is made of In-Ga-Zn-based oxide, and the Si transistor is made of a silicon wafer.

From FIGS. 4A and 4B, it can be seen that the temperature dependence of the rising gate voltage of the OS transistor and the Si transistor is small. Further, the off current of the OS transistor is equal to or less than the lower limit of measurement (I ₀ ) regardless of the temperature, but the off current of the Si transistor has a large temperature dependence. The measurement result of FIG. 4B shows that at 150 ° C., the off-current of the Si transistor increases and the current on / off ratio does not become sufficiently large.

From the graph of FIG. 4A, when the OS transistor is used as a switch, it can be operated even at a temperature of 150 ° C. or higher. Therefore, the heat resistance of the semiconductor device can be made excellent.

Next, the withstand voltage of the OS transistor with respect to the voltage will be described by comparing the withstand voltage of the Si transistor.

FIG. 5 shows a VD-ID characteristic diagram of the Si transistor and the OS transistor in order to explain the drain withstand voltage of the OS transistor. In FIGS. 5A and 5B, in order to compare the withstand voltage of the Si transistor and the OS transistor under the same conditions, the channel length is 0.9 μm, the channel width is 10 μm, and the gate using silicon oxide is used. The film thickness of the insulating film is 20 nm. The gate voltage is 2V.

As shown in FIG. 5, in the Si transistor, the avalanche breakdown occurs at about 4 V with respect to the increase in the drain voltage, whereas in the OS transistor, the avalanche breakdown does not occur up to about 26 V with respect to the increase in the drain voltage. It can be seen that a constant current can be passed through.

FIG. 6A shows a VD-ID characteristic diagram of the OS transistor when the gate voltage is changed. Further, FIG. 6B shows a VD-ID characteristic diagram of the Si transistor when the gate voltage is changed. In FIG. 6A, in order to compare the withstand voltage of the Si transistor and the OS transistor under the same conditions, the channel length is 0.9 μm, the channel width is 10 μm, and the gate insulating film using silicon oxide is used. The thickness is 20 nm. The gate voltage was changed to 0.1V, 2.06V, 4.02V, 5.98V, and 7.94V for the OS transistor shown in FIG. 6 (A), and 0.1V for the Si transistor shown in FIG. 6B. It is changed to 1.28V, 2.46V, 3.64V, and 4.82V.

As shown in FIGS. 6A and 6B, in the Si transistor, avalanche breakdown occurs at about 4 to 5 V with respect to an increase in drain voltage, whereas in an OS transistor, with respect to an increase in drain voltage. It can be seen that at about 9 V, a constant current can be passed without avalanche breakdown.

As can be seen from FIGS. 5 and 6 (A) and 6 (B), the OS transistor has a higher withstand voltage than the Si transistor. Therefore, even if the OS transistor is applied to a place where a high voltage is applied, it can be used stably without causing dielectric breakdown.

<Operation of configuration memory>
FIG. 8 is an example of a timing chart for explaining the operation of the configuration memory. FIG. 8 shows an example of the configuration and context switching operation of the configuration memory MEM_B shown in FIG.

In the description of FIG. 8, the potentials of the data lines data and data will be described as data and data. In FIG. 8, the potentials of the write control signal lines wl0 and wl1 will be described as wl0 and wl1. In FIG. 8, the potentials of the nodes m0 and m1 are described as m0 and m1. In FIG. 8, the potentials of the nodes mb0 and mb1 are described as mb0 and mb1. In FIG. 8, the potentials of the context switch input signal lines win [0] and win [1] are described as win [0] and win [1]. In FIG. 8, the potentials of the context selection signal lines ctx [0] and ctx [1] are described as ctx [0] and ctx [1]. In FIG. 8, the potentials of the context selection signal lines ctxb [0] and ctxb [1] are described as ctxb [0] and ctxb [1]. In FIG. 8, the potential of the context switch output signal line swout is described as swout. In FIG. 8, the potential of the parameter data signal line P _x out of the configuration memory MEM_B will be described as P _x out.

In the description of FIG. 8, the high-level potential for driving the OS transistor is H VDD, and the high-level potential for driving the Si transistor is VDD. The potential of H VDD is higher than the potential of VDD.

In the description of FIG. 8, the logic represented by H VDD is defined as H-high level, the logic represented by VDD is defined as high level, and the logic represented by potential VSS, which is a low power supply potential, is defined as low level.

In the description of FIG. 8, it is assumed that the pull-down enable signal line cfg has a low level potential.

In the description of FIG. 8, the threshold value of the voltage at which the logic of the inverter circuit of the buffer circuit 216 transitions is defined as Vth.

In the description of FIG. 8, the data signals data and data, the context selection signals ctx [0] and ctxb [0], and the context selection signals ctx [1] and ctxb [1] are signals whose logics are inverted, respectively.

Here, as an example, the configuration operation is such that the low level is written to the node m0, the H-high level is written to the node mb0, the H-high level is written to the node m1, and the low level is written to the node mb1.

In the initial state, since node m0 is at the low level and mb0 is at the H-high level, win [0] is at the low level. Since the node m1 has a low level and the node mb1 has an H-high level, the win [1] has a low level.

At time T0, the write operation of the first charge holding circuit M _s as a configuration operation is performed. wl0 becomes H-high level. At this time, since data is at low level and data is at H-high level, the potentials of node m0 and node mb0 do not transition in the initial state, and win [0] does not transition in the low level.

At time T1, the write completion operation of the charge holding circuit M _s is performed. Since wl0 has a low level, m0 maintains a low level and mb maintains an H-high level. Therefore, win [0] maintains a low level.

At time T2, data and data transition to the potential of the data to be written to node m1 and node mb1. That is, data transitions to the H-high level and data transitions to the low level.

At time T3, the write operation of the charge holding circuit M _t is executed. wl1 becomes H-high level. At this time, since data is H-high level and data is low level, m1 is given H-high level and mb1 is given low level.

At time T4, the writing of the node m1 and the node mb1 is completed. Since node m1 is at H-high level and node mb1 is at low level, swing [1] initiates a transition from low level to high level.

At time T5, the potential transition of win [1] is completed. win [1] becomes a high level.

At time T6, the write and configuration complete operation of the charge holding circuit M _s is performed. Since wl1 has a low level, m1 maintains an H-high level and mb maintains a low level. Therefore, win [1] maintains a high level.

In the charge holding circuit M _s and the charge holding circuit M _t , the smaller the capacitance applied to the nodes m0, mb0, m1 and mb1, the faster the configuration becomes possible.

At time T7, the context switching operation is executed. Let context 0 and context 1 be the contexts in which swing [0] and win [1] are selected. Here, it is assumed that the selection of context 1 is started first. ctx [1] is the high level and ctxb [1] is the low level.

Since the switch CS1 is turned on, the switch [1] and the switch are in a conductive state. As a result of the configuration, since win [1] maintains a high level, swout is given a high level. From time T7 to T8, the electric charge held in the node of win [1] is distributed to the node of swout via the Si transistor, so that swout changes to the potential Ve1 at the switching speed of the Si transistor.

Here, the supply of VDD via the transistor 209 at times T7 to T8 is ignored, but when considering this as well, the switching speed is further improved.

By adjusting the capacitance ratio so that the value of the potential Ve1 becomes higher than the threshold value Vth of the inverter circuit of the buffer circuit 216, it is possible to make the P _x out transition to a low level at high speed.

At time T8, charge distribution is complete. After that, since VDD is supplied via the transistor 209, win [1] and swout transition to a high level by the time T9 at the switching speed of the transistor.

At time T10, the context switching operation is completed.

At time T11, the context switching operation is executed again. It is assumed that the selection of context 0 is started. Since ctx [1] is at a low level, ctxb [1] is at a high level, and switch CS1 is turned off, switch [1] and switch are in a non-conducting state.

At time T12, ctx [0] becomes the high level and ctxb [0] becomes the low level.

Since the switch CS0 is turned on, the win [0] and the switch are in a conductive state. As a result of the configuration, since win [0] maintains a low level, swout is given a low level. From time T12 to T13, since the electric charge held in the node of swout is distributed to the node of win [0] via the Si transistor, swout changes to the potential Ve0 at the switching speed of the Si transistor.

Here, the supply of VSS via the transistor 204 at times T12 to T13 is ignored, but when considering this as well, the switching speed is further improved.

Adjust the ratio of the capacitance, if such value of the potential Ve0 is lower than the threshold Vth of the inverter circuit included in the buffer circuit 216, it is possible to transition the P _x out to a high level at a high speed.

At time T13, charge distribution is complete. After that, since VSS is supplied via the transistor 204, win [0] and swout transition to a low level by the time T14 at the switching speed of the transistor.

At time T15, the context switching operation is completed.

Nodes m0, mb0, m1, by reducing the capacitance to be added to the mb1, reduce the write time from the time T3 to the charge holding circuit _{M s} and the charge holding circuit _{M t} at T4.

The interval between the write control signals from time T1 to time T3 and the time from the completion of the configuration to the start of context selection from time T6 to T7 are relative to the time until the logical transition of win [0] and win [1]. There is enough. In addition, although high speed is required for the context switching operation, since the context switching is not usually performed frequently at intervals of several clocks, swing [1] and swout from time T8 to T9 transition to a high level. There is ample time to do so, and time to transition to low levels for win [0] and swout from time T13 to T14. Therefore, even if a transistor is used to supply electric charges to win [0] and win [1], it has almost no effect on the operating speed of the semiconductor device.

In this way, the context switch input signal line swing [0] and swing [1] are provided with a large capacitance with respect to the capacitance of the nodes m0, mb0, m1, mb1 and the context switch output signal line swout. In the configuration memory using the OS transistor, high-speed context switching operation becomes possible.

<Operation example of semiconductor device>
FIG. 9 shows a flow of processing executed by the semiconductor device of FIG.

In the initial state is selected as a context parameter P _s0 is output to the image processor 105 as parameters P _x. The image data processed according to the parameter P _s0 is input to the display device, and the image can be displayed (step S101). The parameter P _s0 is the parameter P _s obtained by calculation in the previous period. Next, the application processor 102 enters a standby state (step S102) waiting for an input from the sensor 101.

When data such as the brightness of external light is input from the sensor 101 (step S103), the application processor 102 determines whether or not the usage environment has changed based on the data from the sensor 101 (step S104).

If there is no change in the usage environment in step S104, the process returns to the state of displaying according to the parameter P _s0 .

If a use environment changes at step S104, the application processor 102 starts the calculation of the parameter _{P s1} (step S107) and selecting parameters _{P t} a (step S105) at the same time. The parameter P _s1 is a parameter P _s updated by an operation corresponding to a new change in the usage environment.

Step S105 the application processor 102 when the selection of the parameter _{P t} is completed in the context switching of the configuration memory array 104 by the context switch signal ctx. Specifically, the closest parameter P _t1 of the parameter P _s1 is output to the image processor 105 as the parameter P _x . Image data that has been image-processed according to the parameter P _t1 is input to the display device, and the image can be displayed. The parameter P _t1 is one of the parameters P _t held in the configuration memory array 104 in advance.

From the time when the calculation of the parameter P _s1 is completed, the application processor 102 starts generating data (step S108) according to the I2C communication standard based on the data of the parameter P _s1 .

From the time when the generation of the I2C data is completed, the application processor 102 outputs the parameter P _s1 to the configuration controller 103 in I2C (step S109).

The application processor 102 switches the context of the configuration memory array 104 by the context switching signal ctx so that the parameter P _s1 is input to the image processor 105 as the parameter P _x when the output of the parameter P _s1 is completed. The image data processed according to the parameter P _s1 is input to the display device, and the image can be displayed (step S110).

As described above, the image processing can be executed using the parameter P _t1 while the parameter P _s1 is calculated by the application processor 102. Therefore, it is possible to change the parameters for image processing the image data in response to changes in the environment immediately.

FIG. 10A shows a timing chart of a process for outputting the parameter P _s and the parameter P _t executed by the semiconductor device of FIG. 1 by calculation.

The FIG. 10 (B), the shown position on the number line of _{P t1, P t2} and _{P t3} a parameter _{P t,} the variation of the parameters _{P s} is output as the parameter _{P x.}

In the initial state, the application processor 102 is in a standby state waiting for input from the sensor 101.

At time T0, data including information on changes in the usage environment is input from the sensor 101 to the application processor 102.

From time T0 to time T1, the application processor 102 determines whether or not there has been a change in the usage environment.

When the application processor 102 determines that the usage environment has changed at time T1, the calculation of the parameter P _s and the selection of the parameter P _t are started.

From time T1 to time T2, the parameter P _t is selected as shown in FIG. 10 (B).

In FIG. 10 (B), the parameters outputted from the configuration memory array 104 to the image processor 105 and the parameter _{P x.}

Parameter _{P x} is the 8 bits as one example, the parameters _{P x} values of 0 to 255 Torieru. Here, as illustrated in FIG. 10B, the regions from 0 to 255 of the parameter P _x are each divided into three by an arbitrary size.

The area of the parameter P _x is divided into three, and the smaller parameter P _x as the boundary value is d0, and the larger parameter P _x is d1. Let P _t1 be a parameter smaller than d0. Let P _t2 be a parameter that is d0 or more and smaller than d1. Let P _t3 be a parameter of d1 or more.

The parameter P _s transferred from the configuration memory to the image processor 105 in the initial state is _defined as the parameter P _s0, and the parameter P _s updated by the calculation is _defined as the parameter P _s1 .

The data obtained by the sensor 101 is defined as the illuminance, and the parameter P _x for performing an appropriate display corresponding to the illuminance is defined as br. Application processor 102, when d0 is larger than br, selecting parameters _{P t1} as a parameter _{P t.} When br is less than d0 or d1, selecting parameters _{P t2} as parameters _{P t.} When br is above d1, selecting parameters _{P t3} as a parameter _{P t.}

As described above, since the selection of the parameter P _t is performed only by a simple magnitude comparison operation, it can be obtained much faster than the calculation of the parameter P _s is completed.

For example a parameter _{P t1} is selected as the parameter _{P t.}

At the time T2 in FIG. 10 (A), the selection of the parameter P _t is completed.

At a time T3 from the time T2 for the parameter _{P t1} is selected as the parameter _{P t,} the application processor 102 switches the context to select the parameters _{P t1} of the configuration memory array 104 as the parameter _{P x.}

At time T3, switch context by controlling the context switching signals to switch the parameter _{P s0} to output as the parameter _{P x} in the parameter _{P t1.} By performing this control, it is possible to switch to the parameter P _t1 close to the parameter P _s1 to be switched thereafter in a short period of time, and to perform image processing by the image processor 105.

At time T4, the calculation of the parameter P _s is completed and the parameter P _s1 is obtained. Based on the obtained parameter P _s1 , I2C data is generated from time T4 to time T5. At time T5, the generation of I2C data is completed.

From time T5 to time T6, the application processor 102 outputs the I2C data based on the parameter P _s1 to the configuration controller 103.

At time T6, the output of I2C data based on the parameter P _s1 is completed.

From time T6 to time T7, the configuration of parameter P _s1 is executed for the configuration memory of the configuration memory array 104.

From time T6 to time T7, the unselected parameters P _t1 , P _{t 2} and P _t 3 may be configured.

From time T7 to time T8, the application processor 102 executes an operation of switching the context of the configuration memory array 104.

At time T8, the parameter P _x switches to the parameter P _s1 .

As described above, when the usage environment changes, one of the parameters P _t1 , P _t2, and P _{t 3} written in advance in the configuration memory while the parameter P _s1 is being calculated by the application processor 102. Image processing can be executed using the parameter P _t1 which is close to the parameter P _s1 . Therefore, it is possible to change the parameters for image processing the image data in response to changes in the environment immediately.

<Example of cross-sectional structure of semiconductor device>
Next, an example of the cross-sectional structure of the semiconductor device will be described with reference to FIGS. 11 to 13.

The above-mentioned semiconductor device can be formed by stacking a layer having a Si transistor, a layer having an OS transistor, and a wiring layer.

FIG. 11 shows a schematic diagram of the layer structure of the semiconductor device. The transistor layer 10, the wiring layer 20, the transistor layer 30, and the wiring layer 40 are provided in this order so as to overlap each other. The wiring layer 20 shown as an example has a wiring layer 20A and a wiring layer 20B. Further, the wiring layer 40 has a plurality of wiring layers 40A and a wiring layer 40B. The wiring layer 20 and / or the wiring layer 40 can form a capacitor by arranging a conductor with an insulator in between.

The transistor layer 10 has a plurality of transistors 12. The transistor 12 has a semiconductor layer 14 and a gate electrode 16. Although the semiconductor layer 14 is shown as being processed into an island shape, it may be a semiconductor layer obtained by separating semiconductor substrates into elements. Although the top gate type is shown as the gate electrode 16, the gate electrode 16 may be a bottom gate type, a double gate type, a dual gate type, or the like.

The wiring layer 20A and the wiring layer 20B have wiring 22 embedded in an opening provided in the insulating layer 24. The wiring 22 has a function as wiring for connecting elements such as transistors.

The transistor layer 30 has a plurality of transistors 32. The transistor 32 has a semiconductor layer 34 and a gate electrode 36. Although the semiconductor layer 34 is shown as being processed into an island shape, it may be a semiconductor layer obtained by separating semiconductor substrates into elements. Although the top gate type is shown, the gate electrode 36 may be a bottom gate type, a double gate type, a dual gate type, or the like.

The wiring layer 40A and the wiring layer 40B have a wiring 42 embedded in an opening provided in the insulating layer 44. The wiring 42 has a function as wiring for connecting elements such as transistors.

The semiconductor layer 14 is a semiconductor material different from the semiconductor layer 34. As an example, assuming that the transistor 12 is a Si transistor and the transistor 32 is an OS transistor, the semiconductor material of the semiconductor layer 14 is silicon, and the semiconductor material of the semiconductor layer 34 is an oxide semiconductor.

An example of a cross-sectional view of the semiconductor device is shown in FIG. 12 (A). FIG. 12B is an enlargement of a part of the configuration of FIG. 12A.

The semiconductor device shown in FIG. 12A has a capacitor 300, a transistor 400, and a transistor 500.

The capacitor 300 is provided on the insulator 602 and has a conductor 604, an insulator 612, and a conductor 616.

As the conductor 604, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When it is formed at the same time as other structures such as a plug and wiring, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.

The insulator 612 is provided so as to cover the side surface and the upper surface of the conductor 604. For the insulator 612, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, hafnium nitride and the like can be used. It may be provided in a laminated or single layer.

The conductor 616 is provided so as to cover the side surface and the upper surface of the conductor 604 via the insulator 612.

As the conductor 616, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When it is formed at the same time as another structure such as a conductor, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.

The conductor 616 included in the capacitor 300 covers the side surface and the upper surface of the conductor 604 via the insulator 612, so that the capacity per projected area of the capacitor can be increased. Therefore, it is possible to reduce the area, increase the integration, and miniaturize the semiconductor device.

The transistor 500 is provided on the substrate 301 and has a conductor 306, an insulator 304, a semiconductor region 302 composed of a part of the substrate 301, and a low resistance region 308a and a low resistance region 308b that function as a source region or a drain region. ..

The transistor 500 may be either a p-channel type or an n-channel type.

It is preferable to include a semiconductor such as a silicon-based semiconductor in a region of the semiconductor region 302 in which a channel is formed, a region in the vicinity thereof, a low resistance region 308a serving as a source region or a drain region, a low resistance region 308b, and the like. It preferably contains crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 500 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

In the low resistance region 308a and the low resistance region 308b, in addition to the semiconductor material applied to the semiconductor region 302, elements that impart n-type conductivity such as arsenic and phosphorus, or p-type conductivity such as boron are imparted. Contains elements that

The conductor 306 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. A material or a conductive material such as a metal oxide material can be used.

The threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

Further, in the transistor 500 shown in FIG. 12A, the semiconductor region 302 (a part of the substrate 301) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 302 are provided so as to be covered with the conductor 306 via the insulator 304. The conductor 306 may be made of a material that adjusts the work function. Such a transistor 500 is also called a FIN type transistor because it utilizes a convex portion of a semiconductor substrate. It should be noted that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

The transistor 500 shown in FIG. 12A is an example, and the transistor 500 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method. For example, as shown in FIG. 13A, the configuration of the transistor 500A may be provided as a planar type.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order so as to cover the transistor 500.

The insulator 322 functions as a flattening film for flattening a step generated by a transistor 500 or the like provided below the insulator 322. The upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

The insulator 324 functions as a barrier film so that hydrogen and impurities do not diffuse from the substrate 301, the transistor 500, or the like to the region where the transistor 400 is provided. For example, a nitride such as silicon nitride may be used for the insulator 324.

Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitor 300, a conductor 328 electrically connected to the transistor 400, a conductor 330, and the like. The conductor 328 and the conductor 330 have a function as a plug or a wiring. As will be described later, a conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, or a metal oxide material can be used as a single layer or laminated. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In particular, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using the above materials.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 12A, the insulator 350, the insulator 352, and the insulator 354 are laminated in this order. Further, the conductor 356 and the conductor 358 are embedded in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 and the conductor 358 have a function as a plug or a wiring.

For example, as the insulator 350, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, as the conductor 356 and the conductor 358, it is preferable to use a conductor having a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 500 and the transistor 400 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 500 to the transistor 400 can be suppressed.

As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 500 while maintaining the conductivity as wiring.

A transistor 400 is provided above the insulator 354. An enlarged view of the transistor 400 is shown in FIG. 12 (B). The transistor 400 shown in FIG. 12B is an example, and the transistor 400 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.

The transistor 400 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 400 has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor 400 for the frame memory of the semiconductor device.

On the insulator 354, the insulator 410, the insulator 412, the insulator 414, and the insulator 416 are laminated in this order. Further, the conductor 218, the conductor 405 and the like are embedded in the insulator 410, the insulator 412, the insulator 414, and the insulator 416. The conductor 218 has a function as a plug or wiring for electrically connecting to the capacitor 300 or the transistor 500. The conductor 405 has a function as a gate electrode of the transistor 400.

It is preferable to use any of the insulator 410, the insulator 412, the insulator 414, and the insulator 416 as a substance having a barrier property against oxygen and hydrogen. In particular, when an oxide semiconductor is used for the transistor 400, the reliability of the transistor 400 can be improved by providing an insulator having an oxygen excess region in an interlayer film or the like in the vicinity of the transistor 400. Therefore, in order to efficiently diffuse the interlayer film in the vicinity of the transistor 400 to the transistor 400, it is preferable to have a structure in which the transistor 400 and the interlayer film are sandwiched between layers having a barrier property against hydrogen and oxygen.

For example, aluminum oxide, hafnium oxide, tantalum oxide and the like may be used. By laminating a film having a barrier property, the function can be further ensured.

An insulator 220, an insulator 222, and an insulator 224 are laminated in this order on the insulator 416. Further, a part of the conductor 244 is embedded in the insulator 220, the insulator 222, and the insulator 224. The conductor 218 has a function as a plug or wiring for electrically connecting to the capacitor 300 or the transistor 500.

The insulator 220 and the insulator 224 are preferably oxygen-containing insulators such as a silicon oxide film and a silicon nitride film. In particular, it is preferable to use an insulator containing excess oxygen (containing more oxygen than the stoichiometric composition) as the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230 in which the channel region of the transistor 400 is formed, oxygen deficiency in the oxide can be compensated. The insulator 222 and the insulator 224 do not necessarily have to be formed by using the same material.

The insulator 222 includes, for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, It is preferable to use an insulator containing a so-called high-k material such as Sr) TiO ₃ (BST) in a single layer or in a laminated state. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium pentoxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxide or silicon nitride may be laminated on the above insulator.

The insulator 222 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.

By having the insulator 222 containing the high-k material between the insulator 220 and the insulator 224, the insulator 222 can capture electrons under specific conditions and increase the threshold voltage. That is, the insulator 222 may be negatively charged.

For example, when silicon oxide is used for the insulator 220 and the insulator 224, and a material having a large electron capture level such as hafnium oxide, aluminum oxide, and tantalum oxide is used for the insulator 222, the operating temperature of the semiconductor device is used. Or, at a temperature higher than the storage temperature (for example, 125 ° C. or higher and 450 ° C. or lower, typically 150 ° C. or higher and 300 ° C. or lower), the potential of the conductor 405 is higher than the potential of the source electrode or the drain electrode. By maintaining for 10 milliseconds or more, typically 1 minute or more, electrons move from the oxide 230 toward the conductor 405. At this time, some of the moving electrons are captured by the electron capture level of the insulator 222.

The threshold voltage of the transistor that has captured the required amount of electrons for the electron capture level of the insulator 222 shifts to the positive side. The amount of electrons captured can be controlled by controlling the voltage of the conductor 405, and the threshold voltage can be controlled accordingly. By having this configuration, the transistor 400 becomes a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.

Further, the process of capturing electrons may be performed in the process of manufacturing the transistor. For example, after forming a conductor to be connected to the source conductor or drain conductor of the transistor, after the completion of the previous step (wafer processing), after the wafer dicing step, after packaging, or before shipment from the factory. It is good to do it in stages.

Further, it is preferable to use a substance having a barrier property against oxygen and hydrogen for the insulator 222. When formed using such a material, it is possible to prevent the release of oxygen from the oxide 230 and the mixing of impurities such as hydrogen from the outside.

The oxide 230a, the oxide 230b, and the oxide 230c are formed of a metal oxide such as an In—M—Zn oxide (M is Al, Ga, Y, or Sn). Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

The oxide used for the oxide 230 preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.

Here, consider the case where the oxide has indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Examples of elements applicable to the other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

One of the conductors 240a and 240b functions as a source electrode and the other functions as a drain electrode.

The conductor 240a and the conductor 240b have a single-layer structure or laminate of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the main component thereof. Used as a structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a tantalum film or a tantalum nitride film is laminated, a two-layer structure in which an aluminum film is laminated on a titanium film, and a two-layer structure in which an aluminum film is laminated on a tungsten film. , Two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or titanium nitride A three-layer structure, a molybdenum film or molybdenum nitride film, and molybdenum thereof, in which a film and an aluminum film or a copper film are laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is formed on the film. There is a three-layer structure in which an aluminum film or a copper film is laminated on a film or a molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed on the aluminum film or a copper film. A transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

The insulator 250 includes, for example, silicon oxide, silicon nitride nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Insulators containing so-called high-k materials such as Sr) TiO ₃ (BST) can be used in single layers or laminates. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium pentoxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxide or silicon nitride may be laminated on the above insulator.

Further, as the insulator 250, it is preferable to use an oxide insulator containing more oxygen than oxygen satisfying the stoichiometric composition, similarly to the insulator 224.

The insulator 250 may have a laminated structure similar to that of the insulator 220, the insulator 222, and the insulator 224. Since the insulator 250 has an insulator that has captured an amount of electrons required for the electron capture level, the transistor 400 can shift the threshold voltage to the positive side. By having this configuration, the transistor 400 becomes a normally-off type transistor that is in a non-conducting state (also referred to as an off state) even when the gate voltage is 0V.

The conductor 260 having a function as a gate electrode is, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above-mentioned metal as a component, an alloy obtained by combining the above-mentioned metals, and the like. Can be formed using. Further, a metal selected from any one or more of manganese and zirconium may be used. Further, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, and a silicide such as nickel silicide may be used. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a tantalum nitride film or a tungsten nitride film. There are a two-layer structure in which a tungsten film is laminated on top, a titanium film, and a three-layer structure in which an aluminum film is laminated on the titanium film and a titanium film is further formed on the titanium film. Further, an alloy film or a nitride film in which one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined with aluminum may be used.

The conductor 260 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. , A translucent conductive material such as indium tin oxide to which silicon oxide is added can also be applied. Further, the conductive material having the translucent property and the metal may be laminated.

As the insulator 280, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating.

As the oxide material that desorbs oxygen by heating, it is preferable to use an oxide containing more oxygen than oxygen satisfying the stoichiometric composition. In an oxide film containing more oxygen than oxygen satisfying a stoichiometric composition, some oxygen is eliminated by heating. Oxide films containing more oxygen than oxygen satisfying the chemical quantitative composition are the amount of oxygen desorbed in terms of oxygen atoms by thermal desorption gas spectroscopy (TDS: Thermal Desorption Gascopy) analysis. It is an oxide film having a value of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower.

For example, as such a material, it is preferable to use a material containing silicon oxide or silicon oxide nitride. Alternatively, a metal oxide can be used. In the present specification, silicon oxide refers to a material whose composition has a higher oxygen content than nitrogen, and silicon nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.

Further, the insulator 280 that covers the transistor 400 may function as a flattening film that covers the uneven shape below the insulator 280.

Further, the insulator 270 may be provided so as to cover the conductor 260. When an oxide material from which oxygen is desorbed is used for the insulator 280, a substance having a barrier property against oxygen is used for the insulator 270 in order to prevent the conductor 260 from being oxidized by the desorbed oxygen. .. With this configuration, oxidation of the conductor 260 can be suppressed, and oxygen desorbed from the insulator 280 can be efficiently supplied to the oxide 230.

An insulator 282 and an insulator 284 are laminated on the insulator 280 in this order. Further, a conductor 244, a conductor 246a, a conductor 246b, and the like are embedded in the insulator 280, the insulator 282, and the insulator 284. The conductor 244 has a function as a plug or wiring for electrically connecting to the capacitor 300 or the transistor 500. The conductor 246a and the conductor 246b function as a plug or wiring that electrically connects to the capacitor 300 or the transistor 400.

It is preferable to use a substance having a barrier property against oxygen and hydrogen for either or both of the insulator 282 and the insulator 284. With this configuration, oxygen desorbed from the interlayer film in the vicinity of the transistor 400 can be efficiently diffused to the transistor 400.

A capacitor 300 is provided above the insulator 284.

A conductor 604 and a conductor 624 are provided on the insulator 602. The conductor 624 has a function as a plug or wiring for electrically connecting the transistor 400 or the transistor 500.

An insulator 612 is provided on the conductor 604, and a conductor 616 is provided on the insulator 612. Further, the conductor 616 covers the side surface of the conductor 604 via the insulator 612. That is, since the side surface of the conductor 604 also functions as a capacitance, the capacitance per projected area of the capacitor can be increased. Therefore, it is possible to reduce the area, increase the integration, and miniaturize the semiconductor device.

The insulator 602 may be provided at least in a region overlapping with the conductor 604. For example, as in the capacitor 300A shown in FIG. 13B, the insulator 602 may be provided only in the region where the conductor 604 and the conductor 624 overlap, and the insulator 602 and the insulator 612 may be in contact with each other. Good.

An insulator 620 and an insulator 622 are laminated on the conductor 616 in this order. Further, the conductor 626 and the conductor 628 are embedded in the insulator 620, the insulator 622, and the insulator 602. The conductor 626 and the conductor 628 have a function as a plug or wiring for electrically connecting the transistor 400 or the transistor 500.

Further, the insulator 620 that covers the capacitor 300 may function as a flattening film that covers the uneven shape below the insulator 300.

The above is an example of a laminated structure of transistors in a semiconductor device.

<Display system>
FIG. 14 is a block diagram illustrating a configuration example of a display system to which the semiconductor device is applied.

The display system includes the sensor 101, the application processor 102, the configuration controller 103, the configuration memory array 104, and the image processor 105 described in FIG. 1, as well as the host controller 106, the interface 107, and the driver IC 110 (IC (Integrated Circuit)). , Driver IC 111, and display device 130.

The display device 130 includes a display unit 112 and a display unit 113. The display unit 112 has a liquid crystal element 114 in each pixel. The display unit 113 has a light emitting element 115 in each pixel. The pixel has two display elements, a liquid crystal element 114 and a light emitting element, and has a function of superimposing the respective display elements to switch the display. A pixel configuration example will be described in detail later.

The liquid crystal element 114 includes an IPS (In-Plane-Switching) mode, a TN (Twisted Nematic) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Cymetrically named Micro-cell) mode, and an Occecycle mode. It can be driven by using a driving method such as (Ferroelectric Liquid Crystal) mode or AFLC (Antiferroelectric Liquid Crystal) mode. Alternatively, a vertical alignment (VA) mode, specifically, an MVA (Multi-Domaine Vertical Alignment) mode, a PVA (Partnered Vertical Alignment) mode, an ECB (Electrical Alignment Birefringence) mode, a CPA mode. It can be driven by using a driving method such as the Advanced Super-View) mode.

As the liquid crystal material included in the liquid crystal element 114, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a strong dielectric liquid crystal, an anti-strong dielectric liquid crystal, or the like can be used. Alternatively, a liquid crystal material exhibiting a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like can be used. Alternatively, a liquid crystal material exhibiting a blue phase can be used.

As the light emitting element 115, an EL element such as an organic electroluminescence element or an inorganic electroluminescence element, or a light emitting diode or the like can be used.

As the EL element, a laminated body laminated so as to emit white light can be used. Specifically, a layer containing a luminescent organic compound containing a fluorescent material that emits blue light and a layer containing a material other than the fluorescent material that emits green and red light or a fluorescent material that emits yellow light. A laminated body obtained by laminating a layer containing a material other than the above can be used.

The image processor 105 includes a correction parameter holding circuit 108 and a correction selection circuit 109 as an example of a specific circuit that performs image processing. The image processor 105 outputs the image data LC _Comp and the image data LC _Comp obtained by image-processing the image data VD to the driver IC 110 and the driver IC 111.

The correction parameter holding circuit 108 includes a gamma correction circuit 116, a dimming correction circuit 117, a curved surface correction circuit 118, a threshold value correction circuit 119, and a toning correction circuit 120 as an example. The gamma correction circuit 116, the dimming correction circuit 117, the curved surface correction circuit 118, the threshold value correction circuit 119, and the toning correction circuit 120 correct the image data VD according to the parameter Px. The correction selection circuit 109 has a function of selecting one or more of the correction circuits included in the correction parameter holding circuit 108 and outputting the corrected image data LC _Comp and the image data LC _Comp .

The gamma correction circuit 116 is a circuit having a function of performing appropriate gamma correction on the image data VD input according to the usage environment. The dimming correction circuit 117 is a circuit having a function of performing appropriate dimming correction for the image data VD input according to the usage environment. The curved surface correction circuit 118 is a circuit having a function of appropriately correcting the image data VD input according to the shape of the display surface of the display device 130. The threshold value correction circuit 119 is a circuit having a function of correcting the threshold voltage of the transistor of each pixel of the display device 130 in consideration of the correction. The toning correction circuit 120 is a circuit having a function of performing appropriate toning correction for the image data VD input according to the usage environment. The color correction is not limited to the three primary colors of R (red), G (green), and B (blue), and can correspond to four colors including white (W). Alternatively, color correction corresponding to the three primary colors of yellow (Y), magenta (M), and cyan (C) can be performed.

The host controller 106 has a function of converting the image data VD into a signal of a predetermined format and outputting it to the interface 107.

The interface 107 includes a circuit that converts a signal conforming to LVDS (Low Voltage Differential Signaling), DVI, HDMI (registered trademark) L, and the like.

The driver IC 110 has a function of generating various signals for display on the display unit 112 of the display device 130 based on the image data LC _Comp image-processed by the image processor 105. The image data LC _Comp is a signal for displaying on the liquid crystal element 114 included in the display unit 112.

The driver IC 111 has a function of generating various signals for display on the display unit 113 of the display device 130 based on the image data EL _Comp image processed by the image processor 105. The image data EL _Comp is a signal for displaying on the light emitting element 115 included in the display unit 112.

In the display device 130, the image can be displayed only on the display unit 112 of the display unit 112 and the display unit 113. By using the reflective liquid crystal element 114 for the display unit 112, external light can be used as a light source when displaying an image. When external light is used, the power consumption of the display device 130 can be suppressed by displaying the image only on the display unit 112. Further, since the display unit 113 uses the light emitting element 115, it is possible to display an image without preparing a separate light source or using external light. Therefore, by displaying the image on the display unit 113, high display quality can be ensured regardless of the usage environment of the display device 130.

Further, in the display device 130, it is also possible to display an image by using both the display unit 112 and the display unit 113. With the above configuration, the number of gradations of the image that can be displayed on the display device 130 can be increased. Alternatively, the range of the color gamut of the image that can be displayed on the display device 130 can be expanded.

Further, the display device 130 has an image processor 105 having a function of performing image processing from the image data VD to generate the image data LC _Comp supplied to the driver IC 110 and the image data EL _Comp supplied to the driver IC 111. Specifically, the image processor 105 also has a function of performing various corrections on the input image data VD by signal processing. In other words, the function of applying various corrections to the image data VD can be said to be a function of applying various corrections to the image data LC _Comp and the image data EL _Comp .

As the above correction, gamma correction according to the characteristics of the liquid crystal element 114, dimming correction according to the deterioration characteristics of the light emitting element 115, and the like can be performed. In addition to the above corrections, the display device 130 can also adjust the intensity of the external light, the incident angle of the external light, the color, the number of gradations, and the like.

<Pixel configuration example and operation example>
FIG. 15A is an example of a cross-sectional view for explaining a configuration example of a pixel having a liquid crystal element and a light emitting element described with reference to FIG.

FIG. 15A is a cross-sectional view for explaining a laminated structure of a pixel circuit 51, a pixel circuit 52, a liquid crystal element LC, and a light emitting element EL.

In FIG. 15A, a layer 61 having a light emitting element EL, a layer 62 having a pixel circuit, and a layer 63 having a liquid crystal element LC are shown. The layers 61 to 63 are provided between the substrate 70 and the substrate 80. Although not shown, other optical members such as a polarizing plate, a circular polarizing plate, and an antireflection film may be provided.

The layer 61 has a light emitting element EL. The light emitting element EL has an electrode 71, a light emitting layer 72, and an electrode 73. Light 92 (shown by a dotted arrow) is emitted by a current flowing through a light emitting layer 72 sandwiched between the electrodes 71 and 73. The intensity of the light 92 is controlled by the pixel circuit 52 on layer 62.

The layer 62 has a pixel circuit 51, a pixel circuit 52, and a color filter 74. Further, the layer 622 has an electrode 87 for connecting the pixel circuit 51 and the reflection electrode 81, and an electrode 75 for connecting the pixel circuit 52 and the electrode 71. The color filter 74 is provided when the light emitted by the light emitting element EL is white, and can emit light 92 having a specific wavelength to the visual recognition side. The color filter 74 is provided at a position overlapping the opening 83. The pixel circuit 51 and the pixel circuit 52 are provided at positions overlapping the reflective electrode 81. Although FIG. 15A shows a configuration in which the pixel circuit 51 and the pixel circuit 52 are provided between the layer on which the liquid crystal element LC is provided and the layer on which the light emitting element EL is provided, the pixel circuit 51 and the pixel circuit 52 are liquid crystals. It may be provided in the upper layer or the lower layer of the element LC and the light emitting element EL.

The layer 63 has an opening 83, a reflective electrode 81 and a conductive layer 82, a liquid crystal 84, a conductive layer 85, and a color filter 86. The conductive layer 82 controls the orientation state of the liquid crystal 84 provided between the conductive layer 82 and the pair of conductive layers 85. The reflective electrode 81 reflects external light and emits reflected light 91 (shown by a dotted arrow). The intensity of the reflected light 91 is controlled by adjusting the orientation state of the liquid crystal 84 by the pixel circuit 51. The opening 83 is provided at a position where the light 92 emitted by the light emitting element EL of the layer 61 is transmitted.

For the reflective electrode 81, for example, a material that reflects visible light can be used. Specifically, a material containing silver can be used for the reflective film. For example, a material containing silver, palladium, etc. or a material containing silver, copper, etc. can be used for the reflective film. Further, for example, a material having irregularities on the surface can be used for the reflective film. As a result, the incident light can be reflected in various directions to display a white color.

For the conductive layer 82 and the conductive layer 85, for example, a material that transmits visible light can be used. Specifically, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide added with gallium, or graphene can be used.

For the substrate 70 and the substrate 80, for example, a translucent inorganic material such as glass or ceramics can be used. Alternatively, a flexible material such as a resin film or an organic material such as plastic can be used for the substrates 631 and 632. Members such as a polarizing plate, a retardation plate, and a prism sheet can be appropriately laminated and used on the substrate 70 and the substrate 80.

As the insulating layer, for example, an insulating inorganic material, an insulating organic material, or an insulating composite material containing the inorganic material and the organic material can be used. For example, the insulating layer may be a silicon oxide film, a silicon nitride film, a silicon nitride film, an aluminum oxide film, or a laminated material obtained by laminating a plurality of selected materials thereof, or polyester, polyolefin, polyamide, polyimide, polycarbonate, polysiloxane, or the like. A film containing an acrylic resin or the like or a laminated material or a composite material of a plurality of resins selected from these can be used.

For the conductive layer such as the electrode 75 and the electrode 87, a material having conductivity can be used for wiring or the like. For example, as the electrode 75 and the electrode 87, a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium or manganese can be used. Alternatively, the above-mentioned alloy containing a metal element or the like can be used for wiring or the like.

The light emitting layer 72 may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, a low molecular weight organic EL material or a high molecular weight organic EL material may be used. Further, as the EL layer, a thin film made of a light emitting material (singlet compound) that emits light (fluorescence) by singlet excitation, or a thin film made of a light emitting material (triplet compound) that emits light (phosphorescence) by triplet excitation can be used. It is also possible to use an inorganic material such as silicon carbide as the charge transport layer and the charge injection layer. Known materials can be used as these organic EL materials and inorganic materials.

The electrode 71 functions as an anode of the light emitting element EL. As the material for forming the anode, a material having a larger work function than the material for forming the cathode is used, and ITO (indium tin oxide), indium zinc oxide (In ₂ O _3- ZnO), zinc oxide (ZnO), etc. Further, a material having a lower sheet resistance than ITO, specifically, a material such as platinum (Pt), chromium (Cr), tungsten (W), or nickel (Ni) can be used.

As the electrode 73, a metal having a small work function (typically a metal element belonging to Group 1 or Group 2 of the periodic table) or an alloy containing these can be used. The smaller the work function, the higher the luminous efficiency. Therefore, as the material used for the cathode, an alloy material containing Li (lithium), which is one of the alkali metals, is particularly desirable.

As shown in FIG. 15A, the liquid crystal element LC and the light emitting element EL are provided in an overlapping manner. The opening 83 is provided at a position where the light 92 emitted by the light emitting element EL is transmitted. With such a configuration, it is possible to switch the display element according to the surrounding environment without increasing the area occupied by the pixels. As a result, it is possible to obtain a display device with improved visibility.

FIG. 15B is a circuit diagram corresponding to the pixel circuit 51, the pixel circuit 52, the liquid crystal element LC, and the light emitting element EL in the cross-sectional view of the pixels shown in FIG. 15A. In the pixel 90 shown in FIG. 15B, the pixel circuit 51 includes a transistor M1 and a capacitive element Cs _LC . The pixel circuit 52 has transistors M2, M3 and a capacitive element Cs _EL . As shown in FIG. 15B, each element included in the pixel 90 includes a gate line GL _LC , a gate line GL _EL , a signal line SL _LC , a signal line SL _EL , a capacitance line L _CS , a current supply line L _ano , and It is connected to the common potential line _Lcas .

The capacitive element Cs _EL is provided to hold the gradation voltage for driving the light emitting element EL at the gate of the transistor M3. With such a configuration, it is possible to more reliably maintain the gradation voltage for driving the light emitting element EL.

The transistor M1 applies a gradation voltage for driving the liquid crystal element LC to the capacitive element Cs _LC by controlling the conduction state. By controlling the conduction state, the transistor M2 applies a gradation voltage for driving the light emitting element EL to the gate of the transistor M3. The transistor M3 drives the light emitting element EL by _passing a current between the current supply line _Lano and the common potential line _Lcas according to the voltage of the gate.

As the transistors M1 to M3, n-channel transistors can be used. The n-channel transistor can be replaced with a p-channel transistor by changing the magnitude relationship of the voltage of each wiring. Silicon can be used as the semiconductor material of the transistors M1 to M3. As the silicon, single crystal silicon, polysilicon, microcrystalline silicon, amorphous silicon and the like can be appropriately selected and used.

Alternatively, an oxide semiconductor can be used as the semiconductor material of the transistors M1 to M3.

The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.

Further, the transistors M1 to M3 included in the pixel 30 can be manufactured by using various types of transistors such as a bottom gate type transistor and a top gate type transistor. Further, the transistors M1 to M3 included in the pixel 30 may be used as a transistor having a back gate. The voltage applied to the back gate may be configured to be applied from another wiring different from the gate line GL _LC and the gate line GL _EL . With such a configuration, it is possible to control the threshold voltage of the transistor or increase the amount of current flowing through the transistor.

FIG. 15C shows a schematic diagram of the pixel 90. The pixel 90 includes the pixel circuit 51, the pixel circuit 52, the opening 83, the liquid crystal element LC, and the light emitting element EL described in FIGS. 15A and 15B. Further, in FIG. 15C, the reflected light 91 and the light 92 are shown.

The pixel circuit 51 and the pixel circuit 52 shown in FIG. 15C are provided between the layer on which the liquid crystal element LC is provided and the layer on which the light emitting element EL is provided. By providing an element layer having transistors of the pixel circuit 51 for driving the liquid crystal element LC and the pixel circuit 52 for driving the light emitting element EL in the same process, the pixel circuit 51 and the pixel circuit 52 are made the same layer. It is configured to be placed. With this configuration, a drive circuit that applies a gradation voltage to the liquid crystal element LC and a drive circuit that applies a gradation voltage to the light emitting element EL can be integrated.

With the configuration shown in FIG. 15C, the pixel 90 has gradation by controlling the intensity of the reflected light 91 by the liquid crystal element LC and controlling the intensity of the light 92 emitted by the light emitting element EL transmitted through the opening 83. Can be displayed. The direction in which the reflected light 91 is emitted and the direction in which the light 35 emitted by the light emitting element EL is emitted are the display surfaces of the display device.

In the configuration of the pixel 90 shown in FIG. 15C, the intensity of the reflected light 91 using the external light is adjusted by the liquid crystal layer by the reflecting electrode of the liquid crystal element LC to perform gradation display. Therefore, the display device having the pixels 90 can improve the visibility outdoors.

Further, in the configuration of the pixel 90 shown in FIG. 15C, the intensity of the light 92 emitted by the light emitting element EL is adjusted to display the gradation. Therefore, the display device having the pixels 90 can improve the visibility indoors where the intensity of the outside light is small.

The configuration in which the liquid crystal element LC is controlled and displayed outdoors or the light emitting element EL is controlled and displayed indoors may be configured to provide a sensor capable of measuring illuminance in the display device.

Further, the configuration shown in FIG. 15C has a pixel circuit 51 capable of controlling the liquid crystal element LC for each pixel and a pixel circuit 52 capable of controlling the light emitting element EL. That is, the gradation display of the liquid crystal element LC and the light emitting element EL can be controlled separately for each pixel 90. In such a configuration, unlike the control of the backlight that lights uniformly with a plurality of pixels, the light emission of the light emitting element EL according to the image to be displayed can be controlled in the smallest unit such as the pixel level, which is extra. Light emission can be suppressed. Therefore, the display device having the pixel 90 of FIG. 15C can reduce the power consumption.

The operation mode of the display device having the pixel 90 shown in FIG. 15 (B) will be described with reference to FIGS. 16 (A) to 16 (D).

The display device can switch the operation mode according to the ambient illuminance. 16 (A) to 16 (C) are schematic views of pixels for explaining a display mode that the display device can take according to the illuminance. From FIGS. 16A to 16C, the reflections of the pixel circuit 51, the pixel circuit 52, the liquid crystal element LC, the light emitting element EL, the opening 83, and the liquid crystal element LC are similar to those in FIG. 15C. The reflected light 91 reflected by the electrodes and the light 92 emitted by the light emitting element EL emitted from the opening 83 are shown.

The display modes that the display device can take include the reflective liquid crystal display mode (R-LC mode) and the reflective liquid crystal + EL display mode (R-LC + EL mode) shown in FIGS. 16 (A) to 16 (C). The EL display mode (EL mode) will be described.

The reflective liquid crystal display mode is a display mode in which the liquid crystal element of the pixel is driven to adjust the intensity of the reflected light to perform gradation display. Specifically, as shown in the schematic diagram of the pixels shown in FIG. 16A, the intensity of the reflected light 91 is adjusted by the liquid crystal layer with the reflective electrode of the liquid crystal element LC to display the gradation.

The reflective liquid crystal + EL display mode (R-LC + EL mode) is a display mode in which both the intensity of the reflected light and the intensity of the light of the light emitting element are adjusted by driving the liquid crystal element and the driving of the light emitting element to perform gradation display. .. Specifically, as shown in the schematic diagram of the pixels shown in FIG. 16B, the intensity of the reflected light 91 by the reflective electrode of the liquid crystal element LC and the intensity of the light 92 emitted by the light emitting element EL from the opening 83 are adjusted. And display the gradation.

The EL display mode (EL mode) is a display mode in which a light emitting element is driven to adjust the intensity of light to display gradation. Specifically, as shown in the schematic diagram of the pixels shown in FIG. 16C, the intensity of the light 92 emitted from the opening 83 by the light emitting element EL is adjusted to display the gradation.

FIG. 16D shows a state transition diagram of the above-mentioned three modes (reflective liquid crystal display mode, reflective liquid crystal + EL display mode, and EL display mode). The state C1 represents the reflective liquid crystal display mode, the state C2 represents the reflective liquid crystal + EL display mode, and the state C3 represents the EL display mode.

As shown in FIG. 16D, the display modes of any of the states C1 to C3 can be taken depending on the illuminance. When the illuminance is large, for example, outdoors, the state C1 can be taken. Further, when the illuminance such as moving from the outside to the inside becomes small, the state C1 is changed to the state C3. Further, even indoors, when the illuminance is large and the gradation display by the reflected light is possible, the state C3 is changed to the state C2.

By configuring the display mode to be switched according to the illuminance as described above, it is possible to reduce the frequency of gradation display due to the light intensity of the light emitting element having a relatively large power consumption. Therefore, the power consumption of the display device can be reduced.

The display device can further switch the operation mode according to the remaining capacity of the battery, the content to be displayed, or the illuminance of the surrounding environment. For example, a normal mode (Normal mode) that operates at a normal frame frequency and an idling stop (IDS) drive mode that operates at a low frame frequency can be mentioned.

The idling stop (IDS) drive is a drive method for stopping the rewriting of the image data after executing the image data writing process. By writing the image data once and then extending the interval until the next image data is written, it is possible to reduce the power consumption required for writing the image data during that period.

The idling stop (IDS) drive mode is effective because it is possible to further reduce power consumption by combining it with a display mode such as the above-mentioned reflective liquid crystal display mode or reflective liquid crystal + EL display mode.

<Electronic components>
An electronic component to which the above-mentioned semiconductor device is applied will be described.

FIG. 17A is a flowchart showing an example of a method for manufacturing an electronic component. Electronic components are also referred to as semiconductor packages or IC packages. There are a plurality of standards and names for this electronic component depending on the terminal take-out direction and the shape of the terminal. Therefore, an example thereof will be described.

A semiconductor device composed of transistors is completed by combining a plurality of removable parts on a printed circuit board through an assembly process (post-process). The post-process can be completed by going through each process shown in FIG. 17 (A). Specifically, after the element substrate obtained in the previous step is completed (step ST71), the back surface of the substrate is ground. At this stage, the substrate is thinned to reduce the warpage of the substrate in the previous process and to reduce the size of the parts. Next, a dicing step of separating the substrate into a plurality of chips is performed (step ST72).

FIG. 17B is a top view of the semiconductor wafer 7100 before the dicing step is performed. FIG. 17C is a partially enlarged view of FIG. 17B. The semiconductor wafer 7100 is provided with a plurality of circuit regions 7102. The semiconductor device according to the embodiment of the present invention is provided in the circuit area 7102.

Each of the plurality of circuit areas 7102 is surrounded by a separation area 7104. A separation line (also referred to as a “dicing line”) 7106 is set at a position overlapping the separation region 7104. In the dicing step ST72, the chip 7110 including the circuit region 7102 is cut out from the semiconductor wafer 7100 by cutting the semiconductor wafer 7100 along the separation line 7106. FIG. 17 (D) shows an enlarged view of the chip 7110.

A conductive layer or a semiconductor layer may be provided in the separation region 7104. By providing the conductive layer or the semiconductor layer in the separation region 7104, ESD that may occur during the dicing step can be alleviated, and a decrease in yield due to the dicing step can be prevented. Further, in general, the dicing step is performed while supplying pure water having a reduced specific resistance by dissolving carbon dioxide gas or the like to the cutting portion for the purpose of cooling the substrate, removing shavings, preventing antistatic, and the like. By providing a conductive layer or a semiconductor layer in the separation region 7104, the amount of pure water used can be reduced. Therefore, the production cost of the semiconductor device can be reduced. Moreover, the productivity of the semiconductor device can be increased.

After performing step ST72, a die bonding step is performed in which the separated chips are individually picked up, mounted on a lead frame, and bonded (step ST73). As the bonding method between the chip and the lead frame in the die bonding process, a method suitable for the product may be selected. For example, adhesion may be performed by resin or tape. In the die bonding step, the chip may be mounted on the interposer substrate and bonded. In the wire bonding step, the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step ST74). A silver wire or a gold wire can be used as the thin metal wire. The wire bonding may be either ball bonding or wedge bonding.

The wire-bonded chips are subjected to a molding process in which they are sealed with an epoxy resin or the like (step ST75). By performing the molding process, the inside of the electronic component is filled with resin, damage to the built-in circuit part and wire due to mechanical external force can be reduced, and deterioration of characteristics due to moisture and dust can be reduced. it can. The leads of the lead frame are plated. Then, a "molding step" of cutting and molding the lead is performed (step ST76). The plating process prevents rust on the leads, and soldering can be performed more reliably when mounting on a printed circuit board later. A printing process (marking) is applied to the surface of the package (step ST77). The electronic component is completed through the inspection step (step ST78) (step ST79). By incorporating the semiconductor device of the above-described embodiment, it is possible to provide a small electronic component with low power consumption.

A schematic perspective view of the completed electronic component is shown in FIG. 17 (E). FIG. 17 (E) shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. As shown in FIG. 17 (E), the electronic component 7000 has a lead 7001 and a chip 7110.

The electronic component 7000 is mounted on, for example, the printed circuit board 7002. A plurality of such electronic components 7000 are combined and electrically connected to each other on the printed circuit board 7002 so that they can be mounted on an electronic device. The completed circuit board 7004 is provided inside an electronic device or the like. By mounting the electronic component 7000, the power consumption of the electronic device can be reduced. Alternatively, it becomes easy to miniaturize the electronic device.

Electronic components 7000 include digital signal processing, software defined radio, bioinformatics (electronic equipment related to aviation such as communication equipment, navigation systems, automatic control devices, flight management systems, etc.), ASIC prototyping, medical image processing, voice recognition, encryption, etc. It can be applied to electronic components (IC chips) of electronic devices in a wide range of fields such as bioinformatics (biological information science), emulators of mechanical devices, and radio telescopes in radio astronomy. Examples of such electronic devices include cameras (video cameras, digital still cameras, etc.), display devices, personal computers (PCs), mobile phones, game machines including portable types, portable information terminals (smartphones, tablet type information terminals, etc.). ), Electronic book terminals, wearable information terminals (clock type, head mount type, goggles type, eyeglass type, arm badge type, bracelet type, necklace type, etc.), navigation system, sound reproduction device (car audio, digital audio player, etc.) , Copiers, facsimiles, printers, printer multifunction devices, automatic cash deposit / payment machines (ATMs), vending machines, household appliances, etc.

<Electronic equipment>
Next, for electronic devices such as computers, personal digital assistants (including mobile phones, portable game machines, sound reproduction devices, etc.), electronic papers, television devices (also called televisions or television receivers), and digital video cameras. , The case where the above-mentioned electronic component is applied will be described.

FIG. 18A is a portable information terminal, which is composed of a housing 801 and a housing 802, a first display unit 803a, a second display unit 803b, and the like. At least a part of the housing 801 and the housing 802 is provided with an electronic component having the above-mentioned semiconductor device. Therefore, a portable information terminal capable of switching operations at high speed is realized.

The first display unit 803a is a panel having a touch input function. For example, as shown in the left figure of FIG. 18A, the selection button 804 displayed on the first display unit 803a "touch input". ", Or" keyboard input "can be selected. Since the selection buttons can be displayed in various sizes, people of all ages can experience the ease of use. Here, for example, when "keyboard input" is selected, the keyboard 805 is displayed on the first display unit 803a as shown in the right figure of FIG. 18A. As a result, it is possible to quickly input characters by key input as in the case of a conventional information terminal.

Further, in the portable information terminal shown in FIG. 18A, one of the first display unit 803a and the second display unit 803b can be removed as shown in the right figure of FIG. 18A. .. The second display unit 803b is also a panel having a touch input function, which makes it possible to further reduce the weight when carrying it, and it is convenient because the housing 802 can be held by one hand and operated by the other hand. is there.

The portable information terminal shown in FIG. 18A has a function of displaying various information (still images, moving images, text images, etc.), a function of displaying a calendar, a date, a time, etc. on the display unit, and a function of displaying on the display unit. It can have a function of manipulating or editing the information, a function of controlling processing by various software (programs), and the like. Further, the back surface or the side surface of the housing may be provided with an external connection terminal (earphone terminal, USB terminal, etc.), a recording medium insertion portion, or the like.

Further, the portable information terminal shown in FIG. 18A may be configured to be able to transmit and receive information wirelessly. It is also possible to purchase desired book data or the like from an electronic book server and download it wirelessly.

Further, the housing 802 shown in FIG. 18A may be provided with an antenna, a microphone function, and a wireless function and used as a mobile phone.

FIG. 18B is an electronic book terminal 810 on which electronic paper is mounted, and is composed of two housings, a housing 811 and a housing 812. The housing 811 and the housing 812 are provided with a display unit 813 and a display unit 814, respectively. The housing 811 and the housing 812 are connected by a shaft portion 815, and the opening / closing operation can be performed with the shaft portion 815 as an axis. Further, the housing 811 includes a power supply 816, operation keys 817, a speaker 818, and the like. At least one of the housing 811 and the housing 812 is provided with an electronic component having the above-mentioned semiconductor device. Therefore, an electronic book terminal capable of switching operations at high speed is realized.

FIG. 18C is a television device, which includes a housing 821, a display unit 822, a stand 823, and the like. The operation of the television device 820 can be performed by the switch provided in the housing 821 or the remote controller operating device 824. The housing 821 and the remote controller operating device 824 are provided with electronic components having the above-mentioned semiconductor device. Therefore, a television device capable of switching operations at high speed is realized.

FIG. 18D shows a smartphone, and the main body 830 is provided with a display unit 831, a speaker 832, a microphone 833, an operation button 834, and the like. An electronic component having the above-mentioned semiconductor device is provided in the main body 830. Therefore, a smartphone capable of switching operations at high speed is realized.

FIG. 18E is a digital camera, which is composed of a main body 841, a display unit 842, an operation switch 843, and the like. The semiconductor device shown in the previous embodiment is provided in the main body 841. Therefore, a digital camera with low power consumption is realized.

<Additional notes regarding the description of this specification, etc.>
In the present specification and the like, the ordinal numbers "first", "second", and "third" are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited.

In the present specification and the like, in the block diagram, the components are classified according to their functions and shown as blocks independent of each other. However, in an actual circuit or the like, it is difficult to separate the components for each function, and there may be a case where a plurality of functions are involved in one circuit or a case where one function is involved in a plurality of circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification, and can be appropriately paraphrased according to the situation.

In the drawings, the same elements or elements having the same function, elements of the same material, elements formed at the same time, and the like may be given the same reference numerals, and the repeated description thereof may be omitted.

In the present specification and the like, when explaining the connection relationship of transistors, one of the source and the drain is referred to as "one of the source or the drain" (or the first electrode or the first terminal), and the source and the drain are referred to. The other is referred to as "the other of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of the transistor change depending on the structure or operating conditions of the transistor. The names of the source and drain of the transistor can be appropriately paraphrased according to the situation, such as the source (drain) terminal and the source (drain) electrode.

Further, in the present specification and the like, the voltage and the potential can be paraphrased as appropriate. The voltage is a potential difference from a reference potential. For example, if the reference potential is a ground potential (ground potential), the voltage can be paraphrased as a potential. The ground potential does not necessarily mean 0V. The electric potential is relative, and the electric potential given to the wiring or the like may be changed depending on the reference electric potential.

In the present specification and the like, the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows. Alternatively, the switch means a switch having a function of selecting and switching a path through which a current flows.

As an example, an electric switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific switch as long as it can control the current.

When a transistor is used as a switch, the "conducting state" of the transistor means a state in which the source and drain of the transistor can be regarded as being electrically short-circuited. Further, the "non-conducting state" of the transistor means a state in which the source and drain of the transistor can be regarded as being electrically cut off. When the transistor is operated as a simple switch, the polarity (conductive type) of the transistor is not particularly limited.

In the present specification and the like, the term "A and B are connected" means that A and B are directly connected and that they are connected. Here, the fact that A and B are connected means that when an object having some kind of electrical action exists between A and B, an electric signal can be exchanged between A and B. To say.

C1 state C2 state C3 state CS0 switch CS1 switch m0 node m1 node M1 transistor M2 transistor M3 transistor mb0 node mb1 node MEM_0 configuration memory MEM_1 configuration memory MEM_3 configuration memory ST72 dicing process T0 time T1 time T2 time T3 time T4 time T5 Time T6 Time T7 Time T8 Time T9 Time T10 Time T11 Time T12 Time T13 Time T14 Time T15 Time Ve0 Potential Ve1 Potential wl0 Control signal line wl1 Control signal line 10 Transistor layer 12 Transistor 14 Semiconductor layer 16 Gate electrode 20 Wiring layer 20A 20B Wiring layer 22 Wiring 24 Insulation layer 30 Transistor layer 32 Transistor 34 Semiconductor layer 35 Optical 36 Gate electrode 40 Wiring layer 40A Wiring layer 40B Wiring layer 42 Wiring 44 Insulation layer 51 Pixel circuit 52 Pixel circuit 61 Layer 62 Layer 63 Layer 70 Board 71 Electrode 72 Light emitting layer 73 Electrode 74 Color filter 75 Electrode 80 Substrate 81 Reflective electrode 82 Conductive layer 83 Opening 84 Liquid crystal 85 Conductive layer 86 Color filter 87 Electron 90 Pixel 91 Reflected light 92 Light 101 Sensor 102 Application processor 103 Configuration controller 104 Configuration Memory array 105 Image processor 106 Host controller 107 Interface 108 Correction parameter holding circuit 109 Correction selection circuit 110 Driver IC
111 driver IC
112 Display 113 Display 114 Liquid crystal element 115 Light emitting element 116 Gamma correction circuit 117 Dimming correction circuit 118 Curved surface correction circuit 119 Threshold correction circuit 120 Toning correction circuit 130 Display device 201 Transistor 202 Transistor 203 Transistor 204 Transistor 205 Transistor 206 Transistor 207 Capsule 208 Transistor 209 Transistor 210 Transistor 211 Transistor 212 Transistor 213 Transistor 214 Capsule 216 Buffer circuit 217 Transistor 218 Conductor 220 Insulation 222 Insulation 224 Insulation 230 Oxide 230a Oxide 230b Oxide 230c Oxide 240a Conductor 240b Conductor 244 Conductor 246a Conductor 246b Conductor 250 Insulation 260 Insulation 270 Insulation 280 Insulation 282 Insulation 284 Insulation 300 Capsule 300A Capsule 301 Substrate 302 Semiconductor Region 304 Insulation 306 Conductor 308a Low Resistance Region 308b Low Resistance Region 320 Insulation 322 Insulation 324 Insulation 326 Insulation 328 Insulation 330 Insulation 350 Insulation 352 Insulation 354 Insulation 356 Insulation 358 Insulation 400 Transistor 405 Insulation 410 Insulation 412 Insulation 414 Insulation 416 Insulation 500 Transistor 500A Transistor 602 Insulation 604 Insulation 612 Insulation 616 Insulation 620 Insulation 622 Insulation 624 Conductor 626 Conductor 628 Conductor 631 Board 632 Board 801 Housing 802 Housing 803a Display 803b Display 804 Select button 805 Keyboard 810 Electronic book terminal 811 Housing 812 Housing 815 Display unit 814 Display unit 815 Shaft unit 816 Power supply 817 Operation key 818 Speaker 820 Television device 821 Housing 822 Display unit 823 Stand 824 Remote control operation machine 830 Main unit 831 Display unit 832 Speaker 833 Microphone 834 Operation button 841 Main unit 842 Display 843 Operation switch 7000 Electronic parts 7001 Lead 7002 Print board 7004 Circuit board 7100 Semiconductor wafer 7102 Circuit area 7104 Separation area 7106 Separation line 7110 Chip

Claims (6)

A sensor that has a function to detect illuminance and
When the change in illuminance is detected, the function of updating the calculated calculation parameter according to the detected illuminance by calculation and one of a plurality of parameters prepared in advance until the calculation parameter is updated. An application processor having a function of generating a context switching signal for selecting a parameter according to the detected illuminance.
A configuration controller having a function of generating a first configuration data corresponding to the operation parameter and a function of generating a plurality of second configuration data corresponding to the plurality of parameters, respectively.
A configuration memory array having a function of holding the first configuration data and the plurality of second configuration data.
Until the calculation parameter is updated by the calculation, image processing is executed according to the second configuration data corresponding to the one parameter selected by the context switching signal, and the calculation parameter is updated. A semiconductor device having an image processor having a function of executing image processing according to the first configuration data corresponding to the updated arithmetic parameters. In claim 1,
The configuration memory array has a plurality of configuration memories.
The configuration memory is
It has a first charge holding circuit, a second charge holding circuit, a first switch, a second switch, and a buffer circuit.
The first charge holding circuit and the second charge holding circuit each have a first transistor and a second transistor, respectively.
The first transistor and the second transistor each have an oxide semiconductor in a semiconductor layer serving as a channel forming region.
One of the source or drain of the first transistor is electrically connected to the gate of the second transistor.
One of the source or drain of the second transistor is electrically connected to one terminal of the first switch or one terminal of the second switch.
The other terminal of the first switch is electrically connected to the other terminal of the second switch.
The other terminal of the first switch and the other terminal of the second switch are electrically connected to the input terminal of the buffer circuit.
The capacitance of one terminal of the first switch is larger than the capacitance of the input terminal of the buffer circuit.
A semiconductor device characterized in that the capacitance of one terminal of the second switch is larger than the capacitance of the input terminal of the buffer circuit. In claim 2,
A semiconductor device characterized in that the on or off of the first switch and the second switch is controlled by the context switching signal. In claim 2 or 3,
The first switch and the second switch each have a third transistor.
The third transistor is a semiconductor device characterized by having silicon in a semiconductor layer serving as a channel forming region. In claim 4,
A semiconductor device, wherein the first transistor and the second transistor are provided on an upper layer of the third transistor. In claim 4,
It has a first capacitive element and a second capacitive element,
The capacitance of the first capacitive element is the capacitance of one terminal of the first switch.
The capacitance of the second capacitive element is the capacitance of one terminal of the second switch.
A semiconductor device characterized in that the first capacitive element and the second capacitive element are provided on an upper layer of the first transistor and the second transistor.

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