JP6676990B2 - Method for manufacturing field effect transistor - Google Patents

Description

  The present invention relates to a method for manufacturing a field effect transistor.

As an example of a field effect transistor (Field Effect Transistor; FET), a field effect transistor using an oxide semiconductor for an active layer is known. In general, in a field-effect transistor including an oxide semiconductor, a patterning process is performed on the oxide semiconductor with an oxalic acid-based acidic etchant in a manufacturing process using photolithography. In a bottom-gate field-effect transistor, when an oxide semiconductor is etched to form an active layer, the selectivity between the gate insulating layer (for example, an SiO ₂ film) and the oxide semiconductor is sufficiently high. Good pattern processing is realized.

However, in recent years, demands for higher integration and lower power consumption of electronic devices have been increasing, and a technique using a material having a higher relative dielectric constant than SiO ₂ as a gate insulating layer has been proposed. As an insulating material having a high relative permittivity, a composite metal oxide of an alkaline earth metal or a rare earth metal is disclosed (for example, see Patent Documents 1 and 2).

  Even when the composite metal oxide film is used for the gate insulating layer, it is required to sufficiently increase the etching selectivity with the oxide semiconductor as described above. If the etching selectivity is not sufficiently high, the gate insulating layer may be damaged, and the electrical characteristics of the field effect transistor may be affected. However, in the above technique, there is no disclosure about damage to the gate insulating layer in an etching step of an oxide semiconductor which is an upper layer of the gate insulating layer.

  The present invention suppresses etching damage to a gate insulating layer when patterning an oxide semiconductor on the gate insulating layer in a method for manufacturing a field-effect transistor having a gate insulating layer formed of a composite metal oxide. The purpose is to:

The method for manufacturing a field effect transistor according to the present invention is a method for manufacturing a field effect transistor having a gate insulating layer and an active layer formed on the gate insulating layer, wherein Ba, Mg , a step of forming Ca, and the element a is at least one of Sr, La, Sc, Sm, and the B element is at least one of Eu, the complex metal oxide film containing the As the active layer, In, an A ′ element that is at least one of Mg, Ca, Sr, Sc, Y, La, Ce, and Sm, and at least any one of Al, Ti, Zr, Sn, Hf, and W Forming an oxide semiconductor containing the element B ′ on the gate insulating layer, and patterning the oxide semiconductor on the gate insulating layer by wet etching using a hydrofluoric acid-based etchant. And a cleaning step.

  According to the disclosed technology, in a method for manufacturing a field-effect transistor having a gate insulating layer formed of a composite metal oxide, etching damage to the gate insulating layer when patterning the oxide semiconductor on the gate insulating layer Can be suppressed.

1 is a cross-sectional view illustrating a field-effect transistor according to a first embodiment. FIG. 4 is a diagram illustrating a manufacturing process of the field-effect transistor according to the first embodiment. FIG. 6 is a cross-sectional view illustrating a field-effect transistor according to a modification of the first embodiment. FIG. 14 is a block diagram illustrating a configuration of a television device according to a second embodiment. FIG. 10 is an explanatory diagram (part 1) of a television device according to a second embodiment. FIG. 10 is an explanatory diagram (part 2) of the television device according to the second embodiment. FIG. 10 is an explanatory diagram (No. 3) of the television device according to the second embodiment. FIG. 9 is an explanatory diagram of a display element according to a second embodiment. It is an explanatory view of an organic EL in a second embodiment. Explanatory drawing of the television device in the second embodiment (part 4) FIG. 10 is an explanatory diagram (part 1) of another display element according to the second embodiment. FIG. 14 is an explanatory view (part 2) of another display element according to the second embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

<First Embodiment>
[Structure of field-effect transistor]
FIG. 1 is a cross-sectional view illustrating a field-effect transistor according to the first embodiment. Referring to FIG. 1, a field-effect transistor 10 has a bottom gate / top having a base material 11, a gate electrode 12, a gate insulating layer 13, an active layer 14, a source electrode 15, and a drain electrode 16. It is a contact type field effect transistor. The field effect transistor 10 is a typical example of the semiconductor device according to the present invention.

  In the field-effect transistor 10, a gate electrode 12 is formed on an insulating base material 11, and a gate insulating layer 13 is formed so as to cover the gate electrode 12. An active layer 14 is formed on the gate insulating layer 13, and a source electrode 15 and a drain electrode 16 are formed on the active layer 14 so that a channel is formed in the active layer 14. Hereinafter, each component of the field-effect transistor 10 will be described in detail.

  In this embodiment, for convenience, the active layer 14 side is an upper side or one side, and the base material 11 side is a lower side or the other side. Also, the surface on the active layer 14 side of each part is the upper surface or one surface, and the surface on the base material 11 side is the lower surface or the other surface. However, the field effect transistor 10 can be used upside down, or can be arranged at any angle. The plan view refers to viewing the object from the normal direction of the upper surface of the base material 11, and the planar shape refers to the shape of the target object viewed from the normal direction of the upper surface of the base material 11. .

  The shape, structure, and size of the substrate 11 are not particularly limited, and can be appropriately selected according to the purpose. The material of the substrate 11 is not particularly limited and can be appropriately selected according to the purpose. For example, a glass substrate, a ceramic substrate, a plastic substrate, a film substrate, or the like can be used.

  The glass substrate is not particularly limited and can be appropriately selected depending on the purpose. Examples thereof include non-alkali glass and silica glass. The plastic substrate and the film substrate are not particularly limited and may be appropriately selected depending on the purpose. Examples thereof include polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate. (PEN) and the like.

  The gate electrode 12 is formed in a predetermined area on the base material 11. The gate electrode 12 is an electrode for applying a gate voltage. The material of the gate electrode 12 is not particularly limited and can be appropriately selected depending on the intended purpose. Examples thereof include aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), and silver (Ag). ), Copper (Cu), zinc (Zn), nickel (Ni), chromium (Cr), tantalum (Ta), molybdenum (Mo), titanium (Ti), and other metals, alloys thereof, and mixtures of these metals. Can be used. Further, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide, and niobium oxide, composite compounds thereof, and mixtures thereof may be used. The average thickness of the gate electrode 12 is not particularly limited and may be appropriately selected depending on the intended purpose. However, the average thickness is preferably 10 nm to 1 μm, and more preferably 50 nm to 300 nm.

  The gate insulating layer 13 is provided between the gate electrode 12 and the active layer 14, and is a layer for insulating the gate electrode 12 and the active layer 14. The average thickness of the gate insulating layer 13 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 50 nm to 3 μm, and more preferably 100 nm to 1 μm.

  Gate insulating layer 13 is a composite metal oxide film. The composite metal oxide film contains at least an element A that is an alkaline earth metal and an element B that is at least one of gallium (Ga), scandium (Sc), yttrium (Y), and a lanthanoid, Preferably, it contains a C element which is at least one of Zr (zirconium) and Hf (hafnium), and further contains other components as necessary.

  The alkaline earth metal contained in the composite metal oxide film may be one kind or two or more kinds. Examples of the alkaline earth element include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), and radium (Ra).

  As lanthanoids, lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

  Preferably, the composite metal oxide film contains a paraelectric amorphous oxide or is formed of paraelectric amorphous oxide itself. The paraelectric amorphous oxide is stable in the air and can form an amorphous structure stably in a wide composition range. However, crystals may be contained in a part of the composite metal oxide film.

  Alkaline earth oxides easily react with atmospheric moisture and carbon dioxide, easily change to hydroxides and carbonates, and are not suitable for application to electronic devices by themselves. In addition, simple oxides such as lanthanoids other than Ga, Sc, Y, and Ce are easily crystallized, causing a problem of leakage current. However, a composite oxide system of an alkaline earth metal and a lanthanoid other than Ga, Sc, Y, and Ce is stable in the air and can form an amorphous film in a wide composition range. Ce is specifically tetravalent among lanthanoids and forms a perovskite structure crystal with an alkaline earth metal. Therefore, in order to obtain an amorphous phase, Ce is preferably a lanthanoid other than Ce.

  Although a crystal phase such as a spinel structure exists between the alkaline earth metal and the Ga oxide, these crystals do not precipitate unless the temperature is extremely high as compared with the perovskite structure crystal (generally, 1000 ° C. or higher). . Further, no stable crystalline phase has been reported between the alkaline earth metal oxide and the oxides composed of lanthanoids except for Sc, Y, and Ce. Is rare. When a composite oxide of an alkaline earth metal and a lanthanoid other than Ga, Sc, Y and Ce is composed of three or more metal elements, the amorphous phase is further stabilized.

  The content of each element contained in the composite metal oxide insulating film is not particularly limited, but includes a metal element selected from each element group so as to have a composition that can take a stable amorphous state. Is preferred.

  From the viewpoint of manufacturing a high dielectric constant film, it is preferable to increase the composition ratio of elements such as Ba, Sr, Lu, and La.

Since the composite metal oxide insulating film according to this embodiment can form an amorphous film in a wide range of composition, the physical properties can be controlled in a wide range. For example, the relative dielectric constant is approximately 6 to 20 which is sufficiently higher than that of SiO ₂ , but can be adjusted to an appropriate value according to the use by selecting the composition.

Furthermore, the film has a thermal expansion coefficient equivalent to that of a general wiring material or semiconductor material having a coefficient of thermal expansion of 10 ⁻⁶ to 10 ⁻⁵ , and has a film even when the heating step is repeated as compared with SiO ₂ having a coefficient of thermal expansion of about 10 ⁻⁷ There are few troubles such as peeling. In particular, a favorable interface is formed with an oxide semiconductor such as a-IGZO.

  Therefore, by using the composite metal oxide insulating film according to this embodiment for the gate insulating layer 13, a high-performance semiconductor device can be obtained.

  The active layer 14 is a thin film formed of an oxide semiconductor formed on the gate insulating layer 13, and is arranged to face the gate electrode 12 with the gate insulating layer 13 interposed. The average thickness of the active layer 14 is not particularly limited and may be appropriately selected depending on the intended purpose. However, the average thickness is preferably 5 nm to 1 μm, more preferably 10 nm to 0.5 μm.

  The active layer 14 can be formed, for example, from an n-type oxide semiconductor. The n-type oxide semiconductor that forms the active layer 14 is not particularly limited and can be appropriately selected depending on the intended purpose. However, at least one of indium (In), Zn, tin (Sn), and Ti and alkali It preferably contains an earth element or a rare earth element, and more preferably contains In and an alkaline earth element or a rare earth element.

  Examples of rare earth elements include scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), Examples include gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

Indium oxide has an electron carrier concentration of about 10 ¹⁸ cm ⁻³ to 10 ²⁰ cm ⁻³ depending on the amount of oxygen deficiency. However, indium oxide has a property of easily causing oxygen vacancies, and in some cases, unintended oxygen vacancies may be formed in a later step after formation of the oxide semiconductor film. Forming an oxide mainly from two metals, indium and an alkaline earth element or a rare earth element, which is more likely to bond with oxygen than indium, prevents unintended oxygen deficiency and facilitates control of the composition, resulting in an improved electron carrier. It is particularly preferable because the concentration can be easily controlled appropriately.

  The n-type oxide semiconductor that forms the active layer 14 is a divalent cation, trivalent cation, tetravalent cation, pentavalent cation, hexavalent cation, heptavalent cation, and octavalent cation. It is preferable that the valence of the dopant is larger than the valence of metal ions (excluding the dopant) included in the n-type oxide semiconductor. Note that substitution doping is also referred to as n-type doping.

  The source electrode 15 and the drain electrode 16 are formed on the gate insulating layer 13. The source electrode 15 and the drain electrode 16 are formed at a predetermined interval. The source electrode 15 and the drain electrode 16 are electrodes for extracting a current according to the application of a gate voltage to the gate electrode 12. Note that the wiring connected to the source electrode 15 and the drain electrode 16 may be formed in the same layer as the source electrode 15 and the drain electrode 16.

  The material of the source electrode 15 and the drain electrode 16 is not particularly limited and can be appropriately selected depending on the purpose. Examples thereof include aluminum (Al), platinum (Pt), palladium (Pd), and gold (Au). , Silver (Ag), copper (Cu), zinc (Zn), nickel (Ni), chromium (Cr), tantalum (Ta), molybdenum (Mo), titanium (Ti) and other metals, alloys thereof, and these metals And the like can be used.

  Further, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide, and niobium oxide, composite compounds thereof, and mixtures thereof may be used. The average film thickness of the source electrode 15 and the drain electrode 16 is not particularly limited and can be appropriately selected depending on the intended purpose, but is preferably 10 nm to 1 μm, more preferably 50 nm to 300 nm.

[Method of manufacturing field effect transistor]
Next, a method for manufacturing the field-effect transistor shown in FIG. 1 will be described. FIG. 2 is a diagram illustrating a manufacturing process of the field-effect transistor according to the first embodiment.

  First, in the step shown in FIG. 2A, a substrate 11 made of a glass substrate or the like is prepared. Then, a conductive film made of aluminum (Al) or the like is formed on the base material 11 by a vacuum deposition method or the like, and the formed conductive film is patterned by photolithography and etching to form a gate electrode 12 having a predetermined shape. From the viewpoint of cleaning the surface of the substrate 11 and improving the adhesion, it is preferable to perform pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning before forming the gate electrode 12. The materials and thicknesses of the base material 11 and the gate electrode 12 can be appropriately selected as described above.

  The method for forming the gate electrode 12 is not particularly limited and can be appropriately selected depending on the purpose. For example, after film formation by a sputtering method, a vacuum evaporation method, a dip coating method, a spin coating method, a die coating method, or the like, There is a method of patterning by photolithography. As another example, there is a method in which a desired shape is directly formed into a film by a printing process such as inkjet, nanoimprint, or gravure.

  Next, in a step shown in FIG. 2B, a gate insulating layer 13 covering the gate electrode 12 is formed on the base material 11. The method for forming the gate insulating layer 13 is not particularly limited and can be appropriately selected depending on the purpose. Examples thereof include a sputtering method, a pulsed laser deposition (PLD) method, a chemical vapor deposition (CVD) method, A film forming process is exemplified by a vacuum process such as a layer deposition (ALD) method or a solution process such as dip coating, spin coating, and die coating. Other examples include printing processes such as inkjet, nanoimprint, gravure, and the like. The material and thickness of the gate insulating layer 13 can be appropriately selected as described above.

  Next, in a step illustrated in FIG. 2C, the oxide semiconductor layer 140 is formed over the entire surface of the gate insulating layer 13. The method for forming the oxide semiconductor layer 140 is not particularly limited and can be appropriately selected depending on the intended purpose. For example, a sputtering method, a pulsed laser deposition (PLD) method, a chemical vapor deposition (CVD) method, A film forming step may be performed by a vacuum process such as an atomic layer deposition (ALD) method or a solution process such as dip coating, spin coating, and die coating. Other examples include printing processes such as inkjet, nanoimprint, gravure, and the like. The oxide semiconductor layer 140 can be formed using, for example, an n-type oxide semiconductor. In the formed oxide semiconductor layer 140, crystalline and amorphous may be mixed.

  Next, in a step shown in FIG. 2D, the oxide semiconductor layer 140 formed over the entire surface of the gate insulating layer 13 is patterned into a predetermined shape by photolithography and wet etching, and the active layer 14 is formed. When the oxide semiconductor layer 140 is etched, a hydrofluoric acid-based etchant can be used. The hydrofluoric acid-based etchant preferably contains at least one of hydrogen fluoride, ammonium fluoride, and ammonium hydrogen fluoride. This makes it possible to stabilize the etching rate and improve the reproducibility of pattern production.

  Next, in a step shown in FIG. 2E, a source electrode 15 and a drain electrode 16 having a predetermined shape are formed on the gate insulating layer 13. From the viewpoint of cleaning the surface of the gate insulating layer 13 and improving adhesion, it is preferable to perform pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning before forming the source electrode 15 and the drain electrode 16.

  The method for forming the source electrode 15 and the drain electrode 16 is not particularly limited and can be appropriately selected depending on the purpose. Examples thereof include a sputtering method, a vacuum evaporation method, a dip coating method, a spin coating method, and a die coating method. After film formation, a method of patterning by photolithography may be used. As another example, there is a method in which a desired shape is directly formed into a film by a printing process such as inkjet, nanoimprint, or gravure. The material and thickness of the source electrode 15 and the drain electrode 16 can be appropriately selected as described above.

  Through the above steps, a bottom-gate / top-contact field-effect transistor 10 can be manufactured.

  As described above, in this embodiment, when the oxide semiconductor on the gate insulating layer formed using the composite metal oxide is patterned, wet etching is performed using a hydrofluoric acid-based etchant. Since the hydrofluoric acid-based etchant can selectively etch an oxide semiconductor with respect to the composite metal oxide, etching damage to the gate insulating layer can be suppressed, and the thickness of the gate insulating layer does not decrease, resulting in favorable insulation. Can maintain sex. As a result, a field-effect transistor having good electric characteristics can be realized.

<Modification of First Embodiment>
In the modification of the first embodiment, an example of a top gate / top contact type field effect transistor will be described. In the modification of the first embodiment, the description of the same components as those of the above-described embodiment may be omitted.

  FIG. 3 is a cross-sectional view illustrating a field-effect transistor according to a modification of the first embodiment. Referring to FIG. 3, the field-effect transistor 10A is a bottom-gate / bottom-contact field-effect transistor. The field effect transistor 10A is a typical example of the semiconductor device according to the present invention.

  The field effect transistor 10A has a different layer structure from the field effect transistor 10 (see FIG. 1). Specifically, the field-effect transistor 10A includes a base 11, a gate electrode 12 formed on the base 11, a gate insulating layer 13 formed on the gate electrode 12, and It has a source electrode 15 and a drain electrode 16 formed and an active layer 14 formed on the source electrode 15 and the drain electrode 16 and between the source electrode 15 and the drain electrode 16.

  The layer structure of the field-effect transistor according to the present invention is not particularly limited, and the structure shown in FIGS. 1 and 3 can be appropriately selected depending on the purpose.

  Note that a bottom-gate / bottom-contact field-effect transistor can be manufactured by forming an active layer after forming a source electrode and a drain electrode. The etching solution used for forming the active layer is the same as in the first embodiment.

[Example 1]
In Example 1, the bottom-gate / top-contact field-effect transistor shown in FIG. 1 was manufactured.

(Formation of gate electrode)
An Al film was formed on the base material 11 using a vacuum deposition method so as to have a thickness of 100 nm. A resist pattern was formed on the formed Al film by photolithography, and etching was performed to form a gate electrode 12 having a predetermined shape.

(Formation of gate insulating layer)
0.6 mL of the coating liquid for forming a gate insulating layer was dropped on the gate electrode 12 and spin-coated under predetermined conditions (rotated at 500 rpm for 5 seconds, then rotated at 3,000 rpm for 20 seconds, and rotated at 0 rpm for 5 seconds. Rotation was stopped.) Subsequently, after a drying treatment at 120 ° C. for 1 hour in the air, baking at 400 ° C. for 3 hours in an O ₂ atmosphere, annealing at 500 ° C. for 1 hour in an air atmosphere to form a gate insulating layer 13 A paraelectric amorphous oxide film having the composition described in Example 1 of Table 1 was formed. The average thickness of the gate insulating layer 13 was about 110 nm.

(Formation of active layer)
On the gate insulating layer 13, a W-doped MgIn ₂ O ₄ (InMgW oxide) to be the oxide semiconductor layer 140 was formed to a thickness of 50 nm by an RF magnetron sputtering method. A polycrystalline sintered body having a composition of MgIn 1.99 W 0.01 O ₄ was used as a target. Argon gas and oxygen gas were introduced as sputtering gases. The total pressure was fixed at 1.1 Pa, and the oxygen concentration was 20% by volume. In the oxide semiconductor layer 140 thus obtained, W is substituted and doped at a concentration of 0.5 mol% with respect to In in MgIn ₂ O ₄ .

  In addition, the temperature control of the base material 11 was not performed. It has been found that the temperature of the substrate 11 naturally rises during sputtering, but is kept at 40 ° C. or lower. That is, the film formation temperature of the InMgWO film is 40 ° C. or less. Next, a resist pattern was formed on the formed oxide semiconductor layer 140 by photolithography, and etching was performed with a hydrofluoric acid-based etchant to form the active layer 14 on the gate insulating layer 13. The formed active layer 14 was further heat-treated at 400 ° C. for 1 hour in the atmosphere.

(Formation of source electrode and drain electrode)
A source electrode 15 and a drain electrode 16 having a thickness of 100 nm were formed on the gate insulating layer 13 and the active layer 14 by using a vacuum evaporation method. Al was used as an evaporation source. The patterning was performed by forming a film through a metal mask. Thus, a bottom-gate / top-contact field-effect transistor was completed.

[Examples 2 to 7]
In Examples 2 to 7, bottom gate / top contact type field effect transistors were manufactured in the same manner as in Example 1 except that the composition of the gate insulating layer 13 was changed as shown in Table 1.

[Examples 8 to 14]
In Examples 8 to 14, the formation of the active layer 14 was performed except that an InLaWO film was formed using an oxide sintered body target having a target composition ratio of In: La: W = 99.5: 5: 0.5. In the same manner as in Examples 1 to 7, bottom-gate / top-contact field-effect transistors were manufactured.

(Inspection of the pattern with a microscope)
In Examples 1 to 14, as an inspection after pattern processing of the oxide semiconductor layer 140 formed on the gate insulating layer 13 (after forming the active layer 14), the gate insulating layer 13 before and after pattern processing of the oxide semiconductor layer 140 was determined. It was confirmed whether the film thickness had decreased or not, and the insulating property was confirmed.

  In Table 1 below, the presence or absence of a decrease in the thickness of the gate insulating layer 13 before and after the etching of the oxide semiconductor layer 140 is evaluated. When the pattern could not be maintained, the shape of the pattern of the active layer 14 formed on the gate insulating layer 13 was changed to × (○ when a good pattern was formed, and 、 when a good pattern was not formed). ).

表１より、実施例１〜１４の全てにおいて、活性層１４の形成工程におけるゲート絶縁層１３が膜厚減少せず、良好な絶縁性を維持できていたことがわかる。

Table 1 shows that in all of Examples 1 to 14, the thickness of the gate insulating layer 13 in the step of forming the active layer 14 did not decrease and good insulating properties were maintained.

<Second embodiment>
In the second embodiment, examples of a display element, an image display device, and a system using the field-effect transistor according to the first embodiment will be described. In the second embodiment, the description of the same components as those in the above-described embodiment may be omitted.

(Display element)
The display element according to the second embodiment has at least a light control element and a drive circuit for driving the light control element, and further has other members as necessary. The light control element is not particularly limited as long as it is an element that controls light output according to a drive signal, and can be appropriately selected according to the purpose. For example, an electroluminescence (EL) element, an electrochromic (EC) ) Elements, liquid crystal elements, electrophoretic elements, electrowetting elements and the like.

  The drive circuit is not particularly limited as long as it has the field-effect transistor according to the first embodiment, and can be appropriately selected depending on the purpose. The other members are not particularly limited and can be appropriately selected according to the purpose.

  Since the display element according to the second embodiment includes the field-effect transistor according to the first embodiment, the gate insulating layer 13 maintains good insulating properties, and has good electric characteristics. Can be obtained. As a result, high quality display can be performed.

(Image display device)
The image display device according to the second embodiment has at least a plurality of display elements, a plurality of wirings, and a display control device according to the second embodiment. It has a member. The plurality of display elements are not particularly limited as long as they are the plurality of display elements according to the second embodiment arranged in a matrix, and can be appropriately selected according to the purpose.

  The plurality of wirings are not particularly limited as long as the gate voltage and the image data signal can be individually applied to each field-effect transistor in the plurality of display elements, and can be appropriately selected depending on the purpose.

  The display control device is not particularly limited as long as the gate voltage and the signal voltage of each field-effect transistor can be individually controlled through a plurality of wirings according to image data, and is appropriately selected according to the purpose. can do. The other members are not particularly limited and can be appropriately selected according to the purpose.

  Since the image display device according to the second embodiment includes the display element including the field-effect transistor according to the first embodiment, a high-quality image can be displayed.

(system)
The system according to the second embodiment includes at least the image display device according to the second embodiment and an image data creation device. The image data creation device creates image data based on image information to be displayed, and outputs the image data to the image display device.

  Since the system includes the image display device according to the second embodiment, it is possible to display image information with high definition.

  Hereinafter, a display element, an image display device, and a system according to the second embodiment will be specifically described.

  FIG. 4 shows a schematic configuration of a television device 500 as a system according to the second embodiment. It should be noted that the connection lines in FIG. 4 show typical flows of signals and information, and do not represent all of the connection relationships between the blocks.

  A television apparatus 500 according to the second embodiment includes a main controller 501, a tuner 503, an AD converter (ADC) 504, a demodulation circuit 505, a TS (Transport Stream) decoder 506, an audio decoder 511, and a DA converter (DAC). 512, audio output circuit 513, speaker 514, video decoder 521, video / OSD synthesis circuit 522, video output circuit 523, image display device 524, OSD drawing circuit 525, memory 531, operation device 532, drive interface (drive IF) 541 , A hard disk device 542, an optical disk device 543, an IR light receiver 551, a communication control device 552, and the like.

  The main control device 501 controls the entire television device 500, and includes a CPU, a flash ROM, a RAM, and the like. The flash ROM stores a program described in codes decodable by the CPU, various data used for processing by the CPU, and the like. The RAM is a working memory.

  The tuner 503 selects a broadcast of a preset channel from broadcast waves received by the antenna 610. The ADC 504 converts an output signal (analog information) of the tuner 503 into digital information. The demodulation circuit 505 demodulates the digital information from the ADC 504.

  The TS decoder 506 performs TS decoding on the output signal of the demodulation circuit 505 to separate audio information and video information. The audio decoder 511 decodes the audio information from the TS decoder 506. The DA converter (DAC) 512 converts an output signal of the audio decoder 511 into an analog signal.

  The audio output circuit 513 outputs an output signal of the DA converter (DAC) 512 to the speaker 514. The video decoder 521 decodes the video information from the TS decoder 506. The video / OSD combining circuit 522 combines the output signal of the video decoder 521 and the output signal of the OSD drawing circuit 525.

  The video output circuit 523 outputs an output signal of the video / OSD synthesis circuit 522 to the image display device 524. The OSD drawing circuit 525 includes a character generator for displaying characters and graphics on the screen of the image display device 524, and outputs a signal including display information in response to an instruction from the operation device 532 or the IR receiver 551. Generate.

  The memory 531 temporarily stores AV (Audio-Visual) data and the like. The operation device 532 includes an input medium (not shown) such as a control panel, for example, and notifies the main control device 501 of various information input by a user. The drive IF 541 is a bidirectional communication interface, and conforms to ATAPI (AT Attachment Packet Interface) as an example.

  The hard disk device 542 includes a hard disk, a driving device for driving the hard disk, and the like. The drive device records data on the hard disk and reproduces data recorded on the hard disk. The optical disk device 543 records data on an optical disk (for example, DVD) and reproduces data recorded on the optical disk.

  IR receiver 551 receives an optical signal from remote control transmitter 620 and notifies main controller 501 of the signal. The communication control device 552 controls communication with the Internet. Various information can be obtained via the Internet.

  The image display device 524 includes a display 700 and a display control device 780 as shown in FIG. 5 as an example. As shown in FIG. 6 as an example, the display 700 has a display 710 in which a plurality (here, n × m) of display elements 702 are arranged in a matrix.

  Also, as shown in FIG. 7 as an example, the display 710 has n scanning lines (X0, X1, X2, X3,..., Xn) arranged at equal intervals along the X-axis direction. -2, Xn-1), m data lines (Y0, Y1, Y2, Y3,..., Ym-1) arranged at equal intervals along the Y-axis direction, M current supply lines (Y0i, Y1i, Y2i, Y3i,..., Ym-1i) arranged at regular intervals along the line. Then, the display element 702 can be specified by the scanning line and the data line.

  Each display element 702 includes an organic EL (electroluminescence) element 750 and a drive circuit 720 for causing the organic EL element 750 to emit light, as shown in FIG. 8 as an example. That is, the display 710 is a so-called active matrix type organic EL display. The display 710 is a 32-inch color display. The size is not limited to this.

  The organic EL element 750 has an organic EL thin film layer 740, a cathode 712, and an anode 714 as shown in FIG. 9 as an example.

The organic EL element 750 can be arranged, for example, beside the field-effect transistor. In this case, the organic EL element 750 and the field-effect transistor can be formed on the same base material. However, the present invention is not limited to this. For example, the organic EL element 750 may be arranged on a field-effect transistor. In this case, since transparency is required for the gate electrode, ITO (Indium Tin Oxide), In ₂ O ₃ , SnO ₂ , ZnO, ZnO to which Ga is added, and ZnO to which Al is added are added to the gate electrode. A transparent oxide having conductivity such as SnO ₂ to which ZnO and Sb are added is used.

In the organic EL element 750, Al is used for the cathode 712. Note that an Mg-Ag alloy, an Al-Li alloy, ITO, or the like may be used. ITO is used for the anode 714. Note that a conductive oxide such as In ₂ O ₃ , SnO ₂ , or ZnO, or an Ag—Nd alloy may be used.

  The organic EL thin film layer 740 has an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. The cathode 712 is connected to the electron transport layer 742, and the anode 714 is connected to the hole transport layer 746. When a predetermined voltage is applied between the anode 714 and the cathode 712, the light emitting layer 744 emits light.

  Further, as shown in FIG. 8, the drive circuit 720 has two field-effect transistors 810 and 820 and a capacitor 830. The field effect transistor 810 operates as a switch element. The gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to one terminal of the capacitor 830.

  The capacitor 830 stores the state of the field-effect transistor 810, that is, data. The other terminal of the capacitor 830 is connected to a predetermined current supply line.

  The field-effect transistor 820 is for supplying a large current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the field effect transistor 810. Then, the drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

  Therefore, when the field-effect transistor 810 is turned on, the organic EL element 750 is driven by the field-effect transistor 820.

  The display control device 780 includes an image data processing circuit 782, a scanning line driving circuit 784, and a data line driving circuit 786, as shown in FIG.

  The image data processing circuit 782 determines the luminance of the plurality of display elements 702 on the display 710 based on the output signal of the video output circuit 523. The scanning line driving circuit 784 individually applies a voltage to n scanning lines in accordance with an instruction from the image data processing circuit 782. The data line driving circuit 786 individually applies a voltage to m data lines in accordance with an instruction from the image data processing circuit 782.

  As is clear from the above description, in the television device 500 according to the present embodiment, the image decoder 521, the image / OSD synthesizing circuit 522, the image output circuit 523, and the OSD drawing circuit 525 constitute an image data creating device. ing.

  In the above description, the case where the light control element is an organic EL element has been described. However, the present invention is not limited to this, and may be a liquid crystal element, an electrochromic element, an electrophoretic element, or an electrowetting element.

  For example, when the light control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 11, the current supply line in the display element 703 becomes unnecessary.

  In this case, as shown in FIG. 12, drive circuit 730 includes only one field-effect transistor 840 similar to the field-effect transistors (810, 820) shown in FIG. Can be. In the field-effect transistor 840, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. Note that reference numerals 762 and 772 in FIG. 12 denote counter electrodes (common electrodes) of the capacitor 760 and the liquid crystal element 770, respectively.

  Further, in the above embodiment, the case where the system is a television device has been described, but the present invention is not limited to this. In short, what is necessary is just to include the image display device 524 as a device for displaying images and information. For example, a computer system in which a computer (including a personal computer) and the image display device 524 are connected may be used.

  Further, the image display device 524 is used as a display means in a portable information device such as a mobile phone, a portable music playback device, a portable video playback device, an electronic book, a PDA (Personal Digital Assistant), and an imaging device such as a still camera or a video camera. Can be used. Further, the image display device 524 can be used as a display unit of various information in a mobile system such as a car, an aircraft, a train, and a ship. Further, the image display device 524 can be used as a display device for various information in a measuring device, an analyzing device, a medical device, and an advertisement medium.

  As described above, the preferred embodiments and the like have been described in detail. However, the present invention is not limited to the above-described embodiments and the like, and various modifications may be made to the above-described embodiments and the like without departing from the scope described in the claims. Variations and substitutions can be made.

DESCRIPTION OF SYMBOLS 10, 10A Field effect transistor 11 Base material 12 Gate electrode 13 Gate insulating layer 14 Active layer 15 Source electrode 16 Drain electrode

JP 2015-111653 A Patent No. 5633346

Claims (4)

A method for manufacturing a field-effect transistor having a gate insulating layer and an active layer formed on the gate insulating layer,
As the gate insulating layer, a composite metal oxide containing an A element that is at least one of Ba, Mg, Ca, and Sr, and a B element that is at least one of La, Sc, Sm, and Eu Forming a film;
As the active layer, In, an A ′ element that is at least one of Mg, Ca, Sr, Sc, Y, La, Ce, and Sm, and at least one of Al, Ti, Zr, Sn, Hf, and W Forming an oxide semiconductor containing any one of the element B ′ on the gate insulating layer;
Patterning the oxide semiconductor on the gate insulating layer by wet etching using a hydrofluoric acid-based etchant.   2. The method according to claim 1, wherein the hydrofluoric acid-based etching solution contains at least one of hydrogen fluoride, ammonium fluoride, and ammonium hydrogen fluoride.   3. The field-effect transistor according to claim 1, wherein the composite metal oxide film contains a paraelectric amorphous oxide or is formed of the paraelectric amorphous oxide itself. Production method.   4. The composite metal oxide film according to claim 1, further comprising a C element that is at least one of Al, Ti, Zr, Hf, Nb, and Ta. 5. Method for manufacturing a field-effect transistor.

Images