JP6538008B2 - Multiplexer and method of manufacturing the same - Google Patents

Description

  The present invention relates to a multiplexer and a method of manufacturing the same, for example, to a multiplexer in which a plurality of dielectric layers are stacked and a method of manufacturing the same.

  Multiplexers such as diplexers are used in wireless communication terminals such as smart phones and mobile phones. It is known to use a laminate in which dielectric layers are laminated as a diplexer. In order to miniaturize a diplexer, it is known to use an LGA (Land Grid Array) having land electrodes on the lower surface of the laminate. It is known to electrically connect one of the land electrodes of LGA to a plating electrode provided on the upper surface of the laminate via the laminate (for example, Patent Document 1)

JP, 2016-39334, A

  In Patent Document 1, a plating electrode and a direction identification mark are provided on the top surface of the laminate. For this reason, miniaturization is difficult.

  The present invention is considered in view of the above-mentioned subject, and aims at miniaturizing.

According to the present invention, there is provided a laminated body in which a plurality of dielectric layers provided with a conductive pattern therebetween are laminated, a common terminal provided on the lower surface of the laminated body, a first terminal, a second terminal, and a ground terminal. A first filter connected between the common terminal and the first terminal and connected between the common terminal and the second terminal, and a first filter including a first inductor and a first capacitor formed of the conductor pattern And a second filter including a second inductor and a second capacitor formed of the conductor pattern, and the common terminal, the first terminal, the second terminal, and the ground terminal among the other through the conductor pattern. is non-conducting terminal that is not electrically connected to the terminal and conduction through the conductor pattern, wherein the conductive via the conductor pattern to the ground terminal, the direction provided on the upper surface of the laminate A multiplexer having a, and another mark.

  In the above configuration, a plurality of the nonconductive terminals may be provided, and the direction identification mark may be conductive to the terminal having the smallest area among the plurality of nonconductive terminals through the conductor pattern.

According to the present invention, there is provided a laminated body in which a plurality of dielectric layers provided with a conductive pattern therebetween are laminated, a common terminal provided on the lower surface of the laminated body, a first terminal, a second terminal, and a ground terminal. A first filter connected between the common terminal and the first terminal and connected between the common terminal and the second terminal, and a first filter including a first inductor and a first capacitor formed of the conductor pattern And a second filter including a second inductor and a second capacitor formed of the conductor pattern, and the common terminal, the first terminal, the second terminal, and the ground terminal among the other through the conductor pattern. It is non-conducting terminal that is not electrically connected to the terminal and conduction through the conductor pattern, anda direction identification mark provided on the upper surface of the laminate, the direction identification mark, the first Inductor, a first capacitor, the second inductor and the multiplexer being electrically connected to said non-conductive terminal through at least a portion extending in a plane direction of the conductor pattern in which the second forms a capacitor.

According to the present invention, there is provided a laminated body in which a plurality of dielectric layers provided with a conductive pattern therebetween are laminated, a common terminal provided on the lower surface of the laminated body, a first terminal, a second terminal, and a ground terminal. A first filter connected between the common terminal and the first terminal and connected between the common terminal and the second terminal, and a first filter including a first inductor and a first capacitor formed of the conductor pattern And a second filter including a second inductor and a second capacitor formed of the conductor pattern, and the common terminal, the first terminal, the second terminal, and the ground terminal among the other through the conductor pattern. is non-conducting terminal that is not electrically connected to the terminal and conduction through the conductor pattern, anda direction identification mark provided on the upper surface of the laminate, said first inductor and said At least one of the second inductor comprises a spiral pattern that is not the pattern is provided at the center, the direction identification mark is a multiplexer which does not overlap the spiral pattern located in the central portion of the spiral pattern in a plan view.

  In the above configuration, the spiral pattern may be formed by the conductor pattern closest to the direction identification mark.

According to the present invention, there is provided a laminated body in which a plurality of dielectric layers provided with a conductive pattern therebetween are laminated, a common terminal provided on the lower surface of the laminated body, a first terminal, a second terminal, and a ground terminal. A first filter connected between the common terminal and the first terminal and connected between the common terminal and the second terminal, and a first filter including a first inductor and a first capacitor formed of the conductor pattern And a second filter including a second inductor and a second capacitor formed of the conductor pattern, and the common terminal, the first terminal, the second terminal, and the ground terminal among the other through the conductor pattern. It is non-conducting terminal that is not electrically connected to the terminal and conduction through the conductor pattern, anda direction identification mark provided on the upper surface of the laminate, set in the most the direction identification mark side Conductive patterns that are is a multiplexer which includes the overlap in the direction identification mark, wherein is conductive in a direction identification mark first capacitor or electrode of the second capacitor in a plan view.

  In the above configuration, the common terminal, the first terminal, the second terminal, and the ground terminal may be provided only on the lower surface of the surfaces of the laminate.

  In the above configuration, it includes a third inductor and a third capacitor connected between the third terminal provided on the lower surface of the laminate, the common terminal and the third terminal, and formed of the conductor pattern. A third filter is provided, and the direction identification mark is electrically connected to another of the common terminal, the first terminal, the second terminal, the third terminal, and the ground terminal through the conductor pattern. It can be set as the structure currently conducted via the non-conductive terminal which is not carried out, and the said conductor pattern.

  In the above configuration, the common terminal, the first terminal, the second terminal, the ground terminal, and the direction identification mark may be plated layers.

The present invention is a first inductor and a first capacitor formed by laminating the plurality of dielectric layers provided with a conductor pattern therebetween, connected between the common terminal and the first terminal, and formed of the conductor pattern. And a second filter including a second inductor and a second capacitor formed between the common pattern and the second terminal and connected between the common terminal and the second terminal. And the other terminal of the common terminal, the first terminal, the second terminal, and the ground terminal, and the common terminal, the first terminal, the second terminal, and the ground terminal provided via the conductor pattern. is conductive conduction that are not non-conductive terminal via the conductor pattern, the conductor pattern are conductively via the orientation identification mer provided on the upper surface of the laminate to the ground terminal When a method of manufacturing a multiplexer comprising forming using a barrel plating method.

  According to the present invention, miniaturization can be achieved.

FIG. 1 is a circuit diagram of the diplexer according to the first embodiment. FIGS. 2A and 2B are a perspective view and a side view of the diplexer according to the first embodiment. FIG. 3: is a disassembled perspective view (the 1) of the laminated body in Example 1. FIG. FIG. 4 is a disassembled perspective view (part 2) of the laminate in the first embodiment. FIG. 5 is a flowchart of the method of manufacturing the diplexer according to the first embodiment. FIG. 6 is a circuit diagram of the diplexer according to Comparative Example 1. FIGS. 7A and 7B are a perspective view and a side view of a diplexer according to Comparative Example 1, respectively. FIG. 8 is a plan view of the laminate in the first embodiment. FIG. 9 is a diagram showing the insertion loss with respect to D1 / D2 in the first embodiment. FIG. 10 is a circuit diagram of the diplexer according to the second embodiment. FIG. 11 is a disassembled perspective view (part 1) of the laminate in the second embodiment. FIG. 12 is a disassembled perspective view (part 2) of the laminate in the second embodiment. FIG. 13 is a plan view of the laminate in the second embodiment. FIG. 14 is a circuit diagram of a triplexer according to a third embodiment. FIG. 15 is a perspective view of a triplexer according to a third embodiment. 16 (a) to 16 (d) are cross-sectional views showing an example of a method of forming a via wire. FIG. 17A to FIG. 17D are cross-sectional views showing another example of the method of forming the via wiring.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram of the diplexer according to the first embodiment. As shown in FIG. 1, in the diplexer 100, an LPF (low pass filter) 24 is connected between the common terminal Ta and the terminal T1. An HPF (high pass filter) 26 is connected between the common terminal Ta and the terminal T2. The ground sides of the LPF 24 and the HPF 26 are connected to the ground terminal Tg. The ground terminal Tg is connected to the direction identification mark 22.

  The LPF 24 includes inductors L11 and L12 and capacitors C11, C12 and C13. The inductors L11 and L12 are connected in series between the common terminal Ta and the terminal T1. The capacitor C11 is connected in parallel to the inductor L12. Capacitors C12 and C13 are respectively connected between nodes on both sides of inductor L12 and ground terminal Tg.

  The HPF 26 includes an inductor L21 and capacitors C21 to C23. The capacitors C21 and C23 are connected in series between the common terminal Ta and the terminal T2. Capacitor C22 and inductor L21 are connected in series between the node between capacitors C21 and C23 and ground terminal Tg.

The inductance of each inductor is as follows.
L11: 7 nH, L12: 4 nH, L21: 6 nH
The capacitance of each capacitor is
C11: 2 pF, C12: 4 pF, C13: 2.5 pF
C21: 2.5 pF, C22: 5 pF, C23: 3 pF
The pass band of each filter is set to include the following frequency bands.
LPF 24: 669 MHz to 960 MHz
HPF 26: 1710 MHz to 2690 MHz

  The LPF 24 passes the signal in the passband of the high frequency signal input to the common terminal Ta (or terminal T1) to the terminal T1 (or common terminal Ta) and suppresses the signal in the passband of the HPF 26. The HPF 26 passes the signal in the passband of the high frequency signal input to the common terminal Ta (or terminal T2) to the terminal T2 (or common terminal Ta) and suppresses the signal in the passband of the LPF 24. For example, an antenna is connected to the common terminal Ta. Low frequency band duplexers and high frequency band duplexers are connected to the terminals T1 and T2 via high frequency switches, for example.

  FIGS. 2A and 2B are a perspective view and a side view of the diplexer according to the first embodiment. FIG. 2A shows the terminal electrode 20 through the stacked body 10. The same is true for the following perspective views. As shown in FIGS. 2A and 2B, the terminal electrode 20 is provided on the lower surface of the laminate 10. The terminal electrode 20 includes a common terminal Ta, terminals T1 and T2, and a ground terminal Tg. The terminal electrode 20 is a land electrode of LGA, and is a terminal for connecting to the motherboard 30 as shown in FIG. For this reason, all the terminals are provided on the lower surface of the laminate 10. The direction identification mark 22 is a mark for identifying the direction of the laminate 10 when viewed from above. As shown in FIG. 2A, the shapes and positions of the terminals T1 and T2 are symmetrical. Therefore, the direction identification mark 22 is provided on the top surface of the laminate 10. In FIG. 2A, the terminal electrode 20 having the direction identification mark 22 can be identified as the terminal T2.

The terminal electrode 20 and the direction identification mark 22 are, for example, plated layers. The film thickness of the terminal electrode 20 and the direction identification mark 22 is, for example, 10 μm. The size of the terminal electrode 20 is, for example, as follows.
Common terminal Ta and ground terminal Tg: 180 μm × 125 μm
Terminal T1 and T2; 180 μm × 400 μm
The diameter of the direction identification mark 22 is, for example, 150 μm.

  The common terminal Ta and the terminal T1 are connected DC (Direct Current) via the inductors L11 and L12 as shown in FIG. 1 (solid line 52 in FIG. 2A). The terminal T2 and the ground terminal Tg are connected with the capacitor C12, C13 or C22 between the other terminal and the other terminal, and are not DC connected with the other terminal. The ground terminal Tg and the direction identification mark 22 are DC-connected as indicated by a broken line 50.

  3 and 4 are exploded perspective views of the laminate 10 in the first embodiment. As shown in FIGS. 3 and 4, a plurality of dielectric layers 11a to 11i are stacked. A conductor pattern 12a is formed on the top surface of the dielectric layer 11a. Conductor patterns 12b to 12i are formed between dielectric layers 11b to 11i. A conductor pattern 12j is formed on the lower surface of the dielectric layer 11i.

  The conductor pattern 12 a is a base layer of the direction identification mark 22. The conductor pattern 12 j is a base layer of the terminal electrode 20. In FIG. 4, the conductor pattern 12h corresponding to the common terminal Ta, the terminals T1 and T2, and the ground terminal Tg is illustrated as the terminals T1 and T2 and the ground terminal Tg.

  The conductor patterns 12b to 12i form the coil 14 of the inductor and the electrode 15 of the capacitor. The conductor patterns 12 a to 12 h are connected by via wires 13. The connection of the via wiring 13 is indicated by a broken line in the vertical direction. In this example, the conductor patterns 12b and 12c form inductors L11 and L21, and the conductor patterns 12d and 12e form an inductor L12. Capacitors C11 and C22 are formed by conductor patterns 12f and 12g. Capacitor C12 is formed of conductor patterns 12f to 12h. Capacitors C21 and C23 are formed by conductor patterns 12g to 12i. Capacitor C13 is formed of conductor patterns 12h and 12j.

  The electrode 15 and the coil 14 of the capacitor included in the LPF 24 and the electrode 15 and the coil 14 of the capacitor included in the HPF 26 do not overlap in a plan view. Thereby, the interference between the LPF 24 and the HPF 26 can be suppressed.

  The ground terminal Tg is connected to the direction identification mark 22 via the electrode 15 of the capacitor C12 of the conductor pattern 12h, the electrode 15 of the capacitor C12 of the conductor pattern 12f, and the coil 14a of the inductor L21 of the conductor pattern 12b. There is. The thickness of each of the dielectric layers 11a to 11i is, for example, 35 μm, 15 μm, 80 μm, 15 μm, 75 μm, 10 μm, 10 μm, 10 μm, and 35 μm.

  FIG. 5 is a flowchart of the method of manufacturing the diplexer according to the first embodiment. As shown in FIG. 5, the sheet-like dielectric layer 11 is formed (step S10). The dielectric layer 11 is produced, for example, using a doctor blade method. The dielectric layer 11 is a ceramic material containing an oxide such as Al, Si and / or Ca, for example. Via wiring 13 is formed to penetrate dielectric layer 11 (step S12). For example, a via hole penetrating the dielectric layer 11 is formed by laser light irradiation. Via interconnections 13 are formed in the via holes using the squeegee method or the like. The conductor pattern 12 is formed on the surface of the dielectric layer 11 (step S14). The conductor pattern 12 is formed using, for example, a screen printing method or a transfer method. The conductor pattern 12 and the via wiring 13 are metal layers, such as Ag, Pd, Pt, Cu, Ni, Au, an Au-Pd alloy or an Ag-Pt alloy, for example. The dielectric layer 11 is stacked to form a stacked body 10 (step S16). For the lamination of the dielectric layer 11, for example, heat pressure or an adhesive is used. The laminate 10 is fired (step S18). The firing temperature is 700 ° C. or more. Thereby, the dielectric layer 11 becomes a sintered body. In addition to the ceramic material, the dielectric material layer 11 can also use a resin material or a glass material.

  The terminal electrode 20 and the direction identification mark 22 are formed by plating (step S20). For example, barrel plating is used to form the terminal electrode 20 and the direction identification mark 22. In the barrel plating method, the laminate 10 and conductive metal particles (media) are immersed in a plating solution. A current is applied to the plating solution while stirring the plating solution. Thereby, plated metal is deposited on the surface of the electrode formed by the conductor patterns 12a and 12j. The current flows as the media contacts the electrodes of the stack 10 and the plated metal deposits. When the area of the electrode is large, the probability that the electrode contacts the media is high. Thereby, the deposition amount of plating metal increases. Thus, the deposition amount of the plated metal depends on the area of the terminal electrode 20 and the direction identification mark 22.

(Comparative example 1)
FIG. 6 is a circuit diagram of the diplexer according to Comparative Example 1. FIGS. 7A and 7B are a perspective view and a side view of a diplexer according to Comparative Example 1, respectively. As shown in FIGS. 6 and 7B, in the diplexer 110, the direction identification mark 22a is not connected to any of the common terminal Ta, the terminals T1 and T2, and the ground terminal Tg. The other configuration is the same as that of FIG. 1 of the first embodiment, and the description will be omitted.

  As shown in FIG. 7A, the common terminal Ta and the ground terminal Tg are smaller than the areas of the terminals T1 and T2. The reason why the common terminal Ta and the ground terminal Tg are small is for miniaturization. The area of the terminal electrode 20 is made different depending on the requirements for mounting on the motherboard 30. In particular, when the terminal electrode 20 is LGA, the terminal electrode 20 is provided only on the lower surface of the surface of the laminate 10. When the diplexer is to be miniaturized, the area of the lower surface of the laminate 10 is reduced. Therefore, the arrangement of the terminal electrodes 20 can be restricted, and the area of a part of the terminal electrodes 20 is reduced.

  As described above, when the area of the terminal electrode 20 is small, the amount of deposited plating metal decreases, and the terminal electrode 20 becomes thin. The common terminal Ta and the terminal T1 are conducted through the conductor patterns 12b to 12i through the inductors L11 and L12. For this reason, the common terminal Ta and the terminal T1 have a large substantial area when performing the plating of step S20. The terminal T2 is not conducted to any of the terminals but has a large area. The ground terminal Tg is not conducted to the other terminals and is small. Therefore, as shown in FIG. 7B, the ground terminal Tg becomes thin. As a result, when the diplexer is mounted on the mother board 30, the connection between the ground terminal Tg and the mother board 30 may be weakened.

  According to the first embodiment, the LPF 24 (first filter) includes inductors L11 and L12 (first inductor) formed by the conductor patterns 12b to 12i and capacitors C11 to C13 (first capacitor). The HPF 26 includes an inductor L21 (second inductor) formed by the conductor patterns 12b to 12i and capacitors C21 to C23 (second capacitor). The ground terminal Tg is electrically connected through the direction identification mark 22 provided on the top surface of the laminate 10 and the conductor patterns 12b to 12i. Thus, the direction identification of the non-conductive terminals not electrically connected to the other terminals through the conductive patterns 12b to 12i among the common terminal Ta, the terminal T1 (first terminal) terminal T2 (second terminal), and the ground terminal Tg Connect with the mark 22 in a DC manner.

  Thereby, when the terminal electrode 20 and the direction identification mark 22 are formed by plating, the area of the ground terminal Tg is substantially increased. Therefore, the film thickness of the ground terminal Tg can be set to about the other terminal electrode 20. Thus, the bonding strength between the ground terminal Tg and the motherboard 30 can be secured. Further, by using the plating electrode and the direction identification mark 22 in common, the size of the diplexer can be reduced. The shape of the direction identification mark 22 may be a polygon such as a quadrangle or a triangle other than a circle, or may be an oval. Also, the direction identification mark 22 may be characters such as alphanumeric characters or symbols such as arrows. The direction may be identified by the shape of the direction identification mark 22, or the direction may be identified by the position of the direction identification mark 22.

  Also, when there are a plurality of non-conductive terminals not connected to other terminals, such as the terminal T2 and the ground terminal Tg, the direction identification mark 22 is a terminal having the smallest area among the non-conductive terminals from the conductor pattern 12b. It is conducted through 12i. Thereby, the film thickness of the terminal electrode 20 which tends to be thinner can be enlarged.

  The terminal electrode 20 connected to the direction identification mark 22 may be other than the ground terminal Tg. By setting the terminal electrode 20 conducted to the direction identification mark 22 as the ground terminal Tg, the connection to the direction identification mark 22 can suppress the influence on the high frequency characteristics.

  As in the coil 14a of FIG. 3, the direction identification mark 22 is preferably electrically connected to the nonconductive terminal through at least a part of the conductor patterns 12a to 12i extending in the planar direction. Thereby, a part of the coil 14 of the inductor or the electrode 15 of the capacitor extending in the planar direction can be shared by the path connecting the ground terminal Tg and the direction identification mark 22. Therefore, the diplexer can be miniaturized.

  The inductor 24 is connected in series between the common terminal Ta and the terminal T1. Therefore, the common terminal Ta and the terminal T1 are connected in a DC manner. The HPF 26 has a capacitor connected in series between the common terminal Ta and the terminal T2. Therefore, the common terminal Ta and the terminal T2 are not connected in a DC manner. Therefore, the terminal T2 of the HPF 26 is likely to be a non-connection terminal. In addition, a capacitor is connected between the ground terminal Tg and the other terminal, which tends to be a non-connection terminal.

  When the terminal T2 is electrically connected to the direction identification mark 22, the direction identification mark 22 is preferably provided on the region of the laminate 10 in which the capacitor and the inductor included in the HPF 26 are formed. Thus, coupling of the direction identification mark 22 and the LPF 24 at high frequency can be suppressed, and deterioration of the isolation characteristic can be suppressed.

  When the ground terminal Tg is electrically connected to the direction identification mark 22, the inductor L21 of the HPF 26 is connected to the ground terminal Tg. Therefore, the direction identification mark 22 is preferably provided on the region of the laminate 10 in which the capacitor and the inductor included in the HPF 26 are formed. Thus, coupling of the direction identification mark 22 and the LPF 24 at high frequency can be suppressed, and deterioration of the isolation characteristic can be suppressed.

  FIG. 8 is a plan view of the laminate in the first embodiment. In FIG. 8, the coils 14a and 14b formed by the direction identification mark 22 and the conductor pattern 12b are illustrated. As shown in FIG. 8, on the top surface of the dielectric layer 11b, coils 14a and 14b are formed of a conductor pattern 12b. Coils 14a and 14b are part of inductors L21 and L11, respectively. Coil 14a includes pads 62a and 62b and a spiral pattern 64. The spiral pattern 64 is connected between the pads 62a and 62b. The pad 62a is connected to the direction identification mark 22 by the via wire 13a. The pad 62b is connected to the ground terminal Tg via the via wiring 13b.

  The spiral pattern 64 is not provided at the center. For example, the center of the spiral pattern 64 and the center of the direction identification mark 22 substantially coincide with each other. The inner diameter of the spiral pattern 64 is D2, and the diameter of the direction identification mark 22 is D1.

  D1 / D2 was varied to simulate insertion loss in the pass band of the HPF 26. FIG. 9 is a diagram showing the insertion loss with respect to D1 / D2 in the first embodiment. As shown in FIG. 9, the insertion loss hardly changes when D1 / D2 × 100% is 80% or less. When D1 / D2 × 100% is 100% or more, the insertion loss increases. In Example 1, D1 = 150 μm, D2 = 250 μm, and D1 / D2 = 60%.

  Thus, at least one of the inductors L11, L12 and L21 includes a spiral pattern 64 which is not provided with a pattern at its center. The direction identification mark 22 is located at the center of the spiral pattern 64 in plan view and does not overlap the spiral pattern 64. As a result, deterioration of the characteristics of the LPF 24 or the HPF 26 can be suppressed.

  In particular, among the conductor patterns 12b to 12i, the spiral pattern 64 formed by the conductor pattern 12b closest to the direction identification mark 22 is susceptible to the direction identification mark. Therefore, it is preferable that the direction identification mark 22 be located at the center of the spiral pattern 64 formed by the conductor pattern 12 b closest to the direction identification mark 22 and not overlap the spiral pattern 64.

  FIG. 10 is a circuit diagram of the diplexer according to the second embodiment. As shown in FIG. 10, in the diplexer 102, of the capacitor C22 and the inductor L21 connected in series between the ground terminal Tg and the node between the capacitors C21 and C23, the capacitor C22 is on the side of the ground terminal Tg, the inductor L21. Are connected to the node side. That is, the capacitor C22 and the inductor L21 are connected reversely to FIG. 1 of the first embodiment. The other configuration is the same as that of FIG.

  11 and 12 are disassembled perspective views of the laminate 10 in the second embodiment. As shown in FIGS. 11 and 12, conductor patterns 12b and 12c form an inductor L11 and a capacitor C22. Conductor patterns 12d and 12e form inductors L12 and L21. Capacitor C11 is formed of conductor patterns 12f and 12g. Capacitor C12 is formed of conductor patterns 12f to 12h. Capacitors C21 and C23 are formed by conductor patterns 12g to 12i. Capacitor C13 is formed of conductor patterns 12h and 12i. The electrode 15a of the capacitor C22 is formed by the conductor pattern 12b closest to the direction identification mark 22.

  The ground terminal Tg is connected to the direction identification mark 22 via the electrode 15 of the capacitor C13 of the conductor pattern 12h, the electrode 15 of the capacitor C12 of the conductor pattern 12f, and the electrode 15a of the capacitor C22 of the conductor pattern 12b. The other configuration is the same as in FIGS. 3 and 4 of the first embodiment, and the description will be omitted.

  FIG. 13 is a plan view of the laminate in the second embodiment. In FIG. 13, the electrode 15a coil 14b formed of the direction identification mark 22 and the conductor pattern 12b is illustrated. As shown in FIG. 13, an electrode 15a and a coil 14b are formed of a conductor pattern 12b on the top surface of the dielectric layer 11b. The electrode 15a and the coil 14b are parts of the capacitor C22 and the inductor L11, respectively. The electrode 15a is connected to the ground terminal Tg via the via wiring 13b. The direction identification mark 22 is connected to the electrode 15a via the via wiring 13a. The direction identification mark 22 overlaps the electrode 15a in plan view.

  According to the second embodiment, the conductor pattern 12b provided closest to the direction identification mark 22 includes the electrode 15a which overlaps the direction identification mark 22 and is conducted to the direction identification mark 22 in plan view. The electrode 15 a is an electrode of a capacitor included in at least one of the LPF 24 and the HPF 26. As a result, capacitive coupling between the direction identification mark 22 and the conductor patterns 12c to 12i below the conductor pattern 12b can be suppressed. Therefore, characteristic deterioration of the LPF 24 and the HPF 26 can be suppressed. The direction identification mark 22 is preferably smaller than the electrode 15a and does not overlap the outside of the electrode 15a in a plan view.

  FIG. 14 is a circuit diagram of a triplexer according to a third embodiment. As shown in FIG. 14, in the triplexer 104, a band pass filter (BPF) 28 is connected between the common terminal Ta and the terminal T3. BPF 28 includes inductors L31 to L33 and capacitors C30 to C33. An inductor L31 and capacitors C30 and C31 are connected in series between the common terminal Ta and the terminal T3. An inductor L32 and a capacitor C32 are connected in parallel between a node between the capacitors C30 and C31 and the ground terminal Tg. An inductor L33 and a capacitor C33 are connected in parallel between the terminal T3 and the ground terminal Tg.

  The BPF 28 has a passband between the LPF 24 and the passband of the HPF 26. The BPF 28 passes the signal in the passband of the high frequency signal input to the common terminal Ta (or terminal T3) to the terminal T3 (or common terminal Ta) and suppresses the signal in the passband of the LPF 24 and the HPF 26. A duplexer for an intermediate frequency band is connected to the terminal T3 via, for example, a high frequency switch.

  FIG. 15 is a perspective view of a triplexer according to a third embodiment. As shown in FIG. 15, the terminal electrode 20 is provided on the lower surface of the laminate 10. The terminal electrode 20 includes a common terminal Ta, terminals T1, T2, and T3 and two ground terminals Tg. The size of the terminal electrode 20 is, for example, 180 μm × 125 μm.

  The common terminal Ta and the terminal T1 are DC-connected via the inductors L11 and L12 as shown in FIG. 14 (solid line 52 in FIG. 15). The terminal T3 and the ground terminal Tg are conducted in a DC manner via the inductor L33 (dotted line 54 in FIG. 15). The capacitor C12, C13 or C22 is connected between the terminal T2 and the other terminal, and is not connected to the other terminal in a DC manner. Therefore, the ground terminal Tg and the direction identification mark 22 are electrically connected via the conductor pattern. Thereby, it can suppress that terminal T3 becomes thin.

  According to the third embodiment, the BPF 28 (third filter) is connected between the common terminal Ta and the terminal T3 (third terminal), and inductors L31 to L33 (first inductor) and capacitors C30 to C33 (third Capacitors). Direction identification mark 22 includes a nonconductive terminal not electrically connected to another terminal through conductive pattern 12b to 12i among common terminal Ta, terminals T1, T2 and T3 and ground terminal Tg and conductive pattern 12b to 12i. It is conducted. This can suppress thinning of the non-conductive terminal. Further, since the direction identification mark 22 is used as a plating electrode, the triplexer can be miniaturized.

  In the first to third embodiments, the first filter is the LPF 24, the second filter is the HPF 26, and the third filter is the BPF 28, but the first to third filters have desired filter characteristics. It can be arbitrarily selected from LPF, BPF and HPF to obtain. The number and size of the capacitors and inductors included in each of the first to third filters can be arbitrarily selected to obtain desired filter characteristics.

  Next, an example of the method of forming the via wiring in step S12 of FIG. 5 will be described. 16 (a) to 16 (d) are cross-sectional views showing an example of a method of forming a via wire. 16 (b) and 16 (d) are enlarged views of the vicinity of the via hole or via wiring of FIGS. 16 (a) and 16 (c).

  As shown in FIG. 16A, the sheet-like dielectric layer 11 is attached onto the support sheet 42. The support sheet 42 is, for example, a resin sheet such as a PET (Polyethylene Terephthalate) sheet. The support sheet 42 is suctioned to the suction table 40. The suction table 40 sucks the support sheet 42 in a vacuum. The laser beam 44 condensed by the condenser lens 44 a is directly irradiated to the dielectric layer 11. Thereby, a via hole 32 penetrating the dielectric layer 11 is formed. As shown in FIG. 16B, when the intensity of the laser beam 44 is reduced to form fine via holes 32, the cross-sectional shape of the via holes 32 in the dielectric layer 11 becomes a trapezoidal shape close to a triangle. That is, the side surface of the via hole 32 is tapered.

  As shown in FIG. 16C, the screen 48 having the opening 47 on the via hole 32 is disposed on the dielectric layer 11. The opening 47 is provided at a position corresponding to the via hole 32. Therefore, the screen 48 is a dedicated mask having the openings 47 matched to the arrangement of the via holes 32. The metal paste 34 is filled in the via hole 32 using the squeegee 46. As shown in FIG. 16D, the metal paste 34 is filled in the via hole 32. The openings 47 form lands 36 larger than the via holes 32 on the via holes 32. Thereafter, the support sheet 42 is peeled off from the dielectric layer 11.

  FIG. 17A to FIG. 17D are cross-sectional views showing another example of the method of forming the via wiring. 17 (b) and 17 (d) are enlarged views of the vicinity of the via hole or via wiring of FIGS. 17 (a) and 17 (c), and FIGS. 17 (a) and 17 (b) and FIG. It is reversed.

  As shown in FIG. 17A, the dielectric layer 11 and the support sheet 42 are disposed on the suction table 40 with the buffer plate 43 interposed therebetween. The buffer plate 43 is, for example, a resin plate such as an acrylic plate. Laser light 44 is irradiated to the dielectric layer 11 through the support sheet 42. An opening 32a, a via hole 32 and an opening 32b are formed in the support sheet 42, the dielectric layer 11 and the buffer plate 43, respectively. The laser beam 44 passes through the support sheet 42 and is irradiated to the dielectric layer 11. Therefore, the via hole 32 can be miniaturized even if the intensity of the laser beam 44 is made larger than that of FIG. The buffer plate 43 protects the suction table 40 from the laser light 44. As shown in FIG. 17B, the sectional shape of the via hole 32 is substantially rectangular. That is, the side surface of the via hole 32 is substantially straight.

  As shown in FIG. 17C, the dielectric layer 11 and the support sheet 42 are peeled off from the buffer plate 43. The dielectric layer 11 and the support sheet 42 are disposed on the suction table 40 with the protective layer 45 interposed therebetween. The protective layer 45 is, for example, clean paper. The protective layer 45 protects the surface of the dielectric layer 11 from the adsorption table 40. The screen 48 is placed on the support sheet 42. The screen 48 has an opening 47 matched to the arrangement of the via holes 32. The metal paste 34 is filled in the via hole 32 using the squeegee 46. As shown in FIG. 17D, the opening 32 a provided in the support sheet 42 is used as an opening for printing together with the opening 47. Thereby, the metal paste 34 is filled in the via hole 32.

  In the method of FIG. 17A to FIG. 17D, in FIG. 17A, the laser light 44 is irradiated to the dielectric layer 11 through the support sheet 42. As a result, as shown in FIG. 17B, it is possible to form the via holes 32 having fine and substantially straight side surfaces. Further, as shown in FIG. 17C, the opening 32a formed in the support sheet 42 is used as a part of the opening for printing. As a result, as shown in FIG. 17D, the lands 36 are not formed. Thereby, the alignment margin of the via hole 32 and the land 36 becomes unnecessary. Thus, the pattern can be miniaturized. As a result, when the dielectric layer 11 is stacked and the via holes 32 are stacked, the land 36 does not exist, and the straight via holes 32 can be formed.

  As mentioned above, although the embodiment of the present invention has been described in detail, the present invention is not limited to such a specific embodiment, and various modifications may be made within the scope of the subject matter of the present invention described in the claims. Changes are possible.

DESCRIPTION OF SYMBOLS 10 laminated body 11, 11a-11i dielectric material layer 12, 12a-12j conductor pattern 13, 13a, 13b via wiring 14, 14a, 14b coil 15, 15a electrode 20 terminal electrode 22 direction identification mark 24 LPF
26 HPF
28 BPF
64 spiral pattern

Claims (10)

A laminated body in which a plurality of dielectric layers provided with a conductor pattern between them are laminated;
A common terminal, a first terminal, a second terminal and a ground terminal provided on the lower surface of the laminate;
A first filter connected between the common terminal and the first terminal and including a first inductor and a first capacitor formed of the conductor pattern;
A second filter connected between the common terminal and the second terminal and including a second inductor and a second capacitor formed of the conductor pattern;
Of the common terminal, the first terminal, the second terminal, and the ground terminal, the non-conductive terminal not electrically connected to the other terminal through the conductor pattern is electrically connected to the ground terminal via the conductor pattern. A direction identification mark which is conducted through the conductor pattern and provided on the upper surface of the laminate;
Equipped with a multiplexer. A laminated body in which a plurality of dielectric layers provided with a conductor pattern between them are laminated;
A common terminal, a first terminal, a second terminal and a ground terminal provided on the lower surface of the laminate;
A first filter connected between the common terminal and the first terminal and including a first inductor and a first capacitor formed of the conductor pattern;
A second filter connected between the common terminal and the second terminal and including a second inductor and a second capacitor formed of the conductor pattern;
The common terminal, the first terminal, the second terminal, and the ground terminal are electrically connected to the nonconductive terminal which is not electrically connected to the other terminal through the conductive pattern, and the conductive pattern; A direction identification mark provided on the upper surface,
Equipped with
The direction identification mark is electrically connected to the non-conductive terminal through at least a portion extending in a planar direction of conductor patterns forming the first inductor, the first capacitor, the second inductor, and the second capacitor. Is a multiplexer . A laminated body in which a plurality of dielectric layers provided with a conductor pattern between them are laminated;
A common terminal, a first terminal, a second terminal and a ground terminal provided on the lower surface of the laminate;
A first filter connected between the common terminal and the first terminal and including a first inductor and a first capacitor formed of the conductor pattern;
A second filter connected between the common terminal and the second terminal and including a second inductor and a second capacitor formed of the conductor pattern;
The common terminal, the first terminal, the second terminal, and the ground terminal are electrically connected to the nonconductive terminal which is not electrically connected to the other terminal through the conductive pattern, and the conductive pattern; A direction identification mark provided on the upper surface,
Equipped with
At least one of the first inductor and the second inductor includes a spiral pattern not provided with a pattern at a central portion, and the direction identification mark is positioned at a central portion of the spiral pattern in plan view and does not overlap the spiral pattern Multiplexer . The multiplexer according to claim 3, wherein the spiral pattern is formed by a conductor pattern closest to the direction identification mark. A laminated body in which a plurality of dielectric layers provided with a conductor pattern between them are laminated;
A common terminal, a first terminal, a second terminal and a ground terminal provided on the lower surface of the laminate;
A first filter connected between the common terminal and the first terminal and including a first inductor and a first capacitor formed of the conductor pattern;
A second filter connected between the common terminal and the second terminal and including a second inductor and a second capacitor formed of the conductor pattern;
The common terminal, the first terminal, the second terminal, and the ground terminal are electrically connected to the nonconductive terminal which is not electrically connected to the other terminal through the conductive pattern, and the conductive pattern; A direction identification mark provided on the upper surface,
Equipped with
The conductor pattern provided on the most side of the direction identification mark overlaps the direction identification mark in plan view, and the multiplexer includes the electrode of the first capacitor or the second capacitor conducted to the direction identification mark. There are a plurality of non-conductive terminals,
The multiplexer according to any one of claims 1 to 5, wherein the direction identification mark is conducted to the terminal having the smallest area among the plurality of nonconductive terminals via the conductor pattern. The multiplexer according to any one of claims 1 to 6 , wherein the common terminal, the first terminal, the second terminal, and the ground terminal are provided only on the lower surface of the surfaces of the laminate. A third terminal provided on the lower surface of the laminate;
A third filter connected between the common terminal and the third terminal and including a third inductor and a third capacitor formed of the conductor pattern;
Equipped with
The direction identification mark is a non-conductive terminal not electrically connected to another terminal through the conductive pattern among the common terminal, the first terminal, the second terminal, the third terminal, and the ground terminal, and the conductive terminal. any one claim of the multiplexer of claims 1, which is conductive through the body pattern 7. The multiplexer according to any one of claims 1 to 8 , wherein the common terminal, the first terminal, the second terminal, the ground terminal, and the direction identification mark are plated layers. A plurality of dielectric layers provided with a conductor pattern between them, and connected between the common terminal and the first terminal, and including a first inductor and a first capacitor formed of the conductor pattern; The lower surface of a laminate including a filter and a second filter connected between the common terminal and the second terminal and including a second inductor and a second capacitor formed of the conductor pattern. A common terminal, the first terminal, the second terminal and a ground terminal;
Of the common terminal, the first terminal, the second terminal, and the ground terminal, the non-conductive terminal not electrically connected to the other terminal through the conductor pattern is electrically connected to the ground terminal via the conductor pattern. Conducted through the conductor pattern,
A direction identification mark provided on the top surface of the laminate;
A method of manufacturing a multiplexer, comprising the step of forming using a barrel plating method.

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