JP6549038B2 - エレクトロニクス適用のための複合組成物 - Google Patents
エレクトロニクス適用のための複合組成物 Download PDFInfo
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Adhesives Or Adhesive Processes (AREA)
Description
本出願は、参照によって本明細書に記載内容のすべてを援用する2012年11月30日に出願のU.S.Provisional Application Serial No.61/731,850への優先権、及び、それからの利益を主張する。
発明の背景
本開示は、チップ・パッケージのためのアンダーフィルに関し、より詳しくは集積回路チップ・パッケージのための接着性エレクトロニクス材料に関する。
nは、1から25の整数である。
mは、1から25の整数である。
Claims (15)
- 複数の電気的インターコネクトを含む電子部品と、
複数の電気的ボンディングパッドを含むサブストレートと、
電子部品とサブストレートとの間に配置される第一の組成物と、
を含むエレクトロニクス・アセンブリであって、
第一の組成物が、メチレン・マロネート・モノマー、メチレン・ベータ・ケトエステル・モノマー、及びメチレン・ベータ・ジケトン・モノマーから成る群から選択される1つ以上のモノマーから形成されるオリゴマー又はポリマーと、充填剤とを含み、
各々の電気的インターコネクトが、複数の電気的ボンディングパッドの1つに、それぞれ電気的に結合している、エレクトロニクス・アセンブリ。 - 第一の組成物が30ppm/℃以下の熱膨張率を有する、請求項1に記載のエレクトロニクス・アセンブリ。
- 第一の組成物が電子部品と等しい熱膨張率を有する、請求項1又は2に記載のエレクトロニクス・アセンブリ。
- 第一の組成物が電気的に絶縁されている、請求項1〜3のいずれか一項に記載のエレクトロニクス・アセンブリ。
- 第一の組成物が、電子部品への接着性アンダーフィルである、請求項1〜4のいずれか一項に記載のエレクトロニクス・アセンブリ。
- 充填剤が導電性充填剤及びCTE充填剤(coefficient of thermal expansion filler)の1つ以上を含む、請求項1〜5のいずれか一項に記載のエレクトロニクス・アセンブリ。
- CTE充填剤が、溶融シリカ、天然シリカ、合成シリカ、天然酸化アルミニウム、合成酸化アルミニウム、中空充填剤、三水酸化アルミニウム、水酸化アルミニウム、ホウ素、シリコン・カーバイド、マイカ、アルミニウム粉、酸化亜鉛、銀、グラファイト、窒化アルミニウム、ムライト、金、カーボン、カーボンナノチューブ、グラフェン、グラスファイバー及びカーボン・ファイバーの1つ以上を含む、請求項6に記載のエレクトロニクス・アセンブリ。
- 第一の組成物が、硬化前に室温で液体である、請求項1〜7のいずれか一項に記載のエレクトロニクス・アセンブリ。
- 第一の組成物が、熱、放射、又は化学的開始剤の1つ以上で硬化する、請求項1〜8のいずれか一項に記載のエレクトロニクス・アセンブリ。
- 電子部品及びサブストレートの少なくとも1つが、第一の組成物を硬化するよう設定された開始剤を含む、請求項1〜9のいずれか一項に記載のエレクトロニクス・アセンブリ。
- 第一の組成物が、周囲温度にて、硬化時間5分以下で硬化する、請求項1〜10のいずれか一項に記載のエレクトロニクス・アセンブリ。
- 電子部品が集積回路チップである、請求項1〜11のいずれか一項に記載のエレクトロニクス・アセンブリ。
- サブストレートがプリント基板を含む、請求項1〜12のいずれか一項に記載のエレクトロニクス・アセンブリ。
- 集積回路チップが第一のチップであり、第二の複数の電気的ボンディングパッドをさらに含み;
エレクトロニクス・アセンブリが、第二の複数の電気的インターコネクトを含む第二の集積回路チップと、第一のチップと第二の集積回路チップとの間に配置された第二の組成物とをさらに含み;
各々の第二の複数の電気的インターコネクトが、第二の複数の電気的ボンディングパッドの1つに、それぞれ電気的に結合している、請求項13に記載のエレクトロニクス・アセンブリ。 - 第一の組成物と第二の組成物が同一である、請求項14に記載のエレクトロニクス・アセンブリ。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261731850P | 2012-11-30 | 2012-11-30 | |
| US61/731,850 | 2012-11-30 | ||
| PCT/US2013/072203 WO2014085570A1 (en) | 2012-11-30 | 2013-11-27 | Composite compositions for electronics applications |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019116984A Division JP6854851B2 (ja) | 2012-11-30 | 2019-06-25 | エレクトロニクス適用のための複合組成物 |
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| Publication Number | Publication Date |
|---|---|
| JP2016506072A JP2016506072A (ja) | 2016-02-25 |
| JP6549038B2 true JP6549038B2 (ja) | 2019-07-24 |
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| JP2015545432A Expired - Fee Related JP6549038B2 (ja) | 2012-11-30 | 2013-11-27 | エレクトロニクス適用のための複合組成物 |
| JP2019116984A Active JP6854851B2 (ja) | 2012-11-30 | 2019-06-25 | エレクトロニクス適用のための複合組成物 |
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| Country | Link |
|---|---|
| US (2) | US10607910B2 (ja) |
| EP (2) | EP2926368B1 (ja) |
| JP (2) | JP6549038B2 (ja) |
| CN (1) | CN105164797B (ja) |
| WO (1) | WO2014085570A1 (ja) |
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| WO2013059479A2 (en) | 2011-10-19 | 2013-04-25 | Bioformix Inc. | Methylene beta-diketone monomers, methods for making methylene beta-diketone monomers, polymerizable compositions and products formed therefrom |
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| CA2869112A1 (en) | 2012-03-30 | 2013-10-03 | Bioformix Inc. | Composite and laminate articles and polymerizable systems for producing the same |
| EP2831185B1 (en) | 2012-03-30 | 2019-09-25 | Sirrus, Inc. | Ink and coating formulations and polymerizable systems for producing the same |
| US10047192B2 (en) | 2012-06-01 | 2018-08-14 | Sirrus, Inc. | Optical material and articles formed therefrom |
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2013
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- 2013-11-27 JP JP2015545432A patent/JP6549038B2/ja not_active Expired - Fee Related
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| JP2016506072A (ja) | 2016-02-25 |
| EP3712928A1 (en) | 2020-09-23 |
| WO2014085570A1 (en) | 2014-06-05 |
| CN105164797A (zh) | 2015-12-16 |
| JP2019195079A (ja) | 2019-11-07 |
| EP2926368B1 (en) | 2020-04-08 |
| US10607910B2 (en) | 2020-03-31 |
| US20150303122A1 (en) | 2015-10-22 |
| US20200219781A1 (en) | 2020-07-09 |
| EP2926368A4 (en) | 2016-08-03 |
| EP2926368A1 (en) | 2015-10-07 |
| JP6854851B2 (ja) | 2021-04-07 |
| CN105164797B (zh) | 2019-04-19 |
| US10978365B2 (en) | 2021-04-13 |
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