JP6364606B2 - Manufacturing method of chip resistor - Google Patents

Description

  The present invention is a chip resistor, in particular, a low resistance having a resistance value of 100 mΩ or less, so-called 0603 (external dimensions of about 0.6 mm in length, 0.3 mm in width, and about 0.23 mm in height) size, and 0402 (length of 0.0. The present invention relates to a manufacturing method of a chip resistor having a micro size of 4 mm, 0.2 mm in width, and 0.13 mm in height) size or smaller.

  A specific method for manufacturing such a chip resistor will be briefly described. After a resistance layer made of AgPd is formed on the upper surface of the sheet-like substrate, a resist is formed on the resistance layer. Thereafter, electrolytic plating is performed to form an electrode layer on the resistance layer not covered with the resist. The component of this electrode layer is Ag. Thereafter, the resist is peeled off, the resistance layer is trimmed to correct the resistance value, and then a protective film is formed so as to cover the exposed resistance layer. Subsequent steps are to divide the sheet-like substrate to form end face electrodes, and further to form a nickel plating layer and a tin plating layer by barrel plating (see Patent Document 1).

JP 2006-19323 A

  The smaller the resistance value of the resistor used for current measurement, the smaller the power consumed by the resistor. On the other hand, the smaller the resistance value, the smaller the voltage drop, and the higher the accuracy of measuring the voltage is required. Therefore, it is preferable to set the resistance value in consideration of the balance between the power consumption by the resistor and the voltage accuracy that can be measured. In particular, when measuring a large current, a chip resistor having a lower resistance value has been demanded in order to suppress the power consumption by the measuring resistor and reduce the heat generated by the resistor. .

  Thus, by making the resistance lower, the ratio of the resistance value of the electrode to the entire resistor is relatively increased. Therefore, it has been found that there is an event regarding the resistance value caused by the electrode, which was not a problem in the past.

  As such an event, there is a change in resistance value. In the prior art, by correcting the resistance value, the resistance value can be set within a desired range once. However, this is an event that the resistance value when it becomes the final chip resistor fluctuates from the resistance value after the resistance value correction, and the variation varies. This is because when the protective film is formed after the resistance value correction, the protective film is baked or when the protective film is placed in an environment of about 200 to 300 ° C. in order to promote solidification of the protective film. This is due to fluctuations. If the variation of the resistance value is constant, the final resistance value of the chip resistor can be set to a desired range by correcting the resistance value in anticipation of the variation. However, if there is variation, such a method cannot be adopted, the final resistance value does not fall within the desired range, and it is handled as a defective product by the inspection process after manufacturing the chip resistor. This will decrease the yield. Therefore, the yield can be improved by forming a resistance layer made of AgPd on the upper surface of the sheet-like substrate and then performing a heat treatment before correcting the resistance value. At this time, a resist is formed on the resistance layer, and then electrolytic plating is performed to form an electrode layer. However, when electrolytic plating is performed also on the primary divided portion, there is a problem that burrs are generated when dicing is performed, unevenness is generated on the upper surface of the resistor, and the mounting efficiency is lowered.

  The present invention solves the above-described conventional problems, and an object of the present invention is to provide a method for manufacturing a resistor that can improve mounting efficiency.

  In order to achieve the above object, the present invention has the following means.

The invention according to claim 1 is a chip resistor manufacturing method for dividing a sheet substrate to obtain a plurality of chip resistors, wherein the sheet substrate includes a plurality of primary division portions and the plurality of primary divisions. Divided into a plurality of secondary division parts intersecting the part, forming a resistance layer by printing a resistor paste on the sheet substrate, and on the resistance layer, the plurality of primary Forming a first protective layer between adjacent primary divided portions in the divided portion, and forming a resist layer so as to straddle the plurality of primary divided portions in a portion not in contact with the first protective layer; A step of forming an electrode layer by plating on a portion of the resistance layer not covered with the first protective layer and the resist layer; and the sheet substrate with the plurality of primary division portions and the plurality of secondary division portions. And dividing the first protective layer Between the resist layer was composed of the same material as glass, and so as to form by firing simultaneously, the the upper surface of the resist layer, an end portion of the resist layer and the primary division unit, This is a method for manufacturing a chip resistor in which another resist layer made of an insulating material mainly composed of resin or glass is formed .

  According to the first aspect of the present invention, since the generation of burrs can be suppressed, the upper surface of the resistor can be smoothed, thereby improving the mounting efficiency and further improving the productivity. Has a working effect.

  As described above, in the method of manufacturing a chip resistor according to the present invention, an electrode layer is formed by electrolytic plating after forming a resist layer containing glass as a main component in the primary divided portion. Since the resist layer is diced instead of the layer, the generation of burrs can be suppressed, so that the upper surface of the resistor can be smoothed. As a result, the mounting efficiency can be improved. Since the protective layer and the resist layer are made of the same material and are formed at the same time, the productivity can be improved.

Front sectional drawing of the manufacturing process of the chip resistor in one embodiment of the present invention Front sectional drawing of the manufacturing process of the chip resistor in one embodiment of the present invention Front sectional drawing of the manufacturing process of the chip resistor in one embodiment of the present invention The top view of the manufacturing process of the chip resistor in one embodiment of the present invention The top view of the manufacturing process of the chip resistor in one embodiment of the present invention The top view of the manufacturing process of the chip resistor in one embodiment of the present invention The top view of the manufacturing process of the chip resistor in one embodiment of the present invention The top view of the manufacturing process of the chip resistor in one embodiment of the present invention

  1 to 3 are front sectional views of a chip resistor manufacturing process according to an embodiment of the present invention, and FIGS. 4 to 8 are plan views of the chip resistor manufacturing process according to an embodiment of the present invention. is there.

  1 (a), FIG. 1 (b), FIG. 1 (c), FIG. 2 (a), FIG. 2 (b), FIG. 2 (c), and FIG. FIG. 9 is a front sectional view of FIG. 5 (a), FIG. 5 (b), FIG. 5 (c), FIG. 6 (a), FIG. 6 (b), FIG. 6 (c), and FIG. In addition, each drawing is described so that it can be easily understood, and the ratio of the length and width of the drawing and the ratio of the thickness of each component in the drawing are different from the actual ones.

  The chip resistor manufacturing method of the present invention is a method of manufacturing a chip resistor 30 that divides a sheet substrate 1 to obtain a plurality of chip resistors 30, wherein the sheet substrate 1 is a linear and parallel primary dividing unit. 1a and a plurality of secondary division parts 1b that are straight lines intersecting at right angles to the primary division part 1a, and the resistance across the primary division part 1a on the sheet substrate 1 A step of forming a layer 2, a first protective layer 3 on the resistive layer 2, and between the primary divided portions 1 a adjacent to each other in the plurality of primary divided portions 1 a, on the resistive layer 2, A step of forming a resist layer 4 across the plurality of primary division parts 1a; and an electrode layer 5 by electrolytic plating on the resistance layer 2 using the first protective layer 3 and the resist layer 4 as a plating resist. And a sheet base on which the electrode layer 5 is formed A step of heat-treating 1, a step of correcting a resistance value after the step of the heat treatment, and a sheet substrate 1 after the correction of the resistance value, the plurality of primary division portions 1 a and the plurality of secondary division portions And 1b.

  In addition to the above manufacturing method, after the step of correcting the resistance value, a step of forming a second protective layer 7 covering the first protective layer 3, and the sheet substrate 1 with the primary division unit A step of obtaining the strip substrate 20 by dividing by 1a, a mask (not shown) is disposed on the second protective layer 7 formed on the strip substrate 20, and the end surface of the strip substrate 20 Forming the end face electrodes 9 and 10 over the electrode layer 5, and after the step of forming the end face electrodes 9 and 10, performing the step of dividing by the secondary dividing portion 1 b, Later, a step of forming a copper plating layer 11, a nickel plating layer 12, and a tin plating layer 13 as a plating layer by electrolytic plating on the electrode layer 5 and the end face electrodes 9, 10 may be provided.

  A more detailed description of the manufacturing method of the chip resistor of the present invention will be described below.

  The sheet substrate 1 is an insulator, and a preferable example is an alumina substrate. As shown in FIG. 4, a plurality of primary division parts 1a that are straight lines parallel to each other and a plurality of secondary division parts 1b that are straight lines that intersect at right angles to the primary division parts 1a are defined on the sheet substrate 1. . The plurality of secondary division parts 1b are parallel to each other.

  The primary division unit 1a and the secondary division unit 1b are virtual lines that indicate division positions when the sheet substrate 1 is divided later. Moreover, the primary division part 1a and the secondary division part 1b are good also as a slit (not shown) formed in the position which the sheet | seat board | substrate 1 divides | segments. Note that the upper surface of the sheet substrate 1 refers to the surface on which the resistance layer 2 is formed in the sheet substrate 1 of FIG.

  FIG. 1A and FIG. 5A are enlarged views of a part of the sheet substrate 1 shown in FIG. Fig.1 (a) is front sectional drawing, The cut surface is parallel to the secondary division part 1b, and is in the center part of arbitrary adjacent secondary division parts 1b.

  One embodiment of the manufacturing method of the present invention uses such a sheet substrate 1 to manufacture as follows.

  First, as shown in FIG. 1B and FIG. 5B, the resistance layer 2 is formed on the sheet substrate 1. The resistance layer 2 is obtained by printing a PdAg paste and then firing it. In addition, the resistance value of the resistance layer 2 can be lowered by printing PdAg twice to form a thick layer. The resistance layer 2 is formed between the adjacent secondary division portions 1b and straddling the primary division portion 1a.

Next, as shown in FIGS. 1C and 5C, the first protective layer 3 and the resist layer 4 are simultaneously baked and formed on the resistance layer 2 . The first protective layer 3 is formed between the primary divided portions 1a. On the other hand, the resist layer 4 is formed so as to straddle the primary divided portion 1a. The 1st protective layer 3 and the resist layer 4 are obtained by baking after printing a glass paste. This firing temperature is performed at 620 ° C., although it depends on the glass material used for the first protective layer 3 and the resist layer 4. The first protective layer 3 and the resist layer 4 are separated and are not connected. As shown in FIG. 5C, the first protective layer 3 and the resist layer 4 are formed wider than the width of the resistance layer 2 and cover the width direction of the resistance layer 2. The width of the resistance layer 2 is a length in a direction parallel to the primary division portion 1a in the resistance layer 2. And this 1st protective layer 3 and the resist layer 4 also become a plating resist in the case of the electrolytic plating of the next process. Furthermore, you may form the 1st protective layer 3 and the resist layer 4 in strip shape ranging over the secondary division part 1b.

  Furthermore, another resist layer made of an insulating material mainly composed of resin or glass between the primary divided portion 1a and the end of the resist layer 4 on the resistance layer 2 side on the upper surface of the resist layer 4 May be formed. Thereby, since it can prevent that the electrode layer 5 is formed in the primary division part 1a, dicing can be performed reliably with the resist layer 4, and this can suppress generation | occurrence | production of a burr | flash more effectively. it can.

  Next, as shown in FIGS. 2A and 6A, the electrode layer 5 is formed by electrolytic plating. Electrolytic plating can be performed by immersing the sheet substrate 1 shown in FIGS. 1C and 5C in a plating solution and causing electricity to flow through the resistance layer 2. Therefore, the electrode layer 5 is formed on the exposed portion of the resistance layer 2. In FIG. 2A, the electrode layer 5 is also formed on part of the upper surface of the first protective layer 3 and the resist layer 4. The reason for this is that, by electrolytic plating, a film by plating is initially formed on the resistance layer 2, but this film by plating is also a conductor, and the electricity that has flowed through the resistance layer 2 flows. A film is formed by plating. In this way, by repeatedly forming a film by plating on the film by plating, the first protective layer 3 and the resist layer 4 are also formed on part of the top surface. A part of the protective layer 3 and the resist layer 4 is not a conductor. These are insulators. The composition of the electrode layer 5 is Ag. Since Ag is excellent in conductivity, it is preferable to use it for an electrode of a low-resistance chip resistor.

  Next, the sheet substrate 1 is subjected to heat treatment. The heat treatment is performed at the same temperature as the firing temperature of the first protective layer 3 and the resist layer 4. The reason is to melt the first protective layer 3 and the resist layer 4. The first protective layer 3 and the resist layer 4 also need to have a temperature at which the viscosity is remarkably lowered and does not flow out like a liquid. For these reasons, the heat treatment temperature is the same as the firing temperature of the first protective layer 3 and the resist layer 4. Since the diffusion between the resistance layer 2 and the electrode layer 5 requires a temperature of 500 ° C. or more, the melting point of the glass used for the first protective layer 3 and the resist layer 4 is the resistance layer 2 and the electrode layer 5. It is necessary that the temperature be higher than the temperature required for diffusion of the.

  Next, as shown in FIGS. 2B and 6B, the resistance value of the resistance layer 2 is corrected. In the correction of the resistance value, a part of the resistance layer 2 together with the first protective layer 3 is lost by the energy by irradiating the laser beam. The trimming trace 6 indicates a portion that has disappeared due to such resistance value correction. Such resistance value correction is also called trimming, and is performed in order to make the resistance value a predetermined resistance value. This resistance value correction is performed while a resistance value measuring meter is brought into contact with each of the electrode layers 5 adjacent in the direction parallel to the secondary divided portion 1b and the resistance value is measured. Note that when the resistance value is corrected, pre-processing may be required to accurately measure the resistance value. For example, if a plurality of resistance layers 2 are electrically connected at the end of the sheet substrate 1, a so-called plating land can be formed in one place, which is convenient for electrolytic plating, but the resistance value correction When the resistance value is measured for this reason, the resistance layer 2 is affected by other resistance layers, and accurate measurement cannot be performed. Thus, the plating land is cut so that each resistance layer 2 is electrically independent. Processing.

  Next, as shown in FIG. 2C and FIG. 6C, a second protective layer 7 is formed so as to cover the first protective layer 3. The second protective layer 7 completely covers the first protective layer 3 and further covers a part of the electrode layer 5. This second protective layer 7 uses a protective material made of resin.

  Next, as shown in FIG. 7A, the upper surface electrode layer 8 is formed at the four corners of the rectangle formed by the primary divided portion 1a and the secondary divided portion 1b. Since the upper surface electrode layer 8 does not exist in the central portion between the adjacent secondary division portions 1b, it does not appear in FIGS. 3 (a) and 3 (b). The upper surface electrode layer 8 is formed by printing a mixed paste of Ag and resin, and then drying. The upper surface electrode layer 8 may be omitted. However, if the upper surface electrode layer 8 is formed, a step difference can be reduced when an end surface electrode 9 described later is formed. Since the upper surface electrode layer 8 contains a resin, even if it is cut by dancing, burrs are hardly generated.

  Next, the sheet substrate 1 is cut at the position of the primary division unit 1 a and divided into a plurality of strip substrates 20. An example of this division method is a method of cutting by dancing. FIG. 7B is an enlarged view of a part of the strip substrate 20 after being divided in this way.

  Next, as shown in FIGS. 3A and 8, end face electrodes 9 and end face electrodes 10 are formed by sputtering. The end surface electrodes 9 are formed on the end surface of the strip substrate 20 and the end portions of the upper surface. In this sputtering method, first, the end face electrode 9 is formed only at a necessary portion by performing sputtering from the upper surface side of the strip substrate 20 using a mask. The end face electrode 9 covers the sheet substrate 1, the resist layer 4, the electrode layer 5, and the re-upper surface electrode layer 8 positioned between the adjacent second protective layers 7 in the secondary divided portion 1 b direction. When the formation of the end face electrode 9 is completed, the end face electrode 10 is now formed by a sputtering method. This end face electrode 10 is formed by sputtering from the back side of the strip substrate 20 using a mask so as to form the end face electrode 10 only in a necessary portion. Both the end face electrode 9 and the end face electrode 10 are made of NiCr. Instead of forming the end face electrode 10 after forming the end face electrode 9, the order may be reversed. Moreover, it is also possible to simultaneously form the end face electrode 9 and the end face electrode 10 by performing sputtering simultaneously from both the upper face and the rear face of the strip substrate 20 using a mask.

  Next, the strip substrate 20 is cut by the secondary division unit 1 b and divided into a plurality of substrates 21. This dividing method is the same as the method of dividing the sheet substrate 1 into the strip substrates 20.

  Next, as shown in FIG. 3B, a plating layer is formed on the end face electrode 9 and the end face electrode 10. This plating layer includes a copper plating layer 11, a nickel plating layer 12, and a tin plating layer 13, all of which are formed by electrolytic plating. As this electrolytic plating method, a barrel plating method is preferable.

  The chip resistor by the above manufacturing method has the following effects.

  First, the resistance layer 2 and the resist layer 4 straddle the primary division part 1a, and the electrode layer 5 does not straddle the primary division part 1a. Since the electrode layer 5 is made of metal, burrs are generated when it is cut. However, since the electrode layer 5 does not straddle the primary division part 1a, even if it is divided by dicing at the primary division part 1a, the effect that burrs are hardly generated Have

  That is, since the electrode layer 5 is formed by electrolytic plating after forming the resist layer 4 in the primary division part 1a, glass (resist layer 4) is diced instead of metal (electrode layer 5) at the time of division. As a result, the generation of burrs can be suppressed, and the upper surface of the resistor can be smoothed. As a result, the mounting efficiency can be increased.

  Furthermore, since the resist layer 4 provided to suppress this burr is made of the same material as the first protective layer 3 and is formed at the same time, productivity can be improved.

  In the present embodiment, the resistance layer 2 is formed only on the upper surface side of the sheet substrate 1, but may be formed on both the upper surface side and the back surface side. That is, the resistance layer 2 may be formed on both sides. By doing so, the resistance value as the chip resistor can be halved. The back side at this time has the same configuration as the top side, and the manufacturing method can be performed in the same manner as the top side.

  The method for manufacturing a chip resistor according to the present invention can be applied as a chip resistor used in electrical equipment, electronic equipment, and the like.

DESCRIPTION OF SYMBOLS 1 Sheet substrate 1a Primary division | segmentation part 1b Secondary division | segmentation part 2 Resistance layer 3 1st protective layer 4 Resist layer 5 Electrode layer 6 Trimming trace 7 2nd protective layer 8 Resurface electrode layer 9 End surface electrode 10 End surface electrode 11 Copper Plating layer 12 Nickel plating layer 13 Tin plating layer 20 Strip substrate 21 Substrate 30 Chip resistor

Claims (1)

A chip resistor manufacturing method for dividing a sheet substrate to obtain a plurality of chip resistors, wherein the sheet substrate is divided into a plurality of primary divided portions and a plurality of secondary divided portions intersecting the plurality of primary divided portions. And is divided by
Printing a resistor paste on the sheet substrate to form a resistance layer;
A first protective layer is formed between the primary divided portions adjacent to each other in the plurality of primary divided portions on the resistance layer, and the plurality of primary divided portions are not in contact with the first protective layer. Forming a resist layer so as to straddle,
Forming an electrode layer by plating on a portion of the resistance layer that is not covered with the first protective layer and the resist layer;
Dividing the sheet substrate by the plurality of primary division units and the plurality of secondary division units,
The first protective layer and the resist layer are made of the same material mainly composed of glass, and fired at the same time,
On the upper surface of the resist layer, another resist layer made of an insulating material containing resin or glass as a main component was formed between the primary divided portion and an end of the resist layer.
Manufacturing method of chip resistor.

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