JP6348755B2 - Method for testing semiconductor transistors - Google Patents

Description

  The present invention relates to a test method for a semiconductor transistor, and more particularly to a test method for efficiently screening a load short-circuit withstand capability defect of a semiconductor integrated circuit handling a large power such as a power device in a short time.

  In general, a semiconductor integrated circuit that handles high power, such as a power device, requires a high degree of reliability because of the high risk when a failure occurs.

  In particular, the problem of destruction of the element when a load short circuit occurs when used in an AC circuit is particularly important, and a load short circuit occurs and a power supply voltage (eg, 300 V to 400 V) is directly applied. Then, an excessive current (e.g., 70 amperes to 80 amperes) flows in the transistor, and the device may be destroyed. The resistance of the transistor to such a load short circuit is called load short circuit tolerance.

  In order to check whether or not the short-circuit withstand capability of the transistor is good, usually, a part of the transistors manufactured in the same lot is inspected and a predetermined high voltage is applied while the load is short-circuited as shown in FIGS. However, this is done by measuring the time until the transistor breaks down.

  FIG. 8 shows a state of connection between a test apparatus and a transistor under test in a load short-circuit withstanding test of a general power device. FIG. 9 shows an example of a timing chart during the load short-circuit withstand test. As shown in FIGS. 8 and 9, each of the drain terminal 13, the source terminal 12, and the gate terminal 11 of the transistor under test 10 is connected to a test apparatus, and a high voltage of about 300 to 400 V is provided between the drain terminal 13 and the source terminal 12. With the voltage applied, the gate voltage is raised to about 10 V, and the transistor under test is turned on. As a result, a device-specific saturation current flows between the source and drain of the transistor under test 10. At this time, the saturation current rises to several tens of amperes, and the power may be several kW to several tens kW. If the drain voltage is 300 V and the drain current is 30 A, a high power state of about 9 kW is generated.

  In this way, by measuring the high voltage application time T until the transistor under test is destroyed, or by measuring whether or not the transistor under test was destroyed by applying a high voltage for a predetermined period, Judging whether there is no problem with the load short-circuit resistance of the transistor

JP 2009-69058 A

  However, in a power device that requires higher reliability, it is preferable to perform a load short-circuit withstand test for each transistor.

  As a method for inspecting the load short-circuit withstand capability of each transistor under test, a DC test (for example, VTH test) that does not directly create a load short-circuit condition and has high temperature characteristic accuracy before and after a test involving heat generation such as a saturation current test. Japanese Patent Laid-Open No. 2004-133867 proposes a method of screening for defects in the load short-circuit withstand capability based on the difference in measured values in the DC test. This is shown in the flowchart of FIG. 10 and the timing chart of FIG. In the VTH test, the drain current Id is measured while gradually increasing the gate terminal voltage (for example, in a step of 0.1 V), and the gate voltage at which the drain current becomes a specified value (for example, Id = 1 mA) is defined as VTH. Then, the amount of change in VTH in the first VTH measurement and the second VTH measurement is obtained before and after the saturation current measurement, and those having a large amount of change are determined as defective.

  The method of Patent Document 1 is based on the knowledge that the load short-circuit tolerance has a correlation with the temperature rise when a power load is applied to the transistor, and the temperature dependence of the threshold voltage is used to determine the amount of change in VTH. This is to estimate the heat generation amount (temperature rise) of the transistor. Here, when the load short-circuit characteristic is abnormal, the amount of heat generation increases.

  On the other hand, at the time of VTH measurement, the drain current is about several mA at most, but at the time of saturation current measurement, the drain current flows about several tens of A, and the current value has a gap of about four digits. For this reason, it is necessary to switch the tester unit (hardware) connected to the drain terminal, and it takes about several ms to several tens of ms for the switching.

  As a result, after performing a test with heat generation such as a saturation current test, the heat dissipation and cooling of the device occur until the next DC test such as VTH measurement, and the actual load short-circuit characteristics (temperature (Change) cannot be measured accurately.

  FIG. 12 shows an example of heat dissipation characteristics of the transistor after heat generation. In particular, semiconductors such as GaN and SiC used for power transistors are materials having high thermal conductivity and excellent heat dissipation compared to silicon. As shown in FIG. 12, even when the temperature rises to 145 ° C. in a test with heat generation such as a saturation current test, it can be seen that the temperature drops to about 98 ° C. after 1 millisecond. For this reason, the temperature rise during the saturation current test cannot be measured accurately. Furthermore, since the heat dissipation characteristics vary depending on individual transistors, it is extremely difficult to accurately measure the actual load short-circuit characteristics.

  In view of the above situation, the present invention provides a short-circuit withstand capability failure particularly in a semiconductor integrated circuit that handles high power, such as a power device. The object is to provide a test method for screening with high accuracy.

A test method according to the present invention for achieving the above object is a test method for detecting a reliability failure in a wafer test or a package test of a semiconductor transistor,
A measurement process for measuring the saturation current of the transistor under test under a plurality of measurement conditions;
A step of comparing the saturation current values of the transistors under test under the plurality of measurement conditions, respectively, and determining whether or not the transistors under test are defective based on a variation amount of the saturation current under the plurality of measurement conditions. It is characterized by.

The test method according to the present invention having the above-mentioned characteristics is preferably further provided.
The measuring step is
A first measurement step of measuring a saturation current of the transistor under test under a first measurement condition;
A second measurement step of measuring a saturation current of the transistor under test under a second measurement condition different from the first measurement condition;
In the determination step,
Comparing the saturation current value in the first measurement step with the saturation current value in the second measurement step, and determining that the transistor under test whose saturation current value difference or increase ratio exceeds a predetermined threshold is defective. it can.

The test method according to the present invention having the above-mentioned characteristics is preferably further provided.
In the measurement step, the saturation current of the transistor under test is measured under three or more measurement conditions,
In the determination step,
A transistor under test whose saturation current value difference or increase ratio exceeds a threshold in at least one of a set of measurement conditions selected by selecting any two of the three or more measurement conditions is determined to be defective. be able to.

  In this case, further, in the determination step, a difference in saturation current value or a change ratio between at least two different sets in a set of measurement conditions obtained by selecting any two of the three or more measurement conditions. The transistor under test whose rate exceeds the threshold can be determined to be defective.

The test method according to the present invention having the above-mentioned characteristics is preferably further provided.
The measuring step is
For each of the plurality of measurement conditions,
Fixing the drain voltage with reference to the source voltage by setting the drain voltage according to the measurement conditions;
Applying a pulse voltage for conducting the transistor under test with a gate voltage setting according to the measurement condition to a gate terminal of the transistor under test for a period according to the measurement condition. .

The test method according to the present invention having the above characteristics is also provided by
The measuring step is
For each of the plurality of measurement conditions,
Fixing the gate voltage at a gate voltage setting according to the measurement conditions to a voltage that causes the transistor under test to conduct with reference to the source voltage;
Applying a pulse voltage to the drain terminal of the transistor under test for a period according to the measurement condition with a drain voltage setting according to the measurement condition.

The test method according to the present invention having the above-mentioned characteristics is preferably further provided.
The plurality of measurement conditions may include two or more measurement conditions having the same gate voltage setting and different drain voltage settings.

The test method according to the present invention having the above-mentioned characteristics is preferably further provided.
The plurality of measurement conditions may include two or more measurement conditions in which the gate voltage setting is the same and the flow time of the saturation current is different.

The test method according to the present invention having the above-mentioned characteristics is preferably further provided.
A first measurement step of measuring a saturation current of the transistor under test under a first measurement condition for each of the transistors under test of the same wafer or the same wafer lot; a second measurement condition different from the first measurement condition And a second measuring step for measuring the saturation current of the transistor under test and a comparison step for obtaining a difference or increase ratio between the saturation current value in the first step and the saturation current value in the second step,
For the transistors under test on the same wafer or the same wafer lot, obtain a distribution of the difference or increase ratio of the saturation current value, and the difference of the saturation current values within a range beyond a predetermined deviation threshold with respect to the distribution Or it can be set as the structure provided with the process of determining the said to-be-tested transistor larger than an average as a defect.

  According to the present invention, the saturation current of the transistor under test is measured under at least two different measurement conditions, the respective saturation current values are compared, and the transistor under test is defective based on the amount of variation in the saturation current value. By determining whether or not, it is possible to accurately detect a load short-circuit withstand capability in a short time without causing destruction of the element or deterioration of element characteristics.

  The saturation current of the transistor should have the same saturation current value regardless of the bias condition if there is no influence of heat generation, but actually becomes a different saturation current value due to the influence of heat generation. The saturation current decreases as the measurement conditions increase in heat generation. When the load short-circuit withstand capability is poor, the heat generation is significantly increased and the saturation current is reduced. By obtaining the amount of variation in the saturation current value under two or more measurement conditions, the variation in saturation current value due to individual differences in transistors is offset, and only the change in saturation current value due to load short-circuit tolerance is extracted. Based on the fluctuation amount, it is possible to accurately determine the load short-circuit tolerance.

  In addition, since the individual variations of transistors generally depend on the wafer or lot, the distribution of saturation current values is calculated for each wafer or wafer lot that exhibits almost the same characteristics, and saturation under two or more measurement conditions is obtained. It is possible to avoid the deterioration of measurement accuracy due to the influence of individual differences by determining whether the fluctuation amount of the current value is out of the distribution.

The flowchart which shows an example of a structure of the test method of the reliability failure based on one Embodiment of this invention. Example of timing chart of waveform of voltage and drain current applied to each terminal of transistor under test in test method of one embodiment of the present invention Example of timing chart of waveform of voltage and drain current applied to each terminal of transistor under test in test method of one embodiment of the present invention Timing chart explaining the method of measuring the saturation current of the transistor under test Timing chart explaining the method of measuring the saturation current of the transistor under test Distribution diagram of saturation current values when transistors manufactured on the same wafer are measured under two measurement conditions with different applied drain voltages Distribution diagram of saturation current values when transistors manufactured on the same wafer are measured under two measurement conditions with different drain voltage application times Diagram showing the connection between the test equipment and the transistor under test Example of timing chart of waveform of voltage and drain current applied to each terminal of transistor under test in conventional load short-circuit withstand capability test A flow chart for explaining a test method described in Patent Document 1 capable of performing a load short-circuit withstand test for each transistor under test Timing chart showing waveforms of voltage and drain current applied to each terminal of a transistor under test for explaining the test method described in Patent Document 1 Diagram showing an example of heat dissipation characteristics of a transistor

<First Embodiment>
Hereinafter, the configuration of a reliability failure test method according to an embodiment of the present invention (hereinafter referred to as “the present invention method 1” as appropriate) will be described in detail with reference to the drawings. An example of a flowchart showing the configuration of the method 1 of the present invention is shown in FIG. FIG. 2 shows a timing chart of the waveforms of the voltage and drain current applied to each terminal of the transistor under test in Method 1 of the present invention.

  The method 1 of the present invention assumes a load short-circuit tolerance test of a power transistor made of a compound semiconductor such as GaN or SiC. However, the method 1 of the present invention is not limited to this.

  Incidentally, there are a linear region and a saturation region as characteristic regions of the transistor. The linear region is a drain voltage range in which the drain current increases in proportion to the drain voltage when the transistor is set to the on state. The saturation region is a drain voltage range in which the drain current does not increase even when the drain voltage is increased, and becomes a substantially constant value (actually decreases due to the effect of heat generation). In the present invention, the drain current value in the saturation region is measured twice or more under different measurement conditions to determine whether or not the product is defective.

  In the method 1 of the present invention, first, as in the conventional case, as shown in FIG. 8, each of the drain terminal 13, the source terminal 12, and the gate terminal 11 of the transistor under test 10 is connected to the test devices 30a to 30c for each terminal. Start the test.

  Thereafter, the saturation current is measured under the first measurement condition (step S101).

  As a measuring method of the saturation current, (1) a gate voltage at which the transistor under test is turned off is applied to the gate terminal, and the drain terminal voltage is set to a predetermined drain voltage setting (V1) for measuring the saturation current. (2) A method of fixing a drain voltage with a source voltage as a reference, then changing a gate voltage, and applying a pulse voltage for turning on the transistor under test to the gate terminal of the transistor under test (see FIG. 4); ) If the voltage of the drain terminal is the same as that of the source terminal and the voltage is applied between the source and drain, the gate voltage is fixed to the voltage at which the transistor under test is turned on, and then the drain voltage is changed. There is a method of applying a pulse voltage to a drain terminal with a predetermined drain voltage setting for measuring a saturation current (see FIG. 5). After applying a pulse of gate voltage or drain voltage for a predetermined period, the current immediately before completion of pulse application is measured to obtain a saturation current value. Note that the pulse application time means a cumulative application time when a plurality of pulses are intermittently applied.

  In this embodiment, as shown in FIG. 2, the latter method, that is, the gate voltage is first fixed to a voltage (10 V in this case) that makes the transistor under test conductive, and then the pulse voltage is applied to the drain terminal. . As a first measurement condition, the bias voltage is applied to the drain terminal with reference to the source terminal when the saturation current flows, and the voltage application time (time for flowing the saturation current) is T1 (for example, about 100 ns to 1 ms). Set conditions. However, as shown in FIG. 3 described later, it is also possible to apply a pulse voltage to the gate terminal after first applying a fixed drain voltage.

  After step S101, after waiting for a sufficient time for cooling the chip for about 1 ms to 10 ms, the saturation current is measured again under the second measurement condition (step S102). At this time, a bias condition in which the voltage applied to the drain terminal 13 is changed from V1 to V2 is set as the second measurement condition. The voltage application time is T1 which is the same as the first measurement condition. V2 may be higher than V1 (V2> V1) or lower than V1 (V2 <V1). As the drain voltage is higher, the amount of heat generation increases, and as a result, the amount of decrease in the saturation current value increases. In particular, in a chip with poor load short-circuit withstand capability, the decrease in the saturation current value becomes significant. Here, the measurement value of the saturation current under the first measurement condition is Id1, and the measurement value of the saturation current under the second measurement condition is Id2.

  While the saturation current flows, the temperature of the transistor under test rises due to heat generation, and the saturation current value decreases accordingly. In FIG. 2C, this is schematically shown as a change in saturation current that gradually decreases. When V2> V1, the second measurement condition generates a larger amount of heat per unit time, so the slope of the saturation current decrease is smaller (absolute value is larger). When the transistor under test has poor load short-circuit tolerance, the increase in the absolute value of this slope is remarkable.

  Thereafter, in step S103, a difference | Id1-Id2 | of the saturation current values in steps S101 and S102 is obtained, and in step S104, it is determined whether the difference in saturation current values exceeds a predetermined threshold value. The threshold value is appropriately set according to the first and second measurement conditions. If the difference between the saturation current values exceeds the threshold value, the chip is determined to be defective.

  By doing in this way, the presence or absence of load short circuit withstand capability defect can be accurately screened in a short time for each individual transistor without being accompanied by element destruction or element characteristic deterioration.

Second Embodiment
As another example, FIG. 3 shows another example of a timing chart of waveforms of voltage and drain current applied to each terminal of the transistor under test in the method of the present invention. In FIG. 3, after fixing the drain voltage to a predetermined drain voltage setting for saturation current measurement, the gate voltage is changed, and a pulse voltage for turning on the transistor under test is applied to the gate terminal of the transistor under test. ing. In the first and second measurement conditions, the drain voltage at the time of measurement is the same at V1, but the voltage application time (the time during which the saturation current flows) is T1 in the case of the first measurement condition, Case T2 is different. T2 may be longer than T1 (T2> T1) or shorter than T1 (T2 <T1). The longer the application time, the greater the amount of heat generated, resulting in a decrease in the saturation current value.

  While the saturation current flows, the temperature of the transistor under test rises due to heat generation, and the saturation current value decreases accordingly. In FIG. 3C, this is schematically shown as a change in saturation current that gradually decreases. Unlike FIG. 2, since the applied drain voltage is the same under the first and second measurement conditions, the slope of the saturation current decrease is the same under both measurement conditions, but the application time is longer due to the different application times. As the amount of decrease in saturation current increases. In particular, in a chip with poor load short-circuit withstand capability, a decrease in saturation current value after completion of voltage application becomes significant.

  Thereafter, a difference between the saturation current values is obtained, and it is determined whether the difference between the saturation current values exceeds a predetermined threshold (corresponding to steps S103 and S104 in FIG. 1). It is possible to determine that the chip that has been exceeded is defective.

<Third Embodiment>
In the above, the conditions for measuring the saturation current are two different conditions, but the saturation current can be measured under three conditions or more than three measurement conditions, and the failure of the transistor under test can be determined based on the amount of variation in the saturation current. . When the measurement condition is 3 or more, if the difference in saturation current value exceeds the threshold in one of the measurement condition groups selected from any two of the 3 or more measurement conditions, the device under test It can be determined that the transistor is defective. Determination accuracy is improved by performing defect determination using data measured under more measurement conditions.

  As an example, when the measurement condition is 3 or more, two sets of measurement conditions consisting of any two of the three or more measurement conditions are selected, and the difference between the saturation current values is obtained for each set, and the two sets It is possible to obtain the rate of change of the difference between the saturation current values (in other words, obtain the second derivative with respect to the saturation current measurement condition). And when the change rate of the difference of the saturation current value between at least two sets exceeds a threshold value, it can be determined as defective. By performing the defect determination based on the change rate, it is possible to screen for a load short circuit defect with high accuracy. For example, in FIG. 2, if the saturation current values under three different measurement conditions with the drain voltages V1 (= 10 V), V2 (= 20 V), and V3 (= 30 V) are Id1, Id2, and Id3, respectively, the saturation current Defect determination is possible by deriving Id1 + Id3-2 * Id2 as the amount of change in value.

  FIG. 6 shows a distribution of saturation current values when the saturation current is measured for each transistor manufactured on the same lot (or the same wafer) with the drain voltages V1 = 10V and V2 = 15V. The saturation current value tends to decrease in V2 having a large drain voltage than V1, but in the case of a load short-circuit failure, the current decrease is significant. In the case of FIG. 6, under the measurement condition with the drain voltage V1 = 10 V, the saturation current Id1 is distributed in the range of 27 to 29 A for both non-defective products and defective products, and good / bad determination cannot be made. On the other hand, under the measurement condition with the drain voltage V2 = 15 V, the saturation current Id2 of the non-defective chip is distributed in the range of 25 to 28 A, and it is possible to determine that the chip whose saturation current is outside this distribution is 23 A is defective. It was possible.

  However, as the drain voltage V2 is increased, the individual variation of the saturation current value between non-defective chips also increases. When individual variation between non-defective chips increases, the saturation current distribution range of non-defective chips and the saturation current distribution range of defective chips overlap, and the two cannot be separated. It may be difficult.

  Here, it can be seen from FIG. 6 that the distribution of the saturation current of the non-defective product is a wide distribution with a large variation in the oblique 45-degree direction (direction parallel to the straight line Id2 = Id1), but perpendicular to the direction. Variation (direction parallel to the straight line Id2 = −Id1) has a small variation and a narrow distribution. This means that by obtaining a distribution for the difference | Id1−Id2 | of the saturation current, a narrower distribution width of non-defective products can be obtained, and defect determination can be performed easily and accurately. Here, the accuracy of determination refers to the accuracy with which a correct product can be determined without performing a misjudgment of determining a non-defective product as a defective product or a defective product as a non-defective product.

  Therefore, rather than simply performing two screenings independently based on the distribution of saturation currents in the two measurement conditions, that is, the distribution for Id1 and the distribution for Id2, 1 based on the distribution for | Id1−Id2 | By performing the screening once, it is possible to accurately perform screening for defective load short-circuit tolerance.

  From FIG. 6, the threshold for determination in step S104 of FIG. 1 can be set from the distribution for | Id1-Id2 |. In the distribution of the saturation current difference | Id1-Id2 |, the boundary of the non-defective product distribution range is set at a position where the distribution range of the non-defective product and the distribution of the defective product can be separated, and the difference of the saturation current value across the boundary is set. What is necessary is just to determine that a transistor with large is defective. The position of the boundary can be set as a position larger by a predetermined deviation threshold than the average value of the entire distribution of the saturation current difference | Id1−Id2 |.

  FIG. 7 shows a case where the drain voltage is constant and the application time of the drain voltage is set to T1 = 300 μs and T2 = 500 μs according to two measurement conditions, for each of the transistors manufactured on the same lot (or the same wafer). It is distribution of the saturation current value when measuring saturation current. The saturation current value tends to decrease in T2 having a longer voltage application time than T1, but in the case of a load short circuit failure, the current decrease is significant. In the case of FIG. 7, under the measurement conditions where the application time T1 is 300 s, the saturation current Id1 is distributed in the range of 27 to 29 A for both non-defective chips and defective chips, and it is not possible to determine good or defective. On the other hand, under the measurement condition with the drain voltage T2 = 500 s, the saturation current Id2 of the non-defective chip is distributed in the range of 25 to 27A, and it is possible to determine that the chip with the saturation current 22A out of this distribution is defective. It was possible.

  As shown in FIG. 7, the distribution of the saturation current of the non-defective product is a wide distribution with a large variation in the oblique 45 degree direction (direction parallel to the straight line Id2 = Id1) as in FIG. In the direction perpendicular to the direction (direction parallel to the straight line Id2 = −Id1), it can be seen that the variation is small and the distribution is narrow. Therefore, by obtaining the distribution with respect to the difference | Id1−Id2 | of the saturation current, a narrower distribution width of non-defective products can be obtained, and the defect determination can be performed easily and accurately. Similar to FIG. 6, the distribution for | Id1−Id2 |, which is a combination of the two, rather than performing the screening twice independently based on the distribution of the saturation current in the two measurement conditions, that is, the distribution for Id1 and the distribution for Id2. By performing the screening once based on the above, it becomes possible to accurately screen for a load short circuit withstand capability failure.

  As described above, according to the method 1 of the present invention, it is possible to screen a load short-circuit withstand defect with high accuracy in a short time without causing destruction of elements or deterioration of element characteristics.

  In the method 1 of the present invention, the load short-circuit tolerance is measured by measuring the saturation current value under at least two measurement conditions with different calorific values, and screening is performed based on the amount of variation between the measured values. As described above, it is not necessary to perform a test involving several tens of A or more), and element destruction and element-specific deterioration do not occur. That is, it is a nondestructive test, and it is possible to inspect all transistors individually, not lot or wafer sampling. Further, it is not necessary to change the setting of the test apparatus, and the determination can be made accurately without being affected by the heat dissipation characteristics of the individual transistors.

  As a result, screening for defective load short-circuit tolerance, which is an important issue in the field of power devices, can be performed reliably, and shipping quality is improved. Moreover, since the determination accuracy is high, it is not determined that a non-defective product is defective, and the manufacturing cost is suppressed.

  In the above embodiment, the failure determination is performed based on the difference between the saturation current values between the two measurement conditions, but instead of the difference between the saturation current values, the increase ratio (the larger saturation current value is the smaller one). The defect determination may be performed based on the divided ratio.

Further, in the above embodiment, the case where only the drain voltage is varied and the case where only the drain voltage application time is varied are described as the measurement conditions of the saturation current, but the present invention is not limited to this. Absent. Both the drain voltage and its application time may be varied.

  The present invention can be used as a test method for a semiconductor device, and in particular, can be suitably used as a reliability test method for a semiconductor transistor having a high breakdown voltage specification such as a power device made of a compound semiconductor.

1: Test method according to an embodiment of the present invention (method of the present invention)
10: Transistor under test 11: Gate terminal 12: Source terminal 13: Drain terminal 30a-30c: Test apparatus

Claims (4)

A test method for detecting a reliability defect in a wafer test or a package test of a semiconductor transistor,
A measurement process for measuring the saturation current of the transistor under test under a plurality of measurement conditions;
Comparing the saturation current values of the transistors under test under the plurality of measurement conditions, respectively, and including a determination step of determining whether the transistor under test is defective based on a variation amount of the saturation current under the plurality of measurement conditions ,
The test method, wherein the plurality of measurement conditions include two or more measurement conditions with the same gate voltage setting and different saturation current flowing times . The measuring step is
A first measurement step of measuring a saturation current of the transistor under test under a first measurement condition;
A second measurement step of measuring a saturation current of the transistor under test under a second measurement condition different from the first measurement condition;
In the determination step,
Comparing the saturation current value in the first measurement step with the saturation current value in the second measurement step, and determining that the transistor under test whose saturation current value difference or increase ratio exceeds a predetermined threshold is defective The test method according to claim 1, wherein: In the measurement step, the saturation current of the transistor under test is measured under three or more measurement conditions,
In the determination step,
A transistor under test whose saturation current value difference or increase ratio exceeds a threshold in at least one of a set of measurement conditions selected by selecting any two of the three or more measurement conditions is determined to be defective. The test method according to claim 1 or 2, characterized in that: The test method according to claim 1, wherein the plurality of measurement conditions include two or more measurement conditions having the same gate voltage setting and different drain voltage settings.

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