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JP6292361B1 - Manufacturing method of optical semiconductor device - Google Patents

Manufacturing method of optical semiconductor device Download PDF

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JP6292361B1
JP6292361B1 JP2017552513A JP2017552513A JP6292361B1 JP 6292361 B1 JP6292361 B1 JP 6292361B1 JP 2017552513 A JP2017552513 A JP 2017552513A JP 2017552513 A JP2017552513 A JP 2017552513A JP 6292361 B1 JP6292361 B1 JP 6292361B1
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ridge
layer
semiconductor device
forming
optical semiconductor
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JPWO2018109982A1 (en
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山口 勉
勉 山口
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Mitsubishi Electric Corp
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Abstract

半導体基板(1)の上に、リッジ下部(6)と、リッジ下部(6)の上に配置されリッジ下部(6)よりも広い幅を持つリッジ上部(8)とを有するリッジ構造(9)を形成する。リッジ下部(6)とリッジ上部(8)の幅の差によりリッジ下部(6)がリッジ上部(8)に対して横方向に奥まったことによって生じるリッジ構造(9)の窪み箇所(11)を原子層堆積法により絶縁膜(10)で完全に埋め込むことにより、半導体基板(1)とリッジ構造(9)と絶縁膜(10)とで側面に段差の無い凸形状(19)を形成する。A ridge structure (9) having a ridge lower part (6) on a semiconductor substrate (1) and a ridge upper part (8) disposed on the ridge lower part (6) and having a width wider than that of the ridge lower part (6). Form. A depression (11) in the ridge structure (9) caused by the difference between the width of the ridge lower part (6) and the ridge upper part (8) is that the ridge lower part (6) is recessed in the lateral direction with respect to the ridge upper part (8). The semiconductor substrate (1), the ridge structure (9), and the insulating film (10) form a convex shape (19) having no step on the side surface by being completely filled with the insulating film (10) by atomic layer deposition.

Description

本発明は、リッジ構造の窪み箇所を絶縁膜で埋め込む光半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing an optical semiconductor device in which a recessed portion of a ridge structure is embedded with an insulating film.

リッジ構造を有する半導体レーザにおいて、抵抗低減のためにリッジ上部の面積を確保し、かつ高速応答実現のためにリッジ下部の幅を狭くする必要がある。このため、リッジ構造を逆メサリッジ構造、T字型構造又はY字型構造としている。また、高速応答実現のためのデバイス構造として安定なリッジ寸法を実現する方法が開示されている(例えば、特許文献1参照)。   In a semiconductor laser having a ridge structure, it is necessary to secure the area of the ridge upper part for reducing the resistance and to narrow the width of the lower part of the ridge for realizing a high-speed response. For this reason, the ridge structure is an inverted mesa ridge structure, a T-shaped structure, or a Y-shaped structure. Further, a method for realizing a stable ridge size as a device structure for realizing a high-speed response is disclosed (for example, see Patent Document 1).

日本特許第5454381号公報Japanese Patent No. 5454381

逆メサリッジ構造、T字型構造又はY字型構造には、リッジ下部がリッジ上部に対して横方向に奥まった窪み箇所が存在する。従来は絶縁膜の成膜にスパッタ法又はプラズマCVD法を用いていたため、絶縁膜のカバレッジが不十分であり、リッジ構造の窪み箇所を絶縁膜で完全に埋め込むことはできなかった。この結果、リッジ構造が、温度等の外部環境変化、経年変化、又は組立時に加わる機械的ストレスに弱いという問題があった。   In the inverted mesa ridge structure, the T-shaped structure, or the Y-shaped structure, there is a recessed portion in which the lower portion of the ridge is recessed in the lateral direction with respect to the upper portion of the ridge. Conventionally, since the sputtering method or the plasma CVD method has been used to form the insulating film, the insulating film has insufficient coverage, and the recessed portion of the ridge structure cannot be completely filled with the insulating film. As a result, there has been a problem that the ridge structure is vulnerable to external environmental changes such as temperature, aging, or mechanical stress applied during assembly.

本発明は、上述のような課題を解決するためになされたもので、その目的はリッジ構造の機械的強度を向上することができる光半導体装置の製造方法を得るものである。   The present invention has been made to solve the above-described problems, and an object thereof is to obtain a method for manufacturing an optical semiconductor device capable of improving the mechanical strength of a ridge structure.

本発明に係る光半導体装置の製造方法は、半導体基板の上に、リッジ下部と、前記リッジ下部の上に配置され前記リッジ下部よりも広い幅を持つリッジ上部とを有するリッジ構造を形成する工程と、前記リッジ下部と前記リッジ上部の幅の差により前記リッジ下部が前記リッジ上部に対して横方向に奥まったことによって生じる前記リッジ構造の窪み箇所を原子層堆積法により絶縁膜で完全に埋め込むことにより、前記リッジ構造の側面に設けた前記絶縁膜側面に段差の無い凸形状を前記半導体基板上に形成する工程とを備えることを特徴とする。
The method of manufacturing an optical semiconductor device according to the present invention includes a step of forming a ridge structure on a semiconductor substrate having a ridge lower portion and a ridge upper portion disposed on the ridge lower portion and having a width wider than the ridge lower portion. In addition, a recess portion of the ridge structure, which is caused by a difference in width between the lower portion of the ridge and the upper portion of the ridge, is recessed in the lateral direction with respect to the upper portion of the ridge, is completely filled with an insulating film by an atomic layer deposition method. the write Mukoto, characterized in that it comprises a step of forming a convex shape without a step on the semiconductor substrate on a side surface of the insulating film provided on a side surface of the ridge structure.

本発明では、リッジ下部がリッジ上部に対して横方向に奥まったリッジ構造の窪み箇所を原子層堆積法により絶縁膜で完全に埋め込む。これにより、リッジ構造の機械的強度を向上することができる。   In the present invention, the recessed portion of the ridge structure in which the lower portion of the ridge is recessed laterally with respect to the upper portion of the ridge is completely filled with the insulating film by the atomic layer deposition method. Thereby, the mechanical strength of the ridge structure can be improved.

本発明の実施の形態1に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 1 of this invention. 比較例に係る光半導体装置を示す断面図である。It is sectional drawing which shows the optical semiconductor device which concerns on a comparative example. 本発明の実施の形態2に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る光半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the optical semiconductor device which concerns on Embodiment 2 of this invention.

本発明の実施の形態に係る光半導体装置の製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A method for manufacturing an optical semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態1.
図1から図7は、本発明の実施の形態1に係る光半導体装置の製造方法を示す断面図である。まず、図1に示すように、半導体基板1の上に活性層2を形成する。活性層2の最表面層2aはInP層である。活性層2の上に、活性層2の最表面層2aとは材料が異なる犠牲層3を形成する。犠牲層3は、InPとエッチングの選択比があることが要求され、例えばInGaAsP層である。なお、InGaAsP層の上にキャップ層として薄いInP層を形成してもよい。犠牲層3の厚みは、後に形成するリッジ下部の高さに一致する。
Embodiment 1 FIG.
1 to 7 are sectional views showing a method for manufacturing an optical semiconductor device according to the first embodiment of the present invention. First, as shown in FIG. 1, an active layer 2 is formed on a semiconductor substrate 1. The outermost surface layer 2a of the active layer 2 is an InP layer. A sacrificial layer 3 made of a material different from that of the outermost surface layer 2 a of the active layer 2 is formed on the active layer 2. The sacrificial layer 3 is required to have a selection ratio between InP and etching, and is, for example, an InGaAsP layer. A thin InP layer may be formed on the InGaAsP layer as a cap layer. The thickness of the sacrificial layer 3 matches the height of the lower portion of the ridge that will be formed later.

次に、図2に示すように、犠牲層3の一部をウェットエッチング又はドライエッチングにより除去して開口4を形成する。次に、図3に示すように、犠牲層3とは材料が異なるInP層5を活性層2及び犠牲層3の上に形成して開口4の内部にリッジ下部6を形成する。InP層5の上にInGaAsコンタクト層7を形成する。なお、InGaAsコンタクト層7の上にキャップ層として薄いInP層を形成してもよい。   Next, as shown in FIG. 2, a part of the sacrificial layer 3 is removed by wet etching or dry etching to form an opening 4. Next, as shown in FIG. 3, an InP layer 5 made of a material different from that of the sacrificial layer 3 is formed on the active layer 2 and the sacrificial layer 3, and a lower ridge 6 is formed inside the opening 4. An InGaAs contact layer 7 is formed on the InP layer 5. A thin InP layer may be formed on the InGaAs contact layer 7 as a cap layer.

次に、図4に示すように、SiO等の絶縁膜ハードマスク等を用いて、InP層5及びInGaAsコンタクト層7を犠牲層3までドライエッチング又はウェットエッチングして、特性に必要とされる所望のリッジ幅にパターニングしてリッジ上部8を形成する。次に、図5に示すように、活性層2の最表面層2a及びInP層5に対して犠牲層3を選択的にウェットエッチングして除去する。これにより、半導体基板1の上に、リッジ下部6と、リッジ下部6の上に配置されリッジ下部6よりも広い幅を持つリッジ上部8とを有するリッジ構造9を形成する。リッジ下部6よりリッジ上部8の幅が広いため、リッジ下部6がリッジ上部8に対して横方向に奥まったリッジ構造9の窪み箇所11が形成され、リッジ構造9の側面に段差17が生じる。この段差により、活性層2の最表面層2aとリッジ上部8の底面16との間に空間18が生じる。空間18は半導体又は絶縁体などの固体が存在しない隙間である。このような空間18を含む段差17が側面に存在した状態ではリッジ構造9の機械的強度は低い。Next, as shown in FIG. 4, an insulating film hard mask such as SiO 2 or the like, by dry etching or wet etching the InP layer 5 and the InGaAs contact layer 7 to the sacrificial layer 3 is required to the characteristics The ridge upper part 8 is formed by patterning to a desired ridge width. Next, as shown in FIG. 5, the sacrificial layer 3 is selectively removed by wet etching with respect to the outermost surface layer 2 a of the active layer 2 and the InP layer 5. Thereby, a ridge structure 9 having a ridge lower part 6 and a ridge upper part 8 disposed on the ridge lower part 6 and having a width wider than that of the ridge lower part 6 is formed on the semiconductor substrate 1. Since the width of the ridge upper part 8 is wider than the ridge lower part 6, a recessed portion 11 of the ridge structure 9 is formed in which the ridge lower part 6 is recessed laterally with respect to the ridge upper part 8, and a step 17 is generated on the side surface of the ridge structure 9. Due to this step, a space 18 is formed between the outermost surface layer 2 a of the active layer 2 and the bottom surface 16 of the ridge top 8. The space 18 is a gap where no solid such as a semiconductor or an insulator exists. The mechanical strength of the ridge structure 9 is low when the step 17 including the space 18 exists on the side surface.

次に、図6に示すように、原子層堆積(Atomic Layer Deposition: ALD)法により絶縁膜10を全面に形成し、リッジ上部8とリッジ下部6の幅の差によりリッジ下部6がリッジ上部8に対して横方向に奥まったことによって生じるリッジ構造9の窪み箇所11を絶縁膜10で完全に埋め込む。最後に、図7に示すように、リッジ構造9の上面において絶縁膜10の一部をエッチング除去して電極12を形成する。   Next, as shown in FIG. 6, an insulating film 10 is formed on the entire surface by atomic layer deposition (ALD), and the ridge lower portion 6 is changed to the ridge upper portion 8 due to the difference in width between the ridge upper portion 8 and the ridge lower portion 6. The recessed portion 11 of the ridge structure 9 caused by the recess in the lateral direction is completely filled with the insulating film 10. Finally, as shown in FIG. 7, an electrode 12 is formed by etching away a part of the insulating film 10 on the upper surface of the ridge structure 9.

続いて、本実施の形態の効果を比較例と比較して説明する。図8は、比較例に係る光半導体装置を示す断面図である。図8(a)では、絶縁膜13の成膜にスパッタ法又はプラズマCVD法を用いるため、絶縁膜13のカバレッジが不十分であり、リッジ構造9の窪み箇所11を絶縁膜13で完全に埋め込むことはできない。この結果、リッジ構造9が温度等の外部環境変化、経年変化、又は組立時に加わる機械的ストレスに弱いという問題がある。これに対して、本実施の形態では、リッジ構造9の窪み箇所11を原子層堆積法により絶縁膜10で完全に埋め込む。これにより、リッジ構造9の機械的強度を向上することができる。ただし、図8(b)に示すように、単に原子層堆積法を使って絶縁膜13を形成しただけでリッジ構造9の窪み箇所11が完全に埋め込まれていない状態では、リッジ構造9の機械的強度を上げることはできない。本実施の形態では、単に原子層堆積法を使うというだけではなく、図6に示すように原子層堆積法を使うことによってリッジ構造9の窪み箇所11を完全に埋め込み、リッジ構造9の側面の段差17を無くし、活性層2の最表面層2aとリッジ上部8の底面16との間の空間18を無くして半導体基板1とリッジ構造9と絶縁膜13とで側面に段差のない凸形状19を形成することで、リッジ構造9の機械的強度を上げることが可能となる。また、リッジ下部6の高さが300nm以下、横幅が3μm以下の場合にリッジ構造9の窪み箇所11を絶縁膜10で完全に埋め込むことができ、高速応答性も良い。   Subsequently, the effect of the present embodiment will be described in comparison with a comparative example. FIG. 8 is a cross-sectional view showing an optical semiconductor device according to a comparative example. In FIG. 8A, since the sputtering method or the plasma CVD method is used for forming the insulating film 13, the coverage of the insulating film 13 is insufficient, and the recessed portion 11 of the ridge structure 9 is completely filled with the insulating film 13. It is not possible. As a result, there is a problem that the ridge structure 9 is vulnerable to external environmental changes such as temperature, aging, or mechanical stress applied during assembly. On the other hand, in this embodiment, the recessed portion 11 of the ridge structure 9 is completely filled with the insulating film 10 by atomic layer deposition. Thereby, the mechanical strength of the ridge structure 9 can be improved. However, as shown in FIG. 8B, when the insulating film 13 is simply formed by using the atomic layer deposition method and the recessed portion 11 of the ridge structure 9 is not completely buried, the machine of the ridge structure 9 Strength cannot be increased. In the present embodiment, not only the atomic layer deposition method is used, but also the depression 11 of the ridge structure 9 is completely buried by using the atomic layer deposition method as shown in FIG. The step 19 is eliminated, the space 18 between the outermost surface layer 2a of the active layer 2 and the bottom surface 16 of the ridge upper portion 8 is eliminated, and the semiconductor substrate 1, the ridge structure 9 and the insulating film 13 have a convex shape 19 with no step on the side surface. By forming the ridge, the mechanical strength of the ridge structure 9 can be increased. Further, when the height of the ridge lower portion 6 is 300 nm or less and the lateral width is 3 μm or less, the recessed portion 11 of the ridge structure 9 can be completely filled with the insulating film 10, and high-speed response is good.

実施の形態2.
図9から図16は、本発明の実施の形態2に係る光半導体装置の製造方法を示す断面図である。まず、図9に示すように、半導体基板1の上に活性層2を形成する。活性層2の最表面層2aはInP層である。活性層2の上にInP層14を形成する。
Embodiment 2. FIG.
9 to 16 are sectional views showing a method for manufacturing an optical semiconductor device according to the second embodiment of the present invention. First, as shown in FIG. 9, the active layer 2 is formed on the semiconductor substrate 1. The outermost surface layer 2a of the active layer 2 is an InP layer. An InP layer 14 is formed on the active layer 2.

次に、図10に示すように、InP層14をドライエッチングによりパターニングしてリッジ下部6を形成する。なお、活性層2の最表面層2aをInGaAsPとすることでウェットエッチングのみ又はドライエッチングとウェットエッチングの組み合わせでリッジ下部6を形成することもできる。   Next, as shown in FIG. 10, the InP layer 14 is patterned by dry etching to form the ridge lower portion 6. In addition, when the outermost surface layer 2a of the active layer 2 is made of InGaAsP, the lower ridge 6 can be formed only by wet etching or by a combination of dry etching and wet etching.

次に、図11に示すように、活性層2の最表面層2a及びInP層14とは材料が異なる犠牲層3を、リッジ下部6の周りにリッジ下部6の上面を覆わない高さまで形成する。犠牲層3は、InPとエッチングの選択比があることが要求され、例えばInGaAsP層である。   Next, as shown in FIG. 11, the sacrificial layer 3 made of a material different from that of the outermost surface layer 2 a and the InP layer 14 of the active layer 2 is formed around the ridge lower portion 6 to a height that does not cover the upper surface of the ridge lower portion 6. . The sacrificial layer 3 is required to have a selection ratio between InP and etching, and is, for example, an InGaAsP layer.

次に、図12に示すように、リッジ下部6及び犠牲層3の上に、犠牲層3とは材料が異なるInP層15を形成する。InP層15の上にInGaAsコンタクト層7を形成する。なお、InGaAsコンタクト層7の上にキャップ層として薄いInP層を形成してもよい。   Next, as shown in FIG. 12, an InP layer 15 made of a material different from that of the sacrificial layer 3 is formed on the ridge lower portion 6 and the sacrificial layer 3. An InGaAs contact layer 7 is formed on the InP layer 15. A thin InP layer may be formed on the InGaAs contact layer 7 as a cap layer.

次に、図13に示すように、SIO等の絶縁膜ハードマスク等を用いて、InP層15及びInGaAsコンタクト層7を犠牲層3までドライエッチング又はウェットエッチングして、特性に必要とされる所望のリッジ幅にパターニングしてリッジ上部8を形成する。Next, as shown in FIG. 13, the InP layer 15 and the InGaAs contact layer 7 are dry-etched or wet-etched up to the sacrificial layer 3 using an insulating film hard mask or the like such as SIO 2 and is required for the characteristics. The ridge upper part 8 is formed by patterning to a desired ridge width.

次に、図14に示すように、活性層2の最表面層2a及びInP層14,15に対して犠牲層3を選択的にウェットエッチングして除去する。次に、図15に示すように、原子層堆積法により絶縁膜10を全面に形成し、リッジ構造9の窪み箇所11を絶縁膜10で完全に埋め込む。最後に、図16に示すように、リッジ構造9の上面において絶縁膜10の一部をエッチング除去して電極12を形成する。   Next, as shown in FIG. 14, the sacrificial layer 3 is selectively removed by wet etching with respect to the outermost surface layer 2 a of the active layer 2 and the InP layers 14 and 15. Next, as shown in FIG. 15, the insulating film 10 is formed on the entire surface by atomic layer deposition, and the recessed portion 11 of the ridge structure 9 is completely filled with the insulating film 10. Finally, as shown in FIG. 16, a part of the insulating film 10 is removed by etching on the upper surface of the ridge structure 9 to form the electrode 12.

本実施の形態でも、実施の形態1と同様に、リッジ構造9の窪み箇所11を原子層堆積法により絶縁膜10で完全に埋め込むことにより、リッジ構造9の機械的強度を向上することができる。   Also in the present embodiment, as in the first embodiment, the mechanical strength of the ridge structure 9 can be improved by completely embedding the recessed portion 11 of the ridge structure 9 with the insulating film 10 by the atomic layer deposition method. .

なお、実施の形態1,2において、リッジ構造9の窪み箇所11が原子層堆積法により絶縁膜10で完全に埋め込められていれば、更にスパッタ法又はプラズマCVD法を用いて絶縁膜を形成してもよい。また、リッジ下部6及びリッジ上部8は垂直リッジ形状であり、リッジ構造9はT字型であるが、これに限らず、リッジ構造9は逆メサリッジ構造又はY字型構造でもよい。また、本実施の形態の光半導体装置は、例えばDFBレーザ、又は変調器レーザ等の光集積化デバイスであるが、これらに限らず本発明を適用できる。   In the first and second embodiments, if the recess 11 of the ridge structure 9 is completely filled with the insulating film 10 by the atomic layer deposition method, an insulating film is further formed using a sputtering method or a plasma CVD method. May be. The ridge lower portion 6 and the ridge upper portion 8 have a vertical ridge shape, and the ridge structure 9 is T-shaped. However, the ridge structure 9 is not limited to this, and may be a reverse mesa ridge structure or a Y-shaped structure. In addition, the optical semiconductor device of the present embodiment is an optical integrated device such as a DFB laser or a modulator laser, but the present invention is not limited thereto.

1 半導体基板、2 活性層、2a 最表面層、3 犠牲層、4 開口、5 InP層(半導体層)、6 リッジ下部、8 リッジ上部、9 リッジ構造、11 窪み箇所、14 InP層(第1の半導体層)、15 InP層(第2の半導体層)、16 リッジ上部の底面、17 段差、18 空間、19 凸形状 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 active layer, 2a outermost surface layer, 3 sacrificial layer, 4 opening, 5 InP layer (semiconductor layer), 6 ridge lower part, 8 ridge upper part, 9 ridge structure, 11 hollow part, 14 InP layer (1st Semiconductor layer), 15 InP layer (second semiconductor layer), 16 bottom surface of the ridge, 17 steps, 18 spaces, 19 convex shape

Claims (7)

半導体基板の上に、リッジ下部と、前記リッジ下部の上に配置され前記リッジ下部よりも広い幅を持つリッジ上部とを有するリッジ構造を形成する工程と、
前記リッジ下部と前記リッジ上部の幅の差により前記リッジ下部が前記リッジ上部に対して横方向に奥まったことによって生じる前記リッジ構造の窪み箇所を原子層堆積法により絶縁膜で完全に埋め込むことにより、前記リッジ構造の側面に設けた前記絶縁膜側面に段差の無い凸形状を前記半導体基板上に形成する工程とを備えることを特徴とする光半導体装置の製造方法。
Forming a ridge structure on a semiconductor substrate having a ridge lower portion and a ridge upper portion disposed on the ridge lower portion and having a width wider than the ridge lower portion;
By completely filling a recess portion of the ridge structure with an insulating film by an atomic layer deposition method, which is caused by a difference in width between the ridge lower portion and the ridge upper portion. the method of the previous SL optical semiconductor device, characterized in that it comprises a step of forming a convex shape without a step on the side surface of the insulating film provided on a side surface of the ridge structure on the semiconductor substrate.
前記半導体基板の上に活性層を形成する工程と、
前記活性層の上に、前記活性層の最表面層とは材料が異なる犠牲層を形成する工程と、
前記犠牲層の一部を除去して開口を形成する工程と、
前記犠牲層とは材料が異なる半導体層を前記活性層及び前記犠牲層の上に形成して前記開口の内部にリッジ下部を形成する工程と、
前記半導体層をパターニングして前記リッジ上部を形成する工程と、
前記リッジ上部を形成した後、前記絶縁膜を形成する前に、前記活性層の前記最表面層及び前記半導体層に対して前記犠牲層を選択的にエッチングして除去する工程とを更に備えることを特徴とする請求項1に記載の光半導体装置の製造方法。
Forming an active layer on the semiconductor substrate;
Forming a sacrificial layer having a material different from that of the outermost surface layer of the active layer on the active layer;
Removing a portion of the sacrificial layer to form an opening;
Forming a semiconductor layer made of a material different from that of the sacrificial layer on the active layer and the sacrificial layer to form a ridge lower part inside the opening;
Patterning the semiconductor layer to form the ridge top;
And a step of selectively etching and removing the sacrificial layer with respect to the outermost surface layer and the semiconductor layer of the active layer after forming the ridge top and before forming the insulating film. The method of manufacturing an optical semiconductor device according to claim 1.
前記半導体基板の上に活性層を形成する工程と、
前記活性層の上に第1の半導体層を形成する工程と、
前記第1の半導体層をパターニングして前記リッジ下部を形成する工程と、
前記活性層の最表面層及び前記第1の半導体層とは材料が異なる犠牲層を、前記リッジ下部の周りに前記リッジ下部の上面を覆わない高さまで形成する工程と、
前記リッジ下部及び前記犠牲層の上に、前記犠牲層とは材料が異なる第2の半導体層を形成する工程と、
前記第2の半導体層をパターニングして前記リッジ上部を形成する工程と、
前記リッジ上部を形成した後、前記絶縁膜を形成する前に、前記活性層の前記最表面層及び前記第1及び第2の半導体層に対して前記犠牲層を選択的にエッチングして除去する工程とを更に備えることを特徴とする請求項1に記載の光半導体装置の製造方法。
Forming an active layer on the semiconductor substrate;
Forming a first semiconductor layer on the active layer;
Patterning the first semiconductor layer to form the lower portion of the ridge;
Forming a sacrificial layer made of a material different from that of the outermost surface layer of the active layer and the first semiconductor layer to a height around the lower portion of the ridge so as not to cover the upper surface of the lower portion of the ridge;
Forming a second semiconductor layer made of a material different from that of the sacrificial layer on the ridge and on the sacrificial layer;
Patterning the second semiconductor layer to form the ridge top;
After forming the ridge top and before forming the insulating film, the sacrificial layer is selectively etched and removed from the outermost surface layer of the active layer and the first and second semiconductor layers. The method for manufacturing an optical semiconductor device according to claim 1, further comprising a step.
前記活性層の前記最表面層、前記リッジ下部及び前記リッジ上部の材料はInPであり、前記犠牲層の材料はInGaAsPであることを特徴とする請求項2又は3に記載の光半導体装置の製造方法。   4. The optical semiconductor device according to claim 2, wherein the material of the outermost surface layer of the active layer, the lower portion of the ridge and the upper portion of the ridge is InP, and the material of the sacrificial layer is InGaAsP. Method. 前記リッジ下部及び前記リッジ上部は垂直リッジ形状であり、
前記リッジ構造はT字型であることを特徴とする請求項1〜4の何れか1項に記載の光半導体装置の製造方法。
The ridge lower part and the ridge upper part have a vertical ridge shape,
The method of manufacturing an optical semiconductor device according to claim 1, wherein the ridge structure is T-shaped.
前記光半導体装置はDFBレーザであることを特徴とする請求項1〜5の何れか1項に記載の光半導体装置の製造方法。   The method of manufacturing an optical semiconductor device according to claim 1, wherein the optical semiconductor device is a DFB laser. 前記光半導体装置は光集積化デバイスであることを特徴とする請求項1〜5の何れか1項に記載の光半導体装置の製造方法。   The method of manufacturing an optical semiconductor device according to claim 1, wherein the optical semiconductor device is an optical integrated device.
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