JP6115564B2 - Data processing system, semiconductor integrated circuit and control method thereof - Google Patents

Description

  The present invention relates to a data processing system, a semiconductor integrated circuit, and a control method thereof.

  In a data processing system that performs data processing using a CPU (Central Processing Unit), specific data processing that takes too much time or consumes too much power when processed by the CPU is more efficient than the CPU. A method is widely used in which another circuit having an appropriate processing performance takes over. Hereinafter, out of data processing to be processed by the CPU, performing specific data processing on behalf of another circuit is referred to as offloading. A circuit that performs processing in place of the CPU is referred to as an offloader. Data processing performed by the offloader is referred to as offload processing. Moreover, what can perform various data processing efficiently among offloaders is called a general purpose offloader.

  FIG. 1 is a diagram showing a main configuration of a data processing system including a general-purpose offloader disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2006-338538) and Patent Document 2 (Japanese Patent Laid-Open No. 2007-034392). is there.

  The data processing system shown in FIG. 1 includes a CPU 10, a memory 20, a general-purpose offloader 30, and a peripheral block 90 connected via a system bus 70. In FIG. 1, circuits other than the CPU 10, the memory 20, and the general-purpose offloader 30 are collectively shown as a peripheral block 90. Specific examples of the peripheral block 90 include an input / output circuit.

  The CPU 10 reads data from the memory 20, performs data processing, and writes the processing result in the memory 20.

  The general-purpose offloader 30 performs specific data processing in place of the CPU 10 among data processing to be processed by the CPU 10. The data processing performed by the CPU 10 and the data processing performed by the general-purpose offloader 30 are defined in advance by a program or the like. When a request for data processing defined as being performed by the CPU 10 is input via an input / output circuit (not shown), the data processing is performed by the CPU 10 and the data defined as being performed by the general-purpose offloader 30 When a request for processing is input, the general-purpose offloader 30 performs data processing.

  FIG. 2 is a block diagram illustrating an example of the configuration of the general-purpose offloader 30.

  The general-purpose offloader 30 includes an input FIFO (First-In First-Out) circuit 31, a data processing accelerator 50, an output FIFO circuit 33, a local memory 34, and a controller 39.

  The input FIFO circuit 31 outputs the input data to the data processing accelerator 50 in the order of input.

  The data processing accelerator 50 is a versatile and highly efficient processing circuit, and includes an array processor, a reconfigurable circuit, and the like. The data processing accelerator 50 performs data processing using the data input from the input FIFO circuit 31 and outputs a processing result.

  The output FIFO circuit 33 continuously outputs the data processing result input from the data processing accelerator 50 independently of the input FIFO circuit 31.

  The local memory 34 is provided in order for the data processing accelerator 50 to perform data processing efficiently, and is accessed from the data processing accelerator 50 as needed. Although FIG. 2 shows an example in which there is one local memory 34, a plurality of local memories 34 may be provided.

  The controller 39 is a DMA (Direct Memory) that performs data transfer via the system bus 70 between the memory 20 and the input FIFO circuit 31 (not shown in FIG. 2) and between the memory 20 and the output FIFO circuit 33. Access) circuit, and controls data transfer.

  A typical example of data processing that can be processed with high efficiency by the data processing accelerator 50 is streaming processing. The streaming process is a process in which data input and data processing result output are performed simultaneously and continuously. Even when complicated processing is required, data is input continuously from the input FIFO circuit 31 to the data processing accelerator 50, and data processing results by the data processing accelerator 50 are output continuously from the output FIFO circuit 33. Can be realized.

JP 2006-338538 A JP 2007-034392 A

  In a data processing system including a general-purpose offloader, it is necessary to transfer a large amount of data between the memory 20 and the input FIFO circuit 31 and between the memory 20 and the output FIFO circuit 33 before and after data processing. . In order to perform the data transfer efficiently, it is necessary to provide a controller 39 including a DMA circuit.

  When a large amount of data is transferred, the data transfer overhead increases. Further, if the controller 39 including the DMA circuit is provided, the circuit scale overhead increases. When the overhead of data transfer and circuit scale increases, there arises a problem that processing time, circuit area, power consumption and the like increase. In the case of large-scale offload processing that requires a large amount of calculation, the increase in processing time, circuit area, power consumption, etc. due to overhead as described above is relatively small and does not cause much problem. However, in an MCU (Micro Control Unit) that performs relatively small scale data processing, an increase in processing time, circuit area, power consumption, and the like due to the overhead described above occupies a large proportion and cannot be ignored. .

  An object of the present invention relates to a data processing system, a semiconductor integrated circuit, and a control method thereof that can reduce data transfer and overhead of circuit scale.

In order to achieve the above object, the data processing system of the present invention provides:
A first data processing unit for performing data processing;
Of the data processing to be processed by the first data processing unit, a second data processing unit that performs specific data processing instead of the first data processing unit;
A memory comprising at least first and second memory blocks;
In the first operation mode, the first data processing unit accesses all the memory blocks included in the memory as one memory having a continuous address space, reads and writes data associated with the data processing, In the second operation mode, it is stopped.
The second data processing unit is stopped in the first operation mode, and in the second operation mode, the first memory block is a read-only memory, and the second data processing unit The memory block is a write-only memory, data is read from the first memory block, the specific data processing is performed, and the result of the specific data processing is written to the second memory block.

In order to achieve the above object, a semiconductor integrated circuit of the present invention includes:
A first processing unit that performs data processing; and a second processing unit that performs specific data processing on behalf of the first data processing unit among the data processings to be processed by the first data processing unit A memory comprising at least first and second memory blocks;
In the first operation mode, the first processing unit reads and writes data associated with the data processing as one memory having a continuous address space for all memory blocks included in the memory, and performs a second operation. In the mode, it will be stopped.
The second processing unit is in a stopped state in the first operation mode, and in the second operation mode, the first memory block is a read-only memory and the second memory The block is used as a write-only memory, data is read from the first memory block, the specific data processing is performed, and the result of the specific data processing is written to the second memory block.

In order to achieve the above object, a method for controlling a semiconductor integrated circuit according to the present invention includes:
A first processing unit that performs data processing; and a second processing unit that performs specific data processing on behalf of the first data processing unit among the data processings to be processed by the first data processing unit A method for controlling a semiconductor integrated circuit, comprising: a memory including at least first and second memory blocks,
In the first operation mode,
The first processing unit reads and writes data associated with the data processing as one memory having a continuous address space for all memory blocks provided in the memory,
The second processing unit is stopped,
In the second mode of operation,
The first processing unit is stopped,
The second processing unit sets the first memory block as a read-only memory, sets the second memory block as a write-only memory, reads data from the first memory block, and reads the specific memory block. Data processing is performed, and the result of the specific data processing is written into the second memory block.

  According to the present invention, data transfer and circuit scale overhead can be reduced.

It is a figure which shows the principal part structure of a related data processing system. It is a block diagram which shows an example of a structure of the general purpose offloader shown in FIG. It is a block diagram which shows the structure of the data processing system of the 1st Embodiment of this invention. It is a block diagram which shows the internal structure of the memory and coupler shown in FIG. It is a figure for demonstrating operation | movement of the data processing system shown in FIG. It is a block diagram which shows the internal structure of the memory and coupler of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of a related memory block. FIG. 8 is a block diagram illustrating a configuration of a read circuit illustrated in FIG. 7. FIG. 8 is a block diagram illustrating a configuration of a writing circuit illustrated in FIG. 7.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.

(First embodiment)
FIG. 3 is a block diagram showing the configuration of the data processing system according to the embodiment of the present invention. 3, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.

  The data processing system 1 illustrated in FIG. 3 includes a CPU 10, a memory 20, a coupler 40, a data processing accelerator 50, a system bus 70, and a peripheral block 90. The CPU 10 is an example of a first data processing unit, and the data processing accelerator 50 is an example of a second data processing unit. The memory 20, the coupler 40, and the data processing accelerator 50 constitute a general-purpose accelerator.

  The memory 20 includes a plurality of memory blocks that incorporate a memory cell array. FIG. 3 shows an example in which the memory 20 includes two memory blocks. A 1-port memory is used as the memory block.

  The combiner 40 combines a plurality of memory blocks provided in the memory 20 as one memory having a continuous address space.

  The data processing accelerator 50 accesses the memory 20 via the coupler 40 and performs specific data processing on behalf of the CPU 10 among data processing to be processed by the CPU 10. The data processing performed by the CPU 10 and the data processing performed by the data processing accelerator 50 are defined in advance by a program or the like. When a request for data processing defined as being performed by the CPU 10 is input via an input / output circuit (not shown), the data processing is performed by the CPU 10 and the data processing accelerator 50 is defined as performing. When a request for data processing is input, the data processing accelerator 50 performs data processing.

  The system bus 70 connects the CPU 10, the coupler 40, and the peripheral circuit 90.

  The data processing system 1 of the present embodiment has first and second operation modes.

  In the first operation mode, the CPU 10 accesses the memory 20 via the coupler 40 and performs data processing. As described above, the memory 20 includes a plurality of memory blocks, but the combiner 40 combines the plurality of memory blocks as one memory having a continuous address space. The CPU 10 accesses the memory 20 as one memory having a continuous address space, and reads / writes data associated with data processing. The data processing accelerator 50 is in a stopped state in the first operation mode.

  In the second operation mode, the data processing accelerator 50 accesses the memory 20 via the coupler 40 and performs specific data processing among the data processing to be processed by the CPU 10 instead of the CPU 10. Here, the data processing accelerator 50 performs data processing by accessing each memory block included in the memory 20 as an independent memory. The CPU 10 is in a stopped state in the second operation mode.

  In the data processing system 1 of the present embodiment, data processing is performed while switching between the first operation mode and the second operation mode.

  In the first operation mode, input data to be processed by the data processing accelerator 50 is held at an appropriate address in the memory 20. In the second operation mode, the input data held at an appropriate address is processed by the data processing accelerator 50, and the processing result is held at the appropriate address in the memory 20. In the next first operation mode, the CPU 10 can access the processing result of the data processing accelerator held at the appropriate address of the memory 20. Here, the input data and the processing result by the data processing accelerator 50 are held in different memory blocks.

  FIG. 4 is a block diagram showing the internal configuration of the memory 20 and the coupler 40.

  The memory 20 includes three memory blocks 21-1 to 21-3 each including a memory cell array. The coupler 40 includes multiplexers 41-1, 41-2, 41-3, 42-2, and 42-3, and an output selector 45.

  In FIG. 4, the case where the memory 20 includes three memory blocks will be described as an example, but the present invention is not limited to this. The memory 20 may include two or four or more memory blocks. In addition, when the memory 20 includes two memory blocks, the memory 20 includes a memory block 21-1 and a memory block 21-3.

  In FIG. 4, an address / control signal 71 is input to the multiplexers 41-1, 41-2, 41-3 and the output selector 45 via the system bus 70 (not shown). The write data signal 72 is input to the DI terminal of the memory block 21-1 and the multiplexers 42-2 and 42-3. Further, the mode signal 74 is input to the multiplexers 41-1, 41-2, 42-2, 41-3 and 42-3, the output selector 45, and the data processing accelerator 50. The address / control signal 71 includes an address signal indicating the address of the memory cell to be accessed and a control signal indicating the control input. The write data signal 72 is a signal indicating data to be held in the memory block. The mode signal 74 is a signal indicating the operation mode of the data processing system 1.

  The data processing accelerator 50 inputs the address / control signals 51-1, 51-2, 51-3 to the multiplexers 41-1, 41-2, 41-3, respectively. The data processing accelerator 50 inputs data signals 52-2 and 52-3 indicating the results of the data processing to the multiplexers 42-2 and 42-3, respectively. Further, when the data processing is completed, the data processing accelerator 50 inputs a data processing end signal 75 to the CPU 10 via the system bus 70.

  Each of the memory blocks 21-1 to 21-3 has an address / control terminal (AC terminal), a data read terminal (DO terminal), and a data write terminal (DI terminal). Each of the memory blocks 21-1 to 21-3 holds data input to the DI terminal according to an address / control signal input from the AC terminal. Further, the memory block 21-1 outputs the held data from the data DO terminal as the data signal 53-1 to the output selector 45 and the data processing accelerator 50 in accordance with the address / control signal input from the AC terminal. To do. Further, the memory block 21-2 outputs the held data from the DO terminal to the output selector 45 and the data processing accelerator 50 as the data signal 53-2 in accordance with the address / control signal input from the AC terminal. . Further, the memory block 21-3 outputs the held data from the DO terminal to the output selector 45 as the data signal 53-3 according to the address / control signal input from the AC terminal.

  The multiplexer 41-1 selects one of the address / control signal 71 input via the system bus 70 and the address / control signal 51-1 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to the AC terminal 21-1.

  The multiplexer 41-2 stores either the address / control signal 71 input via the system bus 70 or the address / control signal 51-2 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to the AC terminal 21-2.

  The multiplexer 42-2 outputs either the write data signal 72 input via the system bus 70 or the data signal 52-2 input from the data processing accelerator 50 according to the operation mode to the memory block 21-2. Input to the DI terminal.

  The multiplexer 41-3 stores either the address / control signal 71 input via the system bus 70 or the address / control signal 51-3 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to AC terminal 21-3.

  The multiplexer 42-3 outputs either the write data signal 72 input via the system bus 70 or the data signal 52-3 input from the data processing accelerator 50 according to the operation mode to the memory block 21-3. Input to the DI terminal.

  The output selector 45 outputs any one of the data signals 53-1, 53-2, and 53-3 as the read data signal 73 to the system bus 70 or outputs the read data signal 73 according to the operation mode. Stop.

  Next, the operation of the data processing system 1 will be described with reference to FIGS.

  In the following description, it is assumed that a request for data processing defined as being performed by the CPU 10 and a request for specific data processing defined as performed by the data processing accelerator 50 are input. . In the following description, when the logic value of the mode signal is the first logic value, the first operation mode is set. When the logic value of the mode signal is the second logic value, the second operation mode is set. Shall be.

  First, the operation in the first operation mode will be described.

  In the first operation mode, the CPU 10 enters an operation state, and inputs an address / control signal 71 and a write data signal 72 to the coupler 40 via the system bus 70 in accordance with data processing. On the other hand, the data processing accelerator 50 is stopped. Therefore, the value of the data processing end signal 75 is don't care.

  The multiplexer 41-1 inputs an address / control signal 71 input via the system bus 70 to the AC terminal of the memory block 21-1. The multiplexer 41-2 inputs an address / control signal 71 input via the system bus 70 to the AC terminal of the memory block 21-2. The multiplexer 41-3 inputs the address / control signal 71 input via the system bus 70 to the AC terminal of the memory block 21-3.

  As described above, the address / control signal 71 includes an address signal and a control signal. Examples of control signals include a data write enable signal WE, a data read enable signal RE, and an output enable signal OE that controls the input / output mode of the memory block. Although there are various memory block control methods such as a method in which the data write enable signal WE and the data read enable signal RE are combined into one signal in an inverted logic relationship, the present invention controls the memory block. It does not depend on the difference in method.

  In the first operation mode, for example, depending on the upper 2 bits of the address signal, any one of the memory blocks 21-1 to 21-3 (hereinafter referred to as memory block 21-k (k = 1, 2, 3)). The remaining memory blocks are in a non-selected state in which reading and writing are not performed. Further, a specific address in the memory block 21-k is designated by lower bits other than the upper two bits of the address signal.

  The multiplexer 42-2 inputs the write data signal 72 input via the system bus 70 to the DI terminal of the memory block 21-2. The multiplexer 42-3 inputs the write data signal 72 input via the system bus 70 to the DI terminal of the memory block 21-3.

  When a write enable signal is input as a control signal to the memory block 21-k and a write data signal 72 is input to the DI terminal, the write data is written to the address indicated by the lower bits other than the upper 2 bits of the address signal. The data indicated by the signal 72 is held.

  Further, when the read enable signal is input as the control signal, the memory block 21-k selects the data held at the address indicated by the lower bits other than the upper 2 bits of the address signal as the data signal 53-k. Input to the device 45.

  The output selector 45 outputs the input data signal 53 -k to the system bus 70 as a read data signal 73. The read data signal 73 is input to the CPU 10 via the system bus 70.

  As described above, in the first operation mode, the plurality of memory blocks included in the memory 20 are accessed from the system bus 70 and, as a result, the CPU 10 as one memory having a continuous address space.

  Next, the operation in the second operation mode will be described.

  In the second operation mode, the CPU 10 is stopped. On the other hand, the data processing accelerator 50 enters an operating state, and inputs the address / control signals 51-1, 51-2, 51-3 to the multiplexers 41-1, 41-2, 41-3, respectively, according to the data processing. The data signals 52-2 and 52-3 are input to the multiplexers 42-2 and 42-3, respectively.

  The multiplexer 41-1 inputs the address / control signal 51-1 input from the data processing accelerator 50 to the AC terminal of the memory block 21-1. The multiplexer 41-2 inputs the address / control signal 51-2 input from the data processing accelerator 50 to the AC terminal of the memory block 21-2. The multiplexer 41-3 inputs the address / control signal 51-3 input from the data processing accelerator 50 to the AC terminal of the memory block 21-3.

  The memory block 21-1 is read-only according to the input of the address / control signal 51-1, and the memory block 21-3 is write-only according to the input of the address / control signal 51-3.

  The memory block 21-1 outputs the data held at the address indicated by the address signal from the DO terminal to the data processing accelerator 50 as the data signal 53-1. The data processing accelerator 50 performs data processing using the data signal 53-1, and outputs a data signal 52-3 indicating the processing result to the multiplexer 42-3. The multiplexer 42-3 inputs the data signal 52-3 to the DI terminal of the memory block 21-3. The memory block 21-3 holds the data indicated by the data signal 52-3 input from the multiplexer 42-3 at the address indicated by the address signal input from the multiplexer 41-3.

  Here, the data processing accelerator 50 performs the streaming process with high efficiency by continuously reading the data from the memory block 21-1 and writing the data to the memory block 21-3 independently. Can do.

  In the second operation mode, the memory block 21-2 is addressed and controlled independently from other memory blocks by the address / control signal 51-2 from the data processing accelerator 50. That is, in the memory block 21-2, the data processing accelerator 50 appropriately reads data from the memory block 21-2 or writes data to the memory block 21-2. Functions as local memory. Depending on the purpose of use of the data processing accelerator 50, the work local memory may not be provided, or a plurality of independent work local memories may be provided.

  In the second operation mode, the output selector 45 does not output the data read signal 73. At this time, if the output of the output selector 45 needs to be high impedance due to the specifications of the system bus 70, an output selector conforming to such specifications is used. In this case, in the second operation mode, the output of the output selector 45 is in a high impedance state. In the first operation mode, the output selector 45 outputs one of the input data signals.

  When the data processing accelerator 50 enters the second operation mode, the logical value of the data processing end signal 75 is set to the second logical value, and when the data processing is completed, the logical value of the data processing end signal 75 is set to the first logical value. Transition. When the logical value of the data processing end signal 75 changes from the second logical value to the first logical value, the logical value of the mode signal 74 changes from the second logical value to the first logical value. The transition of the logical value of the mode signal 74 from the first logical value to the second logical value is, for example, to the memory block 21-1 by the CPU 10 of data necessary for the data processing accelerator 50 to perform data processing. This is done when writing is completed.

  As described above, in the data processing system 1 of the present embodiment, the CPU 10 and the data processing accelerator 50 share the memory 20. In the first operation mode, the CPU 10 accesses a plurality of memory blocks included in the memory 20 as one memory having a continuous address space to perform data processing, and the data processing accelerator 50 is stopped. On the other hand, in the second operation mode, the CPU 10 is stopped, and the data processing accelerator 50 accesses each memory block as each of the plurality of memory blocks provided in the memory 20 as an independent memory block, and performs data processing. .

  FIG. 5 is a diagram illustrating the state of the mode signal and the data processing end signal in the first and second operation modes, and the states of the CPU 10, the data processing accelerator 50, and the memory 20.

  In FIG. 5, since the logic value of the mode signal is the first logic value (Low) from time t1 to time t2, the operation mode is the first operation mode.

  As described above, in the first operation mode, the data processing accelerator 50 is stopped, and the value of the data processing end signal output from the data processing accelerator 50 is don't care. Further, the CPU 10 enters an operating state, and accesses a plurality of memory blocks provided in the memory 20 as one memory having a continuous address space.

  When a request for specific data processing defined as being performed by the data processing accelerator 50 is input, the logic value of the mode signal transitions from the first logic value to the second logic value. Here, after the CPU 10 holds the data necessary for the data processing performed by the data processing accelerator 50, the logic value of the mode signal changes from the first logic value to the second logic value. .

  Since the logic value of the mode signal is the second logic value (High) from time t2 to time t3, the operation mode transitions to the second operation mode.

  As described above, the CPU 10 is stopped in the second operation mode. In addition, the data processing accelerator 50 enters an operating state and changes the logical value of the data processing end signal from the first logical value (Low) to the second logical value (High). The data processing accelerator 50 accesses a plurality of memory blocks provided in the memory 20 as independent memory blocks.

  When the data processing ends, the data processing accelerator 50 changes the logical value of the data processing end signal from the first logical value to the second logical value. When the logic value of the data processing end signal transits from the first logic value to the second logic value, the logic value of the mode signal transits from the second logic value to the first logic value, and at time t3, the first logic value changes. Transition to operation mode. Thereafter, although not shown in FIG. 5, at the time t4, the second operation mode is set again, and the first operation mode and the second operation mode are repeated.

  Thus, in the data processing system 1 of the present embodiment, the CPU 10 and the data processing accelerator 50 share the memory 20. In the first operation mode, the CPU 10 accesses a plurality of memory blocks included in the memory 20 as one memory having a continuous address space, and the data processing accelerator 50 is in a stopped state. In the second operation mode, the CPU 10 is stopped, and the data processing accelerator 50 accesses each memory block by setting each of the plurality of memory blocks included in the memory 20 as independent memory blocks.

  This eliminates the need for a dedicated memory for the general-purpose offloader, so that the circuit area and power consumption for the dedicated memory can be reduced. In addition, since data transfer between the memory used by the CPU and the dedicated memory of the general-purpose offloader becomes unnecessary, an increase in processing time and power consumption associated with data transfer can be suppressed. In addition, since it is not necessary to provide a controller or the like having a DMA circuit, the circuit area can be reduced.

  Further, in the data processing system 1 of the present embodiment, the data processing accelerator 50 makes one memory block read-only among a plurality of memory blocks and another one memory block in the second operation mode. Write only.

  For this reason, it is possible to achieve a highly efficient streaming process in which data reading and output of processing results by data processing using the read data are performed independently and continuously. Usually, a high-cost FIFO circuit or a 2-port memory is used to perform streaming processing. However, in the present embodiment, the memory block can be a one-port memory by separating the input-only memory block and the output-only memory block. Therefore, an inexpensive memory block can be used, and cost reduction can be achieved. Furthermore, when the general-purpose offloader (data processing accelerator) accesses the memory, the circuit configuration can be simplified and the cost can be reduced as compared with the case where all the memory blocks are read / writeable memory blocks.

(Second Embodiment)
The data processing system according to the second embodiment of the present invention differs from the data processing system 1 according to the first embodiment in the configuration of the coupler 40 and the memory block. Therefore, below, it demonstrates focusing on these structures.

  FIG. 6 is a block diagram showing the configuration of the memory 20 and the coupler 40 of this embodiment. In FIG. 6, the same components as those in FIG.

  The memory 20 includes at least two memory blocks 21-10 and 21-30. In FIG. 6, the memory 20 will be described using an example including two memory blocks. However, the present invention is not limited to this, and the memory 20 may include three or more memory blocks as in the first embodiment. Good. Even when the memory 20 includes three or more memory blocks, memory blocks other than the memory blocks 21-10 and 21-30 are incorporated in the same manner as in the first embodiment. Therefore, in FIG. 6, the description of the memory blocks other than the memory blocks 21-10 and 21-30 is omitted.

  The coupler 40 includes multiplexers 41-1, 41-3, 42-0, 43, an output selector 45-2, an OR circuit 49, and buffers 220, 230.

  In FIG. 6, the address / control signal 71 is input to the multiplexers 41-1 and 41-3, the output selector 45-2, and the OR circuit 49 via the system bus 70 (not shown). The write data signal 72 is input to the multiplexer 42-0. The mode signal 74 is input to the multiplexers 41-1, 41-3, 42-0, the output selector 45-2, the OR circuit 49, and the data processing accelerator 50.

  The data processing accelerator 50 inputs the address / control signals 51-1 and 51-3 to the multiplexers 41-1 and 41-3, respectively. Further, the data processing accelerator 50 inputs the data signal 52-3 to the multiplexer 42-0.

  The multiplexer 41-1 selects one of the address / control signal 71 input via the system bus 70 and the address / control signal 51-1 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to AC terminal 21-10.

  The multiplexer 41-3 stores either the address / control signal 71 input via the system bus 70 or the address / control signal 51-3 input from the data processing accelerator 50 according to the operation mode as a memory block. Input to AC terminal 21-30.

  The multiplexer 42-0 outputs either the write data signal 72 input via the system bus 70 or the data signal 52-3 input from the data processing accelerator 50 to the buffer 230 according to the operation mode.

  The multiplexer 43 buffers either the output from the DO terminal of the memory block 21-10 or the output from the DO terminal of the memory block 21-30 according to the logical value of the signal input from the OR circuit 49. Output to.

  The OR circuit 49 calculates the logical sum of the address / control signal 71 and the mode signal 74 input via the system bus 70, and outputs the calculation result to the multiplexer 43.

  The buffer 230 buffers the output of the multiplexer 42-0 and inputs the data signal 52 to the DI terminals of the memory block 21-10 and the memory block 21-30.

  The buffer 220 buffers the output of the multiplexer 43 and inputs it to the output selector 45-2 and the data processing accelerator 50 as the data signal 53-1.

  The output selector 45-2 reads either the data signal 53-1 output from the buffer 220 or the data signal 53-2 input from the DO terminal of another memory block (not shown in FIG. 6). The result is output to the system bus 70 as 73.

  Here, the configuration of a general memory block will be described.

  FIG. 7 is a block diagram showing a configuration of a general memory block 21.

  The memory block 21 shown in FIG. 7 includes a memory cell array. The memory block 21 includes a read circuit 22 used for reading data from the memory cell array, and a write circuit 23 used for writing data to the memory cell array. Whether data is read or written is determined by a control signal included in the address / control signal.

  FIG. 8 is a block diagram showing a configuration of the read circuit 22 shown in FIG.

  The read circuit 22 illustrated in FIG. 8 includes a switch 221, a sense amplifier 222, and an output buffer 223.

  The switch 221 receives the data read enable signal RE and enters a conductive state or a cut-off state depending on the logical value of the data read enable signal RE. The data read enable signal RE becomes the first logical value in the read mode, and the switch 221 becomes conductive when the logical value of the data read enable signal RE is the first logical value.

  The sense amplifier 222 amplifies the signal from the memory cell input via the switch 221 and outputs the amplified signal to the output buffer 223.

  The output buffer 223 buffers the signal input from the sense amplifier 222 and outputs it to the DO terminal.

  FIG. 9 is a block diagram showing a configuration of the write circuit 23 shown in FIG.

  The write circuit 23 illustrated in FIG. 9 includes an input buffer 231, a write buffer 232, and a switch 233.

  The input buffer 231 buffers the data input signal input to the DI terminal and outputs it to the write buffer 232.

  The write buffer 232 buffers the data input from the input buffer 231 and outputs it to the switch 233.

  The switch 233 receives the data write enable signal WE and enters a conductive state or a cut-off state depending on the logical value of the data write enable signal WE. The data write enable signal WE has a first logical value in the write mode, and the switch 233 becomes conductive when the logical value of the data write enable signal WE is the first logical value. When the switch 233 becomes conductive, the signal output from the write buffer 232 is written into the memory cell array.

  Note that the switch 221 and the switch 233 are generally switches composed of pass transistors and transmission gates. The switches 221 and 233 are cut off when the logical values of the data read enable signal RE and the data write enable signal WE are the second logical value. Typically, the data read enable signal RE and the data write enable signal WE are in a logically inverted relationship.

  In the present embodiment, the memory blocks 21-10 and 21-30 do not have the sense amplifier 222 and the output buffer 223 shown in FIG. 8, and the input buffer 231 and the write buffer 232 shown in FIG. Instead, the buffer 230 shown in FIG. 6 functions as a write buffer and an input buffer of the memory block 21-10 and the memory block 21-30, and the buffer 220 senses the memory block 21-10 and the memory block 21-30. Functions as an amplifier and output buffer.

  The operation of the data processing system of this embodiment will be described with reference to FIG.

  Hereinafter, the first logical value of the mode signal 74 is set to 0, and the second logical value is set to 1.

  First, the operation when the logical value of the mode signal 74 is 0, that is, in the first operation mode will be described.

  In the first operation mode, the address / control signal 71 input from the system bus 70 is input to the AC terminal of the memory block 21-10 via the multiplexer 41-1, and the memory block via the multiplexer 41-3. It is input to the AC terminal 21-30. Further, the write data signal 72 input from the system bus 70 is input to the buffer 230 via the multiplexer 42-0. The buffer 230 inputs the data signal 52 to the DI terminals of the memory block 21-10 and the memory block 21-30 according to the input from the multiplexer 42-0. If there is a memory block in the write mode by the input of the address / control signal 71, the data signal 52 is held in the memory block.

  As described above, in the first operation mode, a plurality of memory blocks provided in the memory 20 are accessed as one memory having a continuous address space. Therefore, only one memory block is in the write mode at a certain time. In the present embodiment, the buffer 230 is shared as a writing circuit for the memory block 21-10 and the memory block 21-30. However, since only one memory block is in the writing mode at a certain time, the memory 230 The block 21-10 and the memory block 21-30 can share the buffer 230 as a writing circuit.

  The OR circuit 49 calculates a logical sum of the address / control signal 71 and the mode signal 74 and outputs the calculation result to the multiplexer 43. Here, the address / control signal 71 includes a 1-bit signal for distinguishing between the memory block 21-10 and the memory block 21-30. Since the logical value of the mode signal is 0, the OR circuit 49 outputs a signal having the same logical value as the 1-bit signal that distinguishes the memory block 21-10 and the memory block 21-30 included in the address / control signal 71. Output to the multiplexer 43.

  The multiplexer 43 receives the signal output from the DO terminal of one of the memory blocks 21-10 and 21-30 in the buffer 220 according to the logical value of the signal input from the OR circuit 49. Output. Here, the multiplexer 43 is a passive multiplexer composed of, for example, a pass transistor or a transmission gate, and does not have a buffering function.

  The buffer 220 amplifies a weak signal input from the memory cell array of the memory block 21-10 or the memory block 21-30 via the DO terminal and the multiplexer 43, and supplies the amplified signal to the output selector 45-2 as a data signal 53-1. Output.

  When there is an input of data 53-2 from a memory block other than the memory blocks 21-10 and 21-30, the output selector 45-2 receives data according to the logical value of the address / control signal 71. Either one of the signal 53-1 and the data signal 53-2 is output as a read signal 73.

  As described above, in the first operation mode, a plurality of memory blocks provided in the memory 20 are accessed as one memory having a continuous address space. Therefore, only one memory block is set to the read mode at a certain time. In the present embodiment, the buffer 220 is shared as a read circuit for the memory block 21-10 and the memory block 21-30. However, since only one memory block is in the read mode at a certain time, the memory 220 The block 21-10 and the memory block 21-30 can share the buffer 220 as a read circuit.

  Next, the operation when the logic value of the mode signal 74 is 1, that is, in the second operation mode will be described.

  In the second operation mode, the multiplexer 41-1 inputs the address / control signal 51-1 output from the data processing accelerator 50 to the AC terminal of the memory block 21-10. In response to the input of the address / control signal 51-1, the memory block 21-10 is read-only. The multiplexer 41-3 inputs the address / control signal 51-3 output from the data processing accelerator 50 to the AC terminal of the memory block 21-30. In response to the input of the address / control signal 51-3, the memory block 21-30 is dedicated to writing.

  The output from the DO terminal of the memory block 21-10 is input to the multiplexer 43, and the multiplexer 43 outputs the signal output from the DO terminal of the memory block 21-10 to the buffer 220.

  The buffer 220 amplifies the signal input from the multiplexer 43 and outputs the amplified signal to the data processing accelerator 50 as the data signal 53-1.

  The multiplexer 42-0 outputs the data signal 52-3 output from the data processing accelerator 50 to the buffer 230. The buffer 230 buffers the signal input from the multiplexer 42-0 and outputs the signal as the data signal 52 to the memory buffer 21-10 and the memory buffer 21-30. Here, in the second operation mode, the memory block 21-30 is a write-only memory block and is in the write mode. Therefore, the data signal 52 output from the buffer 230 is held in the memory block 21-30. .

  As described above, the memory block 21-10 and the memory block 21-30 share the buffer 230 as a write circuit and share the buffer 220 as a read circuit. In the second operation mode, since the memory block 21-10 is read-only and the memory block 21-30 is write-only, the memory block 21-10 and the memory block 21-30 share the buffer 220 as a read circuit. can do.

  As described above, according to the data processing system of the present embodiment, the memory block 21-10 and the memory block 21-30 are read from the memory cell array and the writing circuit for writing to the memory cell array incorporated therein. And a readout circuit for performing.

  Therefore, the circuit area can be reduced as compared with the case where a writing circuit and a reading circuit are provided in each of the plurality of memory blocks. In particular, in the case of a memory in a small chip such as an MCU, since the memory capacity is small, the area ratio indicated by the writing circuit and the reading circuit becomes relatively large. By sharing the circuit, the effect of reducing the circuit area is increased.

  In the data processing systems of the first and second embodiments described above, the components such as the CPU 10, the general-purpose offloader (data processing accelerator 50), the peripheral block 90, the system bus 70, and the like are corrected to one semiconductor integrated circuit. It is not essential. However, when the general-purpose offloader including the memory 20 and the data processing accelerator 50 is integrated in one semiconductor integrated circuit, the CPU 10 and the system bus 70 are also integrated in the same semiconductor integrated circuit. The invention can achieve a greater effect.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

This application claims the priority on the basis of the Japanese application 2012-55903 for which it applied on March 13, 2012, and takes in those the indications of all here.

Claims (10)

A first data processing unit for performing data processing;
Of the data processing to be processed by the first data processing unit, a second data processing unit that performs specific data processing instead of the first data processing unit;
A memory comprising at least first and second memory blocks;
In the first operation mode, the first data processing unit accesses all the memory blocks included in the memory as one memory having a continuous address space, reads and writes data associated with the data processing, In the second operation mode, it is stopped.
The second data processing unit is stopped in the first operation mode, and in the second operation mode, the first memory block is a read-only memory, and the second data processing unit the memory block as a write-only memory, performs the particular data processing by reading the data from said first memory block, writes the results of the particular data processing in the second memory block, and the read A data processing system which performs the writing simultaneously . The data processing system of claim 1, wherein
Transition from the first operation mode to the second operation mode at the start of the specific data processing, and transition from the second operation mode to the first operation mode at the end of the specific data processing A data processing system characterized by: The data processing system according to claim 2, wherein
The data processing system, wherein the first data processing unit writes data for performing the specific data processing into the first memory block in the first operation mode. The data processing system according to any one of claims 1 to 3,
The memory further comprises a third memory block;
In the second operation mode, the second data processing unit accesses the third memory block as a local memory that can be read / written independently of the other memory blocks. In the data processing system according to any one of claims 1 to 4,
The data processing system, wherein the memory block is a one-port memory. The data processing system according to any one of claims 1 to 5,
The first memory block and the second memory block share a read circuit for reading data from a built-in memory cell array and a write circuit for writing data to the memory cell array. Data processing system. The data processing system according to any one of claims 1 to 6,
A data processing system, wherein the memory and the second data processing unit are integrated in one semiconductor integrated circuit. The data processing system according to claim 7, wherein
The data processing system, wherein the first data processing unit is further integrated in the semiconductor integrated circuit. A first processing unit that performs data processing; and a second processing unit that performs specific data processing on behalf of the first data processing unit among the data processings to be processed by the first data processing unit A memory comprising at least first and second memory blocks;
In the first operation mode, the first processing unit reads and writes data associated with the data processing as one memory having a continuous address space for all memory blocks included in the memory, and performs a second operation. In the mode, it will be stopped.
The second processing unit is in a stopped state in the first operation mode, and in the second operation mode, the first memory block is a read-only memory and the second memory block a write-only memory, the first from the memory block reads the data subjected to the specific data processing, write the result of the particular data processing in the second memory block, the said read A semiconductor integrated circuit which performs writing simultaneously . A first processing unit that performs data processing; and a second processing unit that performs specific data processing on behalf of the first data processing unit among the data processings to be processed by the first data processing unit A method for controlling a semiconductor integrated circuit, comprising: a memory including at least first and second memory blocks,
In the first operation mode,
The first processing unit reads and writes data associated with the data processing as one memory having a continuous address space for all memory blocks provided in the memory,
The second processing unit is stopped,
In the second mode of operation,
The first processing unit is stopped,
The second processing unit sets the first memory block as a read-only memory, sets the second memory block as a write-only memory, reads data from the first memory block, and reads the specific memory block. It performs data processing, write the result of the particular data processing in the second memory block, a control method for a semiconductor integrated circuit and performs the writing and the reading at the same time.

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