JP5895610B2 - Magnetoresistive memory and method of manufacturing magnetoresistive memory - Google Patents

Description

  The present invention relates to a magnetoresistive memory and a method of manufacturing a magnetoresistive memory.

  In recent electronic devices, the importance of large-capacity nonvolatile memories that can be embedded at low cost with respect to silicon (Si) CMOS logic is increasing.

  Magnetoresistive random access memory (MRAM) is capable of unlimited rewriting of information in addition to non-volatility of information. For this reason, attention is paid to a novel nonvolatile memory that can replace not only a ROM memory such as a flash memory but also a RAM memory such as an SRAM or a DRAM.

  MRAM uses a magnetic tunnel junction (MTJ) in which a ferromagnetic metal electrode is arranged above and below a tunnel insulating film and the tunnel resistance changes depending on the relative magnetization direction of the ferromagnetic metal electrode. To realize. A ferromagnetic metal electrode whose magnetization direction is fixed is called a magnetization fixed layer, and a ferromagnetic metal electrode whose magnetization direction can be reversed is called a magnetization free layer. Until now, the direction of the magnetization free layer has been reversed using a magnetic field induced by passing a current through the wiring. However, in recent years, it has been found that magnetization reversal of the magnetization free layer is possible by spin-transfer torque (STT) (spin injection magnetization reversal). Thereby, the current required for rewriting can be greatly reduced, and the possibility of practical use of MRAM is further increased.

  In the following description, MgO used as a material for realizing the magnetic tunnel junction is magnesium oxide, Co is cobalt, Fe is iron, B is boron (boron), Ta is tantalum, Ru is ruthenium, Si represents silicon, O represents oxygen, and N represents nitrogen. Further, Mn represents manganese, Ir represents iridium, Pt represents platinum, Kr represents krypton, Xe represents xenon, Ar represents argon, Cu represents copper, Pd represents palladium, and Mg represents magnesium.

  An MTJ of CoFeB / MgO / CoFeB using MgO for the tunnel insulating film and CoFeB for the ferromagnetic metal electrodes above and below the tunnel insulating film is known. In this MTJ, by applying a template crystallization technique in which CoFeB is also crystallized while being affected by the (001) orientation of MgO, electrons with a high Δ1 band spin polarization are preferential. Pass MgO through the tunnel. Thereby, it is known that a high MR ratio can be obtained. The MR ratio is defined as MR ratio (%) = 100 × (Rap−Rp) / Rp when the resistance Rp is in the low resistance state and the resistance Rap is in the high resistance state.

  Furthermore, by utilizing the interface perpendicular magnetization induced at the interface between MgO and CoFeB, it became clear that the MTJ structure of CoFeB / MgO / CoFeB, which had been in-plane magnetization, can be used as the perpendicular magnetization type. It was. The perpendicular magnetization type MTJ has higher efficiency of spin injection magnetization reversal than the in-plane magnetization type MTJ, and when the MRAM is manufactured, the information can be rewritten with a lower rewriting current with the same thermal stability. It is expected.

  Based on these research results, research and development of an interface perpendicular magnetization type STT-MRAM using an interface perpendicular MTJ having a CoFeB / MgO / CoFeB structure has been actively conducted.

Japanese Patent No. 4082711 JP 2006-080116 A JP 2007-184063 A

S. Ikeda et al., Nature materials, Vo. 9, pp.721-724, September 2010 W. Kim et al., IEDM11-531 Tech. Dig. 24.1.1-24.1.4 2011 R. Shimabukuro et al., Physica E: Low-dimensional Systems and Nanostructures. 2010, 42 (4), pp.1014-1017 D.C.Worledge et al., Appl. Phys. Lett. 98, 022501 (2011) S. Ikeda et al., Appl. Phys. Lett. 93, 082508 (2008) Y. Maeda et al., Jpn. J. Appl. Phys. Vol. 47, No. 10, 2008, pp. 7879-7885

  The STT-MRAM is required to be formed at the same time as the CMOS forming the selection transistor and the peripheral circuit. In particular, in a CMOS mixed STT-MRAM in which a system LSI and a processor are mounted on the same chip, the MTJ is required to have heat resistance against a standard Cu wiring process of CMOS. At present, considering that the Cu Cu wiring process temperature is about 350 to 400 ° C. and the crystallization heat treatment temperature of CoFeB is about 350 ° C., it is desirable that the MTJ has a heat resistance of 350 ° C. or higher. .

  However, as a result of investigating the heat resistance of the interface perpendicular MTJ composed of MgO and CoFeB, it was found that it is difficult to keep the magnetization perpendicular at 350 ° C., especially for CoFeB formed on the top of MgO. Therefore, it is desired to improve the heat resistance of the CoFeB / MgO / CoFeB interface perpendicular MTJ to 350 ° C. or higher.

  According to a first aspect, a magnetoresistive memory having a plurality of perpendicular magnetization type magnetoresistive memory cells is provided. Each memory cell has a tunnel insulating film and two layers of ferromagnetic metal electrodes formed so as to face each other with the tunnel insulating film interposed therebetween, and utilizes the interface perpendicular magnetization between the tunnel insulating film and the ferromagnetic metal electrode To store the data. Each memory cell has a stack of an amorphous diffusion control layer, an interface cap layer, and a diffusion buffer layer at an interface opposite to the tunnel insulating film of at least one ferromagnetic metal electrode.

  According to a second aspect, a method for manufacturing a magnetoresistive memory having a plurality of perpendicular magnetization type magnetoresistive memory cells is provided. Each memory cell has a lower ferromagnetic metal electrode, a tunnel insulating film on the lower ferromagnetic metal electrode, and an upper ferromagnetic metal electrode on the tunnel insulating film. Each memory cell has a stack of an amorphous diffusion control layer, an interface cap layer, and a diffusion buffer layer provided on the upper ferromagnetic metal electrode, and utilizes the interface perpendicular magnetization between the tunnel insulating film and the ferromagnetic metal electrode. Store data. The interfacial cap layer is implanted by sputtering into the interface opposite to the tunnel insulating film of the upper ferromagnetic metal electrode, and the upper ferromagnetic metal electrode and the interface cap layer are mixed with each other before the crystallization heat treatment of the upper ferromagnetic electrode. An interface control layer is formed.

According to the first aspect described above, the heat resistance and performance of the interface perpendicular magnetization type STT-MRAM are improved.
Furthermore, according to said 2nd viewpoint, the manufacturing method of interface perpendicular magnetization type STT-MRAM which improved heat resistance and performance is implement | achieved.

FIG. 1 is a diagram illustrating a memory cell of an interface perpendicular magnetization type STT-MRAM according to an embodiment. FIG. 2 shows an example of a cross-sectional structure of two adjacent memory cells connected to the same bit line and source line and a transistor in a peripheral circuit portion in the layout of the memory cell shown in FIG. FIG. FIG. 3 is a diagram illustrating a configuration example of the MTJ provided in the memory cell of the interface perpendicular magnetization type STT-MRAM according to the present embodiment. FIG. 4 is a diagram illustrating a manufacturing process of the MTJ portion in the embodiment. FIG. 5 is a diagram illustrating a manufacturing process of the MTJ portion in the embodiment. FIG. 6 is a diagram illustrating a manufacturing process of the MTJ portion in the embodiment. FIG. 7 is a diagram illustrating an example of the structure of the MTJ manufactured in the manufacturing process described with reference to FIGS. 4 to 6 and the thickness range of each layer. FIG. 8 is a diagram showing a modification of the structure of the MTJ. FIG. 9 is a diagram showing a sample of MTJ manufactured for performing characteristic evaluation. FIG. 10 is a diagram showing a change in the amount of magnetization of CoFeB with respect to the thickness of the CoFeB layer when the thickness of the Ta layer is fixed to 1 nm and Kr and Ar are used as the deposition gas. FIG. 11 is a table showing the film thickness of the diffusion control layer in the form of a table when the Ta film thickness is fixed to 1 nm and the gas flow rate is changed for Kr and Ar. FIG. 12 shows the saturation magnetization (Ms) in the vertical direction and the residual magnetization in the vertical direction in the zero magnetic field (Ms) when the gas type and gas flow rate during the Ta layer deposition are changed under the same conditions as in the table of FIG. It is a figure which shows how ratio of Mr changes with respect to the amount of saturation magnetization (Ms). FIG. 13 is a diagram showing a change in the ratio Mr / Ms when Ar gas and 50 sccm are used as the Ta film forming gas and the thickness of the Ta layer is changed. FIG. 14 is a table showing changes in the thickness of the diffusion control layer depending on the Ta layer deposition conditions. FIG. 15 is a diagram showing the results of SIMS analysis of a sample of a 1 nm Ta layer and a 5 nm Ta layer formed under conditions of Ar gas and 50 sccm. FIG. 16 is a block diagram of a semiconductor device in which the interface perpendicular magnetization type STT-MRAM of the embodiment having the MTJ described so far is embedded in a CMOS circuit. FIG. 17 is a block diagram of the MRAM.

  FIG. 1 is a diagram showing a memory cell of an interface perpendicular magnetization type STT-MRAM according to an embodiment, in which (A) shows an electrical equivalent circuit of one memory cell, and (B) shows a plurality of memory cells. A memory cell array is shown.

  As shown in FIG. 1A, the memory cell 10 includes a transistor (nMOSFET) 11 and a variable resistance element 12 in which a resistance value is set. The variable resistance element 12 includes the interface perpendicular MTJ, and the magnetization direction of the magnetization free layer is set according to the stored data. One end of the variable resistance element 12 is connected to the bit line 14, and the other end of the variable resistance element 12 is connected to one controlled terminal (drain) of the transistor 11. The control terminal (gate) of the transistor 11 is connected to the word line 13, and the other controlled terminal (source) of the transistor 11 is connected to the source line 15.

  When data is written to the memory cell 10, the selection voltage (H) is applied to the word line 13 to turn on the transistor 11, and between the bit line 14 and the source line 15 according to the data (H or L) to be written. A voltage is applied so that currents having different polarities flow. Thereby, the magnetization direction of the magnetization free layer of MTJ is set according to the data to be written, and the variable resistance element 12 exhibits different resistance values. When reading data from the memory cell 10, a selection voltage (H) is applied to the word line 13 to turn on the transistor 11, and a voltage smaller than that at the time of writing is applied between the bit line 14 and the source line 15. As a result, a current flows between the bit line 14 and the source line 15 via the transistor 11 and the variable resistance element 12, but the current flowing according to the resistance value of the variable resistance element 12 varies, so that the difference in the amount of current is caused. Correspondingly stored data is detected.

  In FIG. 1A, the bit line 14 and the source line 15 are orthogonal to each other, but it is desirable that the bit line 14 and the source line 15 are adjacently arranged in parallel from the relationship between the write and read operations. FIG. 1B shows a layout of the memory cell when the bit line 14 and the source line 15 are arranged in parallel. As shown in FIG. 1B, the word line 13 is arranged in a direction orthogonal to the set of the bit line 14 and the source line 15. In FIG. 1B, the sources of the transistors 11 of two adjacent memory cells connected to the same bit line 14 and source line 15 are connected, and the connection node is connected to the source line 15.

FIG. 2 shows an example of a cross-sectional structure of two adjacent memory cells connected to the same bit line 14 and source line 15 and transistors in the peripheral circuit portion in the memory cell layout shown in FIG. FIG.
As shown in FIG. 2A, functional elements such as transistors are formed in the layer 22 on the substrate 21 in the memory cell portion and the peripheral circuit portion. In the contact layer CT, gate electrodes 23A and 23B, drain electrodes 24A and 24B, and a source electrode 25 are formed. M1 to M5 represent metal layers, respectively, and V1 to VM4 represent via layers. Although not shown, the gate electrodes 23A and 23B are connected to a word line provided in one of the metal layers and extending in a direction perpendicular to the paper surface. The source electrode 25 is connected to a source line provided in any metal layer and extending in the horizontal direction on the paper surface. The drain electrodes 24A and 24B are guided to the upper layer through the metal layers M1 to M4 and the via layers V1 to V4, and are connected to the lower electrode 26. The above structure is the same in the memory cell portion and the peripheral circuit portion. In the memory cell portion, the MTJ 30 is formed between the lower electrode 26 and the upper electrode 28. The upper electrode 28 is disposed on the metal layer M5 and connected to a bit line extending in the horizontal direction on the paper surface.

  Since parts other than the MTJ 30 are realized by applying a wiring layout and manufacturing method that have been widely used so far, description thereof will be omitted, and only the MTJ will be described.

  As described above, the STT-MRAM is required to be formed at the same time as the CMOS constituting the selection transistor and the peripheral circuit. In particular, in the CMOS mixed STT-MRAM, the MTJ is required to have heat resistance against a standard Cu wiring process of CMOS. Also in FIG. 2, since the metal layer M5 connected to the upper electrode 28 is formed after the MTJ 30 is formed, the MTJ 30 preferably has a heat resistance of a Cu wiring process temperature of about 350 ° C. Further, considering that the CoFeB crystallization heat treatment temperature is about 350 ° C., the MTJ30 is required to have heat resistance of 350 ° C. or higher. However, as a result of testing the heat resistance of the interface perpendicular MTJ made of MgO and CoFeB, the heat resistance is insufficient, and in particular, it is difficult to keep the magnetization perpendicular at 350 ° C. for CoFeB formed on the MgO. I understood that. In other words, it has been found that it is desirable to improve the CoFeB / MgO / CoFeB interface vertical MTJ so as to have a heat resistance of 350 ° C. or higher in the CMOS mixed STT-MRAM.

  An in-plane magnetization type MTJ made of CoFeB / MgO / CoFeB is known. In the in-plane magnetization type MTJ, heat treatment at 350 ° C. is generally performed, and heat resistance is higher than that of an interface perpendicular MTJ having the same structure. Have Differences between the in-plane magnetization type MTJ and the interface perpendicular MTJ that are considered to be related to heat resistance are the following three points.

  (1) In-plane magnetization type MTJ has a high degree of freedom in the film thickness of CoFeB, and generally a relatively thick film thickness of 2 to 3 nm is used. On the other hand, in the interface perpendicular MTJ, the influence of the interface is dominant, so that the CoFeB film thickness cannot be increased, and it is necessary to make it an extremely thin film of 2 nm or less. In other words, the thin film thickness of CoFeB is related.

  (2) It is theoretically expected that the perpendicular magnetization utilized in the interface perpendicular MTJ is generated by orbital hybridization of Fe and O at the interface between MgO and CoFeB. Therefore, it is thought that the factor which inhibits the orbital hybridization of Fe and O has generate | occur | produced.

  (3) In the in-plane magnetization type MTJ, various metals such as Ta and Ru can be used at the interface opposite to the MgO of CoFeB. However, in the interface perpendicular MTJ, Ta needs to be used. Ta at the interface opposite to the MgO of CoFeB has an influence.

  Furthermore, in the in-plane magnetization type MTJ, it has been found that the heat resistance in the case of a spin valve structure using an antiferromagnetic layer such as PtMn or IrMn is determined by Mn diffusion to the CoFeB / MgO interface. Further, it has been found that in the in-plane magnetization type MTJ, the heat resistance of the coercive force difference type structure without using the antiferromagnetic layer is determined by Ta diffusion to the CoFeB / MgO interface.

  From the above, in the interface perpendicular MTJ, it is considered that Ta diffuses in the thin CoFeB during the heat treatment and reaches the CoFeB / MgO interface, thereby inhibiting the expression of the interface perpendicular magnetization. Therefore, if this diffusion can be suppressed, it is considered that the heat resistance of the interface vertical MTJ is improved.

  Therefore, in this embodiment, a diffusion control layer is provided in order to suppress Ta diffusion. Since the diffusion control layer needs to contain Ta from the above condition (3), for example, amorphous CoFeBTa is used as the diffusion control layer.

  FIG. 3 is a view showing a configuration example of the MTJ 30 provided in the memory cell of the interface perpendicular magnetization type STT-MRAM according to the present embodiment. FIG. 3A shows an example in which a diffusion control layer is provided on the upper ferromagnetic metal electrode. (B) shows an example in which a diffusion control layer is provided under the lower ferromagnetic metal electrode.

  In the example of FIG. 3A, the MTJ 30 includes a lower metal 34, a lower ferromagnetic metal electrode 32, a tunnel insulating film 31, an upper ferromagnetic metal electrode 33, a diffusion control layer 41, an interface cap layer 42, and a diffusion buffer layer 43. Are stacked in this order. 3B, in the example of FIG. 3B, the diffusion buffer layer 53, the interface cap layer 52, the diffusion control layer 51, the lower ferromagnetic metal electrode 32, the tunnel insulating film 31, the upper ferromagnetic metal electrode 33, and the upper part It has metal 35 and is laminated in this order.

  In the example of FIGS. 3A and 3B, the diffusion control layer, the interface cap layer, and the diffusion buffer layer are stacked only on one side of the two layers of ferromagnetic metal electrodes that are opposed to each other with the tunnel insulating film 31 interposed therebetween. Was established. However, the two layers of ferromagnetic metal electrodes may be provided at the opposite interface to the tunnel insulating film.

  The tunnel insulating film 31 is made of, for example, MgO. The lower ferromagnetic metal electrode 32 and the upper ferromagnetic metal electrode 33 are made of, for example, CoFeB. The diffusion control layer 41 is made of, for example, CoFeBTa. The interface cap layer is made of Ta, for example. The diffusion buffer layer is made of, for example, Ru.

  The lower diffusion control layer 51 shown in FIG. 3B is desirable because CoFeBTa can be formed by sputtering because the manufacturing process can be simplified.

  The upper diffusion control layer 41 shown in FIG. 3A can simplify the manufacturing process by continuously forming the upper ferromagnetic metal electrode (CoFeB) 33 and the interface gap layer (Ta) 42 and mixing them. desirable.

It is known that when a crystallization heat treatment is applied after a Ta film is formed on CoFeB by sputtering, a magnetic dead layer of 0.4 to 0.5 nm is generated due to the following two effects. ing.
(1) Mixing occurs due to the effect of gas particles and Ta being implanted into CoFeB during film formation.
(2) Due to the heat treatment, Ta diffuses into CoFeB and causes both to mix.

  In general, it is considered that the magnetically inactive layer is an unnecessary layer, and ingenuity has been made so that this layer does not usually occur in thin film formation. Specifically, for example, by using a heavy gas such as Kr or Xe at the time of film formation for the implantation of (1), high energy gas particles recoiling from the target are reduced, and mixing does not occur. A steep interface is formed. In contrast, in this embodiment, the magnetically inactive layer is used as the upper diffusion control layer 41.

  However, it has been found that the normally formed magnetically inactive layer of about 0.4 to 0.5 nm is insufficient as a diffusion control layer for Ta during heat treatment at 350 ° C. For this reason, in order to effectively suppress the diffusion, it was considered desirable to prepare a relatively thick diffusion control layer at the time (1) before the heat treatment. Therefore, light Ar gas was used during Ta film formation, and the gas flow rate during film formation was further reduced to about 50 sccm (Standard Cubic Centimeter per Minutes) to increase the incident energy of the film formation gas particles and Ta on the CoFeB surface. As a result, it has been found that the thickness of the magnetically inactive layer is increased to 0.5 nm or more, the thermal stability at 350 ° C. is greatly improved, and perpendicular magnetization can be realized.

  Providing the amorphous diffusion control layers 41 and 51 prevents diffusion of the interface cap layers 42 and 52 into the lower portion of the Ta and the upper ferromagnetic metal electrodes 32 and 33 during heat treatment, and improves the heat resistance of the MTJ. Can do. In particular, since the diffusion control layers 41 and 51 are amorphous, Ta diffusion does not occur at the crystal grain boundary, and the diffusion suppressing power is improved.

  On the other hand, in order to crystallize CoFeB of the diffusion control layers 41 and 51 at 350 ° C., B in the film needs to escape from CoFeB. Here, even when a diffusion control layer for Ta was provided, it was found that B in CoFeB can escape from the diffusion control layers 41 and 51 during the crystallization heat treatment by satisfying the following conditions.

(1) The film thickness of the interface cap layers (Ta) 42 and 52 is made sufficiently thinner than 5 nm.
(2) In addition to the interface cap layers 42 and 52, diffusion buffer layers (Ru) 43 and 53 for diffusing B are provided.

  From the above, when the diffusion control layer (CoFeBTa) is provided, the film thickness of the interface cap layer (Ta) is reduced and a diffusion buffer layer (Ru) is further provided. As a result, it has been found that both “reducing the amount of Ta diffused into CoFeB” and “diffusing B in CoFeB to the outside of CoFeB” are possible.

  Hereinafter, the manufacturing process of the MTJ portion in the embodiment will be described with reference to FIGS. As shown in FIG. 2, the manufacturing process of the MTJ portion is performed after the via layer VM4 is formed, so that the description will be made from the state where the via connecting the transistor and the lower electrode (BEL) 26 is exposed. .

  In a normal CMOS process, the via material is Cu, and a via (Cu) 61 is formed in the SiO 2 layer 62 as shown in FIG. As shown in FIG. 4A, a Ta layer (3 nm) 63, a Ru layer (25 nm) 64, and a Ta layer (15 nm) 65 to be the lower electrode (BEL) 26 are sequentially formed by sputtering. The intermediate Ru layer 64 of BEL has the effect of lowering the sheet resistance, and the surface flatness is improved as compared with the case where the same sheet resistance is obtained with a Ta single film. The Ta layer 65 on the Ru layer 64 functions as an etching stopper layer when the MTJ is dry-etched (RIE).

  Next, as shown in FIG. 4B, a Ru layer 66 that becomes the diffusion buffer layer 53 is formed on the BEL by sputtering to have a thickness of 8 nm, and then a Ta layer that becomes the interface seed layer (interface cap layer) 52. 67 is deposited to a thickness of 1 nm. Here, the interface seed layer plays the same role as the interface cap layer. For convenience, the interface seed layer is referred to as the seed layer when it is below the CoFeB, and the cap layer when it is above it.

  Subsequently, a CoFeBTa layer 68 serving as the diffusion control layer 51 is formed to a thickness of 0.3 nm by the simultaneous sputtering of CoFeB and Ta. The composition ratio of CoFeB is adjusted to be Co: Fe: B = 20: 60: 20 (atomic%) by adjusting the target composition. The composition ratio of CoFeBTa is adjusted to CoFeB: Ta = 80: 20 (atomic%) by adjusting the sputtering power.

  Next, as shown in FIG. 4C, a CoFeB layer 69, which is the lower ferromagnetic metal layer 32 of the MTJ, is formed to a thickness of 1.2 nm by sputtering. The composition ratio of CoFeB is adjusted to be Co: Fe: B = 20: 60: 20 (atomic%) by adjusting the target composition.

  Next, as shown in FIG. 4C, a Mg film having a thickness of 0.8 nm is formed by sputtering, followed by oxidation of Mg in an oxygen atmosphere for 30 seconds, and then Mg in order to prevent overoxidation at the interface. By forming the film to 0.35 nm, the MgO layer 70 that is the tunnel insulating film 31 is formed.

  Next, as shown in FIG. 4C, a CoFB layer 71 that is the upper ferromagnetic metal layer 33 of the MTJ is formed to a thickness of 1.4 nm by sputtering. The composition ratio of CoFeB is adjusted to be Co: Fe: B = 20: 60: 20 (atomic%) by adjusting the target composition.

  Next, as shown in FIG. 5A, a Ta layer 73 which is the interface cap layer 42 is formed by sputtering to a thickness of 1 nm while supplying Ar gas at a flow rate of 50 sccm. By using such Ta film formation conditions, the deposition gases Ar and Ta are promoted into CoFeB, and mixing occurs at the interface, resulting in a thickness as shown in FIG. A CoFeBTa layer 72 which is a diffusion control layer 41 having a thickness of 0.5 nm or more is formed.

  Next, as shown in FIG. 5C, a Ru layer 74 as the diffusion buffer layer 43 is formed to 7 nm and a Ta layer 75 as the upper electrode (TEL) is formed to 80 nm by sputtering, followed by CVD. Thus, a hard mask (SiO2) layer 76 is formed to a thickness of 100 nm.

  Next, as shown in FIG. 6A, the resist pattern of the upper electrode (TEL) 35 of the MTJ is exposed to a circle having a diameter of 50 nm by immersion ArF lithography and a three-layer resist process. Thereafter, the etching is performed up to the three-layer resist, hard mask, TEL, and MTJ by dry etching, and stopped at Ta of the lower electrode (BEL) 65. The etching of the three-layer resist, the SiO2 hard mask, and the TEL can be applied to the manufacturing process technology other than the MRAM element, and thus detailed description thereof is omitted. For etching from the upper diffusion buffer 43 (Ru layer 74) to the lower diffusion buffer 53 (Ru layer 66), etching using methanol (CH3OH) as an etching gas is performed, and etching is performed with Ta as an etching stopper. stop. At the stage where the etching is completed, the hard mask SiO2 has disappeared due to the etching, and the TEL Ta is exposed.

  Next, as shown in FIG. 6B, an SiN layer 76 that is an interlayer insulating film is formed to a thickness of 30 nm, and then a SiO 2 layer 77 that is a thick interlayer insulating film is formed to a thickness of 100 nm and planarized. Thereafter, in order to electrically isolate the MTJ, the resist pattern of BEL63-65 is exposed so as to cover the MTJ and the Cu plug by immersion ArF lithography and a three-layer resist process. Further, the etching is performed up to the three-layer resist, SiO2, SiN, and BEL by dry etching and stopped at the SiO2 below the BEL.

  Thereafter, the process is almost the same as a normal Cu dual damascene process. As shown in FIG. 6C, an SiO 2 film as an interlayer insulating film is formed to a thickness of 300 nm and planarized by a CMP method. Furthermore, a via is opened in a portion where a via is necessary as a contact of a transistor or the like, and the upper portion of the MTJ is exposed by etching the wiring portion, exposing the upper electrode (TEL), filling with Cu, and planarizing by CMP. Form wiring. Subsequent processes are not particularly limited to the element of this embodiment, and if the upper Cu wiring and Al pad are further formed, the MRAM can be mounted on the CMOS.

FIG. 7 is a view showing the MTJ manufactured in the manufacturing process described with reference to FIGS.
The material, film thickness, conditions, and the like used in the above manufacturing process are optimal examples, and are not limited thereto.

  The film thickness of the MgO layer 70 may be in the range of 0.6 to 1.2 nm, and the MgO film formation method uses the MgO target even in the method of oxidizing metal Mg after sputtering film formation as in this embodiment. Direct sputtering may be used. In the present embodiment, a bottom pin structure is assumed in which the CoFeB layer 71 of the upper ferromagnetic metal electrode 33 is a magnetization free layer and the CoFeB layer 69 of the lower ferromagnetic metal electrode 32 is a magnetization fixed layer. However, the film thickness of the upper and lower CoFeB layers 69 and 71 may be in the range of 0.7 to 1.8 nm, and a top pin structure in which the lower CoFeB layer 69 is a magnetization free layer may be used depending on the magnitude relationship of the magnetization amount. . Further, the composition ratio of CoFeB is not limited to the above embodiment.

  In this embodiment, CoFeBTa layers 68 and 72 are used as the diffusion control layer. However, if the thickness of the CoFeBTa layer 72 that is the upper diffusion control layer is 0.5 nm to 1.0 nm and the thickness of the CoFeBTa layer 68 that is the lower diffusion control layer is 0.2 nm to 1.0 nm. The combination and composition ratio of the materials are not limited.

  In this embodiment, the Ta layer 67 is used as the interface cap (seed) layer 52, but the film thickness may be in the range of 1.0 nm or less. In addition, a thin Ta layer is formed on the CoFeB layer, and includes a state where the Ta film thickness becomes 0 nm by mixing. In this embodiment, the Ru layers 66 and 74 are used as the diffusion buffer layer. However, the film thickness can be freely set, and the material can be selected as long as boron (B) can diffuse including the grain boundary. Is free.

  In the above example, the diffusion control layer (CoFeBTa layers 68 and 72), the interface cap layer (Ta layers 67 and 73) and the diffusion buffer layer (Ru layers 66 and 74) are formed as shown in FIG. The metal electrodes (CoFeB layers 69 and 71) were provided on both sides. However, the lamination of the diffusion control layer, the interface cap layer, and the diffusion buffer layer may be on at least one of the ferromagnetic metal electrodes. FIG. 8A shows a stack of a diffusion control layer (CoFeBTa layer 72), an interface cap layer (Ta layer 73), and a diffusion buffer layer (Ru layer 74), in which only the upper ferromagnetic metal electrode (CoFeB layer 71) is formed. An example provided at the top is shown.

  Furthermore, when installing a stack of a diffusion control layer, an interface cap layer, and a diffusion buffer layer only on one side of the ferromagnetic metal electrode, as shown in FIG. The magnetization fixed layer may fix the perpendicular magnetization with a perpendicular magnetization material through a thin Ta layer. In FIG. 8B, the above-described lamination is provided only on the upper ferromagnetic metal electrode (CoFeB layer 71), and the lower ferromagnetic metal electrode (CoFeB layer 69) is formed of Co / Pd or Pd via a thin Ta layer 67. An example in which perpendicular magnetization is fixed with a perpendicular magnetization material such as Co / Pt is shown.

  Using the vibrating sample magnetometer (VSM), the characteristics of the MTJ of the embodiment were evaluated. By using the vibration sample type magnetization measuring apparatus, the physical property values of the sample such as the direction of magnetization and the saturation magnetization can be easily measured, and the characteristics of the sample can be quantitatively evaluated.

FIG. 9 is a diagram showing a sample of MTJ manufactured for performing characteristic evaluation.
In this sample, as shown in FIG. 9, a ferromagnetic metal electrode of Ta / MgO / CoFeB / Ta / Ru is installed on only one side on the SiO 2 layer 93. This sample evaluates the film thickness of the diffusion control layer formed at the interface between the CoFeB layer 94 and the Ta layer 95 and the ability to prevent diffusion with respect to Ta and B. It is possible to easily examine physical properties such as the direction of magnetization and the amount of saturation magnetization.

  First, the sample will be described. The Ta layer 92 as a base adhesion layer was formed to a thickness of 5 nm. As in the embodiment, the MgO layer 91 that is a tunnel insulating film is formed by depositing 0.8 nm of Mg and then oxidizing it in an oxygen atmosphere for 30 seconds, and forming 0.35 nm of Mg to prevent overoxidation. To form. The CoFeB layer 94, which is a ferromagnetic metal electrode, was prepared by fixing the composition ratio to Co: Fe: B = 20: 60: 20 (atomic%) and changing the film thickness stepwise. In order to change the amount of mixing with the CoFeB layer 94, the Ta layer 95 as the interface cap layer was prepared by changing the film thickness, the type of gas at the time of film formation, and the gas flow rate. As for the diffusion buffer layer, a Ru layer was formed to a thickness of 30 nm so that B could be sufficiently diffused. These laminated structures were continuously formed in a sputtering apparatus, and after the film formation, heat treatment was performed in a vacuum annealing furnace at 350 ° C. for 2 hours.

FIG. 10 is a diagram showing a change in the amount of magnetization of CoFeB with respect to the thickness of the CoFeB layer 94 when the thickness of the Ta layer 95 is fixed to 1 nm and Kr and Ar are used as the deposition gas. In any gas type, the flow rate is 50 sccm (50 × 1.69 × 10 ⁻⁴ Pa · m ³ /sec=8.45×10 ⁻³ Pa · m ³ / sec). In FIG. 10, the film thickness when the magnetization amount on the vertical axis is zero indicates the film thickness of the diffusion control layer formed by mixing magnetically inactive CoFeB and Ta. From FIG. 10, by changing the deposition gas from heavy Kr to light Ar, the energy of Ar gas injected into CoFeB is increased, and the mixing of CoFeB and Ta is promoted, so that the film thickness of the diffusion control layer is increased. It turned out that it increased significantly.

  FIG. 11 is a table showing the film thickness of the diffusion control layer in the form of a table when the Ta film thickness is fixed to 1 nm and the gas flow rate is changed for Kr and Ar. It can be seen that the lighter the gas type and the smaller the deposition gas flow rate, the greater the thickness of the diffusion control layer. It has been found that a diffusion control layer as thick as 0.73 nm can be obtained by optimizing the gas type and flow rate for the generally reported 0.45-0.5 nm magnetically inactive layer. . Note that the film thicknesses in the table of FIG. 11 are the results after the heat treatment, and the film thickness of the diffusion control layer immediately after film formation is expected to be more dependent on the film formation conditions.

  FIG. 12 shows the saturation magnetization (Ms) in the vertical direction and the residual magnetization in the vertical direction in a zero magnetic field when the gas type and gas flow rate during the deposition of the Ta layer 73 are changed under the same conditions as in the table of FIG. It is a figure which shows how the ratio of (Mr) changes with respect to saturation magnetization amount (Ms). As described above, since the film thickness of the diffusion control layer changes depending on the gas type and flow rate, FIG. 12 is also a diagram showing how the ratio Mr / Ms changes with respect to the film thickness of the diffusion control layer. . It is desirable that the ratio Mr / Ms suddenly changes from a value close to zero to a value close to 100% and then maintains a value close to 100%.

  From FIG. 12, it is understood that the ratio Mr / Ms increases in a wider magnetization range as the diffusion control layer is thicker. Therefore, the thickness of the diffusion control layer is increased to 0.5 nm or more to prevent Ta as the interface cap layer from diffusing into the CoFeB layer, thereby suppressing deterioration of the interface perpendicular magnetization of MgO / CoFeB even after heat treatment at 350 ° C. It was found that good perpendicular magnetization can be obtained.

  However, in order to obtain good perpendicular magnetization, it is necessary to optimize the film thickness of the interface cap layer in addition to the optimization of the diffusion control layer. FIG. 13 is a diagram showing a change in the ratio Mr / Ms when Ar gas and 50 sccm are used as the Ta film forming gas and the thickness of the Ta layer is changed. FIG. 13 shows that the perpendicular magnetization characteristics are deteriorated when the thickness of Ta is as thick as 5 nm.

  FIG. 14 is a table showing changes in the thickness of the diffusion control layer depending on the Ta layer deposition conditions. FIG. 14 shows that the diffusion control layer when the thickness of the Ta layer is 5 nm is sufficiently thick, that is, if the interface cap layer is thick even if the diffusion control layer is thick, good characteristics cannot be obtained.

  In order to investigate this cause, SIMS analysis was performed on samples of a 1 nm Ta layer and a 5 nm Ta layer formed under conditions of Ar gas and 50 sccm. FIG. 15 shows the result. FIG. 15 is a diagram showing changes in the B diffusion profile depending on the thickness of the Ta layer. The right side of the figure is the base, and the layers are arranged in the order of SiO 2 / Ta / MgO / CoFeB / Ta / Ru, and the peak of MgO is shown. The depth (Depth) is set at a position of 0 nm.

  As is apparent from FIG. 15, in the case of a 1 nm Ta layer, the Ta layer remaining as the interface cap layer is very thin, so that B in the CoFeB layer passes through the diffusion control layer and the interface cap layer. It can be seen that the diffusion buffer layer has diffused into Ru. On the other hand, when the thickness of the Ta layer is 5 nm, the residual film of Ta, which is the interface cap layer, is thick, so that Ta itself functions as a diffusion barrier for B, and B diffusion into Ru does not occur. I understand.

  From these experimental results, the diffusion control layer diffuses B easily, but B diffusion in the Ta layer which is the interface cap layer is not easy. When the interface cap layer is thick, the B in the CoFeB layer becomes the diffusion buffer. It was found that the layer could not be reached. In this case, since the B residual concentration in CoFeB is high, CoFeB is difficult to crystallize, and the B concentration also increases at the MgO / CoFeB interface, which inhibits the expression of interfacial perpendicular magnetization caused by Fe and O orbital hybridization. There is a possibility that. Therefore, it can be said that the Ta remaining film after the heat treatment is preferably from 0 nm (that is, a state where CoFeB and Ta are completely reacted) to 1 nm or less. In this case, it is important that the thickness of the Ta layer during film formation is in the range of 0.5 nm to 1.8 nm.

  Summarizing the above results, it was found that the following three points are important for improving the heat resistance of interface perpendicular magnetization.

  (1) In order to prevent Ta in the interface cap layer from diffusing into the MgO / CoFeB interface, the film thickness of the diffusion control layer is set to 0.5 nm or more. When the diffusion control layer is formed by mixing CoFeB and Ta, it is desirable to use light gas species (such as Ar) and a low flow rate (50 sccm or less) as the gas for forming the Ta film.

  (2) When the thickness of the Ta layer of the interface cap layer is large, CoFeB B in the ferromagnetic metal electrode cannot easily diffuse this Ta but remains in CoFeB. / CoFeB may inhibit the development of interface perpendicular magnetization. Therefore, the film thickness of the interface cap layer is at least 5 nm or less, preferably 1 nm or less.

  (3) Since a layer for storing B that has passed through the diffusion control layer and the interface cap layer is required, it is necessary to form a diffusion buffer layer such as Ru.

  As described above, the diffusion control layer (CoFeBTa layer) is provided at the interface between the CoFeB layer and the Ta layer, and the following effects are obtained by reducing the thickness of the interface cap layer (Ta layer) and installing the diffusion buffer layer (Ru layer). It became clear.

  (1) As a result of the diffusion control layer suppressing the diffusion of Ta into the CoFeB layer, the heat resistance of the interface perpendicular magnetization in the MgO / CoFeB structure is improved, and is sufficiently wide even after the heat treatment at 350 ° C. necessary for CMOS mounting. The magnetization can be perpendicularized in the magnetization range.

  (2) By installing the interface cap layer and the diffusion buffer layer, B in the CoFeB layer diffuses through the diffusion control layer and the interface cap layer and escapes to the diffusion buffer layer, thereby reducing the B concentration in the CoFeB layer after the heat treatment. As a result, the interface perpendicular magnetization was easily developed.

  Due to these effects, an interface vertical MTJ with high heat resistance and good crystallinity can be produced.

FIG. 16 is a block diagram of a semiconductor device in which the interface perpendicular magnetization type STT-MRAM of the embodiment having the MTJ described so far is embedded in a CMOS circuit.
As illustrated in FIG. 16, the semiconductor device (chip) 100 includes an MRAM 120 and a CMOS circuit unit 110 other than the MRAM 120. The CMOS circuit unit 110 includes, for example, a logic circuit unit 111 such as a processor, an analog circuit unit 112, a power supply circuit, and the like.

FIG. 17 is a block diagram of the MRAM 120.
As shown in FIG. 17, the MRAM 120 includes a memory cell array 201, a row decoder 202, a column decoder 203, a selection switch array 204, a write amplifier 205, a sense amplifier 206, a data I / O unit 207, and a control unit 208. The row decoder 202, the column decoder 203, the data I / O unit 207, and the control unit 208 receive the address signal, input / output data, and control signal from the CMOS circuit unit 110, and access the memory cell array 201. Since the configuration and operation of the MRAM 120 are widely known, a description thereof will be omitted.

  The MRAM 120 mounted on the semiconductor device 100 shown in FIG. 16 is manufactured by a process to which a high temperature of 350 ° C. or higher applied to manufacture the CMOS circuit unit 110 is applied. Since the MTJ of the MRAM 120 has the structure described in the embodiment and is manufactured by the manufacturing process described above, the MTJ has heat resistance of 350 ° C. or higher and does not deteriorate in performance even when a high temperature of 350 ° C. or higher is applied.

  The embodiment has been described above, but all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and technology. In particular, the examples and conditions described are not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

12 Variable resistance element 30 MTJ (Magnetic Tunnel Junction)
31 Tunnel insulating film 32 Lower ferromagnetic metal electrode 33 Upper ferromagnetic metal electrode 41, 51 Diffusion control layer 42, 52 Interface cap layer 43, 53 Diffusion buffer layer

Claims (7)

A first ferromagnetic metal electrode;
A second ferromagnetic metal electrode;
A tunnel insulating film provided between the first ferromagnetic metal electrode and the second ferromagnetic metal electrode;
CoFeBTa provided on the surface of the first ferromagnetic metal electrode or the second ferromagnetic metal electrode on the opposite side of the tunnel insulating film across the first ferromagnetic metal electrode or the second ferromagnetic metal electrode An amorphous diffusion control layer containing,
An interface cap layer provided on the surface of the amorphous diffusion control layer on the opposite side of the first ferromagnetic metal electrode or the second ferromagnetic metal electrode across the amorphous diffusion control layer;
Perpendicular magnetization type magnetoresistive memory, characterized in that it comprises a. 2. The perpendicular magnetization type magnetoresistive memory according to claim 1, further comprising a diffusion buffer layer provided on a surface of the interface cap layer opposite to the amorphous diffusion control layer with the interface cap layer interposed therebetween. . When the amorphous diffusion control layer is provided at the interface of the ferromagnetic metal electrode provided above the tunnel insulating film with respect to the substrate, the film thickness is 0.5 nm or more and 1.0 nm or less. 2. The perpendicular magnetization according to claim 1 , wherein the film has a thickness of 0.2 nm to 1.0 nm when provided at the interface of the ferromagnetic metal electrode provided under the tunnel insulating film. Type magnetoresistive memory. The perpendicular magnetization type magnetoresistive memory according to claim 1 , wherein the interface cap layer has a thickness of 1.0 nm or less. The tunnel insulating film in MgO, the ferromagnetic metal electrode CoFeB, before Symbol interfacial cap layer with Ta, perpendicular magnetization according to claim 2, wherein the diffusion buffer layer is characterized in that it is formed of Ru Type magnetoresistive memory. A plurality of perpendicular magnetization type magnetoresistive memory cells, each memory cell comprising a lower ferromagnetic metal electrode, a tunnel insulating film on the lower ferromagnetic metal electrode, and an upper ferromagnetic metal electrode on the tunnel insulating film; A stack of an amorphous diffusion control layer, an interface cap layer, and a diffusion buffer layer provided on the upper ferromagnetic metal electrode, and using data perpendicular to the interface between the tunnel insulating film and the ferromagnetic metal electrode. A method of manufacturing a magnetoresistive memory for storing,
At the interface opposite to the tunnel insulating film of the upper ferromagnetic metal electrode, the interface cap layer is driven by a sputtering method,
The method of manufacturing a magnetoresistive memory, wherein the amorphous diffusion control layer is formed before the crystallization heat treatment of the upper ferromagnetic metal electrode by mutual mixing of the upper ferromagnetic metal electrode and the interface cap layer. The upper ferromagnetic metal electrode is made of CoFeB and the interface cap layer is made of Ta;
Ar is used as a sputtering gas when forming Ta to form the interface cap layer, the flow rate during film formation is 50 sccm or less, and the film thickness of the interface cap layer is 0.5 nm or more and 1.8 nm or less. The method of manufacturing a magnetoresistive memory according to claim 6.

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