JP5867275B2 - Semiconductor memory device and data writing method thereof - Google Patents

Description

  Embodiments referred to in this specification relate to a semiconductor memory device and a data writing method thereof.

  In recent years, with advances in semiconductor manufacturing technology, semiconductor memory devices have also been miniaturized and highly integrated, and drive voltages have been lowered. Furthermore, in order to realize application to battery-driven portable devices and energy saving, reduction in power consumption of semiconductor memory devices is also being promoted.

  An example of such a semiconductor memory device is an SRAM (Static Random Access Memory). The SRAM is used as a cache memory of an arithmetic processing unit (processor) or a memory that executes high-speed processing.

  An SRAM is generally hierarchized, and includes a plurality of global bit lines, a plurality of local bit lines connected to each global bit line, and a plurality of local bit lines provided between each local bit line and a word line. It has a memory cell.

  By the way, conventionally, various types of hierarchical semiconductor memory devices (for example, SRAM) have been proposed.

K. Takeda et al., "Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-Density SRAMs," Symposium on VLSI Circuits, 2010

  As described above, for example, the SRAM is hierarchized by a plurality of global bit lines and a plurality of local bit lines connected to each global bit line. Here, a plurality of local bit lines are connected to one global bit line, and the wiring length of the global bit line is much longer than the wiring length of the local bit line.

  Therefore, if the global bit line is fully swung, a large amount of power is consumed. Note that a hierarchical semiconductor memory device that causes an increase in power consumption due to a full swing of a global bit line is not limited to an SRAM, and the same applies to a DRAM (Dynamic Random Access Memory) or the like.

  As described above, in the hierarchical semiconductor memory device, an increase in power consumption at the time of data writing is a problem.

  According to one embodiment, a plurality of global bit lines, a plurality of local bit lines connected to each of the global bit lines, a plurality of memory cells provided between each of the local bit lines and the word line, A semiconductor memory device is provided.

When writing data to the memory cell, the global bit line and the local bit line used for writing data in the memory cell are set to the first level. Then, the level of the local bit line is expanded to a second level larger than the first level, and data is written to the memory cell. The first level is defined according to a capacitance ratio of a first capacitance of a wiring that drives the global bit line and a second capacitance obtained by adding the capacitances of both the global bit line and the local bit line.

  The disclosed semiconductor memory device and data writing method thereof have an effect of reducing power consumption during data writing.

FIG. 1 is a circuit diagram illustrating an example of a semiconductor memory device. FIG. 2 is a timing chart for explaining the data write operation of the semiconductor memory device shown in FIG. FIG. 3 is a circuit diagram showing the semiconductor memory device according to this embodiment. FIG. 4 is a circuit diagram showing an example of a sense amplifier circuit in the semiconductor memory device shown in FIG. FIG. 5 is a timing chart for explaining the data write operation of the semiconductor memory device shown in FIG.

  First, before describing embodiments of the semiconductor memory device and its data writing method in detail, an example of the semiconductor memory device and problems in the semiconductor memory device will be described with reference to FIGS.

  FIG. 1 is a circuit diagram showing an example of a semiconductor memory device, and FIG. 2 is a timing diagram for explaining a data write operation of the semiconductor memory device shown in FIG. In FIG. 1, MC is a memory cell, SA is a sense amplifier circuit, GBL <0>, GBLX <0> to GBL <m>, GBLX <m> are global bit lines, LBL <0>, LBLX <0>. ˜LBL <m>, LBLX <m> are local bit lines, and WL is a word line.

  Reference sign PRE is a precharge signal, LSAE is a sense amplifier enable signal, WEN is a write enable signal, COL <0> to COL <m> are column signals, and GC-0 <0> to GC-n <0. >,..., GC-0 <m> to GC-n <m> indicate bank column signals.

Reference symbol C _GBL indicates the capacitance (parasitic capacitance) of the global bit line, and _CLBL indicates the capacitance (parasitic capacitance) of the local bit line. Further, reference sign VDD indicates a high potential power supply line (high potential power supply level), and VSS indicates a low potential power supply line (low potential power supply level).

  Here, an example of the semiconductor memory device is an SRAM, but the semiconductor memory device is not limited thereto, and may be a DRAM (Dynamic Random Access Memory) or the like. In this specification, a complementary semiconductor memory device is described as an example, but it is needless to say that it may be a single-ended device.

  As shown in FIG. 1, the semiconductor memory device has m + 1 columns, and each column has n + 1 banks. In FIG. 1, the leftmost column (column <m>) indicates a selected column, and the rightmost column (column <0>) is representative of other non-selected columns (columns <0> to <m-1>). ) Indicates a non-selected column. Each column has a similar circuit configuration.

In the selected column, complementary write data WD and WDX are input to the first input terminals of the three-input AND gates AND _m 1 and AND _m 2, respectively. The write enable signal WEN is input to the second input terminals of the AND gates AND _m 1 and AND _m 2, and the column signal COL <m> is input to the third input terminal.

The column signal COL <m> has pMOS transistors TP _m 1 and TP _m 2 having a source connected to the high potential power supply line (VDD) and a drain connected to the global bit lines GBL <m> and GBLX <m>. The gate is also input.

The connection between the global bit lines GBL <m> and GBLX <m> and the local bit lines of the respective banks 0 to n is controlled by bank column signals GC-0 <m> to GC-n <m>, respectively. Bank selection transistors TN _m0 1 and T _m0 2 to TN _mn 1 and T _mn 2 are provided.

That is, between the local bit lines LBL <m> and LBLX <m> of the bank n of the column m and the global bit lines GBL <m> and GBLX <m>, the bank column signal GC-n <m> is connected to the gate. Input n-channel MOS (nMOS) transistors TN _mn 1 and TN _mn 2 are arranged.

The local bit lines LBL <m> and LBLX <m> are connected to a plurality of memory cells MC selected by the word line WL, respectively, and a sense amplifier circuit SA controlled by a sense amplifier enable signal LSAE. It is connected. Further, pMOS transistors TP _mn 1 and TP _mn 2 controlled by a precharge signal PRE are also connected to the local bit lines LBL <m> and LBLX <m>.

  Here, for example, when the write data WD of the high level “H” is written to the memory cell MC provided between the word line WL and the local bit lines LBL <m> and LBLX <m> in the bank n of the column m. think of.

As shown in FIG. 2, both the column signal COL <m> and the write enable signal WEN are set to “H”, the transistors TP _m 1 and TP _m 2 are both turned off, and the output of the AND _m 1 is set to “H”. The output of AND _m 2 becomes “L”.

As a result, the transistor TNL _m is turned on, and the global bit line GBL <m> connected to the transistor TNL _m is pulled down to “L” (low potential power supply level VSS). At this time, the transistor TNR _m is turned off, and the global bit line GBLX <m> connected to the transistor TNR _m maintains “H” (high potential power supply level VDD).

The levels of the global bit lines GBL <m> and GBLX <m> are determined by the local bit line via the transistors TN _mn 1 and TN _mn 2 which are turned on by the “H” bank column signal GC-n <m>. LBL <m> and LBLX <m> are transmitted.

At this time, since the precharge signal PRE is “H”, the transistors TP _mn 1 and TP _mn 2 are turned off, and since the word line WL is “H”, the word line WL and the local bit lines LBL <m> and LBLX < Memory cells MC between m> are selected.

  Then, the sense amplifier enable signal LSAE becomes “H”, the sense amplifier circuit SA connected to the local bit lines LBL <m> and LBLX <m> is activated, and WL and LBL <m> and LBLX <m Data is written to the memory cells MC between>. When the write data WD is “L”, the levels of the complementary global bit lines GBL <m>, GBLX <m> and the local bit lines LBL <m>, LBLX <m> are reversed.

  As described above, in the semiconductor memory device shown in FIGS. 1 and 2, when data is written to a predetermined memory cell MC between WL and LBL <m>, LBLX <m>, the global bit lines GBL <m>, GBLX <m> and local bit lines LBL <m> and LBLX <m> are fully swung.

  That is, both the global bit line GBL <m> and the local bit line LBL <m >> change with full swing from VDD to VSS. Note that the level of the local bit lines LBL <m−1> to LBL <0> to which no data is written changes, for example, gradually from VDD (“H”) to VSS (“L”), Thereafter, it returns to “H” by the precharge signal PRE.

  Here, a plurality of local bit lines LBL <0>, LBLX <0> to LBL <m>, LBLX <m> can be connected to one global bit line GBL <m>, GBLX <m>. The wiring length of the global bit line is much longer than the wiring length of the local bit line. For this reason, the global bit lines GBL <m> and GBLX <m> have a large parasitic capacitance. When the global bit line is fully swung, a large amount of power is consumed.

As an example, assuming that the number of banks is 8 and the number of columns is 4, the power per bit at the time of data writing is expressed as follows, assuming that the power consumption of the local bit line is _PLBL .
P _LBL = C _LBL × VDD ² × number of columns
= C _LBL × VDD ² × 4
Further, the power consumption P _GBL of the global bit line is expressed as follows.
P _GBL = C _GBL × VDD ²

Here, since the parasitic capacitance C _GBL of the global bit line is about the number of banks (= 8) −1 times larger than the parasitic capacitance C _LBL of the local bit line,
P _GBL = C _LBL × 7 × VDD ²
Therefore, the power consumption P _BL of 1 bit per time of data writing is expressed as follows.
P _BL = P _LBL + P _GBL
= C _LBL × 11 × VDD ²

  Hereinafter, embodiments of a semiconductor memory device and a data writing method thereof will be described in detail with reference to the accompanying drawings. FIG. 3 is a circuit diagram showing the semiconductor memory device according to this embodiment.

  In FIG. 3, reference symbol MC is a memory cell, SA is a sense amplifier circuit, GBL <0>, GBLX <0> to GBL <m>, GBLX <m> are global bit lines, LBL <0>, LBLX <0>. ˜LBL <m>, LBLX <m> are local bit lines, and WL is a word line.

  Reference sign PRE is a precharge signal, LSAE is a sense amplifier enable signal, WEN is a write enable signal, COL <0> to COL <m> are column signals, and GC-0 <0> to GC-n <0. >,..., GC-0 <m> to GC-n <m> indicate bank column signals.

Further, reference symbol C _GBL indicates the global bit line capacitance (parasitic capacitance), C _LBL indicates the local bit line capacitance (parasitic capacitance), and C _WRVSS indicates the capacitance (parasitic capacitance) of the low-potential power supply line WRVSS of the driver. .

Reference sign VDD indicates a high potential power supply line (high potential power supply level), and VSS indicates a low potential power supply line (low potential power supply level). Reference symbol Cd indicates a dummy capacitance added when the value of the capacitance of the node WRVSS (parasitic capacitance C _WRVSS ) is small.

  As described above, the semiconductor memory device includes, for example, an SRAM, but is not limited to this, and may be a nonvolatile memory such as a DRAM. In this specification, a complementary semiconductor memory device is described as an example, but it is needless to say that it may be a single-ended device.

  As shown in FIG. 3, the semiconductor memory device has m + 1 columns, and each column has n + 1 banks. In FIG. 3, as in FIG. 1 described above, the leftmost column (column <m>) indicates the selected column, and the other non-selected columns (columns <0> to <m-1>) are representative. The rightmost column (column <0>) indicates a non-selected column. Here, each column has the same circuit configuration, but in the following description, the selection column will be mainly described.

In the selected column, complementary write data WDX and WD are input to the first input terminals of the three-input NAND gates NAND _m 1 and NAND _m 2, respectively. Note that the write enable signal WEN is input to the second input terminals of the NAND gates NAND _m 1 and NAND _m 2, and the column signal COL <m> is input to the third input terminal.

Here, the NAND gates NAND _m 1 and NAND _m 2, the transistors TP _m 5, TP _m 6, TPL _m , TPR _m , and TN, the inverter INV correspond to the write driver, and the node WRVSS corresponds to the source line of the write driver.

Further, in this embodiment, AND _m 1 and AND _m 2 in FIG. 1 are NAND gates, and therefore, write data WDX of inverted logic is input to NAND _m 1. It goes without saying that various changes can be made.

The column signal COL <m> has pMOS transistors TP _m 1 and TP _m 2 having a source connected to the high potential power supply line (VDD) and a drain connected to the global bit lines GBL <m> and GBLX <m>. The gate is also input.

The connection between the global bit lines GBL <m> and GBLX <m> and the local bit lines of the respective banks 0 to n is controlled by bank column signals GC-0 <m> to GC-n <m>, respectively. Bank selection transistors TP _m0 3 and T _m0 4 to TN _mn 3 and T _mn 4 are provided.

Here, in the embodiment shown in FIG. _{3, TP m0 3, TP m0} 4~TP mn 3, TP mn 4 but there is a pMOS transistor, which, GBL <m>, GBLX of <m>"H Is transmitted to LBL <m> and LBLX <m> without lowering the level.

That is, between the local bit lines LBL <m> and LBLX <m> of the bank n of the column m and the global bit lines GBL <m> and GBLX <m>, the bank column signal GCX-n <m> is supplied to the gate. The input pMOS transistors TP _mn 3 and TP _mn 4 are arranged. Needless to say, an nMOS transistor or a transfer gate can be used instead of the pMOS transistors TP _mn 3 and TP _mn 4.

A plurality of memory cells MC selected by the word line WL are connected to the local bit lines LBL <m> and LBLX <m>, respectively, and a sense amplifier circuit SA controlled by a sense amplifier enable signal LSAE is connected. ing. Further, pMOS transistors TP _mn 1 and TP _mn 2 controlled by a precharge signal PRE are also connected to the local bit lines LBL <m> and LBLX <m>.

  FIG. 4 is a circuit diagram showing an example of a sense amplifier circuit in the semiconductor memory device shown in FIG. As shown in FIG. 4, the sense amplifier circuit SA in FIG. 3 includes pMOS transistors STP1 to STP4, nMOS transistors STN1 to STN7, and inverters SI1 to SI3.

  Here, reference sign WSAE <m> indicates a latch node of the latch circuit formed by the two inverters SI2 and SI3, and a signal of the latch node WSAE <m> is input to the gate of the nMOS transistor STN7.

  The above-described sense amplifier circuit in the semiconductor memory device shown in FIG. 1 corresponds to, for example, the pMOS transistors STP1, STP2 and STN1 to STN4 surrounded by a broken line in FIG. However, in FIG. 4, an nMOS transistor STN4 is added in order to equalize the number of transistors.

  The pMOS transistors STP3 and STP4 and the nMOS transistor STN5 are connected in series between the high potential power supply line VDD and the low potential power supply line VSS, and the bank column signal GCX-n <m> is input to the gate of the transistor STP3. Yes. The precharge signal PRE inverted by the inverter SI1 is input to the gates of the transistors STP4 and STN5.

  The aforementioned latch node WSAE <m> is also a common connection node (drain) of the transistors STP4 and STN5, and the bank column signal GCX-n <m> is also input to the gate of the transistor STN6.

  FIG. 5 is a timing chart for explaining the data write operation of the semiconductor memory device shown in FIG. Here, for example, when the write data WD of the high level “H” is written to the memory cell MC provided between the word line WL and the local bit lines LBL <m> and LBLX <m> in the bank n of the column m. think of.

As shown in FIG. 5, both the column signal COL <m> and the write enable signal WEN are set to “H”, the transistors TP _m 1 and TP _m 2 are both turned off, and the transistor TN is also turned off. Further, the output of NAND _m 1 is “H” and the output of NAND _m 2 is “L”.

As a result, the transistors TP _m 5 and TPR _m are turned off, and the transistors TP _m 6 and TPL _m are turned on. Here, the levels of the global bit lines GBL <m> and GBLX <m> are locally determined via the transistors TP _mn 3 and TP _mn 4 turned on by the “L” bank column signal GCX-n <m>. It is transmitted to the bit lines LBL <m> and LBLX <m>. Further, since the precharge signal PRE is “H”, the transistors TP _mn 1 and TP _mn 2 are turned off.

As described above, in this embodiment, TP _mn 3 and TP _mn 4 are used as pMOS transistors, and GBL <m> and GBLX <m> are set to LBL <m> and LBLX <m> without lowering the level of “H”. Since the information is transmitted, the bank column signal GCX-n <m> having inverted logic is used.

  Here, as shown in FIG. 5, the sense amplifier SA described with reference to FIG. 4 has latch circuits (SI2, SI3), and its latch node WSAE <m> is normally “L”. Yes. When the bank column signal GCX-n <m> of the selected column m becomes “L”, the latch node WSAE <m> changes from “L” to “H”, and the transistor STN7 is turned on.

  However, since GCX-n <m> is “L”, the transistor STN6 is off, and the sense amplifier SA does not start at this point. Therefore, while GCX-n <m> is “L” (before the sense amplifier SA is activated), the bit lines GBL <m>, LBL <m> (GBLX <m>, LBLX <m>) The level is a small amplitude level change due to charge sharing.

  That is, the source node WRVSS of the write driver is normally discharged to the low potential power supply level VSS. When data is written, when WEN, COL <m> and PRE are “H” and GCX-n <m> is “L”, GBL <m> and LBL <m> are “H” (VDD). The WRVSS floats in the state of “L” (VSS).

The total capacity of the bit lines (GBL <m> and LBL <m>) is C _LBL + C _GBL , and the capacity of the node WRVSS is C _WRVSS . And the "L" level in capacitance C _WRVSS, by volume C _LBL + C _GBL at "H" level is connected, the level change of the global bit line GBL <m> (local bit lines LBL <m>), the charge Small amplitude due to share. Here, the small amplitude due to the charge share is, for example, about 1/10 of the full swing of VDD and VSS.

When the write data WD is “L”, the capacity C _{WRVSS of the} node WRVSS and the capacity (GBL <m>, LBL <m>) of the other of the complementary bit lines (GBLX <m>, LBLX <m>). (Same as the capacity of>) Charge sharing by C _LBL + C _GBL occurs.

As described above, by using the charge share to amplify the global bit lines GBL <m> and GBLX <m>, the amount of amplitude can be made constant regardless of the random variation of the transistors. For example, if the minimum amplitude (bit line amplitude) for operating the sense amplifier circuit SA is 10% of VDD, the total capacity of the bit lines (C _GBL + C _LBL ) and the capacity C _WRVSS of the source node of the write driver are: The capacity ratio may be 9: 1.

  Thus, when a small amplitude level change due to charge sharing occurs in GBL <m> (LBL <m>), the bank column signal GCX-n <m> is raised from “L” to “H”, The sense amplifier circuit SA is activated. That is, by setting GCX-n <m> to “H”, the transistor STP3 is turned off and the transistor STN6 is turned on to activate the sense amplifier circuit SA.

  When the sense amplifier circuit SA is activated, the potential of the small amplitude local bit LBL <m> is amplified to full swing (VSS). At this time, by raising the word line WL from “L” to “H”, the memory cell MC between the word line WL and the local bit lines LBL <m>, LBLX <m> is selected, and this memory cell MC Data writing to is performed.

  When the write data WD is “L”, the levels of the complementary global bit lines GBL <m>, GBLX <m> and the local bit lines LBL <m>, LBLX <m> are reversed.

  As the memory cell MC, for example, a general 6-transistor SRAM cell, a 4-transistor SRAM cell in which a load is replaced with a resistance element, or an 8-transistor SRAM cell can be applied. Further, the memory cell MC is not limited to the SRAM cell, but may be a DRAM cell or the like. Further, the global bit line and the local bit line may be complementary (differential), but a single-ended one is also applicable.

  Thus, according to this embodiment, when writing data, a global bit line having a wiring length longer than that of the local bit line and consuming a large amount of power consumes a small amplitude (for example, about 1/10 of the full swing). By handling signals, it is possible to reduce power consumption.

Further, the small amplitude signal of the global bit line includes the capacity of the source node WRVSS (C _WRVSS : first capacity) of the write driver and the total capacity of the bit lines (capacity C _GBL of the global bit line GBL and capacity C of the local bit line LBL). _{It is} generated by the capacity ratio of the sum of _LBL : second capacity). That is, a charge share is generated between the first capacitor C _WRVSS and the second capacitor (C _GBL + C _LBL ), and a global bit line signal (small amplitude signal) is obtained by the capacitance ratio of the first and second capacitors. It is done.

  Then, after transmitting the small amplitude signal of the global bit line to the local bit line, the global bit line is disconnected, the small amplitude signal of the local bit line is amplified using a sense amplifier circuit, and a full swing (amplitude of VDD to VSS) is obtained. Level).

Here, the first capacitor C _WRVSS eliminates an increase in occupied area by using, for example, the wiring capacitance of the node WRVSS and the junction capacitance of the write driver transistors TPL _{m to} TPL ₀ , TPR _{m to} TPR ₀ and the discharge transistor TN. Can do. When the value of the first capacitor C _WRVSS is small, for example, a dummy capacitor Cd is provided at the node WRVSS, or a transistor having a large junction capacitance is applied.

In this way, the capacity C _WRVSS of the source node of the write driver _{can be set} to, for example, about 1/9 of the total capacity of the bit lines (global bit line capacity C _GBL + local bit line capacity C _LBL ). it can.

  As an example, assuming that the number of banks is 8 and the number of columns is 4, the power per bit at the time of data writing is as follows. First, the power consumption of the local bit line will be described. The local bit line of the selected column is discharged by a certain amount using the charge share. However, since this portion does not consume power, the following occurs.

_Assuming that the power consumption of the local bit line is P _LBL , P _LBL = power of the unselected column + power of the selected column. The power P _LBLNSC of the non-selected column is expressed as follows:
P _LBLNSC = C _LBL × VDD ² × (number of columns −1)
= C _LBL × VDD ² × 3

The power P _{LBLSC of the} selected column is expressed as follows.
P _LBLSC = Discharge power + Charge power
= (1/2 × C _LBL × (C _GBL + C _LBL / C _GBL + C _LBL + C _WRVSS )) × VDD ² ) + (1/2 × C _LBL × VDD ² )

Here, the (C _GBL + C _LBL) and the capacitance ratio of C _WRVSS 9: 1 to (if small amplitude of 1/10 of the full swing), so P _LBLSC, P _LBLSC is be expressed as follows it can.
P _LBLSC = (1/2 × C _LBL × 0.9 × VDD ² ) + (1/2 × C _LBL × VDD ² )
= 0.95 x C _LBL x VDD ²

Therefore, the power consumption P _LBL of the local bit line is
P _LBL = (C _LBL × VDD ² × 3) + (0.95 × C _LBL × VDD ² )
= 3.95 x C _LBL x VDD ²

Next, the power consumption of the global bit line will be described. The global bit line is discharged using the charge share like the local bit line. Therefore, power consumption on the global bit line need only be considered during precharge. Accordingly, the global bit line power consumption P _GBL is expressed as follows.
P _GBL = C _GBL × (C _WRVSS / C _GBL + C _LBL + C _WRVSS ) × VDD ² × (1/2)

Here, since the capacity ratio of (C _GBL + C _LBL ) and C _WRVSS is 9: 1, P _GBL can be expressed as follows.
P _GBL = C _GBL × 0.1 × VDD ² × (1/2)

Since the global bit line capacitance C _GBL is about -1 times larger than the local bit line capacitance C _LBL , P _GBL can be expressed as follows.
P _GBL = C _LBL × 7 × 0.1 × VDD ² × (1/2)
= 0.35 x C _LBL x VDD ²

  Next, the power consumption of the source node of the write driver will be described. Since the source node WRVSS of the write driver charges the node using the charge share, power is not consumed when charging. Therefore, it is only necessary to consider when discharging.

The power consumption P _WRVSS of the source node WRVSS of the write driver is expressed as follows.
P _WRVSS = C _WRVSS × (C _GBL + C _LBL / C _GBL + C _LBL + C _WRVSS ) × VDD ² × (1/2)

Here, since the capacity ratio of (C _GBL + C _LBL ) to C _WRVSS is 9: 1, P _WRVSS can be expressed as follows.
_PWRVSS = (1/9) × (C _GBL + C _LBL ) × 0.9 × VDD ² × (1/2)

Since the global bit line capacitance (parasitic capacitance) C _GBL is about -1 times larger than the local bit line capacitance (parasitic capacitance) C _LBL , P _WRVSS can be expressed as follows.
P _WRVSS = (1/9) x C _LBL x 8 x 0.9 x VDD ² x (1/2)
= 0.4 × C _LBL × VDD ²

Therefore, the power consumption P _BL of 1 bit per time of data writing, as follows, with respect to those with reference to FIGS. 1 and 2, it is possible to reduce to about 57.3%.
P _BL = P _LBL + P _GBL + P _WRVSS
= (3.95 + 0.35 + 0.4) × C _LBL × VDD ²
= 4.7 x C _LBL x VDD ²

  Thus, in this embodiment, instead of charging and discharging a large-capacity global bit line with full swing, for example, the source node of a write driver having a capacity of about a fraction of the global bit line is charged and discharged. The power consumption at the time of data writing can be reduced.

  In addition, according to the present embodiment, since the global bit line is amplified using the charge share, the power consumption can be reduced with almost no influence of the random variation of the transistors. Further, since the source node capacitance (transistor junction capacitance) and the source line wiring capacitance of the write driver are mainly used, an area penalty (an increase in occupied area) hardly occurs.

  It should be noted that the semiconductor memory device and the sense amplifier circuit SA described with reference to FIGS. 3 to 5 are merely examples, and it is needless to say that various circuits and signals can be applied.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
Multiple global bit lines,
A plurality of local bit lines connected to each of the global bit lines;
A plurality of memory cells provided between each local bit line and a word line, and a semiconductor memory device,
When writing data to the memory cell,
The global bit line and the local bit line used for writing data in the memory cell are set to a first level,
Data is written to the memory cell by expanding the level of the local bit line to a second level greater than the first level;
A semiconductor memory device.

(Appendix 2)
The first level is defined according to a capacitance ratio of a first capacitance of a wiring that drives the global bit line and a second capacitance obtained by adding the capacitances of both the global bit line and the local bit line.
2. The semiconductor memory device according to appendix 1, wherein:

(Appendix 3)
further,
A sense amplifier circuit that expands the first level of the local bit line to the second level after separating the local bit line from the global bit line;
The semiconductor memory device according to appendix 1 or appendix 2, characterized in that.

(Appendix 4)
The wiring for driving the global bit line is a source line of a write driver.
The semiconductor memory device as set forth in Appendix 2, wherein

(Appendix 5)
further,
Including a dummy capacitor connected to the source line of the write driver;
The semiconductor memory device according to appendix 4, wherein:

(Appendix 6)
The memory cell is a static random accelerator memory cell;
6. The semiconductor memory device according to any one of appendices 1 to 5, wherein

(Appendix 7)
The global bit line and the local bit line are complementary.
The semiconductor memory device according to any one of appendices 1 to 6, wherein

(Appendix 8)
Multiple global bit lines,
A plurality of local bit lines connected to each of the global bit lines;
A method of writing data in a semiconductor memory device having a plurality of memory cells provided between each local bit line and a word line,
The global bit line and the local bit line used for writing data in the memory cell are obtained by adding the first capacitance of the wiring that drives the global bit line and the capacitance of both the global bit line and the local bit line. The first level according to the capacity ratio of the second capacity,
After the local bit line is disconnected from the global bit line, data is written to the memory cell as a second level larger than the first level.
A method of writing data in a semiconductor memory device.

(Appendix 9)
When expanding the local bit line from the first level to the second level, select a word line corresponding to the memory cell to which the data is written, and connect the local bit line to the memory cell;
The data writing method of the semiconductor memory device according to appendix 8, wherein

C _GBL global bit line capacity C _LBL local bit line capacity C _WRVSS driver low potential power line (write driver source line) capacity COL <0> to COL <m> column signal Cd dummy capacity GBL <0>, GBLX <0> to GBL <m>, GBLX <m> Global bit line GC-0 <0> to GC-n <0>,..., GC-0 <m> to GC-n <m> Bank column signal LBL <0>, LBLX <0> to LBL <m>, LBLX <m> Local bit line LSAE Sense amplifier enable signal MC Memory cell PRE Precharge signal SA Sense amplifier circuit TN nMOS transistor TP pMOS transistor VDD High potential power line (high (Potential power level)
VSS Low potential power line (Low potential power level)
WEN Write enable signal WL Word line WRVSS Driver low potential power line (Write driver source line)

Claims (4)

Multiple global bit lines,
A plurality of local bit lines connected to each of the global bit lines;
A plurality of memory cells provided between each local bit line and a word line, and a semiconductor memory device,
When writing data to the memory cell,
The global bit line and the local bit line used for writing data in the memory cell are set to a first level,
Wherein the level of the local bit line, write the data to the memory cell in an enlarged view of a second level greater than said first level,
The first level is defined according to a capacitance ratio of a first capacitance of a wiring that drives the global bit line and a second capacitance obtained by adding the capacitances of both the global bit line and the local bit line .
A semiconductor memory device. further,
A sense amplifier circuit that expands the first level of the local bit line to the second level after separating the local bit line from the global bit line;
The semiconductor memory device according to claim 1 . Multiple global bit lines,
A plurality of local bit lines connected to each of the global bit lines;
A method of writing data in a semiconductor memory device having a plurality of memory cells provided between each local bit line and a word line,
The global bit line and the local bit line used for writing data in the memory cell are obtained by adding the first capacitance of the wiring that drives the global bit line and the capacitance of both the global bit line and the local bit line. The first level according to the capacity ratio of the second capacity,
After the local bit line is disconnected from the global bit line, data is written to the memory cell as a second level larger than the first level.
A method of writing data in a semiconductor memory device. When expanding the local bit line from the first level to the second level, select a word line corresponding to the memory cell to which the data is written, and connect the local bit line to the memory cell;
4. The method of writing data in a semiconductor memory device according to claim 3 , wherein

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