JP5732990B2 - Semiconductor circuit - Google Patents

Description

  The present invention relates to a semiconductor circuit having a test function for performing failure detection.

  There is a semiconductor circuit equipped with a high-speed interface such as a serial-parallel conversion circuit having an actual operating frequency of, for example, 1 GHz or more. In a semiconductor circuit equipped with such a high-speed interface, when testing a high-speed IO (input / output) part and internal circuit during a mass-production test, an expensive mass-production tester is prepared to test the interface at an actual operating frequency. This increases the test cost.

  On the other hand, by mounting a test circuit (BIST [Built-in Self Test] circuit) inside the semiconductor circuit, the semiconductor circuit has been tested at an actual operating frequency. FIG. 4 is a diagram showing a semiconductor circuit equipped with a test circuit, and shows a serial-parallel conversion circuit as an example. The case of having one clock channel 110 and eight data channels 120 (120-1 to 120-8) is illustrated, and each of the data channels 120 converts an input serial data signal into an 8-bit parallel data signal. To serial-parallel conversion. Note that the number of parallel bits and the number of channels are appropriately determined based on the required specifications.

  The clock channel 110 includes a differential clock input buffer 111, a PLL (Phase Locked Loop) circuit 112, and a frequency dividing circuit 113. The differential clock input buffer 111 receives an input clock signal input from the clock input terminal CKI. Based on the output of the differential clock input buffer 111, the PLL circuit 112 generates and outputs an output clock signal multiplied (8 times in this example) with respect to the output. The frequency divider 113 divides the output clock signal output from the PLL circuit 112 (in this example, divided by 8), and outputs an output clock signal generated by the frequency division. The output clock signal output from the frequency dividing circuit 113 is output as the clock signal CKO for the parallel data signal output from the data channel 120.

  Each of the data channels 120 includes a differential data input buffer 121, a random signal generation circuit (pattern generator) 122, a selector 123, a conversion circuit 124, and a signal verification circuit (pattern checker) 125. The differential data input buffer 121 receives a serial data signal input from the data input terminal DTI. The random signal generation circuit 122 generates a test pattern such as PRBS (pseudo random bit sequence) for performing a test. The selector 123 selectively supplies the output of the differential data input buffer 121 or the output of the random signal generation circuit 122 to the conversion circuit 124 according to the operation state (operation mode) of the semiconductor circuit. The conversion circuit 124 converts the serial data signal supplied from the selector 123 into an 8-bit parallel data signal and outputs it using the output clock signal of the PLL circuit 112 and the output clock signal of the frequency divider circuit 113. The signal verification circuit 125 verifies the presence or absence of a failure based on the output of the conversion circuit 124.

  During normal operation, a serial data signal input from the data input terminal DTI is input to the conversion circuit 124 via the differential data input buffer 121 and the selector 123. The input serial data signal is converted into an 8-bit parallel data signal by the conversion circuit 124 and output as a parallel data signal DTO [1: 8]. On the other hand, at the time of the test, the test pattern generated by the random signal generation circuit 122 is input to the conversion circuit 124 via the selector 123 and converted into an 8-bit parallel data signal. Based on the output of the conversion circuit 124, the signal verification circuit 125 verifies the presence or absence of a failure, and the verification result is output as an error flag output ERF.

  In addition, a digital signal processing apparatus has been proposed in which a test pattern generator is formed in a digital signal processing apparatus that processes a digital signal using combinational logic elements and sequential logic elements, and verification is performed using a series of test patterns (for example, Patent Document 1).

JP-A-57-52950

  As shown in FIG. 4, a test circuit (random signal generation circuit 122 and signal verification circuit 125) is mounted inside the semiconductor circuit, so that a test at an actual operation speed can be performed. However, the number of interfaces and the operation speed have been increased, and it is very circuit to install test circuits (random signal generation circuit and signal verification circuit) with about hundreds of flip-flops. Increase the area of the structure and the load of signal wiring. In addition, the number of man-hours for designing a semiconductor circuit including a test circuit increases, and the cost increases. For example, in the configuration shown in FIG. 4, the random signal generation circuit 122 operates at the output clock signal of the PLL circuit 112 and is required to operate at high speed in order to generate a test pattern corresponding to a serial data signal. Is done. Further, since the random signal generation circuit 125 having a circuit scale of about several hundred flip-flops is connected to the clock line that supplies the output clock signal of the PLL circuit 112, the load of the signal wiring increases.

  An object of the present invention is to provide a semiconductor circuit capable of performing a test for detecting a failure with a simple circuit configuration.

According to one aspect of the present invention, a shift register in which N (N is a natural number of 2 or more) first flip-flops that operate with a first clock signal are cascade-connected, and an output of the first flip-flop A semiconductor circuit is provided that includes a verification circuit that detects a failure of a semiconductor circuit based on a signal, a first selector, and a second selector . The first selector has an output terminal connected to the data input terminal of the first flip-flop of the first stage of the shift register, and a signal obtained by logically inverting the output signal of the first flip-flop of the first stage of the shift register during the test. Is output to the shift register, and the input data signal is output to the shift register when the test is not performed. The second selector outputs the input data signal as the first clock signal during the test, and outputs the second clock signal as the first clock signal when not during the test.

  According to the present invention, at the time of testing, a test pattern is generated to detect a failure in a semiconductor circuit by outputting a signal logically inverted with respect to the output signal of the first flip-flop at the first stage of the shift register to the shift register. Such a test can be conducted. Therefore, a test for detecting a failure can be performed with a simple circuit configuration without mounting a test circuit having a large circuit scale.

It is a figure which shows the structural example of the semiconductor circuit in embodiment of this invention. It is a figure showing an example of composition of a semiconductor circuit which has a plurality of data channels in this embodiment. It is a timing chart explaining the test operation in this embodiment. It is a figure which shows an example of the semiconductor circuit which mounts a test circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
As the failure of the flip-flop in the semiconductor circuit, it is considered that there is a failure related to timing such as setup time and hold time, and a failure related to logic such as no data transition from input to output or penetration. Therefore, when a circuit such as a shift register composed of flip-flops or a serial-parallel conversion circuit using the same is tested, a random pattern is not used as a test pattern, such as “010101. Fault detection is possible with a test pattern in which 1 is repeated. The semiconductor circuit according to the embodiment of the present invention described below enables a test for detecting a failure in a semiconductor circuit without using a random signal generation circuit and a signal verification circuit as shown in FIG. is there.

  FIG. 1 is a diagram illustrating a configuration example of a semiconductor circuit according to an embodiment of the present invention, and illustrates a serial-parallel conversion circuit having a shift register as an example. FIG. 1 shows one clock channel 10 and one data channel 20 in a semiconductor circuit. The data channel 20 serial-parallel converts an input serial data signal into an 8-bit parallel data signal.

  The clock channel 10 includes a differential clock input buffer 11, a PLL (Phase Locked Loop) circuit 12, and a frequency divider circuit 13. The differential clock input buffer 11 receives a clock signal input from the clock input terminal CKI. Based on the output of the differential clock input buffer 11, the PLL circuit 12 generates and outputs an output clock signal SGB multiplied (8 times in the example shown in FIG. 1). The frequency divider 13 receives a clock signal CLK output from a selector 23 described later. The frequency dividing circuit 13 divides the clock signal CLK (divided by 8 in the example shown in FIG. 1), and outputs an output clock signal CDIV generated by the frequency division. Although not shown, the output clock signal CDIV output from the frequency divider circuit 13 is output as a clock signal for a parallel data signal output from the data channel 20.

  The data channel 20 includes a differential data input buffer 21, selectors 22 and 23, a conversion circuit 24, and a verification circuit 25. The differential data input buffer 21 receives a serial signal input from the data input terminal DTI.

  The selector 22 selects the output SGA of the differential data input buffer 21 or the / Q output BS2A of the flip-flop FF1A according to the test pattern enable signal TPE, and outputs it as the output S1A to the D input of the flip-flop FF1A. The test pattern enable signal TPE is set to “0” during normal operation and set to “1” during testing (in test mode). The selector 22 outputs the output SGA of the differential data input buffer 21 as the output S1A during normal operation, and outputs the / Q output BS2A of the flip-flop FF1A as the output S1A during the test (during test mode).

  The selector 23 selects the output clock signal SGB of the PLL circuit 12 or the output SGA of the differential data input buffer 21 according to the clock selection signal CSEL and outputs it as the clock signal CLK. The selector 23 outputs the output clock signal SGB of the PLL circuit 12 as the clock signal CLK if the clock selection signal CSEL is “0”, and the output of the differential data input buffer 21 if the clock selection signal CSEL is “1”. SGA is selected and output as a clock signal CLK.

  The conversion circuit 24 converts the output S1A from the selector 22 into an 8-bit parallel signal using the clock signal CLK output from the selector 23 and the output clock signal CDIV from the frequency dividing circuit 13, and outputs the signal. The conversion circuit 24 includes a flip-flop FFiA that operates with the clock signal CLK (i is a subscript, i = 1 to 8 is a natural number, the same applies to the following), and a flip-flop FF (i + 1) that operates with the minute clock signal CDIV. B.

  The flip-flop FFiA is cascade-connected so that the Q input SiA of the flip-flop FF (i−1) A (however, the output S1A of the selector 22 is input to the D input of the flip-flop FF1A) is input to the D input. . The flip-flop FF (i + 1) B receives the Q output S (i + 1) A of the flip-flop FFiA at its D input. That is, the vertically connected flip-flops FFiA constitute a shift register that shifts data by the clock signal CLK. Further, the flip-flop FF (i + 1) B latches the Q output S (i + 1) A of the flip-flop FFiA constituting the shift register with the clock signal CDIV. The Q output S (i + 1) B of the flip-flop FF (i + 1) B is output from the output terminal as the data signal DTO [i]. The / Q output BS2A of the flip-flop FF1A is output from the output terminal as the output signal CHK [1].

  The verification circuit 25 verifies whether or not there is a failure in the conversion circuit 24 to be tested. The verification circuit 25 includes an exclusive OR operation circuit (EOR circuit) LG (i + 1), LGP, flip-flops FF (i + 1) C, FFP, and an inverter 26. The EOR circuit LG (i + 1) receives the Q output S (i + 1) B of the flip-flop FF (i + 1) B of the conversion circuit 24 and the / Q output BS2A of the flip-flop FF1A, and outputs the calculation result. The EOR circuit LGP receives the / Q output BS2A of the flip-flop FF1A and the Q output S9A of the flip-flop FF8A, and outputs the calculation result.

  The flip-flops FF (i + 1) C and FFP operate with the clock signal CDIV supplied via the inverter 26. In the flip-flop FF (i + 1) C, the output of the EOR circuit LG (i + 1) is input to its D input, and its Q output is output from the output terminal as the output signal ERF [3]. The flip-flop FFP receives the output of the EOR circuit LGP at its D input, and outputs its Q output as an output signal ERF [2] from its output terminal.

Next, the operation will be described.
<During normal operation>
During normal operation, both the test pattern enable signal TPE and the clock selection signal CSEL are set to “0”. Therefore, the selector 22 outputs the output SGA of the differential data input buffer 21, that is, the serial signal input from the data input terminal DTI, to the conversion circuit 24 as the output S1A. The selector 23 outputs a clock signal multiplied by 8 as the clock signal CLK with respect to the output clock signal SGB of the PLL circuit 12, that is, the clock signal input from the clock input terminal CKI.

  The conversion circuit 24 sequentially shifts the output S1A of the selector 22 by the flip-flop FFiA constituting the shift register using the clock signal CLK. Further, the flop FF (i + 1) B of the conversion circuit 24 latches the Q output S (i + 1) A of the flip-flop FFiA with the clock signal CDIV, and outputs it from the output terminal as the data signal DTO [i]. In this way, the serial signal input from the data input terminal DTI is serial-parallel converted to an 8-bit parallel data signal DTO [1: 8] and output.

<During testing (in test mode)>
During the test (in the test mode), both the test pattern enable signal TPE and the clock selection signal CSEL are set to “1”. Therefore, the selector 22 outputs the / Q output BS2A of the first flip-flop FF1A in the flip-flop FFiA constituting the shift register in the conversion circuit 24 to the conversion circuit 24 as an output S1A. The selector 23 outputs the output SGA of the differential data input buffer 21, that is, the signal (test clock signal) input from the data input terminal DTI as the clock signal CLK.

  Thereby, in the shift register constituted by the flip-flop FFiA of the conversion circuit 24, a signal (a signal that changes in a toggle shape) that repeats 0 and 1 alternately every cycle of “010101...” And the clock signal CLK. Propagate. In the present embodiment, failure detection in the conversion circuit 24 is performed using this signal as a test pattern. Further, the flop FF (i + 1) B of the conversion circuit 24 latches the Q output S (i + 1) A of the flip-flop FFiA constituting the shift register with the clock signal CDIV and outputs it as the output S (i + 1) B to the verification circuit 25. . The verification circuit 25 verifies the presence or absence of a failure in the conversion circuit 24 using the outputs BS2A, S9A, S (i + 1) B, etc. from the conversion circuit 24.

  In the example shown in FIG. 1, the following verification can be performed. In addition, the verification method demonstrated below is an example, Comprising: It is not limited to this. By appropriately configuring the verification circuit 25 according to the function to be verified, verifications other than the functions shown below are possible.

(1) The output signal CHK [1] output from the output terminal is compared with the expected value using an LSI tester or the like. As a result, it is possible to confirm at the output terminal whether or not a signal that changes as “010101...” As a test pattern is correctly generated, that is, whether or not the first-stage frequency divider is operating correctly.

(2) In the verification circuit 25, the EOR circuit LGP compares the expected value of the / Q output BS2A of the flip-flop FF1A of the conversion circuit 24 and the Q output S9A of the flip-flop FF8A. In the example shown in FIG. 1, the verification circuit 25 compares the expected value at the timing when the output clock signal CDIV of the frequency divider circuit 13 falls, and outputs the result as an output signal ERF [2] from the output terminal. Thereby, it can be confirmed whether or not the signal “010101...” Is correctly propagating in the shift register including the flip-flop FFiA of the conversion circuit 24, that is, whether or not the shift register is operating. .

(3) In the verification circuit 25, the EOR circuit LG (i + 1) compares the Q output S (i + 1) B of the flip-flop FF (i + 1) B of the conversion circuit 24 with the / Q output BS2A of the flip-flop FF1A. . In the example shown in FIG. 1, the verification circuit 25 compares the expected value at the timing when the output clock signal CDIV of the frequency divider circuit 13 falls, and outputs the result as an output signal ERF [3] from the output terminal. Thereby, it can be confirmed whether or not the parallel signal is correctly generated in the conversion circuit 24, that is, whether or not the conversion to the 8-bit parallel signal is correctly performed.

  FIG. 3 is a timing chart for explaining the test operation in the present embodiment. The signal names shown in FIG. 3 correspond to the clock signal and the output of each flip-flop shown in FIG. Based on the clock signal CLK output from the selector 23, a clock signal CDIV divided by 8 and an output BS2A serving as reference data are generated. The expected value comparison in the verification circuit 25 for detecting the failure in the conversion circuit 24 is performed using the output BS2A, the output S9A, and the outputs S2B to S9B using the falling edge with reference to the clock signal CDIV of the frequency divider circuit 13. Done in In the example shown in FIG. 3, at the time T12 when the clock signal CDIV of the frequency divider circuit 13 falls, the expected value comparison is performed between the output BS2A and the outputs S9A and S3B, S5B, S7B, and S9B. Note that the expected value comparison between the output BS2A and the outputs S2B, S4B, S6B, and S8B is performed at the next falling edge of the clock signal CDIV of the frequency divider circuit 13.

  FIG. 2 is a diagram illustrating a configuration example of a semiconductor circuit having a plurality of data channels in the present embodiment. In FIG. 2, a serial-parallel conversion circuit having one clock channel 10 and eight data channels 20-1 to 20-8 is shown as an example. Each of the data channels 20-1 to 20-8 corresponds to the data channel 20 shown in FIG. 1 and serial-parallel converts an input serial data signal into an 8-bit parallel data signal.

  The clock channel 10 includes a differential clock input buffer 11, a PLL circuit 12, and a frequency divider circuit 13. Each of the data channels 20-1 to 20-8 includes a differential data input buffer 21, selectors 22 and 23, a conversion circuit 24, and a verification circuit 25. The constituent elements of the clock channel 10 and the data channels 20-1 to 20-8 correspond to the constituent elements of the clock channel 10 and the data channel 20 shown in FIG. The description is omitted.

  According to the present embodiment, during a test for detecting a failure of the conversion circuit 24 having a shift register and performing serial-parallel conversion (during test mode), the D input of the first flip-flop FF1A in the shift register is used. The / Q output BS2A is supplied. As a result, a signal that alternately repeats 0 and 1 for each cycle of “010101...” And the clock signal CLK is generated as a test pattern, and verification related to failure detection of the conversion circuit 24 is performed using this test pattern. As a result, it is possible to generate a test pattern by controlling the input to the shift register without mounting a test circuit (random signal generation circuit and signal verification circuit) having a circuit scale of about several hundred flip-flops. it can. Therefore, a test for detecting a failure can be performed with a simple circuit configuration without increasing the area on the circuit configuration, the load on the signal wiring, and the design man-hours. The verification circuit can also be realized with a simple circuit configuration of an EOR circuit and a flip-flop without using a complicated circuit.

  A selector 23 is provided for outputting the output clock signal SGB of the PLL circuit 12 or the output SGA of the differential data input buffer 21 as the clock signal CLK. During the test (in the test mode), the output SGA of the differential data input buffer 21 is provided. Is output as the clock signal CLK. Thus, a test can be performed using a signal input from the data input terminal DTI as a test clock, and a test at an arbitrary operation speed can be performed. For example, it is possible to perform a test by operating at a lower speed than the actual operation speed, or to control the execution or stop of the operation arbitrarily by controlling the supply / stop of the clock signal during the test. become. In the test (in the test mode), by setting the clock selection signal CSEL to “0”, the test at the actual operation speed using the output clock signal SGB of the PLL circuit 12 becomes possible. When only the test at the actual operation speed is performed, the output clock signal SGB of the PLL circuit 12 may be supplied as the clock signal CLK without providing the selector 23.

  In the test (in the test mode), the / Q output BS2A is supplied to the D input of the first flip-flop FF1A in the shift register. However, the present invention is not limited to this. A signal that is logically inverted every cycle of the clock signal CLK may be input to the D input of the flip-flop FF1A. For example, the Q output S2A of the flip-flop FF1A is logically inverted by an inverter and input to the D input. . In the example shown in FIG. 1, the output of the flip-flop FF1A is supplied to the D input via the selector 22, but a delay circuit that gives a delay may be provided as appropriate as a countermeasure against the hold.

  In addition, although a serial-parallel conversion circuit that converts an input serial data signal into an 8-bit parallel data signal is shown as an example of the semiconductor circuit in the present embodiment, the number of parallelization bits is limited to this. Instead, it is determined as appropriate based on the required specifications. If the number of bits for parallelization is N bits (N is a natural number of 2 or more), N flip-flops constitute a shift register, and the output of each flip-flop is operated by the output clock signal CDIV of the frequency divider 13. It is only necessary to latch with N flip-flops. At this time, the PLL circuit 12 generates and outputs an output clock signal SGB multiplied by N with respect to the output of the differential clock input buffer 11, and the frequency dividing circuit 13 divides the clock signal CLK by N and outputs it. What is necessary is just to output as a clock signal CDIV. Further, the number of data channels included in the semiconductor circuit is not limited to the illustrated one, and is appropriately determined based on the required specifications.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 10 Clock channel 11 Differential clock input buffer 12 PLL circuit 13 Dividing circuit 20 Data channel 21 Differential data input buffer 22, 23 Selector 24 Conversion circuit 25 Verification circuit FF1A-FF8A, FF2B-FF9B, FF2C-FF9C, FFP flip-flop LG2 to LG9, LGP Exclusive OR operation circuit (EOR circuit)

Claims (4)

A semiconductor circuit having a test function for performing failure detection,
A shift register in which N (N is a natural number of 2 or more) first flip-flops that are operated by a first clock signal are cascade-connected;
A verification circuit for detecting a failure of the semiconductor circuit based on an output signal of the first flip-flop;
The output terminal is connected to the data input terminal of the first flip-flop of the first stage of the shift register, and at the time of testing, a signal obtained by logically inverting the output signal of the first flip-flop of the first stage of the shift register A first selector that outputs an input data signal to the shift register when not in the test ;
A second selector for outputting the input data signal as the first clock signal during the test and for outputting a second clock signal as the first clock signal when not during the test; A semiconductor circuit. A frequency dividing circuit that divides the first clock signal by N to generate and output a third clock signal;
The output terminal of one corresponding first flip-flop among the N first flip-flops is connected to the data input terminal, and the output signal of the first flip-flop is generated using the third clock signal. N second flip-flops that latch
2. The semiconductor circuit according to claim 1, wherein the verification circuit detects a failure of the semiconductor circuit based on an output signal of the first flip-flop and an output signal of the second flip-flop. Based on the input clock signal, a phase locked loop circuit for outputting as said second clock signal and generates a clock signal by N multiplied to the input clock signal,
Said second selector, wherein in response to the selection control signal, characterized by the Turkey be output as the input data signal and the second of said first clock signal by selecting one of the clock signal Item 3. The semiconductor circuit according to Item 1 or 2.   3. The semiconductor circuit according to claim 2, further comprising a plurality of data processing units each including the shift register, the verification circuit, the first selector, and the N second flip-flops.

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