JP5667868B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for forming an opening in a thin film and a method for manufacturing a semiconductor device. Note that in this specification, a semiconductor device refers to a semiconductor element itself or a device including a semiconductor element, and examples of such a semiconductor element include a transistor (such as a thin film transistor). A display device such as a liquid crystal display device is also included in the semiconductor device.

  In recent years, semiconductor devices have become indispensable for human life. A semiconductor element such as a thin film transistor included in such a semiconductor device is manufactured by forming a thin film on a substrate and processing the thin film into a desired shape by a photolithography method or the like. Such a manufacturing method is also applied to, for example, a liquid crystal display device (for example, a liquid crystal television). In the photolithography method, reducing the number of masks is important for simplifying the process. Therefore, many technical developments have been made in order to reduce the number of masks in the manufacturing process (for example, Patent Document 1).

  In Patent Document 1, using the first resist mask on the first thin film, the first thin film is etched to form a first thin film layer, the first resist mask is removed, A second thin film is formed on the first thin film layer, a second resist mask is formed on the second thin film, and the second resist mask on the second thin film is used to form the second thin film. A technique for reducing the number of photomasks by etching the thin film to form a second thin film layer and forming the first resist mask and the second resist mask with the same photomask is disclosed. ing.

JP 2009-246348 A JP 2006-113571 A

  12A and 12B illustrate an example of a cross-sectional view of a conventional inverted staggered thin film transistor provided in a liquid crystal display device. In the thin film transistor illustrated in FIG. 12A, a gate electrode layer 502 is provided over a substrate 500, a gate insulating layer 504 is provided to cover the gate electrode layer 502, and a semiconductor layer 506 having a depression is formed over the gate insulating layer 504. An impurity semiconductor layer 508 which is provided and does not overlap with the concave portion is provided over the semiconductor layer 506, and a source electrode and a drain electrode layer in which the conductive layer 510 and the conductive layer 512 are stacked in contact with at least part of the impurity semiconductor layer 508 516 is provided, a protective insulating layer 518 is provided to cover the gate insulating layer 504, the semiconductor layer 506, the impurity semiconductor layer 508, the source and drain electrode layers 516, and the pixel electrode layer 522 is provided over the protective insulating layer 518. The conductive layer 512 and the pixel electrode layer 522 are connected to each other through the opening 520.

  However, in the structure shown in FIG. 12A, when the layer exposed in the opening 520 is an Al layer and the pixel electrode layer 522 is, for example, an ITO (indium tin oxide) layer, the Al layer and the ITO The layers come into contact with each other, and galvanic corrosion occurs (see, for example, paragraph [0007] of Patent Document 2). Accordingly, there is a problem that the contact resistance at the opening is very high in this case as well.

In view of the above problems, the Ti layer is not exposed when the recess is formed in the semiconductor layer (in the etching process using CF ₄ gas), and the Ti layer is exposed after the recess is formed in the semiconductor layer. The Ti layer may be connected to the ITO layer. As the thin film transistor having such a structure, a thin film transistor illustrated in FIG.

  In the thin film transistor illustrated in FIG. 12B, a gate electrode layer 602 is provided over a substrate 600, a gate insulating layer 604 is provided to cover the gate electrode layer 602, and a semiconductor layer 606 having a depression is formed over the gate insulating layer 604. A source electrode and a drain electrode layer in which an impurity semiconductor layer 608 which is provided and does not overlap with the concave portion is provided over the semiconductor layer 606, and in which the conductive layer 610 and the conductive layer 612 are stacked in contact with at least part of the impurity semiconductor layer 608 616, a protective insulating layer 618 is provided to cover the gate insulating layer 604, the semiconductor layer 606, the impurity semiconductor layer 608, the source and drain electrode layers 616, and a pixel electrode layer 622 is provided over the protective insulating layer 618. The conductive layer 610 has a region where the conductive layer 612 is not provided, and the conductive layer 610 and the pixel electrode layer 622 are It is connected via the mouth 620.

  However, when the thin film transistor illustrated in FIG. 12B is manufactured, the number of masks used for forming a region where the conductive layer 612 is not provided over the conductive layer 610 is increased by one.

  Thus, one embodiment of the present invention provides a method for forming an opening in an insulating film over a conductive layer so that the conductive layer under the stacked structure is exposed without increasing the number of photomasks. Is an issue.

  An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device having a structure in which a conductive layer under a stacked structure is exposed without increasing the number of photomasks.

  In one embodiment of the present invention, the lower conductive layer of the stacked structure where the opening is provided is exposed in advance using an etching mask formed using the same photomask as the photomask for forming the opening, Thereafter, a protective insulating film is formed, and an opening is formed in the protective insulating film so that the conductive layer above the stacked structure is not exposed in the opening. Such a method for forming an opening can be applied to a method for manufacturing a semiconductor device.

  According to one embodiment of the present invention, a first conductive film and a second conductive film are formed over a substrate, a first etching mask is formed over the second conductive film, and the first etching mask is used. The second conductive film is etched to form a conductive layer, the first etching mask is removed, an insulating film is formed over the first conductive film and the conductive layer, and the insulating film is formed over the insulating film. A second etching mask is formed, an opening is formed in the insulating film using the second etching mask, and the first etching mask and the second etching mask are formed by the same photomask. This is a method for forming an opening.

  According to one embodiment of the present invention, a first conductive film and a second conductive film are formed over a substrate, a first etching mask is formed over the second conductive film, and the first etching mask is reduced. A reduced first etching mask is formed, and the second conductive film is etched using the reduced first etching mask to form a conductive layer, and the reduced first etching mask is formed. The etching mask is removed, an insulating film is formed on the first conductive film and the conductive layer, a second etching mask is formed on the insulating film, and the insulating film is formed using the second etching mask. An opening is formed in the film, and the first etching mask and the second etching mask are formed by the same photomask.

  In the method of forming an opening having the above structure, the first etching mask is a resist mask, and the reduced first etching mask is formed by ashing the first etching mask with oxygen plasma. It is preferable.

  According to one embodiment of the present invention, a first conductive layer is formed by processing a first conductive film using a first etching mask, the first etching mask is removed, and the first conductive layer is formed. Forming a gate insulating layer over the substrate, forming a semiconductor film and a second etching mask on the gate insulating layer, and processing the semiconductor film using the second etching mask to form a thin film stack And removing the second etching mask, forming a second conductive film and a third conductive film on the gate insulating layer and the thin film stack, and performing a third etching on the third conductive film. A mask is formed, the third conductive film is processed to reduce the size, an etched third conductive film is formed, the third etching mask is removed, and the etched third conductive film is formed. Form a fourth etching mask on top The second conductive film and the etched third conductive film are processed using the fourth etching mask to form a second conductive layer and a third conductive layer, and the fourth etching is performed. A thin film transistor having a semiconductor layer is formed by processing the thin film stack using a mask, the fourth etching mask is removed, a protective insulating film is formed to cover the thin film transistor, and a second insulating film is formed on the protective insulating film. And etching the protective insulating film using the fifth etching mask to expose the second conductive layer while covering the third conductive layer, thereby opening the opening. A protective insulating layer is formed, a fourth conductive film is formed so as to be connected to the second conductive layer through the opening, and the third etching mask and the fifth etching mask are the same. No fu A method for manufacturing a semiconductor device characterized by being formed by mask.

  According to one embodiment of the present invention, a first conductive layer is formed by processing a first conductive film using a first etching mask, the first etching mask is removed, and the first conductive layer is formed. Forming a gate insulating layer over the substrate, forming a semiconductor film and a second etching mask on the gate insulating layer, and processing the semiconductor film using the second etching mask to form a thin film stack And removing the second etching mask, forming a second conductive film and a third conductive film on the gate insulating layer and the thin film stack, and performing a third etching on the third conductive film. Forming a mask, reducing the third etching mask to form a reduced third etching mask, and processing and etching the third conductive film to reduce the third conductive film; Forming the reduced third The etching mask is removed, a fourth etching mask is formed on the etched third conductive film, and the second conductive film and the etched third conductive film are formed using the fourth etching mask. The film is processed to form a second conductive layer and a third conductive layer, and the thin film stack is processed using the fourth etching mask to form a thin film transistor having a semiconductor layer. Removing the etching mask, covering the thin film transistor, forming a protective insulating film, forming a fifth etching mask on the protective insulating film, and processing the protective insulating film using the fifth etching mask; Then, a protective insulating layer having an opening is formed by exposing the second conductive layer while covering the third conductive layer, and is connected to the second conductive layer through the opening. Uni form the fourth conductive layer, the third and the fifth etching mask and the etching mask is a method for manufacturing a semiconductor device characterized by being formed of the same photomask.

  In the method for manufacturing a semiconductor device having the above structure, the third etching mask is a resist mask, and the reduced third etching mask is formed by ashing the first etching mask with oxygen plasma. It is preferable.

  In the method for manufacturing a semiconductor device having the above structure, for example, the second conductive film may be a Ti film, and the third conductive film may be an Al film.

  In the method for manufacturing a semiconductor device having the above structure, for example, the fourth conductive film may be an ITO film.

  Note that in this specification, a “film” refers to a film formed over the entire surface by a CVD method (including a plasma CVD method) or a sputtering method. On the other hand, the term “layer” refers to a layer in which a “film” is processed, or a layer that is formed on the entire surface to be processed and does not require processing. However, “film” and “layer” may be used without particular distinction.

  Note that in this specification, a “photomask” refers to a mask used for photolithography exposure, and an “etching mask” prevents etching of a film formed under the etching mask. A mask layer formed for this purpose. Examples of the etching mask include a resist mask. Note that the term “mask” simply includes both a photomask and an etching mask.

  According to one embodiment of the present invention, an opening can be formed in an insulating film over a conductive layer so that the conductive layer under the stacked structure is exposed without increasing the number of photomasks.

  According to one embodiment of the present invention, a semiconductor device can be manufactured by exposing a lower conductive layer of a stacked structure without increasing the number of photomasks.

4A and 4B illustrate a method for forming an opening which is one embodiment of the present invention. The STEM image of the sample which employ | adopted the process of FIG. 4A and 4B illustrate a method for forming an opening which is one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 6A and 6B illustrate a semiconductor device which is one embodiment of the present invention. 6A and 6B illustrate a semiconductor device which is one embodiment of the present invention. 6A and 6B illustrate a semiconductor device which is one embodiment of the present invention. 8A and 8B illustrate a method for manufacturing a conventional semiconductor device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that the insulating film and the insulating layer may not be illustrated in the top view.

(Embodiment 1)
In this embodiment, a method for forming an opening which is one embodiment of the present invention is described with reference to drawings.

  1A to 1D are diagrams illustrating an outline of a method for forming an opening which is one embodiment of the present invention. 1A to 1D, the first conductive film 102 and the second conductive film 104 are formed over the substrate 100, and the first conductive film 104 is formed over the second conductive film 104. An etching mask 106 is formed (FIG. 1A), and the second conductive film 104 is etched (preferably wet etching) using the first etching mask 106 to form a conductive layer 108 (FIG. 1 ( B)), the first etching mask 106 is removed, an insulating film 110 is formed over the first conductive film 102 and the conductive layer 108 (FIG. 1C), and a second etching mask is formed over the insulating film 110. 112 is formed, and an opening 114 is formed in the insulating film 110 using the second etching mask 112 (FIG. 1D). Here, the first etching mask 106 and the second etching mask 112 are formed using the same photomask. Therefore, the shape of the first etching mask 106 and the shape of the second etching mask 112 are substantially equal.

  The substrate 100 is an insulating substrate. As the substrate 100, for example, a glass substrate, a quartz substrate, a ceramic substrate, or a plastic substrate having heat resistance enough to withstand the processing temperature of the manufacturing process can be used. Note that the substrate 100 may not be a light-transmitting substrate.

  The first conductive film 102 is formed using a conductive material (eg, a metal material or a semiconductor material to which an impurity element of one conductivity type is added), for example, by a sputtering method. Note that the first conductive film 102 may be formed as a single layer or a stack of a plurality of films. The first conductive film 102 is a conductive film that is exposed by subsequent formation of the opening.

  The second conductive film 104 is formed by a sputtering method using a conductive material different from that of the second conductive film 104 (eg, a metal material or a semiconductor material to which an impurity element of one conductivity type is added), for example. To do. Note that the second conductive film 104 may be formed as a single layer or a stack of a plurality of films. The second conductive film 104 is a conductive film that is not exposed by subsequent formation of the opening. That is, the conductive film is not preferably in contact with the conductive film provided in the opening formed later.

  For example, a resist mask may be formed as the first etching mask 106, but is not limited to a specific one as long as it can be used as a mask in an etching process.

  As the insulating film 110, for example, an insulating material (eg, silicon nitride, silicon nitride oxide, silicon oxynitride, or silicon oxide) film may be formed by a plasma CVD method. Note that the insulating film 110 may be formed as a single layer or a stack of a plurality of films.

  The second etching mask 112 can be formed using a material and a method similar to those of the first etching mask 106.

  FIG. 2 shows an example (one side surface) of a STEM image of a sample in which an opening is formed in the thin film in the step shown in FIG. In the sample of FIG. 2, the Ti film is formed on the silicon nitride film, the Al layer is formed on the Ti film, the silicon nitride layer is covered to cover the Al layer, and the silicon nitride layer has an opening. An ITO film is provided in the opening, and the Ti film and the ITO film are in contact with each other in the opening. The Al layer is covered with a silicon nitride layer, and the Al layer and the ITO film are not in contact with each other.

  As shown in FIGS. 1A to 1D, by forming the first etching mask 106 and the second etching mask 112 with the same photomask, the first etching mask 106 and the second etching mask 112 are formed at least without increasing the number of photomasks. An opening 114 can be formed in the insulating film 110 so that one conductive film 102 is exposed.

  However, in the method for forming the opening shown in FIGS. 1A to 1D, the shape of the first etching mask 106 and the shape of the second etching mask 112 are approximately equal, and thus the etching of the second conductive film 104 is performed. Depending on the retreat amount, it may be difficult to completely cover the conductive layer 108 with the insulating film 110.

  Thus, a more preferable embodiment of the method for forming an opening which is one embodiment of the present invention is described with reference to FIGS.

  3A to 3D are diagrams illustrating an outline of a method for forming an opening which is one embodiment of the present invention. 3A to 3D, the first conductive film 102 and the second conductive film 104 are formed over the substrate 100, and the first conductive film 104 is formed over the second conductive film 104. An etching mask 106 is formed, the first etching mask 106 is reduced, and a reduced first etching mask 116 is formed (FIG. 3A), and the reduced first etching mask 116 is used. The second conductive film 104 is etched (preferably wet etching) to form a conductive layer 118 (FIG. 3B), the reduced first etching mask 116 is removed, and the first conductive film 102 is removed. An insulating film 110 is formed over the conductive layer 118 (FIG. 3C), a second etching mask 112 is formed over the insulating film 110, and an opening is formed in the insulating film 110 using the second etching mask 112. 120 To formed (FIG. 3 (D)). Here, the first etching mask 106 and the second etching mask 112 are formed using the same photomask. Therefore, the shape of the first etching mask 106 and the shape of the second etching mask 112 are substantially equal. The opening 120 of FIG. 3 formed in this way can have a larger area than the opening 114 of FIG.

  Note that in the case where the material of the first etching mask 106 is a resist, an ashing process using oxygen plasma may be used to reduce the first etching mask 106. Note that in the step of reducing the first etching mask 106, conditions may be set as appropriate in accordance with the reduction amount of the first etching mask 106.

  Here, since the resist mask used for etching the second conductive film 104 is the reduced first etching mask 116, the area of the exposed portion of the first conductive film 102 is as shown in FIG. It is larger than the area of the exposed part. Accordingly, it becomes easy to completely cover the conductive layer 108 with the insulating film 110 regardless of the etching recession amount of the second conductive film 104.

  As described above, according to this embodiment, an opening is formed in the insulating film on the conductive layer so that the conductive layer below the stacked structure is exposed without increasing the number of photomasks. be able to.

(Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor device which is one embodiment of the present invention will be described with reference to drawings.

  First, the first conductive film 202 is formed over the substrate 200, and the first etching mask 204 is formed over the first conductive film 202 (FIG. 4A).

  The substrate 200 is an insulating substrate. As the substrate 200, for example, a glass substrate, a quartz substrate, a ceramic substrate, or a plastic substrate having heat resistance enough to withstand the processing temperature of the manufacturing process can be used. When the substrate 200 is a glass substrate, a substrate of the first generation (for example, 320 mm × 400 mm) to the tenth generation (for example, 2950 mm × 3400 mm) may be used, but is not limited thereto. Note that the substrate 200 may not be a light-transmitting substrate.

  For example, the first conductive film 202 is formed by a sputtering method using a conductive material (eg, a metal material or a semiconductor material to which an impurity element of one conductivity type is added). Note that the first conductive film 202 may be formed as a single layer or a stack of a plurality of films. For example, a three-layer structure in which an Al film is sandwiched between Ti films may be used (not shown).

  For example, a resist mask may be formed as the first etching mask 204, but is not limited to a specific one as long as it can be used as a mask in an etching process.

  Next, the first conductive film 202 is processed using the first etching mask 204 to form a first conductive layer 206, the first etching mask 204 is removed, and the first conductive layer 206 is covered. A gate insulating layer 208 is formed (FIG. 4B).

  For the gate insulating layer 208, for example, an insulating material (eg, silicon nitride, silicon nitride oxide, silicon oxynitride, or silicon oxide) film may be formed by a plasma CVD method. Note that the gate insulating layer 208 may be a single layer or a stack of a plurality of layers. Here, for example, a two-layer structure in which a silicon oxynitride layer is stacked over a silicon nitride layer is preferable.

  Note that “silicon nitride oxide” has a nitrogen content higher than that of oxygen, and is preferably Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering (HFS). When measured using Hydrogen Forward Scattering Spectrometry), the composition range is 5 to 30 atomic% for oxygen, 20 to 55 atomic% for nitrogen, 25 to 35 atomic% for silicon, and 10 to 30 atomic% for hydrogen. It means what is included.

  Note that “silicon oxynitride” has a composition containing more oxygen than nitrogen, and preferably has a composition range of 50 to 70 oxygen when measured using RBS and HFS. The term “atom percent” includes nitrogen in the range of 0.5 to 15 atom%, silicon in the range of 25 to 35 atom%, and hydrogen in the range of 0.1 to 10 atom%.

  However, when the total of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

  Note that the first conductive layer 206 forms at least a scan line and a gate electrode.

  Note that the first conductive layer 206 may be selectively formed by a droplet discharge method (e.g., an inkjet method) or the like. It is preferable to use a droplet discharge method (for example, an ink jet method) or the like for forming the first conductive layer 206 because the number of masks is reduced by one.

Note that in the case where a crystalline semiconductor film is formed over the gate insulating layer 208, plasma treatment is preferably performed on the gate insulating layer 208 with a gas containing oxygen. Here, examples of the gas containing oxygen include N ₂ O gas. By performing plasma treatment on the gate insulating layer 208 with a gas containing oxygen, the crystallinity of the crystalline semiconductor film formed over the gate insulating layer 208 can be improved.

  Next, a first semiconductor film 210, a second semiconductor film 212, and an impurity semiconductor film 214 are formed over the gate insulating layer 208, and a second etching mask 216 is formed over the impurity semiconductor film 214. (FIG. 4C).

  The first semiconductor film 210 is a semiconductor film that is mostly crystalline. An example of the crystalline semiconductor is a microcrystalline semiconductor. Here, a microcrystalline semiconductor refers to a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). A microcrystalline semiconductor is a semiconductor having a third state which is stable in terms of free energy, is a crystalline semiconductor having a short-range order and lattice distortion, and has a crystal grain size of 2 nm to 200 nm, preferably 10 nm. A semiconductor in which columnar or needle-like crystal grains having a size of 80 nm or more and more preferably 20 nm or more and 50 nm or less are grown in a normal direction with respect to the substrate surface. For this reason, a grain boundary may be formed at the interface between columnar or needle-like crystal grains. Here, the crystal grain size is the maximum diameter of crystal grains in a plane parallel to the substrate surface. In addition, the crystal grain includes an amorphous semiconductor region and a crystallite which is a microcrystal that can be regarded as a single crystal. Note that the crystal grains may have twins.

As the microcrystalline semiconductor, microcrystalline silicon may be used. In microcrystalline silicon which is one of microcrystalline semiconductors, the peak of its Raman spectrum is shifted to a lower wave number side than 520 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm ⁻¹ indicating single crystal silicon and 480 cm ⁻¹ indicating amorphous silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as He, Ar, Kr, or Ne to further promote lattice distortion, stability is improved and a favorable microcrystalline semiconductor film can be obtained.

Note that when the concentrations of oxygen and nitrogen (measured by secondary ion mass spectrometry) contained in the crystalline semiconductor film are lowered and preferably these concentrations are less than 1 × 10 ¹⁸ cm ⁻³ , the crystallinity is increased. be able to.

  Note that the crystalline semiconductor film is preferably formed by a two-stage film formation process. In the two-stage film formation process, for example, in the first stage, a microcrystalline silicon film having a thickness of about 5 nm under a pressure of about 500 Pa. In the second stage, a microcrystalline silicon film having a desired thickness may be formed under a pressure of about 5000 Pa. In the second stage, the flow rate ratio of silane is preferably smaller than that in the first stage so that the conditions are highly diluted.

  The second semiconductor film 212 is a semiconductor film that functions as a buffer layer and is mostly amorphous. Preferably, it has an amorphous semiconductor and a small semiconductor crystal grain, and has an Urbach edge measured by a constant photocurrent method (CPM) or photoluminescence spectroscopy as compared with a conventional amorphous semiconductor. It is a semiconductor film with low energy and a small amount of defect absorption spectrum. Such a semiconductor film has fewer defects than a conventional amorphous semiconductor film, and has an orderly structure in which the level tail at the band edge (mobility edge) of the valence band is steep. It is a high semiconductor film.

The second semiconductor film 212 may contain halogen or nitrogen. When nitrogen is contained, it may be contained as an NH group or NH ₂ group.

  Note that here, the interface region between the first semiconductor film 210 and the second semiconductor film 212 includes a microcrystalline semiconductor region and an amorphous semiconductor region filled between the microcrystalline semiconductor regions. Specifically, a microcrystalline semiconductor region extending in a conical shape from the first semiconductor film 210 and a “film including an amorphous semiconductor” similar to the second semiconductor film 212 are formed.

  In addition, since the buffer layer is provided by the second semiconductor film 212, the off-state current of the transistor can be reduced. In addition, since the interface region includes a microcrystalline semiconductor region extending in a conical shape, resistance in the vertical direction (thickness direction), that is, a source region including the second semiconductor film 212 and the impurity semiconductor film 214 Alternatively, resistance between the drain region and the drain region can be reduced, and the on-state current of the transistor can be increased. That is, as compared with the case where a conventional amorphous semiconductor is applied, a decrease in on-state current can be suppressed while sufficiently reducing off-state current, and switching characteristics of the transistor can be improved.

  Note that in the completed transistor, when the first semiconductor layer formed of the first semiconductor film 210 is thinned, the on-state current is decreased, and when the first semiconductor layer formed of the first semiconductor film 210 is thickened, The contact area between the first semiconductor layer formed by the first semiconductor film 210 and the second conductive layer formed later is increased, and the off-state current is increased. Therefore, in order to increase the on / off ratio, the first semiconductor film 210 is thickened, and further, as will be described later, the thin film stack 218 including the first semiconductor layer formed by the first semiconductor film 210. It is preferable to perform an insulating process on the side wall.

  The microcrystalline semiconductor region is preferably mostly formed of cone-shaped crystal grains whose tips become narrower from the first semiconductor film 210 toward the second semiconductor film 212. Alternatively, most of the crystal grains may have a width that increases from the first semiconductor film 210 toward the second semiconductor film 212.

  In addition, in the interface region, when the microcrystalline semiconductor region is a crystal grain extending in a cone shape whose tip is narrowed from the first semiconductor film 210 toward the second semiconductor film 212, the first semiconductor film The proportion of the microcrystalline semiconductor region is higher on the 210 side than on the second semiconductor film 212 side. The microcrystalline semiconductor region grows in the thickness direction from the surface of the first semiconductor film 210, but the flow rate of hydrogen relative to the deposition gas (eg, silane) in the source gas is small (that is, the dilution rate is low), or When the concentration of the source gas containing nitrogen is high, crystal growth in the microcrystalline semiconductor region is suppressed, the crystal grains have a cone shape, and the deposited semiconductor is mostly an amorphous semiconductor.

Incidentally, the interface region, nitrogen, it is particularly preferable to contain an NH group or an NH ₂ group. This is because defects at the interface of the crystal included in the microcrystalline semiconductor region, the interface between the microcrystalline semiconductor region and the amorphous semiconductor region, and nitrogen, particularly NH groups or NH ₂ groups, are bonded to dangling bonds of silicon atoms. This is because the number of carriers is reduced and the carrier flows easily. Therefore, when nitrogen, preferably NH group or NH ₂ group, is contained at a concentration of 1 × 10 ²⁰ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ , dangling bonds of silicon atoms are nitrogen, preferably NH groups or easily cross-linked with an NH ₂ group, the carrier is more easily flow. As a result, bonds that promote the movement of carriers at the grain boundaries and defects can be formed, and the carrier mobility in the interface region can be improved. Therefore, the field effect mobility of the transistor is improved.

  Note that by reducing the oxygen concentration in the interface region, the defect density at the interface between the microcrystalline semiconductor region and the amorphous semiconductor region or the interface between crystal grains can be reduced, and bonds that inhibit carrier movement can be reduced. Can do.

  The impurity semiconductor film 214 is formed using a semiconductor to which an impurity element imparting one conductivity type is added. In the case where the transistor is n-type, a semiconductor to which an impurity element imparting one conductivity type is added includes, for example, silicon to which P or As is added. Alternatively, in the case where the transistor is a p-type, for example, B can be added as an impurity element imparting one conductivity type. However, the transistor is preferably n-type. Therefore, here, silicon added with P is used as an example. Note that the impurity semiconductor film 214 may be formed using an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor.

  In the case where the impurity semiconductor film 214 is formed using an amorphous semiconductor, the flow rate of the dilution gas with respect to the flow rate of the deposition gas may be 1 to 10 times, preferably 1 to 5 times. In the case where the impurity semiconductor film 214 is formed using a crystalline semiconductor, the flow rate of the dilution gas with respect to the flow rate of the deposition gas may be 10 to 2000 times, preferably 50 to 200 times.

  Note that the gate insulating layer 208 to the impurity semiconductor film 214 are preferably formed successively in the same chamber. This is for preventing impurities from being included in the interface between the gate insulating layer 208 and the impurity semiconductor film 214.

  The second etching mask 216 can be formed using a material and a method similar to those of the first etching mask 204.

  Next, the first semiconductor film 210, the second semiconductor film 212, and the impurity semiconductor film 214 are etched using the second etching mask 216. After that, the second etching mask 216 is removed, whereby the thin film stack 218 can be obtained (FIG. 4D).

  Here, as described above, it is preferable to perform insulation treatment on the sidewall of the thin film stack 218. This is because the off-state current often increases when the first semiconductor layer and the second conductive layer of the completed transistor are in contact with each other. Here, as the insulating treatment, an insulating film is formed with the sidewall of the thin film stack 218 exposed to oxygen plasma or nitrogen plasma, or the sidewall of the thin film stack 218 is exposed, and the insulating film is anisotropically formed. A process of forming a sidewall insulating layer in contact with the sidewall of the thin film stack 218 by performing etching in a direction perpendicular to the surface of the substrate 200 by a high etching method can be given.

  Next, a second conductive film 220 and a third conductive film 222 are formed over the gate insulating layer 208 and the thin film stack 218, and a third etching mask 224 is formed over the third conductive film 222 (FIG. 5 (A)).

  Note that the area of the third conductive film 222 exposed to the third etching mask 224 may be increased by reducing the third etching mask 224. When the exposed area of the third conductive film 222 is enlarged, the side surface and the opening of the third conductive layer 232 formed by the third conductive film 222 when the opening 244 is formed in a later step. A sufficient distance between the two conductive layers 244 can be secured, and the third conductive layer 232 can be prevented from being exposed by the opening 244. Here, in the case where the third etching mask 224 is a resist mask, the third etching mask 224 may be reduced by performing an ashing process.

  The second conductive film 220 is a conductive material film that can be in contact with a fourth conductive film 248 to be formed later. For example, a Ti film is used as the second conductive film 220.

  The third conductive film 222 is a conductive material film that causes inconveniences such as an increase in resistance at the interface when brought into contact with a fourth conductive film 248 to be formed later. For example, an Al film is used as the third conductive film 222.

  The third etching mask 224 can be formed using a material and a method similar to those of the first etching mask 204 and the second etching mask 216.

  Next, the third conductive film 222 is processed to be reduced by wet etching or the like (FIG. 5B). In order to process the third conductive film 222 so as to be reduced, the second conductive film 220 is not only exposed by chemically reacting with the material forming the third conductive film 222 but also etched. The condition that the side surface of the third conductive film 226 is provided inside the side surface of the third etching mask 224 may be employed.

  Here, for example, when the third conductive film 222 is an Al film, a chemical solution containing nitric acid, acetic acid, and phosphoric acid may be used as an etchant.

  Next, the third etching mask 224 is removed, a fourth etching mask 228 is formed, and the second conductive film 220 and the etched third conductive film 226 are processed using the fourth etching mask 228. Thus, the second conductive layer 230 and the third conductive layer 232 are formed. Then, the thin film stack 218 is etched using the fourth etching mask 228 (FIG. 5C). Note that the thin film stack 218 may be etched by removing the fourth etching mask 228 and using the second conductive layer 230 as an etching mask.

  Note that the conductive layer in which the second conductive layer 230 and the third conductive layer 232 are stacked constitutes at least a signal line, a source electrode, and a drain electrode.

  Next, the fourth etching mask 228 is removed, and the protective insulating film 240 and the fifth etching mask 242 are formed (FIG. 6A). Here, the fifth etching mask 242 is formed using the same photomask as the third etching mask 224. Note that the protective insulating film 240 is formed so as to cover at least the exposed portion of the first semiconductor layer 234.

  Next, the protective insulating layer 246 provided with the opening 244 is formed by processing to form the opening 244 in the protective insulating film 240 using the fifth etching mask 242 (FIG. 6B). ).

  Next, a fourth conductive film 248 is formed so as to be electrically connected to the second conductive layer 230 through the opening 244.

  Since the fourth conductive film 248 forms a pixel electrode connected to the pixel transistor, the fourth conductive film 248 is preferably formed using a light-transmitting material.

  The fourth conductive film 248 can be formed using a conductive composition including a light-transmitting conductive polymer (also referred to as a conductive polymer). The fourth conductive film 248 formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less. Note that a so-called π-electron conjugated conductive polymer can be used as the conductive polymer. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

  Alternatively, the fourth conductive film 248 can be formed using, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or indium tin oxide. Indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can be used.

  Note that although not illustrated, an organic resin layer formed by a spin coating method or the like may be provided between the protective insulating layer 246 and the fourth conductive film 248.

  Next, a sixth etching mask 250 is formed over the fourth conductive film 248 (FIG. 6C). The fourth conductive film 248 is etched using the sixth etching mask 250 to form a fourth conductive layer 252 (FIG. 7).

  Note that the fourth conductive layer 252 may be selectively formed by a droplet discharge method (for example, an inkjet method) or the like. It is preferable to use a droplet discharge method (for example, an ink jet method) or the like for forming the fourth conductive layer 252 because the number of masks is reduced by one.

  Note that the thin film transistor of this embodiment described above is a preferable mode and is not limited to this. For example, the first semiconductor film 210 may not be a microcrystalline semiconductor film, and the second semiconductor film 212 may not include microscopic semiconductor crystal grains. Alternatively, the first semiconductor film 210 may not be provided, and the second semiconductor film 212 may be provided over the gate insulating layer 208.

  In this embodiment, silicon is used as a material for forming the crystalline semiconductor layer and the amorphous semiconductor layer; however, the present invention is not limited to this, and the material for forming the crystalline semiconductor layer and the amorphous semiconductor layer is used. Alternatively, an oxide semiconductor may be used.

  Furthermore, the timing at which the third conductive film 222 is processed to form the etched third conductive film is not limited to the above description. That is, the third conductive film 222 is formed (FIG. 5A), a fourth etching mask 228 is formed over the third conductive film 222 (FIG. 8A), and the fourth etching mask 228 is formed. The second conductive film 220 and the third conductive film 222 are processed by using to form the second conductive layer 230 and the third conductive layer 260, and the thin film stack 218 is processed to form a thin film transistor. (FIG. 8B), the fourth etching mask 228 is removed, a third etching mask 224 is formed, and the third conductive layer 260 is processed and etched so as to reduce the third conductive layer 260. 262 may be formed (FIG. 8C), and then the protective insulating film 240 may be formed.

(Embodiment 3)
As a semiconductor device to which the thin film transistor manufactured as described in Embodiment Mode 2 is applied, electronic paper can be given. Electronic paper can be used for electronic devices in various fields as long as they display information. For example, it can be applied to electronic books (electronic books), posters, digital signage, PID (Public Information Display), advertisements in vehicles such as trains, displays on various cards such as credit cards, etc. using electronic paper. . An example of the electronic device is illustrated in FIG.

  FIG. 9 illustrates an example of an electronic book. For example, the electronic book 300 includes two housings, a housing 302 and a housing 304. The housing 302 and the housing 304 are integrated by a shaft portion 314, and can be opened and closed with the shaft portion 314 as an axis. With this configuration, it can be handled in the same way as a paper book.

  A display portion 306 and a photoelectric conversion device 308 are incorporated in the housing 302, and a display portion 310 and a photoelectric conversion device 312 are incorporated in the housing 304. The display unit 306 and the display unit 310 may be configured to display a continuation screen or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, text can be displayed on the right display unit (display unit 306 in FIG. 9), and an image can be displayed on the left display unit (display unit 310 in FIG. 9). .

  FIG. 9 illustrates an example in which the housing 302 includes an operation unit and the like. For example, the housing 302 includes a power source 316, operation keys 318, a speaker 320, and the like. A page can be turned by the operation key 318. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, and the like may be provided on the back and side surfaces of the housing. . Further, the electronic book 300 may have a configuration having a function as an electronic dictionary.

  Further, the e-book reader 300 may be configured to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

(Embodiment 4)
As a semiconductor device to which the thin film transistor manufactured as described in Embodiment 2 is applied, various electronic devices (including game machines) can be used in addition to electronic paper. Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device). ), Large game machines such as portable game machines, portable information terminals, sound reproducing devices, and pachinko machines.

  FIG. 10A illustrates an example of a television device. In the television device 322, a display portion 326 is incorporated in a housing 324. An image can be displayed on the display portion 326. Here, a configuration in which the housing 324 is supported by the stand 328 is illustrated.

  The television device 322 can be operated with an operation switch provided in the housing 324 or a separate remote controller 334. Channels and volume can be operated with operation keys 332 provided on the remote controller 334, and an image displayed on the display portion 326 can be operated. The remote controller 334 may be provided with a display unit 330 that displays information output from the remote controller 334.

  Note that the television set 322 is provided with a receiver, a modem, and the like. General TV broadcasts can be received by a receiver, and connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between each other or between recipients).

  FIG. 10B illustrates an example of a digital photo frame. For example, the display portion 340 is incorporated in the housing 338 of the digital photo frame 336. The display unit 340 can display various images. For example, by displaying image data captured by a digital camera or the like, the display unit 340 can function in the same manner as a normal photo frame.

  Note that the digital photo frame 336 includes an operation unit, an external connection terminal (a terminal that can be connected to various cables such as a USB terminal and a USB cable), a recording medium insertion unit, and the like. These configurations may be incorporated on the same surface as the display portion, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory storing image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 340.

Further, the digital photo frame 336 may be configured to transmit and receive information wirelessly. A configuration may be employed in which desired image data is captured and displayed wirelessly.

  FIG. 11 is a perspective view illustrating an example of a portable computer.

  The portable computer in FIG. 11 overlaps an upper housing 342 having a display portion 346 and a lower housing 344 having a keyboard 348 with a hinge unit connecting the upper housing 342 and the lower housing 344 closed. When the user performs keyboard input, the hinge unit is opened, and an input operation can be performed while viewing the display portion 346.

  In addition to the keyboard 348, the lower housing 344 includes a pointing device 352 that performs an input operation. If the display unit 346 is a touch input panel, an input operation can be performed by touching part of the display unit. The lower housing 344 has a calculation function unit such as a CPU or a hard disk. The lower housing 344 has an external connection port 350 into which another device, for example, a communication cable conforming to the USB communication standard is inserted.

  The upper housing 342 further includes a display portion 354 that can be slid and housed inside the upper housing 342, so that a wide display screen can be realized. Further, the user can adjust the orientation of the screen of the display portion 354 that can be stored. Further, when the storable display unit 354 is a touch input panel, an input operation can be performed by touching a part of the storable display unit.

  As the display portion 346 or the storable display portion 354, a video display device such as a liquid crystal display panel, a light emitting display panel such as an organic light emitting element or an inorganic light emitting element, or the like is used.

  In addition, the portable computer in FIG. 11 includes a receiver and the like, and can receive a television broadcast and display an image on a display portion. In addition, with the hinge unit connecting the upper housing 342 and the lower housing 344 closed, the display unit 354 is slid to expose the entire screen, and the screen angle is adjusted to allow the user to watch TV broadcasting. You can also. In this case, since the hinge unit is closed and the display unit 346 is not displayed and only the circuit for displaying the television broadcast is activated, the power consumption can be minimized and the battery capacity can be limited. It is useful in portable computers that are used.

100 substrate 102 first conductive film 104 second conductive film 106 first etching mask 108 conductive layer 110 insulating film 112 second etching mask 114 opening 116 reduced first etching mask 118 conductive layer 120 opening 200 Substrate 202 First conductive film 204 First etching mask 206 First conductive layer 208 Gate insulating layer 210 First semiconductor film 212 Second semiconductor film 214 Impurity semiconductor film 216 Second etching mask 218 Thin film stack 220 Second conductive film 222 Third conductive film 224 Third etching mask 226 Etched third conductive film 228 Fourth etching mask 230 Second conductive layer 232 Third conductive layer 234 First semiconductor Layer 236 second semiconductor layer 238 impurity semiconductor layer 240 protective insulating film 242 fifth Etching mask 244 Opening 246 Protective insulating layer 248 Fourth conductive film 250 Sixth etching mask 252 Fourth conductive layer 260 Third conductive layer 262 Etched third conductive layer 300 Electronic book 302 Case 304 Case Body 306 Display unit 308 Photoelectric conversion device 310 Display unit 312 Photoelectric conversion device 314 Shaft unit 316 Power supply 318 Operation key 320 Speaker 322 Television device 324 Case 326 Display unit 328 Stand 330 Display unit 332 Operation key 334 Remote controller 336 Digital photo Frame 338 Housing 340 Display portion 342 Upper housing 344 Lower housing 346 Display portion 348 Keyboard 350 External connection port 352 Pointing device 354 Display portion 400 Substrate 402 Gate electrode layer 404 Gate insulating layer 406 Semiconductor layer 408 Pure semiconductor layer 410 Conductive layer 412 Conductive layer 414 Conductive layer 416 Source and drain electrode layer 418 Protective insulating layer 420 Opening 422 Pixel electrode layer 500 Substrate 502 Gate electrode layer 504 Gate insulating layer 506 Semiconductor layer 508 Impurity semiconductor layer 510 Conductive Layer 512 Conductive layer 516 Source and drain electrode layer 518 Protective insulating layer 520 Opening 522 Pixel electrode layer 600 Substrate 602 Gate electrode layer 604 Gate insulating layer 606 Semiconductor layer 608 Impurity semiconductor layer 610 Conductive layer 612 Conductive layer 616 Source electrode and drain Electrode layer 618 Protective insulating layer 620 Opening 622 Pixel electrode layer

Claims (6)

Forming a first conductive film on the substrate;
Forming a second conductive film on the first conductive film;
Forming a first etching mask on the second conductive film;
Reducing the first etching mask to form a reduced first etching mask;
Forming a conductive layer by etching the second conductive film using the reduced first etching mask;
Removing the reduced first etching mask;
An insulating film is formed to cover the front Kishirube conductive layer,
Forming a second etching mask on the insulating film;
Using the second etching mask, forming an opening in the insulating film so as to expose the first conductive film while covering the conductive layer ,
The method for manufacturing a semiconductor device, wherein the first etching mask and the second etching mask are formed using the same photomask. In claim 1 ,
The first etching mask is a resist mask;
The method of manufacturing a semiconductor device, wherein the reduced first etching mask is formed by ashing the first etching mask with oxygen plasma. In claim 1 or claim 2,
Forming a conductive film containing Ti as the first conductive film;
A method for manufacturing a semiconductor device, wherein a conductive film containing Al is formed as the second conductive film. A first conductive layer is formed by processing the first conductive film using the first etching mask,
Removing the first etching mask;
Forming a gate insulating layer over the first conductive layer;
Forming a semiconductor film and a second etching mask on the gate insulating layer;
Processing the semiconductor film using the second etching mask to form a thin film stack;
Removing the second etching mask;
The gate insulating layer and over the thin film laminate, to form a second conductive film having a Ti, and a third conductive film having Al,
Forming a third etching mask on the third conductive film;
Forming a third conductive film etched by processing to reduce the third conductive film;
Removing the third etching mask;
Forming a fourth etching mask on the etched third conductive film;
Processing the second conductive film and the etched third conductive film using the fourth etching mask to form a second conductive layer and a third conductive layer;
A thin film transistor having a semiconductor layer is formed by processing the thin film stack using the fourth etching mask,
Removing the fourth etching mask;
Forming a protective insulating film covering the thin film transistor;
Forming a fifth etching mask on the protective insulating film;
By processing the protective insulating film using the fifth etching mask, the second conductive layer is exposed while covering the third conductive layer to form a protective insulating layer having an opening,
Forming a fourth conductive film containing indium tin oxide or indium zinc oxide so as to be connected to the second conductive layer through the opening;
The method for manufacturing a semiconductor device, wherein the third etching mask and the fifth etching mask are formed using the same photomask. A first conductive layer is formed by processing the first conductive film using the first etching mask,
Removing the first etching mask;
Forming a gate insulating layer over the first conductive layer;
Forming a semiconductor film and a second etching mask on the gate insulating layer;
Processing the semiconductor film using the second etching mask to form a thin film stack;
Removing the second etching mask;
The gate insulating layer and over the thin film laminate, to form a second conductive film having a Ti, and a third conductive film having Al,
Forming a third etching mask on the third conductive film;
Reducing the third etching mask to form a reduced third etching mask;
Forming a third conductive film etched by processing to reduce the third conductive film;
Removing the reduced third etching mask;
Forming a fourth etching mask on the etched third conductive film;
Processing the second conductive film and the etched third conductive film using the fourth etching mask to form a second conductive layer and a third conductive layer;
A thin film transistor having a semiconductor layer is formed by processing the thin film stack using the fourth etching mask,
Removing the fourth etching mask;
Forming a protective insulating film covering the thin film transistor;
Forming a fifth etching mask on the protective insulating film;
By processing the protective insulating film using the fifth etching mask, the second conductive layer is exposed while covering the third conductive layer to form a protective insulating layer having an opening,
Forming a fourth conductive film containing indium tin oxide or indium zinc oxide so as to be connected to the second conductive layer through the opening;
The method for manufacturing a semiconductor device, wherein the third etching mask and the fifth etching mask are formed using the same photomask. In claim 5,
The third etching mask is a resist mask;
The method for manufacturing a semiconductor device, wherein the reduced third etching mask is formed by ashing the first etching mask with oxygen plasma.