JP5662574B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device connected to a semiconductor memory device through a plurality of wirings.

  Semiconductor memory devices such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) are semiconductor memory chips mounted on the surface of a package substrate and sealed with resin. The external terminals are arranged in a matrix. A semiconductor memory chip has a plurality of memory cells, write / read circuits, etc. formed on the surface of a semiconductor substrate, and is connected to a plurality of external terminals via a package substrate. The arrangement pattern of the external terminals of the semiconductor memory device differs depending on the model of the semiconductor memory device (see, for example, Japanese Patent Laid-Open No. 2003-51545 (Patent Document 1)).

  A semiconductor device that controls such a semiconductor memory device is a semiconductor chip mounted on the surface of a package substrate and sealed with resin, and a plurality of external terminals are arranged in a matrix on the back surface of the package substrate. Has been. The semiconductor chip has a memory controller or the like formed on the surface of a semiconductor substrate, and is connected to a plurality of external terminals via a package substrate. The arrangement pattern of the external terminals of the semiconductor device is set according to the arrangement pattern of the external terminals of the semiconductor memory device.

  The semiconductor memory device and the semiconductor device are mounted on one motherboard and constitute one semiconductor module. Each external terminal of the semiconductor memory device is connected to a corresponding external terminal of the semiconductor device via a wiring of the mother board (see, for example, JP 2010-123203 A (Patent Document 2)).

JP 2003-51545 A JP 2010-123203 A

  When a semiconductor module is configured by mounting a semiconductor device and one or more semiconductor memory devices on a single motherboard, the semiconductor device is adapted to the model and number of semiconductor memory devices so that the wiring of the motherboard does not cross each other. It is necessary to optimally design the arrangement pattern of external terminals. However, if the arrangement pattern of the external terminals of the semiconductor device is changed each time the model or number of the semiconductor memory device is changed, there is a problem that the cost of the semiconductor device increases.

  Therefore, a main object of the present invention is to provide a low-cost semiconductor device.

The semiconductor device according to the present invention outputs N (where N is an integer larger than M) signals divided in advance into M (where M is an integer equal to or greater than 2) signal groups. A signal generation circuit, M switching circuits provided corresponding to M signal groups, and N buffer circuits divided into M buffer groups respectively corresponding to M switching circuits; N external terminals provided corresponding to N buffer circuits, respectively. Each signal group includes a plurality of signals, and each buffer group includes the same number of buffer circuits as the signals of the corresponding signal group. Each switching circuit applies the plurality of signals of the corresponding signal group in parallel to the plurality of buffer circuits of the corresponding buffer group in the order corresponding to the mode setting signal. Each buffer circuit of each buffer group applies a signal supplied from a corresponding switching circuit to a corresponding external terminal. The M buffer groups include first and second buffer groups. The buffer circuit of the first buffer group outputs a first logic level signal in response to the reset signal. The buffer circuit of the second buffer group outputs a signal of the second logic level in response to the reset signal.

  In the semiconductor device according to the present invention, the switching circuit applies the plurality of signals generated by the signal generation circuit to the plurality of buffer circuits in parallel in the order corresponding to the mode setting signal. Therefore, since the arrangement pattern of the external terminals can be switched according to the type and number of semiconductor memory devices to be connected, the cost of the device can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of the semiconductor device by Embodiment 1 of this invention, and a semiconductor module using the same. It is a figure which shows the effect of Embodiment 1 shown in FIG. It is another figure which shows the effect of Embodiment 1 shown in FIG. FIG. 2 is a block diagram showing a configuration of a semiconductor chip included in the semiconductor device shown in FIG. 1. FIG. 5 is a block diagram illustrating a configuration of a signal input / output circuit illustrated in FIG. 4. FIG. 6 is a block diagram showing a configuration of a buffer circuit B1 shown in FIG. FIG. 6 is a block diagram showing a configuration of a buffer circuit B3 shown in FIG. FIG. 6 is a block diagram showing a configuration of a buffer circuit B4 shown in FIG. FIG. 3 is a diagram showing an arrangement pattern of external terminals in a first mode and a second mode of the semiconductor device shown in FIG. 1. 10 is a time chart showing the waveform of the signal shown in FIG. 9. 2 is a flowchart showing an operation of the semiconductor device shown in FIG. FIG. 2 is a diagram showing an arrangement pattern of external terminals in a first mode of the semiconductor device shown in FIG. 1. FIG. 2 is a diagram showing an arrangement pattern of external terminals of the semiconductor memory device 3 shown in FIG. 1. It is a figure which shows the 1st layer of the motherboard 4 shown in FIG. It is a figure which shows the 3rd layer of the motherboard 4 shown in FIG. It is a figure which shows the 6th layer of the motherboard 4 shown in FIG. FIG. 4 is a diagram showing an arrangement pattern of external terminals in a second mode of the semiconductor device shown in FIG. 1. FIG. 2 is a diagram showing an arrangement pattern of external terminals of the semiconductor memory device 6 shown in FIG. 1. It is a figure which shows the 1st layer of the motherboard 7 shown in FIG. It is a figure which shows the 3rd layer of the motherboard 7 shown in FIG. It is a figure which shows the 6th layer of the motherboard 7 shown in FIG. It is a figure which shows the structure and usage method of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows the effect of the semiconductor device shown in FIG.

[Embodiment 1]
FIG. 1A is a diagram showing a configuration of a semiconductor device (LSI: Large Scale Integration) 1 according to the first embodiment of the present invention, and FIGS. 1B and 1C are semiconductor modules using the semiconductor device 1, respectively. FIG.

  In FIG. 1A, a semiconductor device 1 has a semiconductor chip mounted on the surface of a package substrate and sealed with resin, and a plurality of external terminals TA are arranged in a matrix on the back surface of the package substrate. Yes. The semiconductor chip has a memory controller or the like formed on the surface of a semiconductor substrate, and is connected to a plurality of external terminals TA through a package substrate.

  In FIG. 1B, the semiconductor module 2 has a semiconductor device 1 and two semiconductor memory devices 3 mounted on the surface of a single motherboard 4. The semiconductor memory device 3 is, for example, a DDR3-SDRAM (Double Data Rate 3-Synchronous Dynamic Random Access Memory). The semiconductor memory device 3 has semiconductor memory chips mounted on the front surface of a package substrate and sealed with resin, and a plurality of external terminals TB are arranged in a matrix on the back surface of the package substrate. The semiconductor memory chip has a plurality of memory cells, write / read circuits, etc. formed on the surface of a semiconductor substrate, and is connected to a plurality of external terminals TB via a package substrate.

  The plurality of external terminals TB of the semiconductor memory device 3 are arranged according to a predetermined arrangement pattern. The arrangement pattern of the external terminals TB of the semiconductor memory device 3 is fixed. That is, the type of signal input to each external terminal TB is fixed. On the other hand, the arrangement pattern of the external terminals TA of the semiconductor device 1 is set according to the arrangement pattern of the external terminals TB of the semiconductor memory device 3 by a built-in switching circuit. That is, the type of signal output from each external terminal TA can be changed by the switching circuit. The switching circuit will be described later.

  A plurality of wirings for connecting the plurality of external terminals TA of the semiconductor device 1 and the plurality of external terminals TB of the semiconductor memory device 3 are formed on the mother board 4. The arrangement pattern of the external terminals TA of the semiconductor device 1 is set so that the wirings of the mother board 4 do not intersect in the same layer. Each external terminal TB of the semiconductor memory device 3 is connected to a corresponding external terminal TA of the semiconductor device 1 through wiring of the mother board 4.

  In FIG. 1C, the semiconductor module 5 is obtained by mounting the semiconductor device 1 and two semiconductor memory devices 6 on the surface of one motherboard 7. The semiconductor memory device 6 is a different type of semiconductor memory device from the semiconductor memory device 3, and is, for example, a DDR2-SDRAM. The semiconductor memory device 6 is a semiconductor memory chip mounted on the surface of a package substrate and sealed with resin, and a plurality of external terminals TC are arranged in a matrix on the back surface of the package substrate. The semiconductor memory chip has a plurality of memory cells, write / read circuits, etc. formed on the surface of a semiconductor substrate, and is connected to a plurality of external terminals TC via a package substrate.

  The plurality of external terminals TC of the semiconductor memory device 6 are arranged according to a predetermined arrangement pattern. The arrangement pattern of the external terminals TC of the semiconductor memory device 6 is fixed and is different from the arrangement pattern of the external terminals TB of the semiconductor memory device 3. On the other hand, the arrangement pattern of the external terminals TA of the semiconductor device 1 is set according to the arrangement pattern of the external terminals TC of the semiconductor memory device 6 by a built-in switching circuit.

  A plurality of wirings for connecting the plurality of external terminals TA of the semiconductor device 1 and the plurality of external terminals TC of the semiconductor memory device 6 are formed on the mother board 7. The arrangement pattern of the external terminals TA of the semiconductor device 1 is set so that the wirings of the mother board 7 do not cross each other. Each external terminal TC of the semiconductor memory device 6 is connected to a corresponding external terminal TA of the semiconductor device 1 through wiring of the mother board 7.

  As described above, in the first embodiment, the pattern arrangement of the external terminals TA of the semiconductor device 1 can be changed according to the model of the semiconductor memory device to be connected, so that the cost of the device and the signal transmission characteristics can be reduced. Improvements can be made.

  2A to 2C are diagrams showing the effects of the first embodiment. FIG. 2A is a view of the semiconductor device 1 and the two semiconductor memory devices 3 as seen from the back side. In FIG. 2A, a plurality of external terminals TA are arranged in a matrix on the rectangular back surface of the semiconductor device 1. A plurality of external terminals TB are arranged in a matrix on the rectangular back surface of each semiconductor memory device 3. One side of the semiconductor device 1 and one side of the two semiconductor memory devices 3 are arranged to face each other.

  Assume that four external terminals TB for signals A1, A2, RAS0, and CAS0 are provided along one side of one of the two semiconductor memory devices 3, respectively. It is assumed that four external terminals TB for signals A5, A6, RAS1 and CAS1 are provided along one side of the other semiconductor memory device 3, respectively.

  In this case, eight external terminals TA for the signals A1, A2, RAS0, CAS0, A5, A6, RAS1, CAS1 are provided along one side of the semiconductor device 1 opposite to one side of the two semiconductor memory devices 3. If provided, the eight external terminals TA of the semiconductor device 1 and the total of eight external terminals TB of the two semiconductor memory devices 3 can be connected by eight wirings LB that do not cross each other.

  FIG. 2B is a view of the semiconductor device 1 and the two semiconductor memory devices 6 as seen from the back side. In FIG. 2B, a plurality of external terminals TA are arranged in a matrix on the rectangular back surface of the semiconductor device 1. A plurality of external terminals TC are arranged in a matrix on the rectangular back surface of each semiconductor memory device 6. One side of the semiconductor device 1 and one side of the two semiconductor memory devices 6 are arranged to face each other.

  Assume that four external terminals TC for signals A2, A1, RAS0, and CAS0 are provided along one side of one of the two semiconductor memory devices 6, respectively. Further, it is assumed that four external terminals TC for signals A6, A5, RAS1, and CAS1 are provided along one side of the other semiconductor memory device 6, respectively.

  In this case, the arrangement pattern shown in FIG. 2A is adopted as the arrangement pattern of the external terminals TA of the semiconductor device 1, and each external terminal TA of the semiconductor device 1 is connected to the corresponding external terminal TC via the wiring LC. Then, as shown in FIG. 2B, the eight wirings LC intersect at four places. When two wirings LC cross each other, it is necessary to pass one wiring LC under the other wiring LC, and the wiring length of one wiring LC is larger than that of the other wiring LC, resulting in transmission characteristics between signals. Deviation (skew) may occur, resulting in deterioration of transmission characteristics.

  In contrast, in the first embodiment, as shown in FIG. 2C, when the semiconductor device 1 and the semiconductor memory device 6 are connected, the built-in switching circuit causes the external terminal TA of the semiconductor device 1 to be connected. Since the arrangement pattern is changed according to the external terminal TC of the semiconductor memory device 6, the crossing of the wiring LC can be eliminated.

  That is, in the first embodiment, when the semiconductor module 2 is configured by the semiconductor device 1 and the two semiconductor memory devices 3, the semiconductor device 1 is set to the first mode by the mode setting signal. The semiconductor device 1 set in the first mode outputs signals A1, A2, RAS0, CAS0, A5, A6, RAS1, and CAS1 from eight external terminals TA facing one side of the two semiconductor memory devices 3, respectively. To do. Therefore, the eight wirings LB can be formed on the mother board 4 without crossing.

  Further, when the semiconductor module 5 is configured by the semiconductor device 1 and the two semiconductor memory devices 6, the semiconductor device 1 is set to the second mode by the mode setting signal. The semiconductor device 1 set to the second mode outputs signals A2, A1, CAS0, RAS0, A6, A5, CAS1, RAS1 from eight external terminals TA facing one side of the two semiconductor memory devices 6, respectively. To do. Therefore, the eight wirings LC can be formed on the mother board 7 without crossing.

  3A and 3B are views of the semiconductor device 1 and the semiconductor memory device 6 as seen from the back side, and are other views showing the effects of the first embodiment. 3A and 3B, a plurality of external terminals TA of the semiconductor device 1 and a plurality of external terminals TC of the semiconductor memory device 6 are connected by a plurality of wirings LC.

  In FIG. 3A, since the arrangement pattern of the external terminals TA of the semiconductor device 1 with respect to the semiconductor memory device 6 is not appropriate, a plurality of wirings LC intersect at a plurality of locations. In the place where the two wirings LC intersect, the two wirings LC cannot be formed in the same wiring layer, and one wiring LC is formed in another wiring layer, and the upper wiring LC and the lower wiring LC. Need to be connected via hole. Therefore, the number of wiring layers increases, resulting in an increase in cost. In addition, since the signal is transmitted through a plurality of via holes, the transmission characteristics are deteriorated. Further, the layout area of the wiring LC increases.

  On the other hand, in the present invention, as shown in FIG. 3B, since the arrangement pattern of the external terminals TA of the semiconductor device 1 with respect to the semiconductor memory device 6 is appropriately set, the wirings LC do not intersect each other. Therefore, the semiconductor module 5 having a low cost, good transmission characteristics, and a small layout area can be configured.

  Hereinafter, the configurations of the semiconductor device 1 and the semiconductor modules 2 and 5 will be described in more detail. FIG. 4 is a block diagram showing a configuration of the semiconductor chip 10 included in the semiconductor device 1. In FIG. 4, the semiconductor chip 10 includes a semiconductor substrate 11. On the semiconductor substrate 11, input terminals TI1, TI2, a plurality of pads P, a system controller (SYSC) 12, a bus 13, a memory controller 14, a selector 15, and a signal input / output circuit 20 are formed.

  The power-on reset signal POR is given to the input terminal TI1 from another semiconductor chip in the semiconductor device 1 or from outside the semiconductor device 1. The power-on reset signal POR is a signal that is activated only for a predetermined period when a power supply voltage is supplied to the semiconductor device 1. A mode setting signal MODE is externally applied to the input terminal TI2. For example, when semiconductor device 1 is set to the first mode, mode setting signal MODE is set to “L” level, and when semiconductor device 1 is set to the second mode, mode setting signal MODE is set to “H” level. Is done. Each pad P is connected to the package substrate via a bonding wire, for example, and further connected to a corresponding external terminal TA via wiring on the package substrate.

  The system controller 12 is reset when the power-on reset signal POR is set to the activation level, and controls the entire semiconductor chip 10 via the bus 13. The memory controller 14 generates a plurality of signals S for controlling the semiconductor memory device in accordance with signals given from the system controller 12 or the like via the bus 13. The plurality of signals S are divided in advance into three signal groups.

  Each of the plurality of signals S1 belonging to the first signal group may be set to any one of “H” level and “L” level when the semiconductor chip 10 is reset by the power-on reset signal POR or the like. Signal. The plurality of signals S1 are specifically address signals A00 to A15 and bank address signals BA0 to BA2.

  Each of the plurality of signals S2 belonging to the second signal group is a signal to be forcibly set to “H” level when the semiconductor chip 10 is reset by the power-on reset signal POR or the like. Specifically, the plurality of signals S2 are chip select signals CSN0 and CSN1, a write enable signal WEN, a column address strobe signal CASN, and a row address strobe signal RASN.

  Each of the plurality of signals S3 belonging to the third signal group is a signal that should be forcibly set to the “L” level when the semiconductor chip 10 is reset by the power-on reset signal POR or the like. Specifically, the plurality of signals S3 are signals ODT0 and ODT1 and a clock enable signal CKE. The plurality of signals S1 in the first signal group, the plurality of signals S2 in the second signal group, and the plurality of signals S3 in the third signal group are supplied to the selector 15.

  The mode setting circuit 14a included in the memory controller 14 generates a selector control signal SE in accordance with a mode setting signal MODE given from the outside via the input terminal TI2. The selector control signal SE is given to the selector 15.

  The selector 15 includes a register 16 and switching circuits 17-19. The register 16 holds the selector control signal SE from the mode setting circuit 14a and supplies the selector control signal SE to each of the switching circuits 17-19. The switching circuit 17 supplies a plurality of signals S1 from the memory controller 14 in parallel to the signal input / output circuit 20 in the order corresponding to the selector control signal SE from the register 16. The switching circuit 18 supplies a plurality of signals S2 from the memory controller 14 in parallel to the signal input / output circuit 20 in the order corresponding to the selector control signal SE from the register 16. The switching circuit 19 supplies a plurality of signals S3 from the memory controller 14 in parallel to the signal input / output circuit 20 in the order corresponding to the selector control signal SE from the register 16.

  The signal input / output circuit 20 transmits a plurality of signals S1, a plurality of signals S2, and a plurality of signals S3 supplied from the memory controller 14 via the selector 15 to the plurality of pads P, respectively. Further, the signal input / output circuit 20 generates clock signals CK and CKN and supplies them to the two pads P.

  That is, as shown in FIG. 5, the signal input / output circuit 20 includes a plurality of buffer circuits B1 provided corresponding to the plurality of signals S1 from the switching circuit 17, and a plurality of signals S2 from the switching circuit 18, respectively. Includes a plurality of buffer circuits B2 provided corresponding to the plurality of signals, a plurality of buffer circuits B3 provided corresponding to the plurality of signals S3 from the switching circuit 19, respectively, a clock generation unit 21, and a buffer circuit B4. .

  The plurality of pads P include a plurality of pads P1 corresponding to the plurality of buffer circuits B1, a plurality of pads P2 corresponding to the plurality of buffer circuits B2, respectively, and a plurality of pads P3 corresponding to the plurality of buffer circuits B3, respectively. And two pads P4A and P4B corresponding to the buffer circuit B4.

  Each buffer circuit B1 transmits the signal S1 from the switching circuit 17 to the corresponding pad P1. Each buffer circuit B2 transmits the signal S2 from the switching circuit 18 to the corresponding pad P2. Each buffer circuit B3 transmits the signal S3 from the switching circuit 19 to the corresponding pad P3. The clock generation unit 21 generates a clock signal CK. The buffer circuit B4 generates a complementary signal CKN of the clock signal CK in response to the clock signal CK from the clock generator 21, and applies the clock signals CK and CKN to the pads P4A and P4B, respectively.

  The buffer circuit B1 corresponding to the signal S1 includes level up shifters (LU) 22, 23, 25, a level down shifter (LD) 24, a buffer 26, and a comparator 27 as shown in FIG. The power supply voltage of memory controller 14 is 1.0 V, for example, and the power supply voltage of semiconductor memory devices 3 and 6 is 1.5 V, for example.

  The level-up shifter 22 converts the logic amplitude voltage of the signal S1 from the memory controller 14 from 1.0V to 1.5V and applies the same to the input node of the buffer 26. Further, when the reset signal RE is set to the “H” level of the activation level, the level up shifter 22 outputs the “H” level signal regardless of the logic level of the signal S1. When the power-on reset signal POR is activated, the reset signal RE is activated.

  The level-up shifter 23 converts the logic amplitude voltage of the output enable signal OEN from 1.0 V to 1.5 V, and supplies it to the control node of the buffer 26. The signal OEN is set to the “L” level of the activation level when the signal S1 is output to the outside, and is set to the “H” level of the inactivation level when the signal S1 is not output to the outside. Further, the level-up shifter 23 outputs the “L” level regardless of the logic level of the signal OEN when the reset signal RE is set to the “H” level of the activation level.

  The buffer 26 is driven at 1.5 V, which is the power supply voltage of the semiconductor memory devices 3 and 6. The buffer 26 outputs the signal S1 to the pad P1 when the output signal 26OEN of the level up shifter 23 is set to the activation level “L”, and the signal 26OEN is set to the deactivation level “H”. In this case, the pad P1 is set to a high impedance state. Therefore, when the reset signal RE is set to the activation level “H” level, the pad P1 is set to the “H” level regardless of the logic levels of the signals S1 and OEN.

  The level-down shifter 24, the level-up shifter 25, and the comparator 27 are used when testing the semiconductor device 1 before shipment, and are not normally used, and thus are indicated by dotted lines.

  The level-up shifter 25 converts the logic amplitude voltage of the input enable signal IE from 1.0 V to 1.5 V, and supplies it to the control node of the comparator 27. The signal IE is set to the activation level “H” level in the test mode, and is set to the deactivation level “L” level in the normal operation. Further, when the reset signal RE is set to the activation level “H” level, the level up shifter 25 outputs the “L” level regardless of the logic level of the signal IE.

  The comparator 27 is driven at 1.5 V, which is the power supply voltage of the semiconductor memory devices 3 and 6. The comparator 27 is activated when the output signal 27IE of the level-up shifter 25 is the “H” level of the activation level, and compares the voltage applied from the outside to the pad P1 and the reference voltage Vref, and compares them. A signal indicating the result is output. When the voltage externally applied to the pad P1 is lower than the reference voltage Vref, the output signal of the comparator 27 becomes “L” level. When the voltage externally applied to pad P1 is higher than reference voltage Vref, the output signal of comparator 27 is at “H” level.

  The level down shifter 24 converts the logic amplitude voltage of the output signal of the comparator 27 from 1.5V to 1.0V to generate the test signal CIN. Further, when the reset signal RE is set to the “H” level as the activation level, the level down shifter 24 outputs the “L” level regardless of the logic level of the signal IE.

  The configuration of the buffer circuit B2 corresponding to the signal S2 is the same as that of the buffer circuit B1 corresponding to the signal S1. Signal S2 is a signal to be set to "H" level when reset. The signal S1 may be either “H” level or “L” level when reset. In the first embodiment, the configuration of the semiconductor device 1 is simplified by configuring the buffer circuits B1 and B2 to have the same configuration.

  The buffer circuit B3 corresponding to the signal S3 is obtained by replacing the level up shifter 22 of the buffer circuit B1 with a level up shifter 28 as shown in FIG. The level-up shifter 28 converts the logic amplitude voltage of the signal S3 from the memory controller 14 from 1.0V to 1.5V and applies the converted voltage to the input node of the buffer 26. Further, when the reset signal RE is set to the “H” level of the activation level, the level up shifter 28 outputs the “L” level signal regardless of the logic level of the signal S3.

  As shown in FIG. 8, the buffer circuit B4 is obtained by replacing the level-up shifter 22 of the buffer circuit B1 with a level-up shifter 29 and adding a buffer 30. The level-up shifter 29 converts the logic amplitude voltage of the clock signal CK from the clock generation unit 21 from 1.0 V to 1.5 V and applies the converted voltage to the input node of the buffer 26. Further, the level up shifter 29 generates a complementary signal CKN of the clock signal CK and supplies it to the input node of the buffer 30. The logic amplitude voltage of the signal CKN is 1.5V. Further, when the reset signal RE is set to the “H” level of the activation level, the level up shifter 29 sets the output clock signals CK and CKN to the “H” level regardless of the logic level of the input clock signal CK. And “L” level.

  The buffers 26 and 30 are driven at 1.5 V, which is the power supply voltage for the semiconductor memory devices 3 and 6. The buffer 26 outputs the clock signal CK to the pad P4A when the output signal 26OEN of the level up shifter 23 is set to the activation level “L”, and the signal 26OEN is set to the deactivation level “H”. If this occurs, the pad P4A is brought into a high impedance state.

  The buffer 30 outputs the signal CKN to the pad P4B when the signal 26OEN is set to the activation level “L”, and the pad P4B when the signal 26OEN is set to the “H” level that is the inactivation level. Into a high impedance state. Therefore, when the reset signal RE is set to the activation level “H” level, the pads P4A and P4B are set to the “H” level and the “L” level, respectively, regardless of the logic level of the input clock signal CK. The

  Returning to FIG. 4, the semiconductor device 1 further includes a USB (Universal Serial Bus) 31, a PCI (Peripheral Component Interconnect) Express 32, a boot ROM (Read Only Memory) 33, a video unit 34, and a CPU (Central Processing Unit) 35. These are connected to the bus 13.

  The USB 31 is a USB standard serial interface. The PCI Express 32 is an input / output interface of the PCI Express standard. A program is stored in the boot ROM 33. The video unit 34 generates image data. The CPU 35 controls the entire semiconductor chip 10 according to the program read from the boot ROM 33.

  The selector control signal SE may be stored in the boot ROM 33, and the selector control signal SE read from the boot ROM 33 when the semiconductor chip 10 is activated may be stored in the register 16 of the selector 15. In this case, the input terminal TI2 for the mode setting signal MODE becomes unnecessary.

  In addition, a power-on reset circuit that generates a power-on reset signal POR in response to the power supply to the semiconductor chip 10 is mounted on the semiconductor chip 10, and the generated signal POR is sent to the system controller 12 and the buffer circuits B1 to B4. May be given. In this case, the input terminal TI1 for the signal POR becomes unnecessary.

  FIG. 9 is a diagram illustrating an arrangement pattern of the external terminals TA in the first mode and the second mode. In FIG. 9, in the first mode, the first group of signals A14, BA1, A12, A6, A11, A15, A10, A1, A4 are output to the first to ninth external terminals TA, respectively, and from the 20th to 29th. The first group of signals BA2, BA0, A3, A9, A0, A13, A5, A7, A2, A8 are output to the second external terminal TA, respectively.

  On the other hand, in the second mode, the first group of signals A3, A6, A11, A13, A8, A0, A2, A15, A4 are output to the first to ninth external terminals TA, respectively, and from the 20th to 29th. The first group of signals BA2, BA1, A9, A14, BA0, A10, A12, A5, A1, A7 are output to the second external terminal TA, respectively. As described above, the signals A0 to A15 and BA0 to BA2 of the first group are output to the external terminals TA of Nos. 1 to 9 and 20 to 29, and 1 to 9 depending on whether the mode is the first mode or the second mode. , 20 to 29, the order of the signals A0 to A15 and BA0 to BA2 output to the external terminals TA is changed. In other words, the order (arrangement pattern) of the external terminals TA to which the signals A0 to A15 and BA0 to BA2 are output is changed depending on whether the mode is the first mode or the second mode.

  In the first mode, the second group of signals CSN1, CSN0, WEN, CASN, and RASN are output to the 10th, 12th, 15th, and 19th external terminals TA, respectively. On the other hand, in the second mode, the second group of signals CASN, CSN1, CSN0, RASN, and WEN are output to the 10th, 12th, 15th, and 19th external terminals TA, respectively. In this way, the second group of signals CSN1, CSN0, WEN, CASN, and RASN are output to the 10th, 12th, 15th, and 19th external terminals TA, and whether the first mode or the second mode is 10 The order of the signals CSN1, CSN0, WEN, CASN, and RASN output to the -12th, 15th, and 19th external terminals TA is changed. In other words, the order (arrangement pattern) of the external terminals TA to which the signals CSN1, CSN0, WEN, CASN, and RASN are output is changed depending on whether the mode is the first mode or the second mode.

  In the first mode and the second mode, the third group of signals ODT0, ODT1, and CKE are output to the 13th, 14th, and 18th external terminals TA, respectively. Here, it is exemplified that there is no need to change the order of the signals ODT0, ODT1, and CKE of the third group. Note that the switching circuit 19 can change the order of the signals ODT0, ODT1, and CKE of the third group.

  In the first mode and the second mode, the fourth group of clock signals CK and CKN are output to the 16th and 17th external terminals TA, respectively. The clock signals CK and CKN are complementary signals generated based on the signal from the clock generation unit 21 and serve as a differential clock that determines a reference timing for operating the DDR2-SDRAM and the DDR3-SDRAM. Therefore, the clock signals CK and CKN are set to a fourth group different from the signals of the first to third groups, and the order of the clock signals CK and CKN by the selector 15 is not changed.

  FIGS. 10A to 10G are time charts illustrating level changes of the 16, 17, 1, 10, and 13th external terminals TA16, TA17, TA1, TA10, and TA13 in the first mode and the second mode. is there. In the power-on reset period, the external terminals TA16, TA1, and TA10 are all fixed at “H” level, and the external terminals TA17 and TA13 are fixed at “L” level. When the power-on reset period ends (time t0), clock signals CK and CKN are output to the external terminals TA16 and TA17, respectively.

  When the power-on reset period ends in the first mode (time t0), the signals A14, CSN1, and ODT0 are output to the external terminals TA1, TA10, and TA13, respectively, in synchronization with the clock signals CK and CKN. The semiconductor memory device 3 latches the signals A14, CSN1, and ODT0 in synchronization with the rising edge of the clock signal CK.

  Further, when the power-on reset period ends in the second mode (time t0), the signals A3, CASN, and ODT0 are output to the external terminals TA1, TA10, and TA11 in synchronization with the clock signals CK and CKN, respectively. The semiconductor memory device 6 latches the signals A3, CASN, and ODT0 in synchronization with the rising edge of the clock signal CK.

  FIG. 11 is a flowchart showing the operation of the semiconductor device 1. In FIG. 11, when a power supply voltage is applied to the semiconductor device 1, a power-on reset is started in step ST1. In step ST2, the reset signal RE is set to the “H” level of the activation level, and the buffer circuits B1 to B4 are reset. That is, the output signals of the buffer circuits B1 and B2 are fixed to “H” level, the output signal of the buffer circuit B3 is fixed to “L” level, and the output signals CK and CKN of the buffer circuit B4 are respectively set to “H” level and Fixed to “L” level. After the power-on reset state has elapsed for a predetermined time, the power-on reset is completed in step ST3.

  In step ST4, the mode setting circuit 14a determines whether the semiconductor device 1 is set to the first mode or the second mode. When determining that the semiconductor device 1 is set to the first mode, the mode setting circuit 14a generates a selector control signal SE for setting the selector 15 to the first mode and stores the selector control signal SE in the register 16 in step ST5. When the selector control signal SE for the first mode is stored in the register 16, an array pattern for DDR3-SDRAM is formed by the switching circuits 17-19. The memory controller 14 performs an initialization process for the DDR3-SDRAM in step ST6, and then starts normal access to the DDR3-SDRAM in step ST9.

  If it is determined in step ST4 that the semiconductor device 1 is set to the second mode, the mode setting circuit 14a generates a selector control signal SE for setting the selector 15 in the second mode and stores it in the register 16 in step ST7. Store. When the selector control signal SE for the second mode is stored in the register 16, an array pattern for DDR2-SDRAM is formed by the switching circuits 17-19. In step ST8, the memory controller 14 performs initialization processing for DDR2-SDRAM, and then starts normal access to DDR2-SDRAM in step ST9.

  Next, the arrangement pattern of the external terminals TA of the semiconductor device 1, the arrangement pattern of the external terminals TB and TC of the semiconductor memory devices 3 and 6, and the wirings LB and LC of the mother boards 4 and 7 will be specifically described. FIG. 12 is a diagram showing an arrangement pattern of the external terminals TA of the semiconductor device 1 in the first mode. In FIG. 12, the semiconductor device 1 includes a plurality of external terminals TA arranged in 5 rows (A to E rows) and 25 columns. Here, only the external terminal TA related to the present invention will be described.

  The signals A14, BA1, A12 of the first group G1 are output to the external terminals TA of the ninth to BDth rows, respectively. The signals A6, A11, A15, and A10 of the first group G1 are output to the external terminals TA in the 10th column A to D rows, respectively. The signals A1, A4 of the first group G1 and the signal CSN1 of the second group G2 are output to the external terminals TA of the A, B, D rows in the eleventh column, respectively. The signals CSN0 and WEN of the second group G2 and the signals ODT0 and ODT1 of the third group G3 are output to the external terminals TA in the A to D rows of the twelfth column, respectively. The signal CASN of the second group G2 and the signals CK and CKN of the fourth group are output to the external terminals TA of the A, C, and D rows in the 13th column, respectively.

  The signal CKE of the third group G3, the signal RASN of the second group G2, and the signals BA2 and BA0 of the first group G1 are output to the external terminals TA in the A to D rows of the 14th column, respectively. The signals A3, A9, A0 of the first group G1 are output to the external terminals TA of the 15th column A, B, D rows, respectively. The signals A13, A5, A7, and A2 of the first group G1 are output to the external terminals TA in the 16th column of the A to D rows, respectively. The signal A8 and the reset signal RESETN of the first group G1 are output to the external terminals TA in the 17th column B and C rows, respectively. In addition, VSS and VSSQ are ground voltages, VCCQ is a power supply voltage, and VREF is a reference voltage.

  FIG. 13 is a diagram showing an arrangement pattern of the external terminals TB of the semiconductor memory device 3 (DDR3-SDRAM). In FIG. 13, the semiconductor memory device 3 includes a plurality of external terminals TB arranged in 16 rows (A to H, J to N, P, R, and T rows) and 6 columns (1 to 3, 7 to 9 columns). including. Here, only the external terminal TB related to the present invention will be described.

  Note that the arrangement pattern of the external terminals TB varies depending on the number of data inputs / outputs of the SDRAM. FIG. 13 shows a case where the number of data inputs / outputs is 16 (DQU 0 to 7, DQL 0 to 7). When the number of data input / output is 8 or less, there are no 3 rows A row to C row, 13 rows (D to H, J to N, P, R, T rows), 6 columns (1 to 3, 7 to 9 columns) (patterned with a dotted line in FIG. 13).

  Further, in the DDR3-SDRAM arrangement pattern, the external terminals TB of T row 3 column, T row 7 column, and M row 7 column may be NC (No connection) in some cases. However, when the number of data inputs / outputs is 8 or less, these external terminals TB are used for inputting address signals A13 to A15, respectively. FIG. 13 shows a case where external terminals TB of T rows 3 columns, T rows 7 columns, and M rows 7 columns are used for input of signals A13 to A15.

  The external terminal TB in the Kth row in the first column receives the signal ODT. The external terminals TB in the second row L to N, P, R, and T rows receive signals CSN, BA0, A3, A5, A7, and RESETN, respectively. J to N, P, R, and T in the third column receive signals RASN, CASN, WEN, BA2, A0, A2, A9, and A13, respectively. The external terminals TB in the seventh to Jth rows of J to L, N, P, R, and T receive signals CK, CKN, A10, A15, A12, A1, A11, and A14, respectively. The external terminals TB in the N, P, R, and T rows in the eighth column receive signals BA1, A4, A6, and A8, respectively. The external terminal TB in the ninth row, K row receives the signal CKE.

  14 to 16 are diagrams showing the first, third, and sixth layers of the mother board 4, respectively. The first layer is the surface of the mother board 4, a third layer is provided below the first layer, and a sixth layer is provided below the third layer. On the first layer of the mother board 4, that is, on the surface of the mother board 4, as shown in FIG. 14, a rectangular area 1A on which the semiconductor device 1 is mounted and two rectangular areas 3A and 3B on which two semiconductor memory devices 3 are mounted. And are provided.

  The short side and long side of the rectangular area 1A are directed in the X direction and the Y direction in FIG. 14, respectively. The short side and the long side of each of the rectangular regions 3A and 3B are directed to the Y direction and the X direction, respectively. The rectangular area 1A is arranged on the left side in FIG. 14, the rectangular area 3A is arranged on the upper right side in FIG. 14, and the rectangular area 3B is arranged on the lower right side in FIG. The rectangular areas 1A, 3A, and 3B are arranged with a predetermined gap therebetween.

  The rectangular area 1A is provided with a plurality of electrodes 41 corresponding to the external terminals TA of 5 rows (A to E rows) and 25 columns. Each electrode 41 is soldered to a corresponding external terminal TA of the semiconductor device 1 mounted in the rectangular area 1A. A plurality of electrodes 42 are distributed in the rectangular area 1A. Each electrode 42 is connected to the adjacent electrode 41 by wiring.

  The rectangular region 3A is provided with a plurality of electrodes 43 corresponding to external terminals TB of 16 rows (A to H, J to N, P, R, T rows) and 7 columns (1 to 3, 7 to 9 columns). It has been. Each electrode 43 is soldered to a corresponding external terminal TB of the semiconductor memory device 3 mounted in the rectangular area 3A. A plurality of electrodes 44 are distributed in the rectangular area 3A. Each electrode 44 is connected to the adjacent electrode 43 by wiring.

  In addition, 28 electrodes 45 are arranged in a staggered pattern in the X direction so as to cross the short side opposite to the rectangular region 1A of the two short sides of the rectangular region 3A. The 14 electrodes 45 in the lower row in FIG. 14 and the 14 electrodes 43 in the 1st to 3rd rows of the rectangular area 3A are connected by 14 wires. The 14 electrodes 45 are connected to electrodes 43 for signals A7, RESETN, A5, A13, A9, A3, A2, A0, BA0, BA2, WEN, ODT, CASN, and RASN from the right side in FIG. .

  The 14 electrodes 45 in the upper row in FIG. 14 and the 14 electrodes 43 in the 2nd to 7th to 9th rows in the rectangular area 3A are connected by 14 wires. The 14 electrodes 45 are connected to the electrodes 43 for signals A8, A14, A6, A11, A1, A4, A12, BA1, CSN, A15, A10, CKE, CKN, and CK from the right side in FIG. .

  The rectangular region 3B is provided with a plurality of electrodes 46 corresponding to external terminals TB of 16 rows (A to H, J to N, P, R, T rows) and 7 columns (1 to 3, 7 to 9 columns). It has been. Each electrode 46 is soldered to a corresponding external terminal TB of the semiconductor memory device 3 mounted in the rectangular area 3B. A plurality of electrodes 47 are distributed in the rectangular area 3B. Each electrode 47 is connected to the adjacent electrode 46 by wiring.

  In addition, 28 electrodes 48 are arranged in a staggered pattern in the X direction so as to cross the short side opposite to the rectangular region 1A of the two short sides of the rectangular region 3B. The 14 electrodes 48 in the lower row in FIG. 14 and the 14 electrodes 46 in the 1st to 3rd rows of the rectangular region 3B are connected by 14 wires. The 14 electrodes 48 are connected to electrodes A7, RESETN, A5, A13, A9, A3, A2, A0, BA0, BA2, WEN, ODT, CASN, and RASN from the right side in FIG. .

  The 14 electrodes 48 in the upper row in FIG. 14 and the 14 electrodes 46 in the 2nd to 7th rows in the rectangular area 3A are connected by 14 wires. The 14 electrodes 48 are connected to the electrodes 46 for signals A8, A14, A6, A11, A1, A4, A12, BA1, CSN, A15, A10, CKE, CKN, and CK from the right side in FIG. .

  In addition, 28 electrodes 49 are arranged at an intermediate position between the 28 electrodes 45 and the 28 electrodes 48. The 28 electrodes 49 are arranged in a staggered pattern in the X direction, like the electrodes 45 and 48. In FIG. 14, seven electrodes 49 out of the fourteen electrodes 49 in the lower column and the seven electrodes 41 in the A row and the B row of the rectangular region 1A are connected by seven wires. The seven electrodes 49 of No. 3 to 6, 11, 13, and 14 from the right side in FIG. 14 are connected to electrodes 41 for signals A5, A13, A9, A3, WEN, CASN, and RASN, respectively.

  In FIG. 14, eight electrodes 49 of the fourteen electrodes 49 in the upper column and the eight electrodes 41 in the A and B rows of the rectangular area 1A are connected by eight wires. The eight electrodes 49 of Nos. 1 to 6, 9, and 12 from the right side in FIG. 14 are electrodes 41 for signals A8, A14, A6, A11, A1, A4, CSN0, and CKE from the right side in FIG. Connected.

  In FIG. 14, among the wirings between the electrodes 41 and 49, the first group signal wiring is shown by a solid line, the second group signal wiring is shown by a one-dot chain line, and the third group signal wiring is shown. This wiring is indicated by a dotted line.

  Further, as shown in FIG. 15, the third layer of the mother board 4 is provided with rectangular regions 1B, 3C, 3D facing the rectangular regions 1A, 3A, 3B of the first layer, respectively. In the rectangular region 1B, an electrode 52 is provided to face each electrode 42 of the first layer, and each electrode 52 is connected to the corresponding electrode 42 through a via hole.

  In the rectangular region 3C, electrodes 54 are provided to face the respective electrodes 44 of the first layer, and each electrode 54 is connected to the corresponding electrode 44 through a via hole. Further, an electrode 55 is provided to face each electrode 45 of the first layer, and each electrode 55 is connected to a corresponding electrode 45 through a via hole.

  In the rectangular region 3D, electrodes 57 are provided to face the respective electrodes 47 of the first layer, and each electrode 57 is connected to the corresponding electrode 47 through a via hole. Further, electrodes 58 are provided to face the respective electrodes 48 of the first layer, and each electrode 58 is connected to the corresponding electrode 48 through a via hole. Further, an electrode 59 is provided to face each electrode 49 of the first layer, and each electrode 59 is connected to the corresponding electrode 49 through a via hole. In addition, each electrode 59 is connected to an electrode 55 adjacent in the Y direction by wiring, and is connected to an electrode 58 adjacent in the Y direction by wiring.

  For example, the electrode 41 for signal A8 in B row and 17 column in FIG. 14 is connected to an electrode 49 through a wiring, and the electrode 49 is connected to an electrode 59 in FIG. 15 through a via hole. The electrode 59 is connected to an electrode 55 through a wiring, the electrode 55 is connected to an electrode 45 in FIG. 14 through a via hole, and the electrode 45 is connected to an electrode 43 for signal A8 in T row and 8 column. . As a result, the address signal A8 output from the B row and 17 column external terminal TA of the semiconductor device 1 is transmitted to the T row and 8 column external terminal TB of the semiconductor memory device 3.

  Further, as shown in FIG. 16, the sixth layer of the mother board 4 is provided with rectangular regions 1C, 3E, 3F facing the rectangular regions 1B, 3C, 3D of the third layer, respectively. In the rectangular region 1C, electrodes 62 are provided to face the respective electrodes 52 of the third layer, and each electrode 62 is connected to the corresponding electrode 52 through a via hole.

  In the rectangular area 3E, electrodes 64 are provided to face the respective electrodes 54 of the third layer, and each electrode 64 is connected to the corresponding electrode 54 through a via hole. Further, an electrode 65 is provided to face each electrode 55 of the third layer, and each electrode 65 is connected to the corresponding electrode 55 through a via hole.

  Further, in the rectangular area 3F, an electrode 67 is provided to face each electrode 57 of the third layer, and each electrode 67 is connected to the corresponding electrode 57 through a via hole. Further, an electrode 68 is provided to face each electrode 58 of the third layer, and each electrode 68 is connected to a corresponding electrode 58 through a via hole. Further, an electrode 69 is provided to face each electrode 59 of the third layer, and each electrode 69 is connected to the corresponding electrode 59 through a via hole.

  In FIG. 16, seven electrodes 69 out of the fourteen electrodes 69 in the lower row and the seven electrodes 62 in the rectangular region 1C are connected by seven wires. The seven electrodes 69 of Nos. 1, 2, 7 to 10 and 12 from the right side in FIG. 16 are connected to the electrodes 62 for signals A7, RESETN, A2, A0, BA0, BA2 and ODT0, respectively.

  Six electrodes 69 of the fourteen electrodes 69 in the upper row in FIG. 16 and the six electrodes 62 in the rectangular region 1C are connected by six wires. Six electrodes 69 of Nos. 7, 8, 10, 11, 13, and 14 from the right side in FIG. 16 are respectively connected to electrodes 62 for signals A12, BA1, A15, A10, CKN, and CK from the right side in FIG. Connected.

  For example, the electrode 41 for signal A12 in D row and 9 column in FIG. 14 is connected to the adjacent electrode 42 through the wiring, and the electrode 42 is connected to the electrode 62 in FIG. 16 through the via hole, the electrode 52, and the via hole. Connected. The electrode 62 is connected to the electrode 69 through a wiring, and the electrode 69 is connected to the electrode 59 in FIG. 15 through a via hole. The electrode 59 is connected to an electrode 55 through a wiring, the electrode 55 is connected to an electrode 45 in FIG. 14 through a via hole, and the electrode 45 is connected to an electrode 43 for signal A12 in N rows and 7 columns. . As a result, the address signal A12 output from the external terminal TA of D row and 9 columns of the semiconductor device 1 is transmitted to the external terminal TB of N rows and 7 columns of the semiconductor memory device 3.

  FIG. 17 is a diagram showing an arrangement pattern of the external terminals TA of the semiconductor device 1 in the second mode. In FIG. 17, the semiconductor device 1 includes a plurality of external terminals TA arranged in 5 rows (A to E rows) and 25 columns. Here, only the external terminal TA related to the present invention will be described.

  The signals A3, A6, A11 of the first group G1 are output to the external terminals TA in the ninth to BD rows, respectively. The signals A13, A8, A0, A2 of the first group G1 are output to the external terminals TA in the 10th column of the A to D rows, respectively. The signals A15 and A4 of the first group G1 and the signal CASN of the second group G2 are output to the external terminals TA of the A, B, and D rows in the eleventh column, respectively. The signals CSN1 and CSN0 of the second group G2 and the signals ODT0 and ODT1 of the third group G3 are output to the external terminals TA of the A to D rows of the twelfth column, respectively. The signal RASN of the second group G2 and the signals CK and CKN of the fourth group are output to the external terminals TA of the A, C, and D rows in the 13th column, respectively.

  The signal CKE of the third group G3, the signal WEN of the second group G2, and the signals BA2 and BA1 of the first group G1 are output to the external terminals TA in the A to D rows of the 14th column, respectively. The signals A9, A14, BA0 of the first group G1 are output to the external terminals TA of the 15th column A, B, D rows, respectively. The signals A10, A12, A5, A1 of the first group G1 are output to the external terminals TA of the 16th column A to D rows, respectively. The signal A7 of the first group G1 is output to the external terminal TA in the Bth row of the 17th column. In addition, VSS and VSSQ are ground voltages, VCCQ is a power supply voltage, and VREF is a reference voltage.

  FIG. 18 is a diagram showing an arrangement pattern of the external terminals TC of the semiconductor memory device 6 (DDR2-SDRAM). In FIG. 18, the semiconductor memory device 6 includes a plurality of external terminals TC arranged in 15 rows (A to H, J to N, P, and R rows) and 6 columns (1 to 3, 7 to 9 columns). . Here, only the external terminal TC related to the present invention will be described.

  Note that the arrangement pattern of the external terminals TC varies depending on the number of data inputs / outputs of the SDRAM. FIG. 18 shows a case where the number of data input / output is 16 (DQ0 to 15). When the number of data input / output is 8 or less, there are no four rows A to D, 11 rows (E to H, J to N, P, and R rows), 6 columns (1 to 3, 7 to 9 columns) ) (An area surrounded by a dotted line in FIG. 18).

  Further, in the DDR3-SDRAM arrangement pattern, the external terminals TC of the 3, 7, and 8 columns in the R rows may be NC. However, when the number of data inputs / outputs is 8 or less, these external terminals TC are used for inputting address signals A14, A15, A13, respectively. FIG. 18 shows a case where the external terminals TC of the third, seventh, and eighth columns in the R row are used for inputting signals A14, A15, and A13.

  The external terminal TC in the L row of the first column receives the signal BA2. The external terminals TC in the second column K to N, P, R rows receive signals CKE, BA0, A10, A3, A7, A12, respectively. The external terminals TC of K to N, P, and R in the third column receive signals WEN, BA1, A1, A5, A9, and A14, respectively. The external terminals TC in the 7th column of K to N, P, and R rows receive signals RASN, CASN, A2, A6, A11, and A15, respectively. The external terminals TC in the eighth to Jth rows, Nth, Pth, and Rth rows respectively receive signals CK, CKN, A0, A4, A8, and A13. The external terminal TC in the Kth row in the ninth column receives the signal ODT.

  19 to 21 are diagrams showing the first, third, and sixth layers of the mother board 7, respectively. The first layer is the surface of the mother board 7, the third layer is provided below the first layer, and the sixth layer is provided below the third layer. On the first layer of the mother board 7, that is, on the surface of the mother board 7, as shown in FIG. 19, a rectangular area 1A in which the semiconductor device 1 is mounted and two rectangular areas 6A and 6B in which two semiconductor memory devices 6 are mounted. And are provided.

  The short side and long side of the rectangular area 1A are directed to the X direction and the Y direction in FIG. 19, respectively. The short side and the long side of each of the rectangular regions 6A and 6B are directed to the Y direction and the X direction, respectively. The rectangular area 1A is arranged on the left side in FIG. 19, the rectangular area 6A is arranged on the upper right side in FIG. 19, and the rectangular area 6B is arranged on the lower right side in FIG. The rectangular areas 1A, 6A, and 6B are arranged with a predetermined gap therebetween.

  The rectangular area 1A is provided with a plurality of electrodes 71 corresponding to the external terminals TA of 5 rows (A to E rows) and 25 columns. Each electrode 71 is soldered to a corresponding external terminal TA of the semiconductor device 1 mounted in the rectangular area 1A. A plurality of electrodes 72 are distributed in the rectangular area 1A. Each electrode 72 is connected to the adjacent electrode 71 by wiring.

  The rectangular area 6A is provided with a plurality of electrodes 73 corresponding to external terminals TB of 15 rows (A to H, J to N, P, and R rows) and 7 columns (1 to 3, 7 to 9 columns). Yes. Each electrode 73 is soldered to a corresponding external terminal TC of the semiconductor memory device 6 mounted in the rectangular area 6A. A plurality of electrodes 74 are dispersedly arranged in the rectangular area 6A. Each electrode 74 is connected to the adjacent electrode 73 by wiring.

  In addition, 25 electrodes 75 are arranged in a staggered pattern in the X direction so as to cross the short side opposite to the rectangular region 1A of the two short sides of the rectangular region 6A. The 13 electrodes 75 in the lower row in FIG. 19 and the 13 electrodes 73 in the first to third rows in the rectangular area 6A are connected by 13 wires. Thirteen electrodes 75 are connected to electrodes 73 for signals A3, A7, A12, A10, A14, A9, A5, A1, BA0, BA1, BA2, WEN, and CKE from the right side in FIG.

  The 12 electrodes 75 in the upper row in FIG. 19 and the 12 electrodes 73 in the 7th to 9th rows in the rectangular area 6A are connected by 12 wires. The twelve electrodes 75 are respectively connected to the electrodes 73 for signals A8, A13, A2, A15, A11, A6, A0, A2, CSN0, CASN, ODT0, and RASN from the right side in FIG.

  The rectangular region 6B is provided with a plurality of electrodes 76 corresponding to the external terminals TB of 15 rows (A to H, J to N, P, R rows) and 7 columns (1 to 3, 7 to 9 columns). Yes. Each electrode 76 is soldered to a corresponding external terminal TC of the semiconductor memory device 6 mounted in the rectangular area 6B. A plurality of electrodes 77 are distributed in the rectangular area 6B. Each electrode 77 is connected to an adjacent electrode 76 by wiring.

  Further, 25 electrodes 78 are arranged in a staggered pattern in the X direction so as to cross the short side opposite to the rectangular area 1A of the two short sides of the rectangular area 6B. The 13 electrodes 78 in the lower row in FIG. 19 and the 13 electrodes 76 in the first to third rows of the rectangular region 6B are connected by 13 wires. Thirteen electrodes 78 are connected to electrodes 76 for signals A3, A7, A12, A10, A14, A9, A5, A1, BA0, BA1, BA2, WEN, and CKE from the right side in FIG.

  The 12 electrodes 78 in the upper row in FIG. 19 and the 12 electrodes 76 in the 7th to 9th rows in the rectangular area 6A are connected by 12 wires. The twelve electrodes 78 are connected to electrodes 76 for signals A8, A13, A2, A15, A11, A6, A0, A2, CSN0, CASN, ODT0, and RASN from the right side in FIG.

  In addition, 25 electrodes 79 are arranged at an intermediate position between the 25 electrodes 75 and the 25 electrodes 78. The 25 electrodes 79 are arranged in a staggered pattern in the X direction, like the electrodes 75 and 78. In FIG. 19, seven of the thirteen electrodes 79 in the lower column and the seven electrodes 71 in the A and B rows of the rectangular region 1A are connected by seven wires. The seven electrodes 79 of Nos. 1 to 6, 12, and 13 from the right side in FIG. 19 are connected to electrodes 71 for signals A3, A7, A12, A10, A14, A9, WEN, and CKE, respectively.

  In FIG. 19, six electrodes 79 out of the twelve electrodes 79 in the upper column and the six electrodes 71 in the A row and the B row in the rectangular area 1A are connected by six wires. 19 are connected to the electrodes 71 for signals A8, A13, A2, A15, CSN0, and RASN from the right side in FIG. 19, respectively.

  In FIG. 19, the first group of signal wires among the wires between the electrodes 71 and 79 are indicated by solid lines, the second group signal wires are indicated by one-dot chain lines, and the third group signal wires are indicated. This wiring is indicated by a dotted line.

  As shown in FIG. 20, the third layer of the mother board 7 is provided with rectangular regions 1B, 6C, 6D facing the rectangular regions 1A, 6A, 6B of the first layer, respectively. In the rectangular region 1B, an electrode 82 is provided to face each electrode 72 of the first layer, and each electrode 82 is connected to the corresponding electrode 72 through a via hole.

  In the rectangular region 6C, electrodes 84 are provided to face the respective electrodes 74 of the first layer, and each electrode 84 is connected to the corresponding electrode 74 through a via hole. In addition, an electrode 85 is provided to face each electrode 75 of the first layer, and each electrode 85 is connected to a corresponding electrode 75 through a via hole.

  In the rectangular area 6D, electrodes 87 are provided to face the respective electrodes 77 of the first layer, and each electrode 87 is connected to the corresponding electrode 77 through a via hole. Further, an electrode 88 is provided to face each electrode 78 of the first layer, and each electrode 88 is connected to the corresponding electrode 78 through a via hole. Further, an electrode 89 is provided to face each electrode 79 of the first layer, and each electrode 89 is connected to the corresponding electrode 79 through a via hole. In addition, each electrode 89 is connected to an electrode 85 adjacent in the Y direction by wiring, and is connected to an electrode 88 adjacent in the Y direction by wiring. In addition, two electrodes 83 are provided at an intermediate position between the rectangular regions 6C and 6D. Each electrode 83 is connected to corresponding electrodes 84 and 87 by wiring extending in the Y direction.

  For example, the electrode 71 for signal A7 in B row and 17 column in FIG. 19 is connected to an electrode 79 through a wiring, and the electrode 79 is connected to an electrode 89 in FIG. 20 through a via hole. The electrode 89 is connected to an electrode 85 through a wiring, the electrode 85 is connected to an electrode 75 in FIG. 19 through a via hole, and the electrode 75 is connected to an electrode 73 for signal A7 in N rows and 2 columns. . As a result, the address signal A7 output from the external terminal TA of the B row and 17 column of the semiconductor device 1 is transmitted to the external terminal TC of the N row and 2 column of the semiconductor memory device 6.

  Further, as shown in FIG. 21, the sixth layer of the mother board 7 is provided with rectangular regions 1C, 6E, 6F facing the rectangular regions 1B, 6C, 6D of the third layer, respectively. In the rectangular region 1C, an electrode 92 is provided to face each electrode 82 of the third layer, and each electrode 92 is connected to the corresponding electrode 82 through a via hole.

  In the rectangular area 6E, electrodes 94 are provided so as to face the electrodes 84 of the third layer, and the electrodes 94 are connected to the corresponding electrodes 84 through via holes. Further, an electrode 95 is provided to face each electrode 85 of the third layer, and each electrode 95 is connected to the corresponding electrode 85 through a via hole.

  In the rectangular area 6F, electrodes 97 are provided so as to face the electrodes 87 of the third layer, and the electrodes 97 are connected to the corresponding electrodes 87 through via holes. Further, an electrode 98 is provided to face each electrode 88 of the third layer, and each electrode 98 is connected to the corresponding electrode 88 through a via hole. Further, an electrode 99 is provided to face each electrode 89 of the third layer, and each electrode 99 is connected to a corresponding electrode 89 through a via hole.

  In FIG. 21, five electrodes 99 of the 13 electrodes 99 in the lower row and the five electrodes 92 in the rectangular region 1C are connected by five wires. The five electrodes 99, numbered 11 to 11, from the right in FIG. 21, are connected to electrodes 92 for signals A5, A1, BA0, BA1, and BA2, respectively.

  In FIG. 21, six electrodes 99 of the twelve electrodes 99 in the upper row and the six electrodes 92 in the rectangular region 1C are connected by six wires. The six electrodes 99 of Nos. 5 to 8, 10, and 11 from the right side in FIG. 21 are connected to the electrodes 92 for signals A11, A6, A0, A2, CASN, and ODT0 from the right side in FIG.

  In addition, an electrode 93 is provided to face each electrode 83 of the third layer, and each electrode 93 is connected to the corresponding electrode 83 through a via hole. The two electrodes 93 in FIG. 21 are connected to the electrodes 92 for signals CKN and CK from the right side in FIG.

  For example, the electrode 71 for signal A11 in D row and 9 column in FIG. 19 is connected to an adjacent electrode 92 through a wiring, and the electrode 92 is connected to the electrode 92 in FIG. 21 through a via hole, an electrode 82, and a via hole. Connected. The electrode 92 is connected to the electrode 99 through a wiring, and the electrode 99 is connected to the electrode 89 in FIG. 20 through a via hole. The electrode 89 is connected to an electrode 85 through a wiring, the electrode 85 is connected to an electrode 75 in FIG. 19 through a via hole, and the electrode 75 is connected to an electrode 73 for signal A11 in P row and 7 column. . As a result, the address signal A11 output from the external terminal TA of the D row and the 9th column of the semiconductor device 1 is transmitted to the external terminal TB of the P row and the 7th column of the semiconductor memory device 6.

[Embodiment 2]
FIG. 22A shows a semiconductor device (LSI) 101 according to the second embodiment of the present invention, and FIGS. 22B and 22C show semiconductor modules 102 and 105, respectively.

  In FIG. 22A, a semiconductor device 101 is obtained by mounting a semiconductor chip on the surface of a package substrate and sealing it with a resin, and a plurality of external terminals TD are arranged in a matrix on the back surface of the package substrate. Yes. The semiconductor chip has a memory controller or the like formed on the surface of a semiconductor substrate, and is connected to a plurality of external terminals TD via a package substrate.

  In FIG. 22B, the semiconductor module 102 is obtained by mounting the semiconductor device 101 and one semiconductor memory device 3 on the surface of one motherboard 103. Semiconductor memory device 3 is, for example, a DDR3-SDRAM. The semiconductor memory device 3 has semiconductor memory chips mounted on the front surface of a package substrate and sealed with resin, and a plurality of external terminals TB are arranged in a matrix on the back surface of the package substrate. The semiconductor memory chip has a plurality of memory cells, write / read circuits, etc. formed on the surface of a semiconductor substrate, and is connected to a plurality of external terminals TB via a package substrate.

  The plurality of external terminals TB of the semiconductor memory device 3 are arranged according to a predetermined arrangement pattern. The arrangement pattern of the external terminals TB of the semiconductor memory device 3 is fixed. That is, the type of signal input to each external terminal TB is fixed. On the other hand, the arrangement pattern of the external terminals TB of the semiconductor device 101 is changed according to the number of semiconductor memory devices 3 by a built-in switching circuit. That is, the type of signal output from each external terminal TB can be changed by the switching circuit. The configuration of the semiconductor device 101 is the same as the configuration of the semiconductor device 1.

  A plurality of wirings for connecting the plurality of external terminals TD of the semiconductor device 101 and the plurality of external terminals TB of the semiconductor memory device 3 are formed on the mother board 103. The arrangement pattern of the external terminals TD of the semiconductor device 101 is set so that the wirings of the mother board 103 do not intersect on the same layer. Each external terminal TB of the semiconductor memory device 3 is connected to a corresponding external terminal TD of the semiconductor device 101 via the wiring of the mother board 103.

  In FIG. 22C, a semiconductor module 105 is obtained by mounting the semiconductor device 101 and the four semiconductor memory devices 3 on the surface of one motherboard 106. The arrangement patterns of the external terminals TB of the four semiconductor memory devices 3 are the same, but when one semiconductor memory device 3 is connected to the semiconductor device 101 and when four semiconductor memory devices 3 are connected to the semiconductor device 101. Then, the wiring arrangement is different. The arrangement pattern of the external terminals TD of the semiconductor device 101 is changed according to the number of semiconductor memory devices 3 by a built-in switching circuit.

  On the mother board 106, a plurality of wirings for connecting the plurality of external terminals TD of the semiconductor device 101 and the plurality of external terminals TB of the four semiconductor memory devices 3 are formed. The arrangement pattern of the external terminals TD of the semiconductor device 101 is set so that the wirings of the mother board 106 do not intersect on the same layer. Each external terminal TB of each semiconductor memory device 3 is connected to a corresponding external terminal TD of the semiconductor device 101 via the wiring of the mother board 106.

  As described above, in the second embodiment, since the arrangement pattern of the external terminals TD of the semiconductor device 101 is switched according to the number of semiconductor memory devices 3 to be connected, the cost of the semiconductor device 101 can be reduced.

  FIGS. 23A to 23C are diagrams showing the effects of the second embodiment. FIG. 23A is a view of the semiconductor device 101 and one semiconductor memory device 3 as seen from the back side. In FIG. 23A, a plurality of external terminals TD are arranged in a matrix on the rectangular back surface of the semiconductor device 101. A plurality of external terminals TB are arranged in a matrix on the rectangular back surface of each semiconductor memory device 3. One side of the semiconductor device 101 and one side of the semiconductor memory device 3 are arranged to face each other.

  It is assumed that eight external terminals TB for signals RAS, A1, A2, CAS, CS, A5, CK, and CKN are provided along the three sides of the semiconductor memory device 3, respectively. In this case, eight external terminals TD for signals RAS, A1, A2, CAS, CS, A5, CK, and CKN are provided along one side of the semiconductor device 101 opposite to one side of the semiconductor memory device 3. For example, the eight external terminals TD of the semiconductor device 101 and the total eight external terminals TB of one semiconductor memory device 3 can be connected by eight wirings LB that do not intersect.

  FIG. 23B is a diagram of the semiconductor device 101 and the two semiconductor memory devices 3 as seen from the back side. In FIG. 23B, a plurality of external terminals TD are arranged in a matrix on the rectangular back surface of the semiconductor device 101. A plurality of external terminals TB are arranged in a matrix on the rectangular back surface of each semiconductor memory device 3. One side of the semiconductor device 1 and one side of the two semiconductor memory devices 3 are arranged to face each other.

  It is assumed that eight external terminals TB for signals RAS, A1, A2, CAS, CS, A5, CK, and CKN are provided along three sides of each semiconductor memory device 3, respectively. In this case, the arrangement pattern shown in FIG. 22A is adopted as the arrangement pattern of the external terminals TD of the semiconductor device 101, and each external terminal TD of the semiconductor device 101 is connected to the corresponding external terminal TB via the wiring LB. Then, as shown in FIG. 22B, the wirings LB intersect at many places. In addition, nine wirings LB crossing between the semiconductor device 101 and the semiconductor memory device 3 are arranged. Therefore, cost increases, transmission characteristics deteriorate, and the substrate area increases.

  On the other hand, in the second embodiment, as shown in FIG. 23C, when the semiconductor device 101 and the two semiconductor memory devices 3 are connected, the external terminal of the semiconductor device 101 is connected by a built-in switching circuit. Since the TD array pattern is changed in accordance with the external terminals TB of the two semiconductor memory devices 3, the number of times the wiring lines LB intersect each other can be reduced. In addition, the number of wirings LB between the semiconductor device 101 and the semiconductor memory device 3 can be reduced. For example, in FIG. 22B, nine wirings LB are provided between the semiconductor device 101 and the semiconductor memory device 3, whereas in FIG. 22C, between the semiconductor device 101 and the semiconductor memory device 3. Six wirings LB are provided.

  That is, in the second embodiment, when the semiconductor module 102 is configured by the semiconductor device 101 and one semiconductor memory device 3, the semiconductor device 101 is set to the first mode by the mode setting signal. The semiconductor device 101 set to the first mode outputs signals RAS, A1, A2, CAS, CS, A5, CK, and CKN from eight external terminals TD facing one side of one semiconductor memory device 3, respectively. To do. Therefore, the eight wirings LB can be formed on the mother board 103 without crossing.

  In the case where the semiconductor module 5 is configured by the semiconductor device 101 and the two semiconductor memory devices 3, the semiconductor device 101 is set to the second mode by the mode setting signal. The semiconductor device 1 set to the second mode outputs signals CS, CAS, A5, RAS, A2, A1, CK, and CKN from eight external terminals TD facing one side of the two semiconductor memory devices 3, respectively. To do. In this case, the number of intersections between the wirings LB on the mother board 106 can be reduced, and the number of wirings LB crossing between the semiconductor device 101 and the semiconductor memory device 3 can be reduced. Also in this second embodiment, the same effect as in the first embodiment can be obtained.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1,101 Semiconductor device, 1A-1C, 3A-3F, 6A-6F Rectangular area | region, 2,5,102,105 Semiconductor module, 3,6 Semiconductor memory device, 4,7,103,106 Mother board, 10 Semiconductor chip, 11 semiconductor substrate, 12 system controller, 13 bus, 14 memory controller, 14a mode setting circuit, 15 selector, 16 register, 17-19 switching circuit, 20 signal input / output circuit, 21 clock generator, 22, 23, 25, 28 , 29 Level up shifter, 24 level down shifter, 26, 30 buffer, 27 comparator, 31 USB, 32 PCI Express, 33 boot ROM, 34 video unit, 35 CPU, 41-49, 52, 54, 55, 57-59 62, 64, 65, 67 To 69, 71 to 79, 82 to 85, 87 to 89, 92 to 95, 97 to 99 electrode, B1 to B4 buffer circuit, LB, LC wiring, P pad, TA, TB, TC, TD external terminal, TI1, TI2 input terminal, TI2 input terminal.

Claims (5)

Advance the M (where, M is an integer of 2 or more and is) N pieces which are divided into the signal groups (where, N represents an integer greater at a than M) and the signal generation circuits for outputting a signal,
And M switching circuits which are provided corresponding to said M signal group,
And N buffers circuits which are each divided into M number of buffer group corresponding to the M switching circuits,
Wherein a N buffers circuits the N external pin provided corresponding to each
Each signal group comprises a plurality of signals, each buffer group includes a signal the same number of buffer circuits of the corresponding group of signals,
Each switching circuit provides a plurality of signals corresponding group of signals, in parallel to a plurality of buffer circuits of the corresponding buffer group in the order corresponding to the control signal,
Each buffer circuits for each buffer group gives the given corresponding switching circuit or found signal to an external pin of the corresponding,
The M buffer groups include first and second buffer groups;
The buffer circuit of the first buffer group outputs a signal of a first logic level in response to a reset signal;
The buffer circuit of the second buffer group, you outputting a second logic level signal in response to the reset signal, the semiconductor device. The semiconductor equipment can be connected to a sub-semiconductor device of the desired type of auxiliary semiconductor equipment of a plurality of models,
Each switching circuit, a plurality of signals corresponding group of signals, follow the control signals, in parallel to a plurality of buffer circuits of the corresponding buffer group in the order corresponding to the model of the sub-semiconductor device to be connected The semiconductor device according to claim 1. The sub semiconductor equipment is a semiconductor memory device, the semiconductor device according to claim 2. The semiconductor equipment can be connected to a secondary semiconductor equipment desired number,
Each switching circuit, a plurality of signals corresponding group of signals, follow the control signals, in parallel to a plurality of buffer circuits of the corresponding buffer group in the order corresponding to the number of the sub semiconductor equipment to be connected The semiconductor device according to claim 1. The sub semiconductor equipment is a semiconductor memory device, the semiconductor device according to claim 4.

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