JP5656321B2 - Semiconductor device, display device, display module, and electronic apparatus - Google Patents

Description

  The present invention relates to a structure of a display device having a transistor. The present invention particularly relates to a structure of an active matrix display device having a thin film transistor manufactured over an insulator such as glass or plastic. The present invention also relates to an electronic device using such a display device for a display portion.

  In recent years, so-called self-luminous display devices in which pixels are formed by light-emitting elements such as light-emitting diodes (LEDs) have attracted attention. As a light-emitting element used in such a self-luminous display device, an organic light-emitting diode (also referred to as an OLED (Organic Light Emitting Diode), an organic EL element, or an electroluminescence (EL) element) attracts attention. It has been used for EL displays and the like. Since light-emitting elements such as OLEDs are self-luminous, there are advantages such as higher pixel visibility than a liquid crystal display, no need for a backlight, and high response speed. The luminance of the light emitting element is controlled by the value of current flowing therethrough.

  In recent years, an active matrix display device in which a light-emitting element and a transistor for controlling light emission of the light-emitting element are provided for each pixel has been developed. The active matrix display device not only enables high-definition and large-screen display, which is difficult with a passive matrix display device, but also achieves lower power consumption and higher reliability than a passive matrix display device. There is a need for practical use.

  As a method for driving a pixel in an active matrix display device, a voltage input method and a current input method can be given when classified according to the type of signal input to the pixel. The former voltage input method is a method in which a video signal (voltage) input to a pixel is input to a gate terminal of a driving element, and the luminance of the light emitting element is controlled using the driving element. In the latter current input method, the luminance of the light emitting element is controlled by flowing a set signal current to the light emitting element.

  Here, an example of a pixel structure in a display device to which the voltage input method is applied and a driving method thereof will be briefly described with reference to FIGS. Note that an EL display device will be described as an example of a typical display device.

  FIG. 64 is a diagram illustrating an example of a pixel configuration in a display device to which a voltage input method is applied (see Patent Document 1). The pixel illustrated in FIG. 64 includes a driving transistor 6401, a switching transistor 6402, a storage capacitor 6403, a signal line 6404, a scanning line 6405, a first power supply line 6406, a second power supply line 6407, and a light emitting element 6408.

  Note that in this specification, a transistor is on refers to a state in which the voltage between the gate and the source of the transistor exceeds the threshold voltage and current flows between the source and the drain, and the transistor is turned off. In this case, the voltage between the gate and the source of the transistor is equal to or lower than the threshold voltage, and no current flows between the source and the drain.

  When the potential of the scanning line 6405 changes and the switching transistor 6402 is turned on, the video signal input to the signal line 6404 is input to the gate of the driving transistor 6401. The voltage between the gate and the source of the driving transistor 6401 is determined according to the potential of the input video signal, and the current flowing between the source and the drain of the driving transistor 6401 is determined. This current is supplied to the light emitting element 6408, and the light emitting element 6408 emits light.

  As described above, in the voltage input method, the voltage between the gate and the source of the driving transistor 6401 and the current flowing between the source and the drain are set by the potential of the video signal, and the light-emitting element 6408 has luminance corresponding to the current. Is a method of emitting light.

  A polysilicon (p-Si) transistor is used as a semiconductor element for driving the light emitting element. However, the polysilicon transistor tends to vary in electrical characteristics such as threshold voltage, on-current, and mobility due to defects in the crystal grain boundaries. In the pixel shown in FIG. 64, when the characteristics of the driving transistor 6401 vary from pixel to pixel, the magnitude of the drain current of the driving transistor 6401 corresponding to the same video signal is different. The brightness of 6408 varies.

In the conventional pixel circuit (FIG. 64), the storage capacitor is connected between the gate and source of the driving transistor. When this storage capacitor is formed of a MOS transistor, the voltage between the gate and source of the MOS transistor. Is substantially equal to the threshold voltage of the MOS transistor, a channel region is not induced in the MOS transistor, and the MOS transistor does not function as a storage capacitor. As a result, the video signal cannot be held correctly.
JP 2001-147659 A

  As described above, in the conventional voltage input method, variations in luminance occur due to variations in the electrical characteristics of the transistors.

  In view of such problems, the present invention has an object to provide a display device that can compensate for variations in threshold voltage of transistors and can reduce variations in luminance, and a driving method using the same. To do.

  One embodiment of the present invention is a display device including a pixel including a light-emitting element, a first transistor, a second transistor, a storage capacitor, a power supply line, and a capacitor line. The transistor has a gate terminal connected to the first electrode of the storage capacitor, a first terminal connected to the first power supply line, a storage capacitor connected to the second electrode of the capacitor line, and the first transistor The second transistor has a function of supplying a current to the light emitting element, and the second transistor has a function as a switch for bringing the first transistor into a diode-connected state, and the second transistor is turned on to be the first transistor The display device is characterized in that a voltage based on the threshold voltage of the first transistor is held in the storage capacitor by making the diode connected.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a storage capacitor, a first power supply line, a second power supply line, a scan line, and a capacitor The first transistor has a gate terminal connected to the first terminal of the second transistor and the first electrode of the storage capacitor, and the first terminal connected to the first power supply line. The second terminal is connected to the second terminal of the second transistor and the first electrode of the light emitting element, the second transistor has the gate terminal connected to the scanning line, and the storage capacitor is connected to the second electrode. Is connected to the capacitor line, the light-emitting element has a second electrode connected to the second power supply line, the first transistor has a function of supplying a current to the light-emitting element, As a switch to turn the 1 transistor in a diode-connected state And a voltage based on the threshold voltage of the first transistor is held in the storage capacitor by making the second transistor conductive and the first transistor in a diode connection state. It is a display device.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first storage capacitor, and a second storage A display device including a capacitor, a first power supply line, a second power supply line, a signal line, and a capacitor line, wherein the first transistor has a gate terminal that is a first storage capacitor. And the second electrode of the second storage capacitor, the first terminal is connected to the first power supply line, the second terminal is connected to the first electrode of the light emitting element, and the second holding The capacitor has a function in which the second electrode is connected to the capacitor line, the light emitting element has a second electrode connected to the second power supply line, and the first transistor has a function of supplying current to the light emitting element. The second transistor functions as a switch that connects the second electrode of the first storage capacitor and the signal line. The third transistor has a function as a switch for connecting the second electrode of the first storage capacitor and the capacitor line, and the fourth transistor makes the first transistor in a diode-connected state. The fourth transistor is turned on, and the first transistor is diode-connected, so that the first and second holding capacitors can be connected to the threshold voltage of the first transistor. The display device is characterized in that a voltage based thereon is held.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first storage capacitor, and a second storage A display device including a capacitor, a first power supply line, a second power supply line, a first scan line, a second scan line, a signal line, and a capacitor line, The transistor has a gate terminal connected to the second terminal of the fourth transistor, the first electrode of the first storage capacitor, and the first electrode of the second storage capacitor, and the first terminal of the first power source The second terminal is connected to the first terminal of the fourth transistor and the first electrode of the light emitting element, the second transistor has the gate terminal connected to the first scan line, A terminal connected to the second electrode of the first storage capacitor and the first terminal of the third transistor; The child is connected to the signal line, the gate terminal of the third transistor is connected to the second scanning line, the second terminal is connected to the capacitor line, and the gate terminal of the fourth transistor is the third scanning line. The second storage capacitor is connected to the capacitor line, the light emitting element is connected to the second power supply line, and the first transistor is connected to the light emitting element. The second transistor has a function as a switch for connecting the second electrode of the first storage capacitor and the signal line, and the third transistor has the first storage capacitor. The fourth transistor has a function as a switch for connecting the second electrode and the capacitor line, and the fourth transistor has a function as a switch for bringing the first transistor into a diode connection state. In the conducting state, the first transistor is By the state of the diode connected to the first and second storage capacitors, a display device, wherein a voltage based on the threshold voltage of the first transistor is maintained.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first storage capacitor And a second storage capacitor, a first power supply line, a second power supply line, a signal line, and a capacitor line, wherein the first transistor has a first gate terminal. Connected to the first electrode of the storage capacitor and the first electrode of the second storage capacitor, the first terminal is connected to the first power supply line, and the second electrode is connected to the second electrode. The light-emitting element has a second electrode connected to the second power supply line, the first transistor has a function of supplying a current to the light-emitting element, and the second transistor The third transistor has a function as a switch for connecting the second electrode of the storage capacitor and the signal line. The star has a function as a switch for connecting the second electrode of the first storage capacitor and the capacitor line, and the fourth transistor has a function as a switch for bringing the first transistor into a diode connection state. And the fifth transistor has a function as a switch for controlling the supply of current to the light emitting element, and the fourth transistor is turned on, and the first transistor is in a diode-connected state. The display device is characterized in that a voltage based on a threshold voltage of the first transistor is held in the first and second holding capacitors.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first storage capacitor A second storage capacitor, a first power line, a second power line, a first scan line, a second scan line, a third scan line, and a fourth scan line. , A display device having a signal line and a capacitor line, wherein the first transistor has a gate terminal having a second terminal of the fourth transistor, a first electrode of the first storage capacitor, and a second transistor. Connected to the first electrode of the storage capacitor, the first terminal is connected to the first power supply line, the second terminal is connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor; The second transistor has a gate terminal connected to the first scanning line and a first terminal of the first storage capacitor. 2 and the first terminal of the third transistor, the second terminal is connected to the signal line, the third transistor has the gate terminal connected to the second scanning line, and the second terminal has a capacitance. A gate terminal of the fourth transistor is connected to the third scanning line, a gate terminal of the fifth transistor is connected to the fourth scanning line, and a second terminal is the first of the light emitting element. The second storage capacitor is connected to the capacitor line, the second electrode is connected to the capacitor line, the light emitting element is connected to the second power line, and the first transistor is connected to the light emitting element. The second transistor has a function as a switch for connecting the second electrode of the first storage capacitor and the signal line, and the third transistor has the function of supplying the current to the first transistor. Function as a switch for connecting the second electrode of the storage capacitor and the capacitor line The fourth transistor has a function as a switch for bringing the first transistor into a diode connection state, and the fifth transistor has a function as a switch for controlling supply of current to the light-emitting element. Then, the voltage based on the threshold voltage of the first transistor is held in the first and second storage capacitors by setting the fourth transistor in a conductive state and the first transistor in a diode-connected state. This is a display device.

  In the present invention, the gate terminals of at least two of the transistors may be connected to the same scanning line.

  In the present invention, the fourth transistor may be an N-channel type.

  In the present invention, any one of the scanning lines can be used in place of the capacitor line.

  In the present invention, the display device includes a sixth transistor. The sixth transistor has a gate terminal connected to the fifth scan line, a first terminal connected to the second terminal of the first transistor, and a fourth transistor. Of the first transistor and the first terminal of the fifth transistor, the second terminal of the second transistor, the first terminal of the third transistor, and the first storage capacitor. The sixth transistor connected to the second electrode may function as a switch for applying an initial potential to the second terminal of the first transistor.

  In the present invention, the display device may include an initialization line, and the initialization line may be connected to the second terminal of the sixth transistor.

  Note that in the display device of the present invention, the display device includes a reference line, the capacitor line is connected to the second electrode of the second storage capacitor, and the reference line is connected to the second terminal of the third transistor. It may be connected.

  Note that in the display device of the present invention, another wiring may be used as the capacitor line instead of separately providing the capacitor line.

  Note that in the display device of the present invention, among the values of the ratio W / L of the channel length L to the channel width W of each transistor, the value of W / L of the first transistor is maximized. Also good.

  One embodiment of the present invention includes a pixel provided with a light-emitting element, a first transistor, a second transistor, a storage capacitor, a power supply line, and a capacitor line, and the first transistor includes a gate. The terminal is connected to the first electrode of the storage capacitor, the first terminal is connected to the first power supply line, the storage capacitor has the second electrode connected to the capacitor line, and the first transistor is connected to the light emitting element. A display device driving method having a function of supplying current, wherein the second transistor has a function of a switch for bringing the first transistor into a diode-connected state. Then, by supplying a current to the light emitting element, the initial voltage is held in the storage capacitor. In the second period, the second transistor is turned on, and the first transistor is held in a diode connection state. To capacity, A voltage based on the threshold voltage of one transistor is held, and in the third period, a video signal is input to the signal line, and the video signal input to the signal line and the threshold voltage of the first transistor are input to the storage capacitor. In the fourth period, the voltage held in the storage capacitor in the third period is applied to the gate terminal of the first transistor, and the light-emitting element is connected to the first transistor through the first transistor. The display device is driven by supplying current to the light emitting element to emit light.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a storage capacitor, a first power supply line, a second power supply line, a scan line, and a capacitor The first transistor has a gate terminal connected to the first terminal of the second transistor and the first electrode of the storage capacitor, the first terminal connected to the first power supply line, and the second transistor The terminal is connected to the second terminal of the second transistor and the first electrode of the light emitting element, the gate terminal of the second transistor is connected to the scanning line, and the storage capacitor is connected to the capacitor line of the second electrode. The light-emitting element has a second electrode connected to the second power supply line, the first transistor has a function of supplying current to the light-emitting element, and the second transistor includes the first transistor. It has a function as a switch to connect the diode In the first period, the initial voltage is held in the storage capacitor by passing a current through the light-emitting element in the first period, and the second transistor is turned on in the second period. By setting the first transistor in a diode-connected state, a voltage based on the threshold voltage of the first transistor is held in the storage capacitor, and in the third period, a video signal is input to the signal line, and the storage capacitor A voltage based on the video signal input to the signal line and the threshold voltage of the first transistor is held in the first signal line. In the fourth period, the voltage held in the holding capacitor in the third period is the first voltage. A display device driving method is characterized in that a current is supplied to the light-emitting element through the first transistor and applied to the gate terminal of the transistor to cause the light-emitting element to emit light.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first storage capacitor, and a second storage A first transistor including a capacitor, a first power line, a second power line, a signal line, and a capacitor line; the first transistor includes a first electrode whose gate terminal is a first storage capacitor; The second storage capacitor is connected to the second electrode, the first terminal is connected to the first power supply line, the second terminal is connected to the first electrode of the light emitting element, and the second storage capacitor is The second electrode is connected to the capacitor line, the second electrode is connected to the second power supply line, and the first transistor has a function of supplying current to the light-emitting element. Has a function as a switch for connecting the second electrode of the first storage capacitor and the signal line, and the third transistor The register has a function as a switch for connecting the second electrode of the first storage capacitor and the capacitor line, and the fourth transistor has a function as a switch for bringing the first transistor into a diode connection state. In the display device driving method, an initial voltage is held in the first storage capacitor by passing a current through the light-emitting element in the first period, and the fourth period in the second period. By setting the first transistor in a conductive state and the first transistor in a diode-connected state, a voltage based on the threshold voltage of the first transistor is held in the first and second storage capacitors. In the third period, The video signal is input to the signal line, and the first and second storage capacitors hold the voltage based on the video signal input to the signal line and the threshold voltage of the first transistor, and the fourth period Then, in the third period, the voltage held in the first and second storage capacitors is applied to the gate terminal of the first transistor, and a current is supplied to the light-emitting element through the first transistor to emit light. A display device driving method is characterized in that an element emits light.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first storage capacitor, and a second storage A display device including a capacitor, a first power supply line, a second power supply line, a first scan line, a second scan line, a signal line, and a capacitor line, The transistor has a gate terminal connected to the second terminal of the fourth transistor, the first electrode of the first storage capacitor, and the first electrode of the second storage capacitor, and the first terminal of the first power source The second terminal is connected to the first terminal of the fourth transistor and the first electrode of the light emitting element, the second transistor has the gate terminal connected to the first scan line, A terminal connected to the second electrode of the first storage capacitor and the first terminal of the third transistor; The child is connected to the signal line, the gate terminal of the third transistor is connected to the second scanning line, the second terminal is connected to the capacitor line, and the gate terminal of the fourth transistor is the third scanning line. The second storage capacitor is connected to the capacitor line, the light emitting element is connected to the second power supply line, and the first transistor is connected to the light emitting element. The second transistor has a function as a switch for connecting the second electrode of the first storage capacitor and the signal line, and the third transistor has the first storage capacitor. The display device has a function as a switch for connecting the second electrode and the capacitor line, and the fourth transistor has a function as a switch for bringing the first transistor into a diode-connected state. Driving method in the first period By supplying a current to the light emitting element, the initial voltage is held in the first and second holding capacitors, and in the second period, the fourth transistor is turned on and the first transistor is set in a diode connection state. Thus, a voltage based on the threshold voltage of the first transistor is held in the first and second holding capacitors, and a video signal is input to the signal line in the third period, and the first and second holding capacitors are supplied. A voltage based on the video signal input to the signal line and the threshold voltage of the first transistor is held in the capacitor. In the fourth period, the voltage is held in the first and second holding capacitors in the third period. The display device is driven by applying the applied voltage to the gate terminal of the first transistor, supplying current to the light emitting element through the first transistor, and causing the light emitting element to emit light.

  Note that in the method for driving a display device of the present invention, the voltage applied to the second power supply line may be different between the first and fourth periods and the second and third periods.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first storage capacitor And a second storage capacitor, a first power supply line, a second power supply line, a signal line, and a capacitor line. The first transistor has a gate terminal whose first storage capacitor is the first storage capacitor. 1 electrode and the first electrode of the second storage capacitor, the first terminal is connected to the first power line, the second storage capacitor is connected to the capacitor line, The light-emitting element has a second electrode connected to the second power supply line, the first transistor has a function of supplying a current to the light-emitting element, and the second transistor has a second storage capacitor. The third transistor has a function as a switch for connecting the electrode and the signal line, and the third transistor The fourth transistor has a function as a switch for connecting the first transistor to a diode connection state, and a fifth transistor. Is a method for driving a display device, which has a function as a switch for controlling supply of current to the light-emitting element. In the first period, the first method is performed by flowing current to the light-emitting element. An initial voltage is applied to the electrode of the transistor, and in the second period, the first transistor is connected to the first and second storage capacitors by bringing the fourth transistor into a conductive state and the first transistor in a diode connection state. A voltage based on the threshold voltage of the transistor is held, a video signal is input to the signal line in the third period, and a video signal is input to the signal line to the first and second holding capacitors A voltage based on the threshold voltage of the first transistor is held, and in the fourth period, the voltage held in the first and second holding capacitors in the third period is applied to the gate terminal of the first transistor. The display device driving method is characterized in that a current is supplied to the light-emitting element through the first transistor and the light-emitting element is caused to emit light by being applied and turning on the fifth transistor.

  According to one embodiment of the present invention, a pixel provided with a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first storage capacitor A second storage capacitor, a first power line, a second power line, a first scan line, a second scan line, a third scan line, and a fourth scan line. , A signal line, and a capacitor line. The first transistor has a gate terminal having a second terminal of the fourth transistor, a first electrode of the first storage capacitor, and a second storage capacitor. Connected to the first electrode, the first terminal is connected to the first power supply line, the second terminal is connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor, The transistor has a gate terminal connected to the first scan line, a first terminal connected to the second electrode of the first storage capacitor, and 3 transistor is connected to the first terminal, the second terminal is connected to the signal line, the third transistor has a gate terminal connected to the second scanning line, a second terminal connected to the capacitor line, In the transistor No. 4, the gate terminal is connected to the third scanning line, and in the fifth transistor, the gate terminal is connected to the fourth scanning line, and the second terminal is connected to the first electrode of the light emitting element, The second storage capacitor has a second electrode connected to the capacitor line, the light emitting element has a second electrode connected to the second power supply line, and the first transistor supplies a current to the light emitting element. The second transistor has a function as a switch for connecting the second electrode of the first storage capacitor and the signal line, and the third transistor has a second function of the first storage capacitor. It has a function as a switch that connects the electrode and the capacitor line, The transistor has a function as a switch for bringing the first transistor into a diode connection state, and the fifth transistor has a function as a switch for controlling supply of current to the light-emitting element. In the driving method of the device, an initial voltage is held in the first and second holding capacitors by passing a current through the light emitting element in the first period, and the fourth transistor is turned on in the second period. As a state, by setting the first transistor in a diode connection state, a voltage based on the threshold voltage of the first transistor is held in the first holding capacitor and the second holding capacitor, and in the third period, A video signal is input to the signal line, a voltage based on the video signal input to the signal line and the threshold voltage of the first transistor is held in the first and second storage capacitors, and the fourth period Then, in the third period, the voltage held in the first and second storage capacitors is applied to the gate terminal of the first transistor, and the fifth transistor is turned on, whereby the first transistor The display device driving method is characterized in that a current is supplied to the light emitting element through the light emitting element to cause the light emitting element to emit light.

  In the present invention, the display device includes a sixth transistor. The sixth transistor has a gate terminal connected to the fifth scan line, a first terminal connected to the second terminal of the first transistor, The first terminal of the fourth transistor and the first terminal of the fifth transistor, the second terminal is the second terminal of the second transistor, the first terminal of the third transistor, and the first storage capacitor. The sixth transistor has a function as a switch for applying an initial potential to the first transistor, and makes the sixth transistor conductive in the first period. Thus, the capacitor line potential may be applied to the second terminal of the first transistor as the initial potential.

  In the present invention, the display device includes an initialization line. The initialization line is connected to the second terminal of the sixth transistor, and the sixth transistor is turned on in the first period. The configuration may be such that the potential of the initialization line is applied as the initial potential to the second terminal of the first transistor.

  One aspect of the present invention is an electronic device including the display device described above.

  One embodiment of the present invention is an electronic device including a display device using the driving method described above.

  Note that it is difficult to distinguish between a source and a drain because of the structure of a transistor. Further, depending on the operation of the circuit, the level of the potential may be switched. Therefore, in this specification, a source and a drain are not particularly specified, and are described as a first terminal and a second terminal. For example, when the first terminal is a source, the second terminal indicates a drain, and conversely, when the first terminal is a drain, the second terminal indicates a source.

  In the present invention, one pixel represents one color element. Therefore, in the case of a color display device composed of R (red), G (green), and B (blue) color elements, the minimum unit of an image is composed of three pixels, an R pixel, a G pixel, and a B pixel. Shall be. Note that the color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, white (W) may be added to obtain RGBW. Further, for example, one or more colors such as yellow, cyan, and magenta may be added to RGB.

  Further, for example, a similar color may be added for at least one color of RGB. For example, R, G, B1, and B2 may be used. B1 and B2 are both blue, but have different wavelengths. By using such color elements, it is possible to perform display closer to the real thing and to reduce power consumption. Note that the brightness of one color element may be controlled using a plurality of regions. In this case, one color element is one pixel, and each area for controlling the brightness is a sub-pixel. Thus, for example, when the area gradation method is used, there are a plurality of areas for controlling the brightness for each color element, and the gradation is expressed as a whole. Let it be a pixel. Therefore, in that case, one color element is composed of a plurality of sub-pixels. In that case, the size of the region contributing to display may be different depending on the sub-pixel. In addition, in a region where a plurality of brightnesses are controlled for one color element, that is, in a plurality of sub-pixels constituting one color element, a signal supplied to each is slightly different to widen the viewing angle. You may do it.

  In the present invention, the pixels may be arranged (arranged) in a matrix. Here, the pixel being arranged (arranged) in a matrix includes a case where the pixels are arranged on a straight line or a jagged line in the vertical direction or the horizontal direction. Therefore, for example, when full color display is performed with three color elements (for example, RGB), the case where stripes are arranged and the case where dots of three color elements are arranged in a delta are included. Furthermore, the case where a Bayer is arranged is included.

  Note that various types of transistors can be used as the transistor of the present invention. Thus, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) including a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon can be used. Thus, the manufacturing temperature can be lowered, it can be manufactured at low cost, it can be manufactured on a large substrate, it can be manufactured on a transparent substrate, a transistor having translucency can be manufactured, or a display element using a transistor can be manufactured. Can control the transmission of light. In addition, a transistor can be formed using a semiconductor substrate or an SOI substrate. Further, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor in this specification. As a result, transistors with little variation in characteristics, high current supply capability, and small size can be formed, and a circuit with less power consumption than these transistors can be formed.

  Further, a transistor having a compound semiconductor such as ZnO, a-InGaZnO, SiGe, or GaAs, or a thin film transistor obtained by thinning them can be used. Accordingly, the manufacturing temperature can be lowered, the device can be manufactured at room temperature, or the transistor can be directly formed on a substrate having low heat resistance, such as a plastic substrate or a film substrate. In addition, a transistor formed using an inkjet method or a printing method can be used. By these, it can manufacture at room temperature, can manufacture at a low vacuum degree, and can manufacture on a large sized board | substrate. Further, since the transistor can be manufactured without using a mask (reticle), the layout of the transistor can be easily changed. In addition, a transistor including an organic semiconductor or a carbon nanotube, or another transistor can be used. Thus, a transistor can be formed over a substrate that can be bent.

  Note that the non-single-crystal semiconductor film may contain hydrogen or halogen. In addition, various types of substrates on which the transistor is arranged can be used, and the substrate is not limited to a specific type. For example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, a substrate having stainless steel foil, or the like is used. Can do. Alternatively, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on another substrate. By using these substrates, a transistor with excellent characteristics can be formed, a transistor with low power consumption can be formed, and a device which is not easily broken can be obtained, or heat resistance can be given.

  Note that various types of switches can be used as a switch shown in the present invention, and examples thereof include an electrical switch and a mechanical switch. In other words, any device can be used as long as it can control the flow of current, and it is not limited to a specific device, and various devices can be used. For example, it may be a transistor, a diode (for example, a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, or the like), a thyristor, or a logic circuit that combines them. Therefore, when a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desirable that the off-state current is small, it is desirable to use a transistor having a polarity with a small off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region and a transistor having a multi-gate structure.

  In addition, when the transistor operated as a switch operates at a source terminal potential close to a low potential side power supply (VSS, GND, 0 V, etc.), the N channel type is used. On the contrary, the source terminal potential is a high potential. When operating in a state close to a side power supply (VDD or the like), it is desirable to use a P channel type. Because the absolute value of the voltage between the gate and the source can be increased, it is easy to function as a switch. Note that both N-channel and P-channel switches may be used as CMOS switches. A CMOS switch can easily function as a switch because a current can flow when the P-channel or N-channel switch is turned on. For example, the voltage can be appropriately output regardless of whether the voltage of the input signal to the switch is high or low. In addition, since the voltage amplitude value of a signal for turning on or off the switch can be reduced, power consumption can be reduced.

  In the present invention, the description of B on A or B on A is not limited to the direct contact of B on A. The case where it is not in direct contact, that is, the case where another object is interposed between A and B is also included. Therefore, for example, when the layer B is formed on the layer A (or on the layer A), the case where the layer B is formed in direct contact with the layer A and the case where the layer B is formed In which another layer (for example, layer C or layer D) is formed in direct contact with layer B and layer B is formed in direct contact therewith. The same applies to the description of B above A. The description is not limited to the case where B is in direct contact with A, and includes the case where another is interposed between A and B. Therefore, for example, when the layer B is formed above the layer A, the case where the layer B is formed in direct contact with the layer A and the case where another layer is formed in direct contact with the layer A. (For example, the layer C or the layer D) is formed, and the layer B is formed in direct contact therewith. Note that the description of B below A or B below A is the same, and includes the case of direct contact and the case of no contact.

  Note that the display device of the present invention can use various modes or have various display elements. For example, EL elements (organic EL elements, inorganic EL elements or EL elements including organic and inorganic substances), electron-emitting elements, liquid crystal elements, electronic ink, grating light valves (GLV), plasma displays (PDP), digital micromirrors A display medium whose contrast is changed by an electromagnetic action, such as a device (DMD), a piezoelectric ceramic display, or a carbon nanotube, can be applied. Note that a display device using an EL element is an EL display, and a display device using an electron-emitting device is a liquid crystal display such as a field emission display (FED) or a SED type flat display (SED: Surface-conduction Electron-Emitter Display). A display device using the element includes a liquid crystal display, a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, and a display device using electronic ink includes electronic paper.

  Note that the light-emitting element in the present invention refers to an element whose emission luminance can be controlled by the value of current flowing through the element. Typically, an EL element can be used. In addition to the EL element, for example, an element used in a field emission display (FED) or a light-emitting element such as an SED (Surface-Condition Electron-Emitter Display) which is a kind of FED can be applied.

In the present invention, being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, another element (for example, another element or a switch) that enables electrical connection may be disposed therebetween.

  In the display device of the present invention, since the current flowing through the light-emitting element is determined in a manner that does not depend on the threshold voltage of the transistor, variations in the threshold voltage of the transistor can be compensated. Accordingly, variation in luminance of the light emitting element can be reduced, and image quality can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
First, a basic configuration of a pixel circuit in the display device of this embodiment will be described with reference to FIG. Note that an EL element is described as an example of a light-emitting element.

FIG. 1 is a diagram showing a minimum circuit configuration for obtaining a threshold voltage of a transistor in the pixel configuration of the present embodiment. FIG. 1 includes a first transistor 101 and a second transistor 102, a storage capacitor 103, a scanning line 104, a first power supply line 105 and a second power supply line 106, a capacitor line 107, and a light emitting element 108. .

  Note that in FIG. 1, the first transistor 101 and the second transistor 102 are p-channel transistors.

  The first transistor 101 has a gate terminal connected to the second electrode of the second transistor and the first electrode of the storage capacitor 103, the first terminal connected to the first power supply line 105, The two electrodes are connected to the first terminal of the second transistor 102. The gate terminal of the second transistor 102 is connected to the scanning line 104. The storage capacitor 103 has a second electrode connected to the capacitor line 107. In the light-emitting element, the second electrode is connected to the second power supply line 106.

Further, the power supply potential VDD is applied to the first power supply line 105, the power supply potential VSS is applied to the second power supply line 106, and the potential _VCL is applied to the capacitor line 107. Note that the potential relationship is VDD> VSS and VDD> _VCL .

  Here, the first transistor 101 has a function of supplying current to the light-emitting element 108. The second transistor has a function as a switch for bringing the first transistor 101 into a diode connection state.

Note that in this specification, diode connection refers to a state where a gate terminal of a transistor is connected to a first or second electrode.

In the pixel circuit illustrated in FIG. 1, when the second transistor 102 is turned on, the first transistor 101 is in a diode connection state, a current flows through the storage capacitor 103, and the storage capacitor 103 is charged. When the storage capacitor 103 is charged, the voltage held in the storage capacitor 103 is a difference between the power supply potential VDD and the threshold voltage | V _th | of the first transistor 101 and the potential V _CL of the capacitor line 107 VDD− | V _th | The voltage continues to be −V _CL until the voltage held in the storage capacitor 103 becomes VDD− | V _th | −V _CL , the first transistor 101 is turned off and no current flows through the storage capacitor 103.

Through the above operation, a voltage based on the threshold voltage | V _th | of the first transistor 101 can be held in the storage capacitor 103.

FIG. 2 shows a minimum circuit configuration for obtaining the threshold voltage of the first transistor when the first transistor is an N-channel type.

  2 includes a first transistor 201 and a second transistor 202, a storage capacitor 203, a scanning line 204, a first power supply line 205, a second power supply line 206, a capacitor line 207, and a light emitting element 208. .

  Note that in FIG. 2, the second transistor 202 is an n-channel transistor.

Note that the power supply potential VSS is applied to the first power supply line 205, the power supply potential VDD is applied to the second power supply line 206, and the potential _VCL is applied to the capacitor line 207. Note that the potential relationship is VDD> VSS and V _CL > VSS.

In the pixel circuit illustrated in FIG. 2, when the second transistor 202 is turned on, the first transistor 201 is in a diode connection state, a current flows through the storage capacitor 203, and the storage capacitor 203 is charged. When the storage capacitor 203 is charged, the voltage stored in the storage capacitor 203 is different from the potential V _CL of the capacitor line 207, the power supply potential VSS, and the threshold voltage | V _th | of the first transistor 201 V _CL −VSS− | The voltage continues until V _th |, and when the voltage held in the storage capacitor 203 becomes V _CL −VSS− | V _th |, the first transistor 201 is turned off and no current flows through the storage capacitor 203.

Through the above operation, a voltage based on the threshold voltage | V _th | of the first transistor 201 can be held in the storage capacitor 203.

  Next, the pixel configuration of this embodiment having the basic circuit configuration shown in FIG. 1 or FIG. 2 will be described with reference to FIG. Note that an EL element is described as an example of a light-emitting element.

  FIG. 3 is a diagram illustrating the pixel circuit of the present embodiment. The pixel circuit of this embodiment includes a first transistor 301 to a fifth transistor 305, a first storage capacitor 306 and a second storage capacitor 307, a signal line 308, and a first scan line 309 to a fourth scan line. 312, a first power supply line 313, a second power supply line 314, a capacitor line 315, and a light emitting element 316.

  Here, the first transistor 301 is used as a transistor that supplies current to the light-emitting element 316, and the second transistor 302 to the fifth transistor 305 are used as switches for selecting whether or not to connect a wiring. .

  The first transistor 301 has a gate terminal connected to the second terminal of the fourth transistor 304, the first electrode of the first storage capacitor 306, and the first electrode of the second storage capacitor 307. The first terminal is connected to the first power supply line 313, and the second terminal is connected to the first terminal of the fourth transistor 304 and the first terminal of the fifth transistor 305. The second transistor 302 has a gate terminal connected to the first scan line 309, a first terminal connected to the signal line 308, a second terminal connected to the first terminal of the third transistor 303, and the second transistor 302. It is connected to the second electrode of one storage capacitor 306. The third transistor 303 has a gate terminal connected to the second scanning line 310 and a second terminal connected to the capacitor line 315. The gate terminal of the fourth transistor 304 is connected to the third scanning line 311. The fifth transistor 305 has a gate terminal connected to the fourth scanning line 312 and a second terminal connected to the first electrode of the light-emitting element 316. The second storage capacitor 307 has a second electrode connected to the capacitor line 315. The light emitting element 316 has a second electrode connected to the second power supply line 314.

Further, the power supply potential VDD is applied to the first power supply line 313, the power supply potential VSS is applied to the second power supply line 314, and the potential _VCL is applied to the capacitor line 315. Note that the potential relationship is VDD> VSS and VDD> _VCL .

  Note that in the pixel circuit illustrated in FIG. 3, the first transistor 301 to the fifth transistor 305 are all P-channel transistors.

  Note that the fourth transistor 304 in FIG. 3 corresponds to the second transistor 102 in FIG. 1, and the second storage capacitor 307 in FIG. 3 corresponds to the storage capacitor 103 in FIG.

  Next, the operation of the pixel circuit of the present embodiment will be described with reference to FIGS.

  FIG. 4 is a timing chart of video signal voltages and pulses input to the signal line 308 and the first scan line 309 to the fourth scan line 312, and each operation of the pixel circuit shown in FIGS. 5 to 8. Accordingly, the period is divided into four periods of a first period T1 to a fourth period T4.

  5 to 8 are diagrams showing connection states of the pixel circuit of this embodiment in each period. 5-8, the location shown by the solid line is conducting, and the location shown by the broken line is not conducting.

  First, operation of the pixel circuit in the first period T1 is described with reference to FIG. FIG. 5 is a diagram illustrating a connection state of the pixel circuit in the first period T1. In the first period T1, the second scan line 310 to the fourth scan line 312 are at the L level, and the third transistor 303 to the fifth transistor 305 are turned on. In addition, the first scanning line 309 becomes an H level, and the second transistor 302 is turned off. Accordingly, the first transistor 301 is in a diode connection state, and a current flows through the light-emitting element 316. As a result, the potentials of the second terminal of the first transistor 301, the first electrode of the first storage capacitor 306, and the first electrode of the second storage capacitor 307 drop, and the first storage capacitor 306 A certain initial voltage is held in the second holding capacitor 307.

  Through the above operation, a certain initial voltage is held in the first storage capacitor 306 and the second storage capacitor 307 in the first period T1. In this specification, this operation is called initialization.

Next, operation of the pixel circuit in the second period T2 is described with reference to FIG. FIG. 6 is a diagram illustrating a connection state of the pixel circuit in the second period T2. In the second period T2, the second scan line 310 and the third scan line 311 are at the L level, and the third transistor 303 and the fourth transistor 304 are turned on. In addition, the first scan line 309 and the fourth scan line 312 are at an H level, and the second transistor 302 and the fifth transistor 305 are turned off. As a result, the first transistor 301 is in a diode-connected state, a current flows through the first storage capacitor 306 and the second storage capacitor 307 connected in parallel, and the first storage capacitor 306 and the second storage capacitor 307 are connected. Are both charged. When the first storage capacitor 306 and the second storage capacitor 307 are charged, the voltage held in the first storage capacitor 306 and the second storage capacitor 307 is the power supply potential VDD and the threshold voltage of the first transistor 301 | The difference between V _th | and the potential V _CL of the capacitor line 315 continues until VDD− | V _th | −V _CL is reached, and the voltage held in the first holding capacitor 306 and the second holding capacitor 307 is VDD− | When V _th | −V _CL is satisfied, the first transistor 301 is turned off, so that no current flows through the first storage capacitor 306 and the second storage capacitor 307.

Through the above operation, in the second period T2, a voltage based on the threshold voltage | V _th | of the first transistor 301 is held in the first storage capacitor 306 and the second storage capacitor 307.

Note that in order for the first storage capacitor 306 and the second storage capacitor 307 to hold a voltage based on the threshold voltage | V _th | The potential of the second terminal of the transistor 301 must be lower than the difference VDD− | V _th | between the power supply potential VDD and the threshold voltage | V _th | of the first transistor 301. Therefore, by supplying a current to the light-emitting element 316 in the first period T1, the potential of the second terminal of the first transistor 301 can be surely lower than VDD− | V _th | and the threshold voltage can be obtained. Can be performed reliably.

Next, the operation of the pixel circuit in the third period T3 is described with reference to FIG. FIG. 7 is a diagram illustrating a connection state of the pixel circuit in the third period T3. In the third period T3, the first scanning line 309 is at the L level, and the second transistor 302 is turned on. In addition, the second scan line 310 to the fourth scan line 312 are at the H level, and the third transistor 303 to the fifth transistor 305 are turned off. A video signal voltage V _data is applied to the signal line 308. As a result, the first storage capacitor 306 and the second storage capacitor 307 are connected in series, and the voltage based on the capacity ratio of each storage capacitor is applied to each of the first storage capacitor 306 and the second storage capacitor 307. Retained. At this time, if the voltages held in the first holding capacitor 306 and the second holding capacitor 307 are V _C1 (T3) and V _C2 (T3), V _C1 (T3) and V _C2 (T3) are It is expressed as the following equations (1) and (2).

C ₁ represents the capacitance value of the first storage capacitor 306, and C ₂ represents the capacitance value of the second storage capacitor 307.

Through the above operation, in the third period T3, the first storage capacitor 306 and the second storage capacitor 307 are supplied with voltages based on the video signal voltage V _data and the threshold voltage | V _th | of the first transistor 301. Hold.

Next, operation of the pixel circuit in the fourth period T4 is described with reference to FIG. FIG. 8 is a diagram illustrating a connection state of the pixel circuit in the fourth period T4. In the fourth period T4, the fourth scanning line 312 is at the L level, and the fifth transistor 305 is turned on. In addition, the first scan line 309 to the third scan line 311 are at the H level, and the second transistor 302 to the fourth transistor 304 are turned off. Thus, the sum V _C2 (T3) + V _{CL of the} voltage V _C2 (T3) held in the second holding capacitor 307 and the potential V _CL of the capacitor line 315 is added to the gate electrode of the first transistor 301. Therefore, when the gate-source voltage of the first transistor 301 in the period T4 is V _gs (T4), V _gs (T4) is expressed by the following equation (3).

Therefore, a current _IOLED flowing between the drain and the source of the first transistor 301 is expressed by the following equation (4). This current flows to the light emitting element 316 through the fifth transistor 305, and the light emitting element 316 emits light.

  Here, β is a constant given by the mobility and size of the transistor, the capacitance due to the oxide film, and the like.

By the above operation, the fourth period T4, the current _{I OLED} which is dependent on the video signal voltage _{V data} to the light emitting element 316 flows, the light emitting element 316 emits light.

  Here, functions of the first transistor 301 to the fifth transistor 305 in the operation process of the pixel circuit illustrated in FIG. 3 will be described again.

  The first transistor 301 has a function of supplying current to the light-emitting element 316 in the fourth period T4.

The second transistor 302 functions as a switch for connecting the second electrode of the first storage capacitor 306 and the signal line 308 in order to input the video signal voltage V _data to the pixel in the third period T3.

The third transistor 303 stores the voltage based on the threshold voltage | V _th | of the first transistor 301 in the first storage capacitor 306 in the second period T2. It functions as a switch that connects the two electrodes and the capacitor line 315.

In the second period T2, the fourth transistor 304 stores the voltage based on the threshold voltage | V _th | of the first transistor 301 in the first storage capacitor 306 and the second storage capacitor 307. 1 transistor 301 functions as a switch for diode connection.

  The fifth transistor 305 does not pass a current through the light emitting element 316 in the second period T2 and the third period T3, but flows a current through the light emitting element 316 in the first period T1 and the fourth period T4. It functions as a switch for controlling, that is, controlling the supply of current to the light emitting element 316.

Through the above operation process, the current I _OLED can be supplied to the light emitting element 316, and the light emitting element 316 can emit light with the luminance corresponding to the current I _OLED . At this time, as shown in the equation (4), the current I _OLED that flows through the light emitting element 316 is expressed in a form that does not depend on the threshold voltage | V _th | of the first transistor 301. Variations can be compensated.

Note that the video signal voltage V _data is set to be equal to or lower than the potential V _CL of the capacitor line 315 in order to turn on the first transistor 301 in the fourth period T4.

Note that the potential V _CL of the capacitor line 315 may be lower than the difference VDD− | V _th | between the power supply potential VDD and the threshold voltage | V _th | of the first transistor 301. Note that a voltage based on the threshold voltage | V _th | of the first transistor 301, the video signal voltage V _data, or the like can be reliably held in the first holding capacitor 306 and the second holding capacitor 307. In addition, the potential V _CL of the capacitor line 315 is desirably lower. However, in order to set the video signal voltage _{V data} below the potential _{V CL} of the capacitor line 315, when the potential _{V CL} of the capacitor line 315 is too too low, will have to be further reduced video signal voltage _{V data.} Therefore, it is more desirable to set the potential _VCL of the capacitor line 315 within a certain appropriate range. For example, the range of the potential V _CL of the capacitor line 315 may be set to − (VDD + VSS) / 2 ≦ V _CL ≦ (VDD + VSS) / 2.

  In the pixel circuit shown in FIG. 3, the first transistor 301 is a P-channel type; however, the first transistor 301 may be an N-channel type. Here, FIG. 9 illustrates a pixel structure in the case where the first transistor is an n-channel transistor.

  9 includes a first transistor 901 to a fifth transistor 905, a first storage capacitor 906 and a second storage capacitor 907, a signal line 908, a first scan line 909 to a fourth scan line 912. , A first power line 913, a second power line 914, a capacitor line 915, and a light emitting element 916.

  Note that in the pixel circuit in FIG. 9, the second transistor 902 to the fifth transistor 905 are all N-channel transistors.

  Here, the first transistor 901 is used as a transistor for supplying current to the light-emitting element 916, and the second transistor 902 to the fifth transistor 905 are used as switches for selecting whether or not to connect a wiring. .

  The first transistor 901 has a gate electrode connected to the second terminal of the fourth transistor 904, the first electrode of the first storage capacitor 906, and the first electrode of the second storage capacitor 907. The first terminal is connected to the first power supply line 913, and the second terminal is connected to the first terminal of the fourth transistor 904 and the first terminal of the fifth transistor 905. The second transistor 902 has a gate terminal connected to the first scan line 909, a first terminal connected to the signal line 908, a second terminal connected to the first terminal of the third transistor 903, and the second transistor 903. One storage capacitor 906 is connected to the second electrode. The third transistor 903 has a gate terminal connected to the second scanning line 910 and a second terminal connected to the capacitor line 915. The gate terminal of the fourth transistor 904 is connected to the third scanning line 911. The fifth transistor 905 has a gate terminal connected to the fourth scanning line 912 and a second terminal connected to the second electrode of the light-emitting element 916. The second storage capacitor 907 has a second electrode connected to the capacitor line 915. The light-emitting element 916 has a first electrode connected to the second power supply line 914.

In addition, the power supply potential VSS is applied to the first power supply line 913, the power supply potential VDD is applied to the second power supply line 914, and the potential _VCL is applied to the capacitor line 915. Note that the potential relationship is VDD> VSS and V _CL > VSS.

  Note that the fourth transistor 904 in FIG. 9 corresponds to the second transistor 202 in FIG. 2, and the second storage capacitor 907 in FIG. 9 corresponds to the storage capacitor 203 in FIG.

  Next, the operation of the pixel circuit of this embodiment will be described with reference to FIG.

  FIG. 10 is a timing chart of video signal voltages and pulses input to the signal line 908 and the first scan line 909 to the fourth scan line 912. Since the first to fifth transistors are all n-channel transistors, the timing of the pulses input to the first scan line 909 to the fourth scan line 912 is a case where all the transistors are p-channel transistors. The H level and the L level are inverted with respect to FIG. Further, according to each operation of the pixel circuit, it is divided into four periods of a first period T1 to a fourth period T4.

The operation of the pixel circuit in FIG. 9 in the first period T1 to the fourth period T4 is the same as the operation of the pixel circuit shown in FIG. That is, in the first period T1, a certain initial voltage is held in the first holding capacitor 906 and the second holding capacitor 907. That is, initialization is performed. Next, in the second period T2, the voltage based on the threshold voltage | V _th | of the first transistor 901 is held in the first storage capacitor 906 and the second storage capacitor 907. Next, in the third period T3, a voltage based on the video signal voltage V _data and the threshold voltage | V _th | of the first transistor 901 is held in the first holding capacitor 906 and the second holding capacitor 907. . Then, in the fourth period T4, the current _{I OLED} which is dependent on the video signal voltage _{V data} to the light emitting element 916 flows, the light emitting element 916 emits light. Incidentally, _the current _{I OLED} flowing through the light emitting element 916, similar to the pixel circuit of FIG. 3 (4) represented by the formula.

Note that in order for the first storage capacitor 906 and the second storage capacitor 907 to hold a voltage based on the threshold voltage | V _th | The potential of the second terminal of the transistor 901 must be higher than the sum VSS + | V _th | of the power supply potential VSS and the threshold voltage | V _th | of the first transistor 901. Therefore, by causing a current to flow through the light-emitting element 916 in the first period T1, the potential of the second terminal of the first transistor 901 can be reliably made higher than VSS + | V _th | Compensation can be reliably performed.

  Note that in the operation process of the pixel circuit illustrated in FIG. 9, the functions of the first transistor 901 to the fifth transistor 905 are the first transistor 301 to the fifth transistor in the pixel circuit illustrated in FIG. 305 has the same function.

Through the operation process as described above, the current _IOLED is supplied to the light emitting element 916, and the light emitting element 916 can emit light with the luminance corresponding to the current _IOLED . At this time, the variation of (4) as indicated formula, _the current I _OLED flowing through the light emitting element 916, since it is represented in the form that is not dependent on the threshold voltage V _th of the first transistor 901, the threshold voltage of the transistor Can be compensated.

Note that the video signal voltage V _data is set to be equal to or higher than the potential V _CL of the capacitor line 915 in order to turn on the first transistor 901 in the fourth period T4.

Note that the potential V _CL of the capacitor line 915 only needs to be higher than the sum VSS + | V _th | of the power supply potential VSS and the threshold voltage | V _th | of the first transistor 901. Note that a voltage based on the threshold voltage | V _th | of the first transistor 901, the video signal voltage V _data, or the like can be reliably held in the first holding capacitor 906 and the second holding capacitor 907. The potential V _CL of the capacitor line 915 is desirably higher. However, in order to set the video signal voltage _{V data} than the potential _{V CL} of the capacitor line 915, it is too too high a potential _{V CL} of the capacitor line 915, will have to be even higher video signal voltage _{V data.} Therefore, it is more desirable to set the potential _VCL of the capacitor line 915 within a certain appropriate range. For example, the range of the potential V _CL of the capacitor line 915 may be set as (VDD + VSS) / 2 ≦ V _CL ≦ 3 × (VDD + VSS) / 2.

  As described above, according to the pixel configuration of this embodiment, variations in threshold voltage of transistors can be compensated and variations in luminance can be reduced, so that image quality can be improved.

In the pixel circuit of the present embodiment, as shown in the equation (4), the current _IOLED flowing through the light emitting element depends on the capacitance ratio of the first and second storage capacitors, and the capacitance ratio is constant. For example, _{IOLED is} also constant. Here, since the first and second storage capacitors are usually formed in the same process, even if a mask pattern alignment during manufacturing is shifted, the error in capacitance is the first and second. The holding capacity is almost equal. Therefore, even if a manufacturing error occurs, the value of [C ₁ / (C ₁ + C ₂ )] can be maintained at a substantially constant value, and I _OLED can also be maintained at a substantially constant value. Is possible.

In addition, when many pixels emit light simultaneously, the magnitude of the power supply potential VDD applied to the power supply line changes for each pixel arrangement position due to the voltage drop in the power supply line to which the power supply potential VDD is applied. However, in the pixel circuit of this embodiment, as shown in the equation (4), the current _IOLED flowing through the light emitting element is expressed in a form independent of the power supply potential VDD. The influence of variations in the power supply potential VDD due to the voltage drop can be eliminated.

  In the present embodiment, the first and second storage capacitors may be formed of metal or MOS transistors.

  For example, FIG. 11 and FIG. 12 show examples in which the first and second storage capacitors are formed by MOS transistors in the pixel circuit shown in FIG.

  FIG. 11 shows the case where the first storage capacitor 306 and the second storage capacitor 307 are formed of P-channel transistors. In the case of forming a storage capacitor with a P-channel transistor, it is necessary to induce a channel region in the P-channel transistor in order to retain electric charge. Therefore, the potential of the gate terminal of the P-channel transistor is set to the P-channel transistor. It must be lower than the potential of the first and second terminals of the type transistor. In the case of the pixel circuit shown in FIG. 3, in the first storage capacitor 306 and the second storage capacitor 307, the potential of the first electrode is higher than that of the second electrode. In order to function as a storage capacitor, the first and second terminals of the P-channel transistor are connected as the first electrodes of the first storage capacitor 306 and the second storage capacitor 307, and the P-channel transistor The gate terminal is connected as the second electrode of the first storage capacitor 306 and the second storage capacitor 307.

  FIG. 12 shows the case where the first storage capacitor 306 and the second storage capacitor 307 are formed of N-channel transistors. In the case of forming a storage capacitor with an N-channel transistor, it is necessary to induce a channel region in the N-channel transistor in order to retain electric charge. The potential of the first and second terminals of the type transistor must be higher. Therefore, in order to cause the N-channel transistor to function as a storage capacitor, the gate terminal of the N-channel transistor is connected as the first electrode of the first storage capacitor 306 and the second storage capacitor 307, and the N The first and second terminals of the channel transistor are connected as second electrodes of the first storage capacitor 306 and the second storage capacitor 307.

  As another example, FIGS. 13 and 14 show examples in which the first and second storage capacitors are formed of MOS transistors in the pixel circuit shown in FIG.

  FIG. 13 shows the case where the first storage capacitor 906 and the second storage capacitor 907 are formed using N-channel transistors. In the pixel circuit illustrated in FIG. 9, in the first storage capacitor 306 and the second storage capacitor 307, the potential of the second electrode is higher than that of the first electrode. In order to function as a storage capacitor, the first and second terminals of the N-channel transistor are connected as the first electrodes of the first storage capacitor 906 and the second storage capacitor 907, and the N-channel transistor The gate terminal is connected as the second electrode of the first storage capacitor 906 and the second storage capacitor 907.

  FIG. 14 shows the case where the first storage capacitor 906 and the second storage capacitor 907 are formed of P-channel transistors. In order for the P-channel transistor to function as a storage capacitor, the gate terminal of the P-channel transistor is connected as the first electrode of the first storage capacitor 906 and the second storage capacitor 907, and the P-channel transistor The first and second terminals are connected as the second electrodes of the first storage capacitor 906 and the second storage capacitor 907.

  11 to 14, the first and second storage capacitors are formed of transistors having the same conductivity type, but the present invention is not limited to this. You may form by the transistor of the conductivity type which mutually differs.

  As in this embodiment, the first and second storage capacitors are connected between the gate terminal of the first transistor and the capacitor line, so that the first and second storage capacitors are formed by MOS transistors. In this case, since a voltage higher than the threshold voltage of the MOS transistor is always applied between the gate and source of the MOS transistor, a channel region can always be induced in the MOS transistor and can always function as a storage capacitor. . Therefore, it is possible to correctly hold a desired voltage in the storage capacitor during the operation process of the pixel circuit.

In the pixel configuration of this embodiment, the value of W / L of the first transistor among the ratio W / L of the channel length L and the channel width W of each of the first to fifth transistors. Is maximized, the current flowing between the drain and source of the first transistor can be increased. Accordingly, when a voltage based on the threshold voltage | V _th | of the first transistor is acquired in the first period T1, the operation can be performed with a larger current, so that the operation can be performed more quickly. Become. In addition, the current _IOLED flowing through the light emitting element in the fourth period T4 can be increased, and the luminance can be further increased.

  Note that in this embodiment, the timings of pulses input to the second scan line and the third scan line are the same, so the third transistor and the fourth transistor are connected to the second scan line or the second scan line. It may be controlled by any one of the three scanning lines.

  For example, FIG. 15 illustrates an example in which the third transistor 303 and the fourth transistor 304 are controlled by the second scanning line 310 in the pixel circuit illustrated in FIG. Note that in FIG. 15, the gate terminal of the third transistor 303 and the gate terminal of the fourth transistor 304 are connected to the second scanning line 310.

  As another example, FIG. 16 illustrates an example in which the third transistor 903 and the fourth transistor 904 are controlled by the second scanning line 910 in the pixel circuit illustrated in FIG. Note that in FIG. 16, the gate terminal of the third transistor 903 and the gate terminal of the fourth transistor 904 are connected to the second scanning line 910.

  Thus, by controlling the third and fourth transistors with the same scanning line, the number of scanning lines can be reduced and the aperture ratio of the pixel can be increased.

  In this embodiment, the second to fifth transistors are all P-channel type or all N-channel type transistors having the same conductivity type. However, the present invention is not limited to this. A circuit may be configured using both the P-channel type and the N-channel type.

  For example, in FIG. 3, the fourth transistor 304 may be an n-channel transistor, and transistors other than the fourth transistor 304 may be a p-channel transistor. This pixel circuit is shown in FIG. FIG. 18 shows a timing chart of video signal voltages and pulses inputted to the signal line 308 and the first scan line 309 to the fourth scan line 312.

  In this manner, when the fourth transistor 304 is an n-channel transistor, leakage current in the fourth transistor 304 is smaller than that in the case of a p-channel transistor, and thus the first storage capacitor 306 and the second storage capacitor The leakage of the charge held in 307 is reduced, and the fluctuation of the voltage held in the first holding capacitor 306 and the second holding capacitor 307 is reduced. Accordingly, since a constant voltage is always applied to the gate terminal of the first transistor 301, particularly in the light emission period (T4), a constant current can be supplied to the light emitting element 316. As a result, the light-emitting element 316 can emit light with a constant luminance, and luminance unevenness can be reduced.

  Note that the conductivity type of the second transistor to the fifth transistor is not limited to the above.

(Embodiment 2)
In the first embodiment, the capacitor line is provided separately, but other existing wiring may be used instead of the capacitor line. For example, the capacitance line can be deleted by using any one of the first to fourth scanning lines instead of the capacitance line. In the present embodiment, a case where any one of the first to fourth scanning lines is used instead of the capacitor line will be described. Note that an EL element is described as an example of a light-emitting element.

  For example, FIG. 19 shows an example of the pixel circuit in the case where the first scanning line in the previous row is used instead of the capacitor line in FIG. In FIG. 19, the first scanning line 1909 of the pixel Pixel (i−1) in the (i−1) th row is used instead of the capacitance line of the pixel Pixel (i) in a certain ith row, The second terminal of the third transistor 1923 of the pixel Pixel (i) of the eye and the second terminal of the second storage capacitor 1927 are connected to the first pixel Pixel (i-1) of the (i−1) -th row. It is connected to the scanning line 1909.

  In addition, the first scan line 1909 to the fourth scan line 1912 of the pixel Pixel (i−1) in the pixel line (i−1) in the (i−1) th row and the first pixel Pixel (i) in the i th row. FIG. 20 shows a timing chart of video signal voltages and pulses input to the first scan line 1929 to the fourth scan line 1932. Note that periods T1 to T4 illustrated in FIG. 20 correspond to the operation of the pixel Pixel (i) in the i-th row.

  In the pixel configuration as shown in FIG. 19, the second terminal of the third transistor 1923 of the pixel Pixel (i) in the i-th row and the second terminal of the second storage capacitor 1927 have (i−1) A potential applied to the first scanning line 1909 of the pixel Pixel (i-1) in the row is applied. Accordingly, an L-level potential is applied to the second terminal of the third transistor 1923 of the pixel Pixel (i) in the i-th row and the second electrode of the second storage capacitor 1927 in the period T2, and the period T1 , T3, T4, an H level potential is applied. Accordingly, a constant potential can be applied to the second terminal of the third transistor 1923 of the pixel Pixel (i) in the i-th row and the second electrode of the second storage capacitor 1927 in each period. The operation of the pixel circuit as described in Embodiment Mode 1 can be performed.

  As another example, FIG. 21 shows an example in which the first scanning line in the previous row is used instead of the capacitor line in FIG. In FIG. 21, the first scanning line 2109 of the pixel Pixel (i-1) in the (i-1) th row is used instead of the capacitance line of the pixel Pixel (i) in a certain ith row. The second terminal of the third transistor 2123 of the pixel Pixel (i) of the eye and the second electrode of the second storage capacitor 2127 are connected to the first pixel Pixel (i-1) of the (i-1) th row. Are connected to the scanning line 2109.

  In addition, the first scanning line 2109 to the fourth scanning line 2112 of the pixel Pixel (i−1) in the pixel line (i−1) of the signal line 2108 and the first pixel Pixel (i) of the i th row. FIG. 22 shows a timing chart of video signal voltages and pulses inputted to the scanning line 2129 to the fourth scanning line 2132. Note that periods T1 to T4 illustrated in FIG. 22 correspond to the operation of the pixel Pixel (i) in the i-th row.

  With the pixel configuration as shown in FIG. 21, the second terminal of the third transistor 2123 of the pixel Pixel (i) in the i-th row and the second electrode of the second storage capacitor 2127 have (i−1 ) A potential applied to the first scanning line 2109 of the pixel Pixel (i-1) in the row is applied. Therefore, an H-level potential is applied to the second terminal of the third transistor 2123 of the pixel Pixel (i) in the i-th row and the second electrode of the second storage capacitor 2127 in the period T2, and the period T1 , T3, T4, an L level potential is applied. Accordingly, a constant potential can be applied to the second terminal of the third transistor 2123 of the pixel Pixel (i) in the i-th row and the second electrode of the second storage capacitor 2127 in each period. The operation of the pixel circuit as described in Embodiment Mode 1 can be performed.

  In this manner, by using the first scanning line in the previous row instead of the capacitor line, it is not necessary to newly provide a capacitor line, so that the number of wirings can be reduced and the aperture ratio of the pixel can be increased. it can. In addition, since it is not necessary to newly generate a voltage to be applied to the capacitor line, it is possible to reduce a circuit therefor and to reduce power consumption.

  Note that the scanning line used instead of the capacitor line is not limited to the first scanning line in the previous row. Any one of the second to fourth scanning lines in the previous row may be used instead of the capacitor line. Also, any one of the first to fourth scanning lines in the next row may be used. Note that, during the light emission period (T4) of the pixels in this row, a constant potential is applied to the first scan line and the fourth scan line in the previous row, and thus light emission occurs during the light emission period of the pixels in this row. The current flowing through the element can be maintained at a constant value, and the light emitting element can emit light with constant luminance. Therefore, it is desirable to use the first scanning line in the previous row or the fourth scanning line in the previous row instead of the capacitor line.

  Note that the contents described in this embodiment can be implemented by being freely combined with the contents described in Embodiment 1.

(Embodiment 3)
In the first and second embodiments, a current is supplied to the light emitting element when initialization is performed. However, the initialization can be performed by adding a new initialization transistor to the pixel circuit described so far. It is also possible to perform. In this embodiment, a method for performing initialization using an initialization transistor will be described. Note that an EL element is described as an example of a light-emitting element.

  In order to perform initialization, it is necessary to set the second terminal of the first transistor to a certain initial potential. At this time, the second terminal of the first transistor is connected to an electrode of another element or another wiring through the initialization transistor, and the initialization transistor is turned on, whereby the first transistor of the first transistor is turned on. Two terminals can be set to a potential of a connection destination electrode or wiring.

  That is, the initialization transistor connects the second terminal of the first transistor and the electrode of another element or another wiring in order to set the potential of the second terminal of the first transistor to a certain initial potential. Functions as a switch.

For example, in the case of the pixel circuit illustrated in FIG. 3, in order for the first storage capacitor 306 and the second storage capacitor 307 to hold a voltage based on the threshold voltage | V _th | The potential of the second terminal of the first transistor 301 must be lower than the difference VDD− | V _th | between the power supply potential VDD and the threshold voltage | V _th | of the first transistor 301. Therefore, in the first period T1, the second terminal of the first transistor 301 is connected to the second terminal of the first transistor 301 and the electrode of another element or another wiring through an initialization transistor. The potential of the terminal can be set to an initial voltage lower than VDD− | V _th |.

  Here, FIG. 23 shows an example in which an initialization transistor is provided in the pixel circuit shown in FIG. In FIG. 23, a sixth transistor 2317 and a fifth scanning line 2318, which are initialization transistors, are newly added to the pixel circuit shown in FIG. Note that the sixth transistor 2317 has a gate terminal connected to the fifth scan line 2318, a first terminal connected to the second terminal of the first transistor 301, a first terminal of the fourth transistor 304, and The second terminal is connected to the first terminal of the fifth transistor 305, the second terminal is the second terminal of the second transistor 302, the first terminal of the third transistor 303, and the second terminal of the first storage capacitor 306. Connected to the electrode.

  Next, the operation of the pixel circuit shown in FIG. 23 will be described with reference to FIGS.

  FIG. 24 shows a timing chart of video signal voltages and pulses inputted to the signal line 308 and the first scan line 309 to the fifth scan line 2318, and T1 to T4 according to each operation of the pixel circuit. It is divided into four periods.

The operation of the pixel circuit in the first period T1 is described with reference to FIG. In the period T1, the second scan line 310, the third scan line 311, and the fifth scan line 2318 are at an L level, and the third transistor 303, the fourth transistor 304, and the sixth transistor 2317 are turned on. In addition, the first scan line 309 and the fourth scan line 312 are at an H level, and the second transistor 302 and the fifth transistor 305 are turned off. Accordingly, since the second terminal of the first transistor 301 and the capacitor line 315 are connected, the second terminal of the first transistor 301, the first electrode of the first storage capacitor 306, and the second storage The potential of the first electrode of the capacitor 307 becomes equal to the potential V _CL of the capacitor line 315.

Through the above operation, in the period T1, the potentials of the second terminal of the first transistor 301, the first electrode of the first storage capacitor 306, and the first electrode of the second storage capacitor 307 are set to the initial potential. As described above, the potential V _CL of the capacitor line 315 is set.

In this manner, in the period T1, the potential of the second terminal of the first transistor 301 is set to the potential V _CL of the capacitor line 315 which is lower than VDD− | V _th |, so that the first transistor The potential of the second terminal 301 can be reliably made lower than VDD− | V _th |, and the threshold voltage can be reliably compensated.

  Note that in the period T2 to T4, the fifth scan line 2318 is set at an H level and the sixth transistor 2317 is turned off. Then, the same operation as that of the pixel circuit shown in FIG. 3 is performed.

Note that the sixth transistor 2317 may be connected so that the second terminal of the first transistor 301 is set to a potential lower than VDD− | V _th | during the initialization period T1.

  For example, as illustrated in FIG. 26, the first terminal of the sixth transistor 2317, the gate terminal of the first transistor 301, the second terminal of the fourth transistor 304, and the first terminal of the first storage capacitor 306 are provided. And the first electrode of the second storage capacitor 307 may be connected. In addition, as illustrated in FIG. 27, the second terminal of the sixth transistor 2317 may be connected to the capacitor line 315. As shown in FIG. 65, the second terminal of the sixth transistor 2317 may be connected to the second scanning line 310, or the second terminal of the sixth transistor 2317 as shown in FIG. May be connected to the third scanning line 311.

  Further, in order to set the second terminal of the first transistor 301 to a certain initial potential, a new initialization line (initialization power supply line) may be provided.

  For example, FIG. 28 shows an example in which an initialization transistor and an initialization line are provided in the pixel circuit shown in FIG. 28, a sixth transistor 2317, a fifth scanning line 2318, and an initialization line 2819, which are initialization transistors, are newly added to the pixel circuit illustrated in FIG. Note that the sixth transistor 2317 has a gate terminal connected to the fifth scan line 2318, a first terminal connected to the second terminal of the first transistor 301, a first terminal of the fourth transistor 304, and The fifth transistor 305 is connected to the first terminal, and the second terminal is connected to the initialization line 2819.

The initialization potential V _ini is applied to the initialization line 2819. Note that the potential relationship is V _ini <VDD− | V _th |.

FIG. 29 shows an operation of the pixel circuit shown in FIG. 28 in the first period T1. In the period T1, the first transistor 301 is in a diode connection state, and a current flows through the initialization line 2819. As a result, the potentials of the second terminal of the first transistor 301, the first electrode of the first storage capacitor 306, and the first electrode of the second storage capacitor 307 are equal to the potential of the initialization line 2819. The difference V _ini −V _CL between the initialization potential V _ini and the potential V _CL of the capacitor line 315 is held in the first storage capacitor 306 and the second storage capacitor 307.

  Through the above operation, in the period T1, the first storage capacitor 306 and the second storage capacitor 307 hold a voltage corresponding to the difference between the potential of the initialization line 2819 and the potential of the capacitor line 315 as the initial voltage.

In this manner, the initialization line 2819 is provided, and the potential of the second terminal of the first transistor 301 is set such that the initialization potential V _ini which is lower than VDD− | V _th | and the potential V _{CL of the} capacitor line 315 By setting to the difference V _ini −V _CL , the potential of the second terminal of the first transistor 301 can be surely made lower than VDD− | V _th |, and the threshold voltage can be reliably compensated. Will be able to.

Note that the sixth transistor 2317 may be connected so that the second terminal of the first transistor 301 is set to the initialization potential _Vini . For example, as illustrated in FIG. 30, the first terminal of the sixth transistor 2317 is connected to the gate terminal of the first transistor 301, the second terminal of the fourth transistor 304, and the first terminal of the first storage capacitor 306. And the first electrode of the second storage capacitor 307 may be connected.

  In this way, by performing initialization by newly adding an initialization transistor and an initialization line, the threshold voltage of the first transistor can be acquired and compensated more reliably.

  Further, in the initialization method described in Embodiment Mode 1, since current flows through the light emitting element during initialization, the light emitting element emits light in the period T1, but in this method, initialization is performed. Since no current flows through the light-emitting element during the light emission, the light-emitting element does not emit light during the period T1, and light emission of the light-emitting element outside the light-emitting period can be suppressed.

  In the present embodiment, the sixth transistor, which is an initialization transistor, is a P-channel type, but the present invention is not limited to this. N-channel type may be used.

  In this embodiment, only the example in the case where the first transistor is a P-channel type (FIG. 3) has been described. However, the contents of this embodiment are similar to those of the pixel circuit shown in FIG. This can also be applied to the case where the first transistor is an N-channel type.

Note that in the case where an initialization transistor is added to the pixel circuit illustrated in FIG. 9, the potential of the second terminal of the first transistor is the sum VSS + of the power supply potential VSS and the threshold voltage | V _th | of the first transistor. It connects so that it may be set to a potential higher than | V _th |. When an initialization line is added, the potential V _ini applied to the initialization line is set to a potential higher than the sum VSS + | V _th | of the power supply potential VSS and the threshold voltage | V _th | of the first transistor. To do.

  In this embodiment, the initialization line is provided separately, but other existing wiring may be used instead of the initialization line. For example, any one of the first to fifth scanning lines may be used instead of the initialization line. Note that a wiring used instead of the initialization line is not limited to any wiring included in the pixel in this row. Any wiring included in pixels in other rows may be used. Thereby, since there is no need to newly provide an initialization line, the number of wirings can be reduced and the aperture ratio of the pixel can be increased.

  Note that the contents described in this embodiment mode can be implemented by being freely combined with the contents described in Embodiment Modes 1 and 2.

(Embodiment 4)
In Embodiments 1 to 3, the potential of the second power supply line is set to a fixed potential. However, the potential of the second power supply line may be changed according to the first to fourth periods. In this embodiment, a case where the potential of the second power supply line is changed in accordance with the first to fourth periods will be described. Note that an EL element is described as an example of a light-emitting element.

  For example, in the pixel circuit illustrated in FIG. 3, in the second period T2 and the third period T3, the fifth transistor 305 is turned off so that no current flows through the light-emitting element 316. For example, the fifth transistor 305 is deleted, the second terminal of the first transistor 301 and the first terminal of the light-emitting element 316 are directly connected, and the second power supply is supplied in the second period T2 and the third period T3. By making the potential of the line 314 higher than the potential of the first terminal of the light-emitting element 316, current can be prevented from flowing through the light-emitting element 316. This is because by making the potential of the second power supply line 314 higher than the potential of the first terminal of the light-emitting element 316, a reverse bias is applied to the light-emitting element 316. An example of this case is shown in FIGS.

  In FIG. 31, the second terminal of the first transistor 301 is connected to the first terminal of the light emitting element 316 with respect to the pixel circuit shown in FIG. FIG. 32 shows a timing chart of video signal voltages and pulses inputted to the signal line 308, the first scanning line 309 to the third scanning line 311 and the second power supply line 314. Note that the timing of pulses input to the first scan line 309 to the third scan line 311 is the same as that of the pixel circuit shown in FIG.

Note that in the second period T2 and the third period T3, the potential of the second power supply line 314 is set to a difference VDD− | V _th | between the power supply potential VDD and the threshold voltage | V _th | of the first transistor 301. With the above, a reverse bias is applied to the light-emitting element 316, so that no current flows through the light-emitting element 316 in the second period T2 and the third period T3.

  Note that as an initialization method, the initialization method described in Embodiment 3 using an initialization transistor may be used. In this case, in the period T1, the potential of the second power supply line 314 is set higher than the potential of the second terminal of the first transistor, so that initialization can be performed without flowing current through the light-emitting element 316. Become.

As an initialization method, the method described in Embodiment 3 for initialization using an initialization transistor and an initialization line may be used. In this case, in the period T1, initialization can be performed without flowing current to the light-emitting element 316 by setting the potential of the second power supply line 314 to be equal to or higher than the initialization potential _Vini .

  As another example, FIGS. 33 and 34 show an example in which the potential of the second power supply line is changed in the pixel circuit shown in FIG.

  In FIG. 33, the second terminal of the first transistor 901 is connected to the second electrode of the light emitting element 916 with respect to the pixel circuit shown in FIG. FIG. 34 shows a timing chart of video signal voltages and pulses input to the signal line 908, the first scan line 909 to the third scan line 911, and the second power supply line 914. Note that the timing of pulses input to the first scan line 909 to the third scan line 911 is the same as that of the pixel circuit shown in FIG.

  By making the potential of the second power supply line 914 lower than the potential of the second electrode of the light emitting element 916 in the second period T2 and the third period T3, a reverse bias is applied to the light emitting element 916. The current can be prevented from flowing through the light emitting element 916 in the periods T2 and T3.

Note that in the second period T2 and the third period T3, the potential of the second power supply line 914 is equal to or lower than the sum VSS + | _Vth | of the power supply potential VSS and the threshold voltage | _Vth | of the first transistor 901. Thus, the above operation can be performed.

  Note that as an initialization method, the initialization method described in Embodiment 3 using an initialization transistor may be used. In this case, in the period T1, the potential of the second power supply line 914 is set lower than the potential of the second terminal of the first transistor, so that initialization can be performed without flowing current through the light-emitting element 916. Become.

As an initialization method, the method described in Embodiment 3 for initialization using an initialization transistor and an initialization line may be used. In this case, in the period T1, initialization can be performed without flowing current through the light-emitting element 916 by setting the potential of the second power supply line 914 to be equal to or lower than the initialization potential _Vini .

  In this manner, by changing the potential of the second power supply line depending on the period, current can be prevented from flowing in the light-emitting element during a period other than the light-emitting period (T4), and thus the light-emitting element in a period other than the light-emitting period Luminescence can be suppressed. In addition, since it is not necessary to provide the fifth transistor and the fourth scan line, the aperture ratio of the pixel can be increased. In addition, since the number of scan line driver circuits can be reduced, power consumption can be reduced.

  Note that the content described in this embodiment mode can be implemented by being freely combined with the content described in Embodiment Modes 1 to 3.

(Embodiment 5)
In Embodiments 1 to 4, the second terminal of the third transistor and the second electrode of the second storage capacitor are connected to the common capacitor line. The two terminals and the second electrode of the second storage capacitor may be connected to separate wirings. In this embodiment, a case will be described in which a reference line is newly provided, the second electrode of the second storage capacitor is connected to the capacitor line, and the second terminal of the third transistor is connected to the reference line. Note that an EL element is described as an example of a light-emitting element.

  For example, FIG. 35 shows an example in which the second electrode of the second storage capacitor is connected to the capacitor line and the second terminal of the third transistor is connected to the reference line in the pixel circuit shown in FIG. In FIG. 35, a reference line 3517 is newly added to the pixel circuit shown in FIG. The second electrode of the second storage capacitor 307 is connected to the capacitor line 315, and the second terminal of the third transistor 303 is connected to the reference line 3517.

A reference potential V _ref is applied to the reference line 3517.

The operation process of the pixel circuit shown in FIG. 35 is almost the same as the operation process of the pixel circuit shown in FIG. 3 is different from the operation process of the pixel circuit shown in FIG. 3 in that each time period, the voltage held in the first holding capacitor 306 and the second holding capacitor 307 and the light emitting element in the light emitting period (T4). This is the magnitude of the current _IOLED flowing through 316.

  First, initialization is performed in the period T1.

Next, in the period T2, the first storage capacitor 306 and the second storage capacitor 307 hold a voltage based on the threshold voltage | V _th | of the first transistor 301. At this time, the first storage capacitor 306 holds the difference VDD− | V _th | −V _ref between the power supply potential VDD and the threshold voltage | V _th | of the first transistor 301 and the reference potential V _ref . The second storage capacitor 307 holds a difference VDD− | V _th | −V _CL between the power supply potential VDD and the threshold voltage | V _th | of the first transistor 301 and the potential V _CL of the capacitor line 315. The

Next, in the period T <b> 3, a voltage based on the video signal voltage V _data and the threshold voltage | V _th | of the first transistor 301 is held in the first holding capacitor 306 and the second holding capacitor 307. At this time, if the voltages held in the first holding capacitor 306 and the second holding capacitor 307 are V _C1 (T3) and V _C2 (T3), V _C1 (T3) and V _C2 (T3) are It is expressed as the following equations (5) and (6).

Then, in the period T4, the current _{I OLED} which is dependent on the video signal voltage _{V data} to the light emitting element 316 flows, the light emitting element 316 emits light. At this time, assuming that the gate-source voltage of the first transistor 301 is V _gs (T4), V _gs (T4) is expressed by the following equation (7). _{The OLED} is expressed as the following equation (8).

Note that in the period T < _{b > 4} , the video signal voltage V _data is set to be equal to or lower than the reference potential V _ref in order to turn on the first transistor 301.

  As another example, in the pixel circuit shown in FIG. 9, the second electrode of the second storage capacitor is connected to the capacitor line, and the second terminal of the third transistor is connected to the reference line. As shown in FIG. In FIG. 36, a reference line 3617 is newly added to the pixel circuit shown in FIG. The second electrode of the second storage capacitor 907 is connected to the capacitor line 915, and the second terminal of the third transistor 903 is connected to the reference line 3617.

A reference potential V _ref is applied to the reference line 3617.

The operation process of the pixel circuit shown in FIG. 36 is almost the same as the operation process of the pixel circuit shown in FIG. 9 is different from the operation process of the pixel circuit shown in FIG. 9 in that each time period, the light-emitting element is in the magnitude of the voltage held in the first holding capacitor 906 and the second holding capacitor 907 and in the light-emitting period (T4). It is the magnitude of the current _{I OLED} flowing to 916. _The current _{I OLED} flowing through the light emitting element 916 in the light emitting period (T4), like the pixel circuit shown in FIG. 35 is expressed as (8).

Note that in the period T _<b > 4, the video signal voltage V _data is set to be equal to or higher than the reference potential V _ref in order to turn on the first transistor 901.

Thus, in the pixel circuits shown in FIGS. 35 and 36, the current _IOLED flowing through the light emitting element depends on the difference between the video signal voltage _Vdata and the reference potential _Vref as shown in the equation (8). To do.

Note that in the pixel circuit illustrated in FIGS. 35 and 36, the range that the reference potential V _ref can take is not particularly limited.

In this manner, by providing the capacitor line and the reference line separately, the potentials of the capacitor line and the reference line can be controlled separately. In the pixel configurations described in Embodiments 1 to 4, the range that the video signal voltage V _data can take depends on the potential V _{CL of the} capacitor line. However, in the pixel configuration of this embodiment, video since the possible range of the signal voltage V _data is dependent on the reference voltage V _ref, by fixing the potential V _CL of the capacitor line to an appropriate value, setting the reference potential V _ref in the appropriate range, the video signal voltage The possible range of V _data can be set to an appropriate range.

  In this embodiment, the reference line is provided separately, but other existing wiring may be used instead of the reference line. For example, any one of the first to fifth scanning lines may be used instead of the reference line. Note that a wiring used instead of the reference line is not limited to any wiring included in the pixel of this row. Any wiring included in pixels in other rows may be used. Accordingly, since it is not necessary to newly provide a reference line, the number of wirings can be reduced and the aperture ratio of the pixel can be increased.

  Note that the content described in this embodiment mode can be freely combined with the content described in Embodiment Modes 1 to 4.

(Embodiment 6)
In this embodiment mode, a pixel layout in the display device of the present invention will be described. For example, FIG. 37 shows a layout diagram of the pixel circuit shown in FIG. The numbers given in FIG. 37 coincide with the numbers given in FIG. The layout diagram is not limited to FIG.

  3 includes a first transistor 301 to a fifth transistor 305, a first storage capacitor 306 and a second storage capacitor 307, a signal line 308, and a first scan line 309 to a fourth scan. A line 312, a first power line 313, a second power line 314, a capacitor line 315, and a light emitting element 316 are included.

  The first scan line 309 to the fourth scan line 312 are formed by the first wiring, and the signal line 308, the first power supply line 313, the second power supply line 314, and the capacitor line 315 are formed by the second wiring. Has been.

  In the case of the top gate structure, the film is formed in the order of the substrate, the semiconductor layer, the gate insulating film, the first wiring, the interlayer insulating film, and the second wiring. In the case of the bottom gate structure, the film is formed in the order of the substrate, the first wiring, the gate insulating film, the semiconductor layer, the interlayer insulating film, and the second wiring.

Note that in the pixel configuration of this embodiment, the first transistor 301 has a ratio W / L of the channel length L to the channel width W of each of the first transistor 301 to the fifth transistor 305. When the value of W / L is maximized, the current flowing between the drain and source of the first transistor 301 can be increased. Accordingly, when a voltage based on the video signal voltage V _data and the threshold voltage | V _th | of the first transistor 301 is acquired in the third period T3, the operation can be performed with a larger current. It becomes possible to operate quickly. In addition, the current _IOLED flowing through the light emitting element in the period T4 can be further increased, and the luminance can be further increased. Therefore, in order to maximize the value of W / L included in the first transistor 301, the first transistor 301 has the first transistor 301 to the fifth transistor 305 in FIG. The channel width W is maximized.

  Note that although the first transistor 301 to the fifth transistor 305 are described with a single gate structure in this embodiment, the present invention is not limited to this. The structures of the first transistor 301 to the fifth transistor 305 can take various forms. For example, a multi-gate structure having two or more gate electrodes may be used. When the multi-gate structure is used, the channel regions are connected in series, so that a plurality of transistors are connected in series. With the multi-gate structure, off-state current is reduced, the withstand voltage of the transistor is improved, reliability is improved, and even when the voltage between the drain and the source changes when operating in the saturation region, The inter-current does not change so much, and a flat characteristic can be obtained. Alternatively, a structure in which gate electrodes are arranged above and below the channel may be employed. By adopting a structure in which the gate electrodes are arranged above and below the channel, the channel region is increased, so that the current value is increased, a depletion layer is easily formed, and the S value can be decreased. When gate electrodes are provided above and below a channel, a structure in which a plurality of transistors are connected in parallel is obtained.

  Further, a structure in which a gate electrode is disposed above a channel, a structure in which a gate electrode is disposed below a channel, a normal staggered structure, or an inverted staggered structure may be employed. The channel region may be divided into a plurality of regions, may be connected in parallel, or may be connected in series. In addition, a source electrode or a drain electrode may overlap with the channel (or part thereof). By using a structure in which a source electrode or a drain electrode overlaps with a channel (or part thereof), it is possible to prevent electric charges from being accumulated in part of the channel and becoming unstable. There may also be an LDD region. By providing the LDD region, the off-state current is reduced, the breakdown voltage of the transistor is improved, the reliability is improved, and even when the voltage between the drain and the source changes when operating in the saturation region, the drain and the source During this period, the current does not change so much and a flat characteristic can be obtained.

  The wiring and electrodes are made of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt ), Gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P ), Boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), one or more elements selected from the group, or a group A compound or an alloy material containing one or more elements selected from (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide to which silicon oxide is added (ITS)) ), Zinc oxide (ZnO), aluminum neodymium (Al-Nd), magnesium silver (Mg-Ag), etc.), or is formed with a like material that combines these compounds. Alternatively, a silicon compound (silicide) (for example, aluminum silicon, molybdenum silicon, nickel silicide, or the like) or a nitrogen compound (for example, titanium nitride, tantalum nitride, molybdenum nitride, or the like) is formed. .

  Note that silicon (Si) may contain a large amount of N-type impurities (such as phosphorus) and P-type impurities (such as boron). By containing these impurities, the conductivity is improved and the same behavior as a normal conductor is obtained, so that it becomes easy to use as a wiring or an electrode. Silicon may be single crystal, polycrystalline (polysilicon), or amorphous (amorphous silicon). The resistance can be reduced by using single crystal silicon or polycrystalline silicon. By using amorphous silicon, it can be manufactured by a simple manufacturing process. Note that since aluminum and silver have high conductivity, signal delay can be reduced and etching is easy, so that patterning is easy and microfabrication can be performed.

  Note that since copper has high conductivity, signal delay can be reduced. Molybdenum can be manufactured without causing problems such as defective materials even when it comes into contact with oxide semiconductors such as ITO and IZO, and silicon, and is easy to pattern and etch, and has high heat resistance. Therefore, it is desirable. Titanium is desirable because it can be manufactured without causing problems such as failure of the material even when it comes into contact with an oxide semiconductor such as ITO or IZO or silicon, and has high heat resistance. Tungsten is desirable because of its high heat resistance. Neodymium is desirable because of its high heat resistance. In particular, an alloy of neodymium and aluminum is preferable because the heat resistance is improved and aluminum does not easily cause hillocks. Silicon is preferable because it can be formed at the same time as a semiconductor layer included in the transistor and has high heat resistance. Note that indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), zinc oxide (ZnO), and silicon (Si) have translucency. Therefore, it is desirable because it can be used for a portion that transmits light. For example, it can be used as a pixel electrode or a common electrode.

  In addition, these may form wiring and an electrode with a single layer, and may have a multilayer structure. By forming with a single layer structure, the manufacturing process can be simplified, the number of process days can be reduced, and the cost can be reduced. In addition, by using a multilayer structure, it is possible to take advantage of each material, reduce demerits, and form wiring and electrodes with good performance. For example, by including a low-resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. In addition, if a material having high heat resistance is included, for example, a wiring or electrode as a whole can be obtained by forming a laminated structure in which a material having low merit is sandwiched between materials having another merit. As a result, the heat resistance can be increased.

  For example, it is preferable to form a layered structure in which a layer containing aluminum is sandwiched between layers containing molybdenum or titanium. In addition, if there is a portion that is in direct contact with a wiring or electrode of another material, it may adversely affect each other. For example, one material may be contained in the other material, changing its properties and failing to fulfill its original purpose, or producing a problem and making it impossible to manufacture normally. is there. In such a case, the problem can be solved by sandwiching or covering one layer with another layer. For example, when indium tin oxide (ITO) and aluminum are in contact with each other, it is desirable to sandwich titanium or molybdenum between them. In addition, when silicon and aluminum are to be brought into contact with each other, it is desirable to sandwich titanium or molybdenum between them.

  According to the pixel of this embodiment mode, as in the pixel circuit illustrated in FIG. 3, when the fourth transistor 304 is an N-channel transistor, the leakage current in the fourth transistor 304 is a P-channel transistor. Therefore, the leakage of charges held in the first holding capacitor 306 and the second holding capacitor 307 is reduced, and the fluctuation of the voltage held in the first holding capacitor 306 and the second holding capacitor 307 is small. Become. Accordingly, since a constant voltage is always applied to the gate electrode of the first transistor 301, particularly during the light emission period, a constant current can be supplied to the light emitting element. As a result, the light-emitting element can emit light with a constant luminance, and luminance unevenness can be reduced.

  Note that the content described in this embodiment mode can be freely combined with the content described in Embodiment Modes 1 to 5.

(Embodiment 7)
In this embodiment, the configuration and operation of a signal line driver circuit, a scan line driver circuit, and the like in a display device will be described.

  For example, a display device having a pixel circuit whose operation is controlled using signal lines and first to fourth scanning lines as shown in FIGS. 3 and 9 has a structure as shown in FIG. Yes. The display device illustrated in FIG. 38 includes a pixel portion 3801, a first scan line driver circuit 3802, a fourth scan line driver circuit 3805, and a signal line driver circuit 3806.

  Here, the first scan line driver circuit 3802 to the fourth scan line driver circuit 3805 are drive circuits for sequentially outputting selection signals to the first scan line 3807 to the fourth scan line 3810, respectively. .

  First, the signal line driver circuit will be described. The signal line driver circuit 3806 sequentially outputs video signals to the pixel portion 3801 through the signal line 3811. The pixel portion 3801 displays an image by controlling the light emission state of the pixel in accordance with the video signal.

  An example of the structure of the signal line driver circuit 3806 is shown in FIG. FIG. 39A illustrates an example of a signal line driver circuit 3806 in the case where a signal is supplied to a pixel by line sequential driving. The signal line driver circuit 3806 in this case mainly includes a shift register 3901, a first latch circuit 3902, a second latch circuit 3903, and an amplifier circuit 3904. Note that the amplifier circuit 3904 may have a function of converting a digital signal into analog or a function of performing gamma correction.

  Here, operation of the signal line driver circuit 3806 illustrated in FIG. 39A is briefly described. A clock signal (S-CLK), a start pulse (S-SP), and a clock inversion signal (S-CLKB) are input to the shift register 3901, and sampling pulses are sequentially output according to the timing of these signals.

The sampling pulse output from the shift register 3901 is input to the first latch circuit 3902. A video signal is input to the first latch circuit 3902 from the video signal line with the voltage V _data , and the video signal is held in each first latch circuit 3902 according to the timing at which the sampling pulse is input. Go.

When the holding of the video signal is completed in each first latch circuit 3902, the latch signal is input from the latch control line during the horizontal blanking period, and the video signal held in the first latch circuit 3902 is The data is transferred all at once to the second latch circuit 3903. Thereafter, one row of the video signal held in the second latch circuit 3903 is input to the amplifier circuit 3904 at the same time. Then, the amplitude of the video signal voltage V _data is amplified by the amplifier circuit 3904, and the video signal is input from each signal line to the pixel portion 3801.

  While the video signal held in the second latch circuit 3903 is input to the amplifier circuit 3904 and is input to the pixel portion 3801, the shift register 3901 outputs a sampling pulse again. That is, two operations are performed simultaneously. Thereby, line-sequential driving becomes possible. Thereafter, this operation is repeated.

Note that a signal may be supplied to the pixel by dot sequential driving. An example of the signal line driver circuit 3806 in that case is illustrated in FIG. In this case, the signal line driver circuit 3806 includes a shift register 3901 and a sampling circuit 3905. A sampling pulse is output from the shift register 3901 to the sampling circuit 3905. In addition, a video signal is input to the sampling circuit 3905 from the video signal line at the voltage V _data , and the video signal is sequentially output to the pixel portion 3801 in accordance with the sampling pulse. Thereby, dot sequential driving becomes possible.

  Next, the scanning line driving circuit will be described. The first scan line driver circuit 3802 to the fourth scan line driver circuit 3805 sequentially output selection signals to the pixel portion 3801. An example of the structure of the first scan line driver circuit 3802 to the fourth scan line driver circuit 3805 is shown in FIG. The scanning line driver circuit mainly includes a shift register 4001 and an amplifier circuit 4002.

  Next, operations of the first scan line driver circuit 3802 to the fourth scan line driver circuit 3805 shown in FIG. 40 will be briefly described. A clock signal (G-CLK), a start pulse (G-SP), and a clock inversion signal (G-CLKB) are input to the shift register 4001, and sampling pulses are sequentially output according to the timing of these signals. The output sampling pulse is amplified by the amplifier circuit 4002 and input to the pixel portion 3801 from each scanning line.

  Note that the amplifier circuit 4002 may have a buffer circuit or a level shifter circuit. In addition to the shift register 4001 and the amplifier circuit 4002, a pulse width control circuit or the like may be provided in the scan line driver circuit.

  By using the signal line driver circuit and the scan line driver circuit as described above, the pixel circuit of the present invention can be driven.

  Note that, for example, when the third transistor and the fourth transistor have different conductivity types as in the pixel circuit illustrated in FIG. 17, selection signals that are inverted from each other are applied to the second and third scanning lines. Is entered. Therefore, the selection signal input to one of the second and third scanning lines is controlled using one of the second and third scanning line driving circuits, and the other scanning line has its An inversion signal may be input. A configuration example of the display device in this case is shown in FIG. In FIG. 41, a selection signal input to the second scan line 3808 is controlled using the second scan line driver circuit 3803. In addition, an inverted signal of the selection signal input to the second scan line 3808 is generated using the inverter 3812 and input to the third scan line 3809.

  Further, for example, when the third transistor and the fourth transistor have the same conductivity type as in the pixel circuit shown in FIGS. 3 and 9, the same selection is used for the second and third scanning lines. A signal is input. Therefore, the third and fourth transistors may be controlled using the same scanning line as in the pixel circuit shown in FIGS. A configuration example of the display device in this case is shown in FIG. FIG. 42 illustrates the case where the third transistor and the fourth transistor are controlled using the second scan line 3808, and the second scan line 3808 is controlled by the second scan line driver circuit 3803.

  Note that the structures of the signal line driver circuit, the scan line driver circuit, and the like are not limited to FIGS.

  Note that the transistor in the present invention may be any type of transistor, and may be formed on any substrate. Therefore, the circuits as shown in FIGS. 38 to 42 may all be formed on a glass substrate, may be formed on a plastic substrate, or may be formed on a single crystal substrate. It may be formed on an SOI substrate or on any substrate. Alternatively, part of the circuits in FIGS. 38 to 42 may be formed on a certain substrate, and another part of the circuits in FIGS. 38 to 42 may be formed on another substrate. That is, not all of the circuits in FIGS. 38 to 42 need to be formed on the same substrate. For example, in FIGS. 38 to 42, the pixel portion and the scan line driver circuit are formed using a transistor over a glass substrate, and the signal line driver circuit (or part thereof) is formed over a single crystal substrate. The IC chip may be connected to the glass substrate by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed board.

  Note that the content described in this embodiment mode can be freely combined with the content described in Embodiment Modes 1 to 6.

(Embodiment 8)
In this embodiment, a display panel used in the display device of the present invention will be described with reference to FIG. 67A is a top view showing the display panel, and FIG. 67B is a cross-sectional view taken along line AA ′ in FIG. 67A. A signal line driver circuit 6701, a pixel portion 6702, a first scan line driver circuit 6703, and a second scan line driver circuit 6706 indicated by dotted lines are included. Further, a sealing substrate 6704 and a sealing material 6705 are provided, and an inner side surrounded by the sealing material 6705 is a space 6707.

  Note that the wiring 6708 is a wiring for transmitting a signal input to the first scan line driver circuit 6703, the second scan line driver circuit 6706, and the signal line driver circuit 6701, and is supplied from the FPC 6709 serving as an external input terminal to the video. Receive signals, clock signals, start signals, etc. An IC chip 6719 and an IC chip 6720 (a semiconductor chip on which a memory circuit, a buffer circuit, and the like are formed) are mounted by COG (Chip On Glass) or the like on a joint portion between the FPC 6709 and the display panel. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC.

  Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 6702 and its peripheral driver circuits (a first scan line driver circuit 6703, a second scan line driver circuit 6706, and a signal line driver circuit 6701) are formed over a substrate 6710. Here, signal lines A driver circuit 6701 and a pixel portion 6702 are shown.

  Note that the signal line driver circuit 6701 includes a plurality of transistors such as a transistor 6721 and a transistor 6722. In this embodiment, a display panel in which peripheral drive circuits are integrally formed on a substrate is shown. However, this is not always necessary, and all or part of the peripheral drive circuits are formed on an IC chip or the like and mounted by COG or the like. May be.

  The pixel portion 6702 includes a plurality of circuits included in a pixel including a switching transistor 6711 and a driving transistor 6712. Note that the source electrode of the driving transistor 6712 is connected to the first electrode 6713. An insulator 6714 is formed so as to cover an end portion of the first electrode 6713. Here, a positive photosensitive acrylic resin film is used.

  In order to improve the coverage, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 6714. For example, in the case where positive photosensitive acrylic is used as a material for the insulator 6714, it is preferable that only the upper end portion of the insulator 6714 has a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 6714, either a negative type that becomes insoluble in an etchant by light or a positive type that becomes soluble in an etchant by light can be used.

  Over the first electrode 6713, a layer 6716 containing an organic compound and a second electrode 6717 are formed. Here, as a material used for the first electrode 6713 which functions as an anode, a material having a high work function is preferably used. For example, ITO (Indium Tin Oxide) film, Indium Zinc Oxide (IZO) film, Titanium nitride film, Chromium film, Tungsten film, Zn film, Pt film, etc., as well as titanium nitride and aluminum as main components And a three-layer structure of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained.

  The layer 6716 containing an organic compound is formed by an evaporation method using an evaporation mask or an inkjet method. For the layer 6716 containing an organic compound, a Group 4 metal complex of the periodic table of elements is used as a part thereof, and other materials that can be used in combination include high molecular weight materials even if they are low molecular weight materials. It may be. In addition, as a material used for a layer containing an organic compound, an organic compound is usually used in a single layer or a stacked layer, but in this embodiment, an inorganic compound is also used for a part of a film made of an organic compound. Include. Further, a known triplet material can be used.

Further, as a material used for the second electrode 6717 which is a cathode and is formed over the layer 6716 containing an organic compound, a material having a low work function (Al, Ag, Li, Ca, or alloys thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride) may be used. Note that in the case where light generated in the layer 6716 containing an organic compound passes through the second electrode 6717, the second electrode 6717 includes a thin metal film and a transparent conductive film (ITO (indium tin oxide oxide)). Or the like), a stack of indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used.

  Further, a sealing substrate 6704 is attached to a substrate 6710 with a sealant 6705, whereby a light-emitting element 6718 is provided in a space 6707 surrounded by the substrate 6710, the seal substrate 6704, and the sealant 6705. . Note that the space 6707 includes a structure filled with a sealing material 6705 in addition to a case where the space 6707 is filled with an inert gas (nitrogen, argon, or the like).

  Note that an epoxy-based resin is preferably used for the sealant 6705. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible. In addition to a glass substrate and a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, acrylic, or the like can be used as a material used for the sealing substrate 6704.

  As described above, a display panel having the pixel configuration of the present invention can be obtained.

  As shown in FIG. 67, the signal line driver circuit 6701, the pixel portion 6702, the first scan line driver circuit 6703, and the second scan line driver circuit 6706 are integrally formed, whereby the cost of the display device can be reduced. Note that since the transistors used for the signal line driver circuit 6701, the pixel portion 6702, the first scan line driver circuit 6703, and the second scan line driver circuit 6706 have a single polarity, the manufacturing process can be simplified, so that the manufacturing process can be further reduced. Cost can be reduced. Further, by using amorphous silicon for a semiconductor layer of a transistor used in the signal line driver circuit 6701, the pixel portion 6702, the first scan line driver circuit 6703, and the second scan line driver circuit 6706, cost can be further reduced. be able to.

  Note that as a structure of the display panel, as shown in FIG. 67A, a signal line driver circuit 6701, a pixel portion 6702, a first scan line driver circuit 6703, and a second scan line driver circuit 6706 are integrally formed. The configuration is not limited, and the signal line driver circuit 6701 may be formed over an IC chip and mounted on the display panel with COG or the like.

  That is, only a signal line driver circuit that requires high-speed operation is formed on an IC chip using a CMOS or the like to reduce power consumption. Further, by using a semiconductor chip such as a silicon wafer as the IC chip, higher speed operation and lower power consumption can be achieved.

  The cost can be reduced by forming the scanning line driving circuit integrally with the pixel portion. Note that the scan line driver circuit and the pixel portion are formed of unipolar transistors, thereby further reducing the cost. As the structure of the pixel included in the pixel portion, the structure described in Embodiment Mode 3 can be applied. In addition, by using amorphous silicon for the semiconductor layer of the transistor, the manufacturing process can be simplified and further cost reduction can be achieved.

  Thus, the cost of a high-definition display device can be reduced. Further, by mounting an IC chip on which a functional circuit (memory or buffer) is formed at a connection portion between the FPC 6709 and the substrate 6710, the substrate area can be effectively used.

  In addition, the signal line driver circuit 6701, the first scan line driver circuit 6703, and the second scan line driver circuit 6706 in FIG. 67A are formed over an IC chip and mounted on a display panel with COG or the like. Also good. In this case, a high-definition display device can have lower power consumption. Therefore, in order to obtain a display device with lower power consumption, it is preferable to use polysilicon for a semiconductor layer of a transistor used in the pixel portion.

  In addition, cost can be reduced by using amorphous silicon for the semiconductor layer of the transistor in the pixel portion 6702. Further, a large display panel can be manufactured.

  Note that the scan line driver circuit and the signal line driver circuit are not limited to being provided in the row direction and the column direction of the pixel.

  Next, an example of a light-emitting element applicable to the light-emitting element 6718 is illustrated in FIG.

  An anode 6802 on a substrate 6801, a hole injection layer 6803 made of a hole injection material, a hole transport layer 6804 made of a hole transport material, a light emitting layer 6805, an electron transport layer 6806 made of an electron transport material, and an electron It is an element structure in which an electron injection layer 6807 made of an injection material and a cathode 6808 are laminated. Here, the light emitting layer 6805 may be formed of only one kind of light emitting material, but may be formed of two or more kinds of materials. Further, the structure of the element of the present invention is not limited to this structure.

  In addition to the layered structure in which the functional layers shown in FIG. 68 are stacked, variations such as an element using a polymer compound and a high-efficiency element using a triplet light emitting material that emits light from a triplet excited state in the light emitting layer are available. Wide range. The present invention can also be applied to a white light emitting element obtained by controlling a carrier recombination region by a hole blocking layer and dividing a light emitting region into two regions.

  Next, the element manufacturing method of the present invention shown in FIG. 68 will be described. First, a hole injecting material, a hole transporting material, and a light emitting material are sequentially deposited on a substrate 6801 having an anode 6802 (ITO (indium tin oxide)). Next, an electron transport material and an electron injection material are vapor-deposited, and finally a cathode 6808 is formed by vapor deposition.

  Next, materials suitable for the hole injection material, the hole transport material, the electron transport material, the electron injection material, and the light emitting material are listed below.

As the hole injection material, porphyrin compounds, phthalocyanine (hereinafter referred to as “H ₂ Pc”), copper phthalocyanine (hereinafter referred to as “CuPc”), and the like are effective as long as they are organic compounds. In addition, any material that has a smaller ionization potential than the hole transport material used and has a hole transport function can also be used as the hole injection material. There is also a material obtained by chemically doping a conductive polymer compound, and examples thereof include polyethylenedioxythiophene (hereinafter referred to as “PEDOT”) doped with polystyrene sulfonic acid (hereinafter referred to as “PSS”), polyaniline, and the like. An insulating polymer compound is also effective in terms of planarization of the anode, and polyimide (hereinafter referred to as “PI”) is often used. In addition, inorganic compounds are also used. In addition to metal thin films such as gold and platinum, there are ultra thin films of aluminum oxide (hereinafter referred to as “alumina”).

  The most widely used hole transport material is an aromatic amine-based compound (that is, a compound having a benzene ring-nitrogen bond). As widely used materials, 4,4′-bis (diphenylamino) -biphenyl (hereinafter referred to as “TAD”) and its derivative 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “TPD”), 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “α-NPD”) ). 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (hereinafter referred to as “TDATA”), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) And starburst aromatic amine compounds such as -N-phenyl-amino] -triphenylamine (hereinafter referred to as "MTDATA").

As an electron transport material, a metal complex is often used, and tris (8-quinolinolato) aluminum (hereinafter referred to as “Alq ₃ ”), BAlq, tris (4-methyl-8-quinolinolato) aluminum (hereinafter referred to as “Almq”). And a metal complex having a quinoline skeleton or a benzoquinoline skeleton such as bis (10-hydroxybenzo [h] -quinolinato) beryllium (hereinafter referred to as “Bebq”). Further, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”) There is also a metal complex having an oxazole-based or thiazole-based ligand such as “Zn (BTZ) ₂ ”). In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (hereinafter referred to as “PBD”), OXD-7, and the like An oxadiazole derivative of TAZ, 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4-triazole (hereinafter referred to as “p-EtTAZ”) ) And other phenanthroline derivatives such as bathophenanthroline (hereinafter referred to as “BPhen”) and BCP have electron transport properties.

  The electron transport material described above can be used as the electron injection material. In addition, an ultra-thin film of an insulator such as a metal halide such as calcium fluoride, lithium fluoride, or cesium fluoride, or an alkali metal oxide such as lithium oxide is often used. In addition, alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as “Li (acac)”) and 8-quinolinolato-lithium (hereinafter referred to as “Liq”) are also effective.

As the luminescent material, various fluorescent dyes are effective in addition to the metal complexes such as Alq ₃ , Almq, BeBq, BAlq, Zn (BOX) ₂ , Zn (BTZ) _{2 described} above. As the fluorescent dye, blue 4,4′-bis (2,2-diphenyl-vinyl) -biphenyl and red-orange 4- (dicyanomethylene) -2-methyl-6- (p-dimethylaminostyryl)- 4H-pyran. A triplet light emitting material is also possible, and is mainly a complex having platinum or iridium as a central metal. As the triplet light emitting material, tris (2-phenylpyridine) iridium, bis (2- (4′-tolyl) pyridinato-N, C ^{2 ′} ) acetylacetonatoiridium (hereinafter referred to as “acacIr (tpy) ₂ ”), 2,3,7,8,12,13,17,18-octaethyl-21H, 23H porphyrin-platinum and the like are known.

  A highly reliable light-emitting element can be manufactured by combining the materials having the functions described above.

  Further, a light-emitting element in which layers are formed in the reverse order to that in FIG. 68 can also be used. That is, the cathode 6808 on the substrate 6801, the electron injection layer 6807 made of an electron injection material, the electron transport layer 6806 made of an electron transport material thereon, the light emitting layer 6805, the hole transport layer 6804 made of a hole transport material, This is an element structure in which a hole injection layer 6803 made of a hole injection material and an anode 6802 are laminated.

  Further, in order to extract light emission from the light emitting element, at least one of the anode and the cathode may be transparent. Then, a transistor and a light emitting element are formed over the substrate, and a top emission that extracts light from a surface opposite to the substrate, a bottom emission that extracts light from a surface on the substrate side, and a surface opposite to the substrate side and the substrate. The pixel structure of the present invention can be applied to a light emitting element having any emission structure.

  First, a light-emitting element having a top emission structure will be described with reference to FIG.

  A driving transistor 6901 is formed over a substrate 6900, a first electrode 6902 is formed in contact with a source electrode of the driving transistor 6901, and a layer 6903 containing an organic compound and a second electrode 6904 are formed thereover. Yes.

  The first electrode 6902 is an anode of the light emitting element. The second electrode 6904 is a cathode of the light emitting element. That is, a region where the layer 6903 containing an organic compound is sandwiched between the first electrode 6902 and the second electrode 6904 is a light-emitting element.

  Here, as a material used for the first electrode 6902 which functions as an anode, a material having a high work function is preferably used. For example, in addition to a single layer film such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a stack of titanium nitride and a film containing aluminum as a main component, a film containing a titanium nitride film and aluminum as a main component A three-layer structure of titanium nitride film and the like can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained. By using a metal film that reflects light, an anode that does not transmit light can be formed.

A material used for the second electrode 6904 that functions as a cathode is a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), or the like) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

  In this manner, light from the light emitting element can be extracted to the upper surface as shown by an arrow in FIG. That is, when applied to the display panel in FIG. 67, light is emitted to the sealing substrate 6704 side. Therefore, in the case where a light-emitting element having a top emission structure is used for a display device, the sealing substrate 6704 is a light-transmitting substrate.

  In the case where an optical film is provided, an optical film may be provided over the sealing substrate 6704.

  Note that the first electrode 6902 can also be formed using a metal film formed of a material with a low work function, such as MgAg, MgIn, or AlLi, which functions as a cathode. In this case, a transparent conductive film such as an ITO (indium tin oxide) film or indium zinc oxide (IZO) can be used for the second electrode 6904. Therefore, according to this configuration, it is possible to increase the transmittance of top emission.

  Next, a light-emitting element having a bottom emission structure will be described with reference to FIG. Since the light-emitting element has the same structure as that of FIG. 69A except for the emission structure, the description will be made using the same reference numerals.

  Here, as a material used for the first electrode 6902 which functions as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

A material used for the second electrode 6904 that functions as a cathode is a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A metal film can be used. Thus, by using a metal film that reflects light, a cathode that does not transmit light can be formed.

  In this manner, light from the light emitting element can be extracted to the lower surface as indicated by an arrow in FIG. That is, when applied to the display panel of FIG. 67, light is emitted to the substrate 6710 side. Therefore, in the case where a light-emitting element having a bottom emission structure is used for a display device, the substrate 6710 is a light-transmitting substrate.

  In the case of providing an optical film, the substrate 6710 may be provided with an optical film.

  Next, a light-emitting element having a dual emission structure will be described with reference to FIG. Since the light-emitting element has the same structure as that of FIG. 69A except for the emission structure, the description will be made using the same reference numerals.

  Here, as a material used for the first electrode 6902 which functions as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

A material used for the second electrode 6904 that functions as a cathode is a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

  In this manner, light from the light emitting element can be extracted on both sides as indicated by arrows in FIG. That is, when applied to the display panel in FIG. 67, light is emitted to the substrate 6710 side and the sealing substrate 6704 side. Therefore, in the case where a light-emitting element having a dual emission structure is used for a display device, both the substrate 6710 and the sealing substrate 6704 are light-transmitting substrates.

  In the case where an optical film is provided, the optical film may be provided on both the substrate 6710 and the sealing substrate 6704.

In addition, the present invention can be applied to a display device that realizes full color display using a white light emitting element and a color filter.

  As shown in FIG. 70, a base film 7002 is formed over a substrate 7000, a driving transistor 7001 is formed over the base film 7002, and a first electrode 7003 is formed in contact with the source electrode of the driving transistor 7001. A layer 7004 containing an organic compound and a second electrode 7005 are formed thereover.

  The first electrode 7003 is an anode of the light emitting element. The second electrode 7005 is a cathode of the light emitting element. That is, a region where the layer 7004 containing an organic compound is sandwiched between the first electrode 7003 and the second electrode 7005 is a light-emitting element. 70 emits white light. A red color filter 7006R, a green color filter 7006G, and a blue color filter 7006B are provided above the light-emitting element, so that full color display can be performed. In addition, a black matrix 7007 (also referred to as BM) for separating these color filters is provided.

  The above structures of the light-emitting elements can be used in combination and can be used as appropriate for the display device of the present invention. Further, the structure of the display panel and the light-emitting element described above are examples, and the present invention can be applied to a display device having another structure different from the structure described above.

  Next, a partial cross-sectional view of a pixel portion of the display panel is shown.

First, the case where a polysilicon (p-Si: H) film is used for a semiconductor layer of a transistor will be described with reference to FIGS. 71, 72, and 73. FIG.

  Here, as the semiconductor layer, for example, an amorphous silicon (a-Si) film is formed on a substrate by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film) may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used.

  Then, the amorphous silicon film is crystallized by a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization. Of course, these may be combined.

  By the above crystallization, a partially crystallized region is formed in the amorphous semiconductor film.

  Further, a pattern is formed in a desired shape from the crystalline semiconductor film partially improved in crystallinity, and an island-shaped semiconductor film is formed from the crystallized region. This semiconductor film is used for a semiconductor layer of a transistor.

  As shown in FIG. 71A, a base film 7102 is formed on a substrate 7101, and a semiconductor layer is formed thereon. The semiconductor layer includes a channel formation region 7103, an LDD region 7104, and an impurity region 7105 that serves as a source region or a drain region of the driving transistor 7118, and a channel formation region 7106, an LDD region 7107, and an impurity region 7108 that serve as a lower electrode of the capacitor 7119. Have Note that channel doping may be performed on the channel formation region 7103 and the channel formation region 7106.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 7102, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

  Over the semiconductor layer, a gate electrode 7110 and an upper electrode 7111 of the capacitor 7119 are formed with a gate insulating film 7109 interposed therebetween.

  An interlayer insulating film 7112 is formed to cover the capacitor 7119 and the driving transistor 7118, and a wiring 7113 is in contact with the impurity region 7105 over the interlayer insulating film 7112 through a contact hole. A pixel electrode 7114 is formed in contact with the wiring 7113, and an insulator 7115 is formed to cover the end portion of the pixel electrode 7114 and the wiring 7113. Here, a positive photosensitive acrylic resin film is used. A layer 7116 containing an organic compound and a counter electrode 7117 are formed over the pixel electrode 7114, and a light-emitting element 7120 is formed in a region where the layer 7116 containing an organic compound is sandwiched between the pixel electrode 7114 and the counter electrode 7117. Yes.

  In addition, as illustrated in FIG. 71B, a region 7121 in which an LDD region that forms part of the lower electrode of the capacitor 7119 overlaps with the upper electrode 7111 of the capacitor 7119 may be provided. In addition, the same code | symbol is used for the location which is common in Fig.71 (a), and description is abbreviate | omitted.

  72A, the capacitor 7123 may include a second upper electrode 7122 formed in the same layer as the wiring 7113 in contact with the impurity region 7105 of the driving transistor 7118. Since the second upper electrode 7122 is in contact with the impurity region 7108, the first capacitor element including the upper electrode 7111 and the channel formation region 7106 sandwiching the gate insulating film 7109, the upper electrode 7111, And the second capacitor element sandwiching the interlayer insulating film 7112 between the upper electrode 7122 and the capacitor element 7123 including the first capacitor element and the second capacitor element. . Since the capacitance of the capacitor 7123 is a combined capacitance obtained by adding the capacitances of the first capacitor and the second capacitor, a capacitor having a large capacity can be formed with a small area. That is, the aperture ratio can be further improved when used as a capacitor having a pixel structure of the present invention.

  Alternatively, a structure of a capacitor as shown in FIG. A base film 7202 is formed over a substrate 7201, and a semiconductor layer is formed thereover. The semiconductor layer includes a channel formation region 7203, an LDD region 7204, and an impurity region 7205 serving as a source region or a drain region of the driving transistor 7218. Note that the channel formation region 7203 may be channel-doped.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 7202, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

  Over the semiconductor layer, a gate electrode 7207 and a first electrode 7208 are formed with a gate insulating film 7206 interposed therebetween.

  A first interlayer insulating film 7209 is formed to cover the driving transistor 7218 and the first electrode 7208, and a wiring 7210 is in contact with the impurity region 7205 over the first interlayer insulating film 7209 through a contact hole. In addition, a second electrode 7211 made of the same material as the wiring 7210 is formed in the same layer as the wiring 7210.

  Further, a second interlayer insulating film 7212 is formed so as to cover the wiring 7210 and the second electrode 7211, and a pixel electrode 7213 is formed on the second interlayer insulating film 7212 in contact with the wiring 7210 through a contact hole. Has been. A third electrode 7214 made of the same material as the pixel electrode 7213 is formed in the same layer as the pixel electrode 7213. Here, a capacitor element 7219 including the first electrode 7208, the second electrode 7211, and the third electrode 7214 is formed.

  A layer 7216 containing an organic compound and a counter electrode 7217 are formed over the pixel electrode 7213, and a light-emitting element 7220 is formed in a region where the layer 7216 containing an organic compound is sandwiched between the pixel electrode 7213 and the counter electrode 7217.

  As described above, the structure of the transistor in which the crystalline semiconductor film is used for the semiconductor layer includes the structures illustrated in FIGS. Note that the structure of the transistor illustrated in FIGS. 71 and 72 is an example of a top-gate transistor. That is, the LDD region may overlap with the gate electrode, may not overlap with the gate electrode, or a part of the LDD region may overlap. Further, the gate electrode may have a tapered shape, and an LDD region may be provided in a self-aligned manner below the tapered portion of the gate electrode. Further, the number of gate electrodes is not limited to two, but may be three or more multi-gate structures or one gate electrode.

  By using a crystalline semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in a pixel of the present invention, a scan line driver circuit and a signal line driver circuit are formed integrally with a pixel portion. Becomes easier. Alternatively, part of the signal line driver circuit may be formed integrally with the pixel portion, and part of the signal line driver circuit may be formed over an IC chip and mounted by COG or the like as shown in the display panel in FIG. With such a configuration, the manufacturing cost can be reduced.

  In addition, as a transistor structure using polysilicon (p-Si: H) as a semiconductor layer, a structure in which a gate electrode is sandwiched between a substrate and a semiconductor layer, that is, a bottom where the gate electrode is located under the semiconductor layer. A transistor having a gate structure may be used. Here, FIG. 73 is a partial cross-sectional view of a pixel portion of a display panel to which a bottom-gate transistor is applied.

  As shown in FIG. 73A, a base film 7302 is formed on a substrate 7301. Further, a gate electrode 7303 is formed over the base film 7302. A first electrode 7304 made of the same material as the gate electrode 7303 is formed in the same layer as the gate electrode 7303. As a material for the gate electrode 7303, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

  A gate insulating film 7305 is formed so as to cover the gate electrode 7303 and the first electrode 7304. As the gate insulating film 7305, a silicon oxide film, a silicon nitride film, or the like is used.

  A semiconductor layer is formed over the gate insulating film 7305. The semiconductor layer includes a channel formation region 7306, an LDD region 7307, and an impurity region 7308 serving as a source region or a drain region of the driving transistor 7322, and a channel formation region 7309, an LDD region 7310, and an impurity region serving as a second electrode of the capacitor 7323. 7311. Note that channel doping may be performed on the channel formation region 7306 and the channel formation region 7309.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 7302, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ), or a stacked layer thereof can be used.

  A first interlayer insulating film 7312 is formed so as to cover the semiconductor layer. A wiring 7313 is in contact with the impurity region 7308 over the first interlayer insulating film 7312 through a contact hole. A third electrode 7314 is formed using the same material as the wiring 7313 in the same layer as the wiring 7313. A capacitor 7323 is formed by the first electrode 7304, the second electrode, and the third electrode 7314.

  An opening 7315 is formed in the first interlayer insulating film 7312. A second interlayer insulating film 7316 is formed so as to cover the driving transistor 7322, the capacitor 7323, and the opening 7315, and a pixel electrode 7317 is formed over the second interlayer insulating film 7316 through a contact hole. . An insulator 7318 is formed so as to cover an end portion of the pixel electrode 7317. For example, a positive photosensitive acrylic resin film can be used. A layer 7319 containing an organic compound and a counter electrode 7320 are formed over the pixel electrode 7317, and a light-emitting element 7321 is formed in a region where the layer 7319 containing an organic compound is sandwiched between the pixel electrode 7317 and the counter electrode 7320. Yes. An opening 7315 is positioned below the light emitting element 7321. That is, when light emitted from the light-emitting element 7321 is extracted from the substrate side, the opening 7315 is provided, so that the transmittance can be increased.

  In FIG. 73A, the fourth electrode 7324 may be formed using the same material in the same layer as the pixel electrode 7317 so that the structure shown in FIG. Then, a capacitor 7325 including the first electrode 7304, the second electrode, the third electrode 7314, and the fourth electrode 7324 can be formed.

  Next, the case where an amorphous silicon (a-Si: H) film is used for the semiconductor layer of the transistor will be described with reference to FIGS.

  FIG. 43A shows a cross section of a top-gate transistor in which amorphous silicon is used for a semiconductor layer. As shown, a base film 4302 is formed on the substrate 4301. Further, a pixel electrode 4303 is formed on the base film 4302. A first electrode 4304 made of the same material is formed in the same layer as the pixel electrode 4303.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 4302, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

  Further, a wiring 4305 and a wiring 4306 are formed over the base film 4302, and an end portion of the pixel electrode 4303 is covered with the wiring 4305. An N-type semiconductor layer 4307 and an N-type semiconductor layer 4308 each having an N-type conductivity are formed over the wirings 4305 and 4306. A semiconductor layer 4309 is formed between the wiring 4305 and the wiring 4306 and over the base film 4302. A part of the semiconductor layer 4309 is extended over the N-type semiconductor layer 4307 and the N-type semiconductor layer 4308. Note that this semiconductor layer is formed of an amorphous semiconductor film such as amorphous silicon (a-Si: H) or microcrystalline semiconductor (μ-Si: H). A gate insulating film 4310 is formed over the semiconductor layer 4309. An insulating film 4311 made of the same material and in the same layer as the gate insulating film 4310 is also formed over the first electrode 4304. Note that a silicon oxide film, a silicon nitride film, or the like is used as the gate insulating film 4310.

  A gate electrode 4312 is formed over the gate insulating film 4310. A second electrode 4313 made of the same material and in the same layer as the gate electrode is formed over the first electrode 4304 with an insulating film 4311 interposed therebetween. A capacitor element 4319 in which an insulating film 4311 is sandwiched between the first electrode 4304 and the second electrode 4313 is formed. Further, an interlayer insulating film 4314 is formed so as to cover an end portion of the pixel electrode 4303, the driving transistor 4318, and the capacitor 4319.

  A region 4315 containing an organic compound and a counter electrode 4316 are formed over the interlayer insulating film 4314 and the pixel electrode 4303 located in the opening, and the pixel electrode 4303 and the counter electrode 4316 sandwich the layer 4315 containing an organic compound. Then, a light emitting element 4317 is formed.

  Alternatively, the first electrode 4304 illustrated in FIG. 43A may be formed using the first electrode 4320 as illustrated in FIG. The first electrode 4320 is formed using the same material in the same layer as the wirings 4305 and 4306.

  FIG. 44 shows a partial cross section of a panel of a display device using a bottom-gate transistor using amorphous silicon as a semiconductor layer.

  A gate electrode 4403 is formed over the substrate 4401. In addition, a first electrode 4404 made of the same material is formed in the same layer as the gate electrode 4403. As a material for the gate electrode 4403, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used. As the substrate 4401, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used.

  A gate insulating film 4405 is formed so as to cover the gate electrode 4403 and the first electrode 4404. As the gate insulating film 4405, a silicon oxide film, a silicon nitride film, or the like is used.

  In addition, a semiconductor layer 4406 is formed over the gate insulating film 4405. In addition, a semiconductor layer 4407 made of the same material is formed in the same layer as the semiconductor layer 4406.

  N-type semiconductor layers 4408 and 4409 having N-type conductivity are formed over the semiconductor layer 4406, and an N-type semiconductor layer 4410 is formed over the semiconductor layer 4407.

  Wirings 4411 and 4412 are formed over the N-type semiconductor layers 4408 and 4409, respectively, and a conductive layer 4413 made of the same material as the wirings 4411 and 4412 is formed over the N-type semiconductor layer 4410.

  A second electrode including the semiconductor layer 4407, the N-type semiconductor layer 4410, and the conductive layer 4413 is formed. Note that a capacitor 4420 having a structure in which the gate insulating film 4405 is sandwiched between the second electrode and the first electrode 4404 is formed.

  One end portion of the wiring 4411 extends, and a pixel electrode 4414 is formed in contact with the upper portion of the extended wiring 4411.

  In addition, an insulator 4415 is formed so as to cover an end portion of the pixel electrode 4414, the driving transistor 4419, and the capacitor 4420.

  A layer 4416 containing an organic compound and a counter electrode 4417 are formed over the pixel electrode 4414 and the insulator 4415, and a light-emitting element 4418 is formed in a region where the layer 4416 containing an organic compound is sandwiched between the pixel electrode 4414 and the counter electrode 4417. Has been.

  The semiconductor layer 4407 and the N-type semiconductor layer 4410 which are part of the second electrode of the capacitor may not be provided. That is, the capacitor may have a structure in which the second electrode is the conductive layer 4413 and the gate insulating film is sandwiched between the first electrode 4404 and the conductive layer 4413.

  Note that in FIG. 44A, the pixel electrode 4414 is formed before the wiring 4411 is formed, whereby the second electrode 4421 including the pixel electrode 4414 and the first electrode as illustrated in FIG. A capacitor 4422 having a structure in which the gate insulating film 4405 is sandwiched between 4404 can be formed.

  Note that although an inverted staggered channel-etched transistor is shown in FIG. 44, a channel-protective transistor may of course be used. The case of a transistor with a channel protective structure will be described with reference to FIGS.

  A transistor with a channel protective structure shown in FIG. 45A is an insulator 4501 serving as an etching mask over a region where a channel of the semiconductor layer 4406 of the driving transistor 4419 with a channel etch structure shown in FIG. 44A is formed. Are different from each other, and other common parts use common reference numerals.

  Similarly, in the channel protective type transistor illustrated in FIG. 45B, an etching mask is formed over a region where the channel of the semiconductor layer 4406 of the channel-etched driving transistor 4419 illustrated in FIG. 44B is formed. The difference is that an insulator 4501 is provided, and other common parts are denoted by common reference numerals.

  By using an amorphous semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in the pixel of the present invention, manufacturing cost can be reduced.

  Note that the structure of the transistor and the structure of the capacitor that can be applied to the pixel structure of the present invention are not limited to the above structures, and transistors having various structures and structures of the capacitor can be used. .

  Note that the contents described in this embodiment mode can be implemented by being freely combined with the contents described in Embodiment Modes 1 to 7. That is, in the display device according to this embodiment, since the current flowing through the light-emitting element is determined in a manner that does not depend on the threshold voltage of the transistor, variations in the threshold voltage of the transistor can be compensated. Accordingly, variation in luminance of the light emitting element can be reduced, and image quality can be improved.

(Embodiment 9)
In this embodiment mode, a method for manufacturing a display device using plasma treatment will be described as a method for manufacturing a display device including a transistor.

  FIG. 46 is a diagram illustrating a structure example of a display device including a transistor. 46B, FIG. 46B corresponds to a cross-sectional view taken along line ab in FIG. 46A, and FIG. 46C corresponds to a cross-sectional view taken along line cd in FIG. 46A. To do.

  A display device illustrated in FIG. 46 includes semiconductor films 4603a and 4603b provided over a substrate 4601 through an insulating film 4602, and a gate electrode 4605 provided over the semiconductor films 4603a and 4603b through a gate insulating film 4604. And insulating films 4606 and 4607 provided so as to cover the gate electrode, and a conductive film 4608 provided on the insulating film 4607 and electrically connected to the source region or the drain region of the semiconductor films 4603a and 4603b. Yes. Note that FIG. 46 shows the case where an N-channel transistor 4610a using part of the semiconductor film 4603a as a channel region and a P-channel transistor 4610b using part of the semiconductor film 4603b as a channel region are shown. However, it is not limited to this configuration. For example, in FIG. 46, an LDD (lightly doped drain) region is provided in the N-channel transistor 4610a and an LDD region is not provided in the P-channel transistor 4610b. However, the structure may be provided in both, or not provided in both. A configuration is also possible.

  Note that in this embodiment, at least one of the substrate 4601, the insulating film 4602, the semiconductor films 4603a and 4603b, the gate insulating film 4604, the insulating film 4606, and the insulating film 4607 is oxidized or nitrided using plasma treatment. By performing oxidation or nitrogenation on the semiconductor film or the insulating film, the display device shown in FIG. 46 is manufactured. In this manner, the surface of the semiconductor film or the insulating film is modified by oxidizing or nitriding the semiconductor film or the insulating film using plasma treatment, and compared with an insulating film formed by a CVD method or a sputtering method. Since a dense insulating film can be formed, defects such as pinholes can be suppressed and characteristics of the display device can be improved.

  Note that in this embodiment, the semiconductor films 4603a and 4603b or the gate insulating film 4604 in FIG. 46 are subjected to plasma treatment, and the semiconductor films 4603a and 4603b or the gate insulating film 4604 are oxidized or nitrided to manufacture a display device. The method will be described with reference to the drawings.

  First, the case where an island-shaped semiconductor film provided over a substrate is provided with an end portion of the island-shaped semiconductor film having a shape close to a right angle is described.

First, island-shaped semiconductor films 4603a and 4603b are formed over the substrate 4601 (FIGS. 47A-1 and A-2). The island-shaped semiconductor films 4603a and 4603b are mainly composed of silicon (Si) by using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) over an insulating film 4602 formed in advance on a substrate 4601. An amorphous semiconductor film can be formed using a material (eg, Si _x Ge _1-x or the like), the amorphous semiconductor film can be crystallized, and the semiconductor film can be selectively etched. Note that the crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. It can carry out by the well-known crystallization method. Note that in FIGS. 47A-1 and A-2, the end portions of the island-shaped semiconductor films 4603a and 4603b are provided in a shape close to a right angle (θ = 85 to 100 °).

Next, by performing plasma treatment to oxidize or nitride the semiconductor films 4603a and 4603b, insulating films 4621a and 4621b (oxide films or nitride films) are formed on the surfaces of the semiconductor films 4603a and 4603b, respectively (FIG. 47 (( B-1, B-2))). For example, when Si is used for the semiconductor films 4603a and 4603b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the insulating films 4621a and 4621b. Alternatively, the semiconductor films 4603a and 4603b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 4603a and 4603b, and silicon nitride oxide (SiNxOy) (x> y) is formed on the surface of the silicon oxide. Note that in the case where the semiconductor film is oxidized by plasma treatment, an oxygen atmosphere (eg, oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or oxygen is used. Plasma treatment is performed under an atmosphere of hydrogen (H ₂ ) and a rare gas or dinitrogen monoxide and a rare gas. On the other hand, in the case of nitriding a semiconductor film by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or nitrogen Plasma treatment is performed under a hydrogen and rare gas atmosphere or a NH ₃ and rare gas atmosphere. As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the insulating films 4621a and 4621b include a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. When Ar is used, the insulating films 4621a and 4621b are used. Contains Ar.

In addition, the plasma treatment is performed in the above gas atmosphere at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less and an electron temperature of plasma of 0.5 eV or more and 1.5 eV or less. . Since the electron density of plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor films 4603a and 4603b) formed over the substrate 4601 is low, damage to the object to be processed is prevented. Can do. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point temperature of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Note that the plasma treatment is performed using the above conditions unless otherwise specified.

  Next, a gate insulating film 4604 is formed so as to cover the insulating films 4621a and 4621b (FIGS. 47C-1 and C-2). The gate insulating film 4604 is formed using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), nitride using a known means (sputtering method, LPCVD method, plasma CVD method, or the like). A single-layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide (SiNxOy) (x> y) or a stacked structure thereof can be used. For example, in the case where silicon is used as the semiconductor films 4603a and 4603b and silicon oxide is formed as the insulating films 4621a and 4621b on the surfaces of the semiconductor films 4603a and 4603b by oxidizing the Si by plasma treatment, over the insulating films 4621a and 4621b Then, silicon oxide (SiOx) is formed as a gate insulating film. In FIGS. 47B-1 and B-2, when the insulating films 4621a and 4621b formed by oxidizing or nitriding the semiconductor films 4603a and 4603b by plasma treatment are sufficient, The insulating films 4621a and 4621b can also be used as gate insulating films.

Next, by forming a gate electrode 4605 and the like over the gate insulating film 4604, a display device including an N-channel transistor 4610a and a P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 47 (D-1, D-2)).

  As described above, before the gate insulating film 4604 is provided over the semiconductor films 4603a and 4603b, the surface of the semiconductor films 4603a and 4603b is oxidized or nitrided by plasma treatment, so that the gate insulation in the end portions 4651a and 4651b of the channel region is obtained. A short-circuit between the gate electrode and the semiconductor film due to the coating failure of the film 4604 can be prevented. That is, when the end portion of the island-shaped semiconductor film has a shape close to a right angle (θ = 85 to 100 °), the gate insulating film is formed so as to cover the semiconductor film by a CVD method, a sputtering method, or the like. However, there is a possibility that the problem of poor coating due to step breakage of the gate insulating film may occur at the end of the semiconductor film. However, by oxidizing or nitriding the surface of the semiconductor film in advance using plasma treatment, the end of the semiconductor film It is possible to prevent a defective coating of the gate insulating film at the portion.

  In FIGS. 47C-1 and C-2, the gate insulating film 4604 may be oxidized or nitrided by performing plasma treatment after the gate insulating film 4604 is formed. In this case, plasma treatment is performed on the gate insulating film 4604 (FIGS. 48A-1 and 48A-2) formed so as to cover the semiconductor films 4603a and 4603b, and the gate insulating film 4604 is oxidized or nitrided. An insulating film 4623 (an oxide film or a nitride film) is formed on the surface of the gate insulating film 4604 (FIGS. 48B-1 and B-2). The conditions for the plasma treatment can be the same as those in FIGS. 47B-1 and B-2. The insulating film 4723 contains a rare gas used for plasma treatment. For example, when Ar is used, the insulating film 4723 contains Ar.

  In FIG. 48B, the gate insulating film 4604 may be oxidized by once performing plasma treatment in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. In this case, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is formed in the semiconductor films 4603a and 4603b, and silicon nitride oxide (SiNxOy) (x> y) is formed in contact with the gate electrode 4605. Is done. After that, by forming the gate electrode 4605 and the like over the insulating film 4623, a display device including the N-channel transistor 4610a and the P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 48 (C-1, C-2)). In this manner, by performing plasma treatment on the gate insulating film, the surface of the gate insulating film is oxidized or nitrided, whereby the surface of the gate insulating film can be modified and a dense film can be formed. An insulating film obtained by plasma treatment is denser and has fewer defects such as pinholes than an insulating film formed by a CVD method or a sputtering method, so that the characteristics of the transistor can be improved.

  Note that FIG. 48 illustrates the case where the surfaces of the semiconductor films 4603a and 4603b are oxidized or nitrided by performing plasma treatment on the semiconductor films 4603a and 4603b in advance, but the semiconductor films 4603a and 4603b are subjected to plasma treatment. Alternatively, a method in which plasma treatment is performed after the gate insulating film 4604 is formed may be used. As described above, by performing the plasma treatment before forming the gate electrode, even if a coating failure occurs due to a step breakage of the gate insulating film at the end of the semiconductor film, the semiconductor film exposed due to the coating failure Therefore, short-circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end of the semiconductor film can be prevented.

  In this manner, even when the end portion of the island-shaped semiconductor film is provided in a shape that is nearly perpendicular, plasma treatment is performed on the semiconductor film or the gate insulating film to oxidize or nitride the semiconductor film or the gate insulating film. As a result, a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end of the semiconductor film can be prevented.

  Next, in the island-shaped semiconductor film provided over the substrate, the case where the end portion of the island-shaped semiconductor film is provided in a tapered shape (θ = 30 to 85 °) is described.

First, island-shaped semiconductor films 4603a and 4603b are formed over the substrate 4601 (FIGS. 49A-1 and A-2). The island-shaped semiconductor films 4603a and 4603b are mainly composed of silicon (Si) by using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) over an insulating film 4602 formed in advance on a substrate 4601. An amorphous semiconductor film is formed using a material (for example, Si _x Ge _1-x ) and the like, and the amorphous semiconductor film is subjected to laser crystallization, thermal crystallization using RTA or a furnace annealing furnace, crystallization The semiconductor film can be provided by being crystallized by a known crystallization method such as a thermal crystallization method using a metal element that promotes and selectively removing the semiconductor film by etching. Note that in FIGS. 49A-1 and A-2, the end portion of the island-shaped semiconductor film is provided in a tapered shape (θ = 30 to 85 °).

  Next, a gate insulating film 4604 is formed so as to cover the semiconductor films 4603a and 4603b (FIGS. 49B-1 and B-2). The gate insulating film 4604 is formed using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), nitride using a known means (sputtering method, LPCVD method, plasma CVD method, or the like). A single-layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide (SiNxOy) (x> y) or a stacked structure thereof can be used.

  Next, plasma treatment is performed to oxidize or nitride the gate insulating film 4604, thereby forming insulating films 4624 (oxide film or nitride film) on the surface of the gate insulating film 4604 (FIGS. 49C-1 and C-3). -2)). The plasma treatment conditions can be the same as described above. For example, in the case where silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is used as the gate insulating film 4604, plasma treatment is performed in an oxygen atmosphere to oxidize the gate insulating film 4604, whereby the gate insulating film A dense film with few defects such as pinholes can be formed on the surface of this film as compared with a gate insulating film formed by CVD or sputtering. On the other hand, by performing plasma treatment in a nitrogen atmosphere to nitride the gate insulating film 4604, silicon nitride oxide (SiNxOy) (x> y) can be provided as the insulating film 4624 on the surface of the gate insulating film 4604. Alternatively, the gate insulating film 4604 may be oxidized by performing plasma treatment once in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. The insulating film 4624 contains a rare gas used for plasma treatment. For example, when Ar is used, the insulating film 4624 contains Ar.

  Next, by forming a gate electrode 4605 and the like over the gate insulating film 4604, a display device including an N-channel transistor 4610a and a P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 49 (D-1, D-2)).

  In this manner, by performing plasma treatment on the gate insulating film, an insulating film made of an oxide film or a nitride film can be provided on the surface of the gate insulating film, and the surface of the gate insulating film can be modified. An insulating film oxidized or nitrided by plasma treatment is denser and has fewer defects such as pinholes than a gate insulating film formed by a CVD method or a sputtering method, so that transistor characteristics can be improved. it can. In addition, by forming the end portion of the semiconductor film in a tapered shape, a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end portion of the semiconductor film can be suppressed. By performing plasma treatment after the formation, a short circuit between the gate electrode and the semiconductor film can be further prevented.

  Next, a method for manufacturing a display device which is different from that in FIG. 49 is described with reference to drawings. Specifically, a case where plasma treatment is selectively performed on an end portion of a semiconductor film having a tapered shape is described.

First, island-shaped semiconductor films 4603a and 4603b are formed over the substrate 4601 (FIGS. 50A-1 and A-2). The island-shaped semiconductor films 4603a and 4603b are mainly composed of silicon (Si) by using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) over an insulating film 4602 formed in advance on a substrate 4601. An amorphous semiconductor film is formed using a material (eg, Si _x Ge _1-x or the like), the amorphous semiconductor film is crystallized, and the semiconductor film is selectively etched using the resists 4625a and 4625b as masks. Can be provided. Note that the crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. It can carry out by the well-known crystallization method.

  Next, before removing the resists 4625a and 4625b used for etching the semiconductor film, plasma treatment is performed to selectively oxidize or nitride the end portions of the island-shaped semiconductor films 4603a and 4603b. An insulating film 4626 (an oxide film or a nitride film) is formed on end portions of the films 4603a and 4603b, respectively (FIGS. 50B-1 and B-2). The plasma treatment is performed under the conditions described above. The insulating film 4626 contains a rare gas used for plasma treatment.

  Next, a gate insulating film 4604 is formed so as to cover the semiconductor films 4603a and 4603b (FIGS. 50C-1 and C-2). The gate insulating film 4604 can be provided in a manner similar to the above.

  Next, by forming a gate electrode 4605 and the like over the gate insulating film 4604, a display device including an N-channel transistor 4610a and a P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 50 (D-1, D2)).

  In the case where the end portions of the semiconductor films 4603a and 4603b are provided in a tapered shape, the end portions 4652a and 4602b of the channel region formed in part of the semiconductor films 4603a and 4603b are also tapered and the thickness of the semiconductor film or the gate insulating film Since the film thickness changes as compared with the central portion, the characteristics of the transistor may be affected. Therefore, here, by selectively oxidizing or nitriding an end portion of the channel region by plasma treatment and forming an insulating film in the semiconductor film which is the end portion of the channel region, a transistor caused by the end portion of the channel region The influence on can be reduced.

  Note that FIG. 50 shows an example in which oxidation or nitridation is performed by plasma treatment only on the end portions of the semiconductor films 4603a and 4603b. However, as shown in FIG. 49 (C-1 and C-2), of course. The gate insulating film 4604 can also be oxidized or nitrided by plasma treatment (FIGS. 52A-1 and A-2).

  Next, a method for manufacturing a display device different from the above is described with reference to drawings. Specifically, a case where plasma treatment is performed on a semiconductor film having a tapered shape is described.

  First, island-shaped semiconductor films 4603a and 4603b are formed over the substrate 4601 in the same manner as described above (FIGS. 51A-1 and A-2).

  Next, plasma treatment is performed to oxidize or nitride the semiconductor films 4603a and 4603b, whereby insulating films 4627a and 4627b (oxide films or nitride films) are formed on the surfaces of the semiconductor films 4603a and 4603b, respectively (FIG. 51B). ―1, B-2)). The plasma treatment can be similarly performed under the above-described conditions. For example, when Si is used for the semiconductor films 4603a and 4603b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the insulating films 4627a and 4627b. Alternatively, the semiconductor films 4603a and 4603b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is formed in contact with the semiconductor films 4603a and 4603b, and silicon nitride oxide (SiNxOy) (x> y) is formed on the surface of the silicon oxide. It is formed. Therefore, the insulating films 4627a and 4627b contain a rare gas used for plasma treatment. Note that the end portions of the semiconductor films 4603a and 4603b are simultaneously oxidized or nitrided by performing the plasma treatment.

  Next, a gate insulating film 4604 is formed so as to cover the insulating films 4627a and 4627b (FIGS. 51C-1 and C-2). The gate insulating film 4604 is formed using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), nitride using a known means (sputtering method, LPCVD method, plasma CVD method, or the like). A single-layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide (SiNxOy) (x> y) or a stacked structure thereof can be used. For example, when silicon oxide is formed as the insulating films 4627a and 4627b on the surfaces of the semiconductor films 4603a and 4603b by oxidizing the semiconductor films 4603a and 4603b by plasma treatment using Si, a gate is formed over the insulating films 4627a and 4627b. Silicon oxide (SiOx) is formed as an insulating film.

  Next, by forming a gate electrode 4605 and the like over the gate insulating film 4604, a display device including an N-channel transistor 4610a and a P-channel transistor 4610b using the island-shaped semiconductor films 4603a and 4603b as channel regions is manufactured. (FIG. 51 (D-1, D-2)).

  When the end portion of the semiconductor film is provided in a tapered shape, the end portions 4653a and 4653b of the channel region formed in part of the semiconductor film are also tapered, which may affect the characteristics of the semiconductor element. Therefore, by oxidizing or nitriding the semiconductor film by plasma treatment, as a result, the end portion of the channel region is also oxidized or nitrided, so that the influence on the semiconductor element can be reduced.

  Note that FIG. 51 shows an example in which oxidation or nitridation is performed by plasma treatment only on the semiconductor films 4603a and 4603b. However, as shown in FIG. 49, the gate insulating film 4604 is oxidized or oxidized by plasma treatment. Nitridation is also possible (FIG. 52B). In this case, the gate insulating film 4604 may be oxidized by performing plasma treatment once in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. In this case, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is formed in the semiconductor films 4603a and 4603b, and silicon nitride oxide (SiNxOy) (x> y) is formed in contact with the gate electrode 4605. Is done.

  In this manner, by performing plasma treatment to oxidize or nitride the semiconductor film or the gate insulating film to modify the surface, a dense insulating film with good film quality can be formed. As a result, even when the insulating film is formed thin, defects such as pinholes can be prevented, and miniaturization and high performance of semiconductor elements such as transistors can be achieved.

  Note that in this embodiment, the semiconductor films 4603a and 4603b or the gate insulating film 4604 in FIG. 46 are subjected to plasma treatment, and the semiconductor films 4603a and 4603b or the gate insulating film 4604 are oxidized or nitrided. The layer used for oxidation or nitridation is not limited to this. For example, plasma treatment may be performed on the substrate 4601 or the insulating film 4602, or plasma treatment may be performed on the insulating film 4606 or the insulating film 4607.

  Note that the content described in this embodiment mode can be freely combined with the content described in Embodiment Modes 1 to 8. In other words, the display device manufactured by the process according to this embodiment can drive a transistor at a low voltage and reduce variation in threshold voltage, so that a current flowing through the light-emitting element does not depend on the threshold voltage of the transistor. In combination with this effect, variation in luminance of the light-emitting element can be reduced, and image quality can be improved.

(Embodiment 10)
In this embodiment, a halftone method will be described as a method for manufacturing a display device including a transistor.

  FIG. 53 illustrates a cross-sectional structure of a display device including a transistor, a capacitor, and a resistor. FIG. 53 shows an N-channel transistor 5301, an N-channel transistor 5302, a capacitor 5304, a resistor 5305, and a P-channel transistor 5303. Each transistor includes a semiconductor layer 5405, an insulating layer 5408, and a gate electrode 5409. The gate electrode 5409 is formed with a stacked structure of a first conductive layer 5403 and a second conductive layer 5402. 54A to 54E are top views corresponding to the transistor, the capacitor, and the resistor shown in FIG. 53, and can be referred to together.

  In FIG. 53, an N-channel transistor 5301 is also referred to as a low concentration drain (LDD) on both sides of the channel region, and is lower than the impurity concentration in the impurity region 5406 that forms a source region and a drain region that are in contact with the wiring 5404. A heavily doped impurity region 5407 is formed in the semiconductor layer 5405. In the case where the N-channel transistor 5301 is formed, phosphorus or the like is added to the impurity region 5406 and the impurity region 5407 as an impurity imparting N-type conductivity. LDD is formed as a means for suppressing hot electron degradation and short channel effect.

  As shown in FIG. 54A, in the gate electrode 5409 of the N-channel transistor 5301, the first conductive layer 5403 is formed so as to spread on both sides of the second conductive layer 5402. In this case, the first conductive layer 5403 is formed thinner than the second conductive layer. The first conductive layer 5403 is formed to have a thickness that allows the ion species accelerated by an electric field of 10 to 100 kV to pass therethrough. The impurity region 5407 is formed so as to overlap with the first conductive layer 5403 of the gate electrode 5409. That is, an LDD region overlapping with the gate electrode 5409 is formed. In this structure, an impurity region 5407 is formed in a self-aligned manner in the gate electrode 5409 by adding one conductivity type impurity through the first conductive layer 5403 using the second conductive layer 5402 as a mask. That is, the LDD overlapping with the gate electrode is formed in a self-aligning manner.

  In FIG. 53, an N-channel transistor 5302 has an impurity region 5407 doped in a lower concentration than the impurity concentration of the impurity region 5406 in one side of the channel region in the semiconductor layer 5405. As shown in FIG. 54B, in the gate electrode 5409 of the N-channel transistor 5302, the first conductive layer 5403 is formed so as to spread on one side of the second conductive layer 5402. In this case as well, an LDD can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 5403 using the second conductive layer 5402 as a mask.

  A transistor having an LDD on one side of a channel region may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between a source electrode and a drain electrode. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

  In FIG. 53, the capacitor 5304 is formed by sandwiching an insulating layer 5408 between a first conductive layer 5403 and a semiconductor layer 5405. A semiconductor layer 5405 which forms the capacitor 5304 includes an impurity region 5410 and an impurity region 5411. The impurity region 5411 is formed in the semiconductor layer 5405 so as to overlap with the first conductive layer 5403. Further, the impurity region 5410 forms a contact with the wiring 5404. Since the impurity region 5411 can be doped with one conductivity type impurity through the first conductive layer 5403, the impurity concentrations in the impurity region 5410 and the impurity region 5411 can be the same or can be different. It is. In any case, since the semiconductor layer 5405 functions as an electrode in the capacitor 5304, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as shown in FIG. 54C, the first conductive layer 5403 can function sufficiently as an electrode by using the second conductive layer 5402 as an auxiliary electrode. In this manner, by using a composite electrode structure in which the first conductive layer 5403 and the second conductive layer 5402 are combined, the capacitor 5304 can be formed in a self-aligning manner.

  In FIG. 53, the resistance element 5305 is formed of a first conductive layer 5403. Since the first conductive layer 5403 is formed to a thickness of about 30 to 150 nm, a resistance element can be configured by appropriately setting the width and length thereof.

  The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small. A top view of the resistor 5305 is shown in FIG.

  In FIG. 53, a P-channel transistor 5303 is provided with an impurity region 5412 in a semiconductor layer 5405. The impurity region 5412 forms a source region and a drain region that form a contact with the wiring 5404. The gate electrode 5409 has a structure in which the first conductive layer 5403 and the second conductive layer 5402 overlap each other. The P-channel transistor 5303 is a single drain transistor without an LDD. In the case of forming the P-channel transistor 5303, boron or the like is added to the impurity region 5412 as an impurity imparting P-type conductivity. On the other hand, when phosphorus is added to the impurity region 5412, an N-channel transistor having a single drain structure can be obtained. A top view of the P-channel transistor 5303 is shown in FIG.

One or both of the semiconductor layer 5405 and the gate insulating layer 5408 is excited by microwaves, has an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 10 ¹¹ to 10 ¹³ cm ^−3. Oxidation or nitridation may be performed depending on the treatment. At this time, the substrate temperature is set to 300 to 450 ° C., and treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, or the like) or a nitriding atmosphere (N ₂ , NH _3, or the like), whereby the interface between the semiconductor layer 5405 and the gate insulating layer 5408 is obtained. The defect level of can be reduced. By performing this treatment on the gate insulating layer 5408, the insulating layer can be densified. That is, the generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 5408. In the case where the driving voltage of the transistor is 3 V or more, a gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 5405 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 5408 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 5304. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 53 and 54, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 54A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  53 and 54, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN) or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used for the first conductive layer, and a tungsten film can be used for the second conductive layer.

In this embodiment mode, transistors, capacitors, and resistors having different electrode structures are formed in the same patterning process using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function including a diffraction grating pattern or a semi-transmissive film. It shows that it can be made separately. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

  Note that the content described in this embodiment mode can be implemented by being freely combined with the content described in Embodiment Modes 1 to 9. That is, the display device according to this embodiment mode can form elements having different forms according to circuit characteristics without increasing the number of steps, so that the current flowing through the light-emitting element does not depend on the threshold voltage of the transistor. Combined with the effect, variation in luminance of the light emitting element can be reduced, and the image quality can be improved.

(Embodiment 11)
In this embodiment, an example of a mask pattern for manufacturing a display device including a transistor will be described with reference to FIGS.

  The semiconductor layers 5510 and 5511 shown in FIG. 55A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

  In any case, the semiconductor layer to be formed first is formed over the entire surface or a part of the substrate having an insulating surface (a region having a larger area than that defined as the semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. The semiconductor layer is etched using the mask pattern, whereby island-shaped semiconductor layers 5510 and 5511 having a specific shape including a source region and a drain region of the transistor and a channel formation region are formed. The semiconductor layers 5510 and 5511 are determined in consideration of appropriate layout.

  A photomask for forming the semiconductor layers 5510 and 5511 shown in FIG. 55A includes a mask pattern 5530 shown in FIG. This mask pattern 5530 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. In the case of using a positive resist, a mask pattern 5530 shown in FIG. 55B is manufactured as a light shielding portion. The mask pattern 5530 has a shape obtained by deleting the top A of the polygon. Further, the bent portion B has a shape that is bent over a plurality of steps so that the corner portion does not become a right angle. In the photomask pattern, for example, the corners of the pattern (right triangles) are removed so that one side is 10 μm or less.

  The shape of the mask pattern 5530 illustrated in FIG. 55B is reflected in the semiconductor layers 5510 and 5511 illustrated in FIG. At the time of photolithography, a shape similar to the mask pattern 5530 may be transferred, or the corner of the mask pattern 5530 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 5530 may be provided.

  Over the semiconductor layers 5510 and 5511, an insulating layer containing at least part of silicon oxide or silicon nitride is formed. One purpose of forming this insulating layer is a gate insulating layer. Then, as illustrated in FIG. 56A, gate wirings 5612, 5613, and 5614 are formed so as to partially overlap the semiconductor layer. Gate wiring 5612 is formed corresponding to semiconductor layer 5510. Gate wiring 5613 is formed corresponding to semiconductor layers 5510 and 5511. The gate wiring 5614 is formed corresponding to the semiconductor layers 5510 and 5511. For the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and its shape is formed on the insulating layer by a photolithography technique.

  A photomask for forming this gate wiring is provided with a mask pattern 5631 shown in FIG. This mask pattern 5631 is a corner, and one side of the (right triangle) is 10 μm or less, or less than 1/2 of the line width of the wiring, and the corner is deleted to a size of 1/5 or more of the line width. doing. The shape of the mask pattern 5631 illustrated in FIG. 56B is reflected in the gate wirings 5612, 5613, and 5614 illustrated in FIG. Although a shape similar to the mask pattern 5631 may be transferred, the corner of the mask pattern 5631 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 5631 may be provided. That is, the corners of the gate wirings 5612, 5613, and 5614 are 10 μm or less, or 1/2 or less of the line width of the wiring, and the corners are rounded to 1/5 or more. When the convex part is rounded, the generation of fine powder due to abnormal discharge is suppressed during dry etching by plasma, and when the concave part is rounded, even if it is fine powder, it collects at the corner. As a result of washing out what is easy, the yield can be improved.

  The interlayer insulating layer is a layer formed next to the gate wirings 5612, 5613, and 5614. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material such as polyimide or acrylic resin. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wirings 5612, 5613, and 5614. Further, an insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities such as exogenous metal ions and moisture which are not good for the transistor.

  An opening is formed at a predetermined position in the interlayer insulating layer. For example, it is provided corresponding to the gate wiring or semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 57A, wirings 5715 to 5720 are formed so as to partially overlap the semiconductor layer. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in the contact portion and other regions. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width changes so as to increase in that portion.

  A photomask for forming the wirings 5715 to 5720 includes a mask pattern 5732 shown in FIG. Even in this case, the wiring is a corner portion (right triangle) having a side of 10 μm or less, or 1/2 or less of the line width of the wiring and 1/5 or more of the line width. Remove the corners so that the corners have a rounded pattern. Such wiring, when the convex part is rounded, suppresses the generation of fine powder due to abnormal discharge during dry etching by plasma, and when the concave part is rounded, even if it is fine powder produced at the time of cleaning As a result of washing away the tendency to gather at the corner, the yield can be improved. By rounding the corners of the wiring, it is possible to prevent the electric field from concentrating on the corners of the wiring. Thereby, it becomes difficult to cut the wiring. In addition, a plurality of parallel wirings are very convenient for washing away dust.

  In FIG. 57A, N-channel transistors 5721 to 5724 and P-channel transistors 5725 and 5726 are formed. The N-channel transistor 5723 and the P-channel transistor 5725 and the N-channel transistor 5724 and the P-channel transistor 5726 constitute inverters 5727 and 5728. An insulating layer such as silicon nitride or silicon oxide may be formed over these transistors.

  Note that the contents described in this embodiment mode can be implemented by being freely combined with the contents described in Embodiment Modes 1 to 10. In other words, since the display device according to this embodiment can effectively remove dust during wiring formation, defects in the light-emitting element due to remaining foreign matters such as dust can be reduced, and light emission can be reduced. In combination with the feature that the current flowing through the element does not depend on the threshold voltage of the transistor, variation in luminance of the light-emitting element can be reduced and image quality can be improved.

(Embodiment 12)
In the present embodiment, hardware for controlling the driving method described in the first to seventh embodiments will be described.

  A rough block diagram is shown in FIG. A pixel portion 5804 is provided over the substrate 5801. In many cases, a signal line driver circuit 5806 and a scanning line driver circuit 5805 are provided. In addition, a power supply circuit, a precharge circuit, a timing generation circuit, and the like may be arranged. In some cases, the signal line driver circuit 5806 and the scan line driver circuit 5805 are not provided. In that case, what is not arranged on the substrate 5801 is often formed in an IC. In many cases, the IC is arranged on a substrate 5801 by COG (Chip On Glass). Alternatively, an IC may be arranged on the connection substrate 5807 that connects the peripheral circuit substrate 5802 and the substrate 5801.

  A signal 5803 is input to the peripheral circuit board 5802. Then, the controller 5808 controls and signals are stored in the memories 5809 and 5810. In the case where the signal 5803 is an analog signal, it is often stored in the memories 5809 and 5810 after analog-to-digital conversion. Then, the controller 5808 outputs a signal to the substrate 5801 using the signal stored in the memories 5809 and 5810.

  In order to realize the driving method described in Embodiments 1 to 7, the controller 5808 controls the appearance order of subframes and outputs a signal to the substrate 5801.

Note that the content described in this embodiment mode can be implemented by being freely combined with the content described in Embodiment Modes 1 to 11.

(Embodiment 13)
In this embodiment, a configuration example of an EL module and an EL television receiver using the display device of the present invention will be described.

  FIG. 59 shows an EL module in which a display panel 5901 and a circuit board 5902 are combined. A display panel 5901 includes a pixel portion 5903, a scan line driver circuit 5904, and a signal line driver circuit 5905. On the circuit board 5902, for example, a control circuit 5906, a signal dividing circuit 5907, and the like are formed. The display panel 5901 and the circuit board 5902 are connected by a connection wiring 5908. An FPC or the like can be used for the connection wiring.

  The control circuit 5906 corresponds to the controller 5808, the memories 5809, 5810, and the like in the twelfth embodiment. The control circuit 5906 mainly controls the appearance order of subframes.

  In the display panel 5901, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are formed over a substrate using transistors, and some peripheral driver circuits (a plurality of driver circuits) are formed. A driver circuit having a high operating frequency among the circuits) is formed over the IC chip, and the IC chip is preferably mounted on the display panel 5901 with COG (Chip On Glass) or the like. Alternatively, the IC chip may be mounted on the display panel 5901 using TAB (Tape Auto Bonding) or a printed board.

  In addition, by performing impedance conversion of a signal set to the scanning line or the signal line using a buffer, the pixel writing time for each row can be shortened. Therefore, a high-definition display device can be provided.

  In order to further reduce power consumption, a pixel portion is formed using a transistor on a glass substrate, all signal line driver circuits are formed on an IC chip, and the IC chip is displayed on a COG (Chip On Glass) display. It may be mounted on a panel.

  For example, the entire screen of the display panel is divided into several areas, and an IC chip in which a part or all of peripheral drive circuits (signal line drive circuit, scan line drive circuit, etc.) are formed is arranged in each area. (Chip On Glass) or the like may be mounted on the display panel. The structure of the display panel in this case is shown in FIG.

  FIG. 60 shows an example in which the entire screen is divided into four regions and driven using eight IC chips. The structure of the display panel includes a substrate 6010, a pixel portion 6011, FPCs 6012a to 6012h, and IC chips 6013a to 6013h. Among the eight IC chips, signal line driver circuits are formed in 6013a to 6013d, and scanning line driver circuits are formed in 6013e to 6013h. Then, by driving an arbitrary IC chip, it is possible to drive only an arbitrary screen area among the four screen areas. For example, when only the IC chips 6013a and 6013e are driven, only the upper left area of the four screen areas can be driven. By doing so, it is possible to reduce power consumption.

  An example of a display panel having another structure is shown in FIG. 61 includes a pixel portion 6121 in which a plurality of pixels 6130 are arranged over a substrate 6120, a scanning line driver circuit 6122 for controlling signals on the scanning line 6133, and a signal line driver circuit 6123 for controlling signals on the signal line 6131. Have. In addition, a monitor circuit 6124 for correcting a luminance change of the light emitting element included in the pixel 6130 may be provided. The light emitting element included in the pixel 6130 and the light emitting element included in the monitor circuit 6124 have the same structure. The structure of the light-emitting element is such that a layer containing a material that exhibits electroluminescence is sandwiched between a pair of electrodes.

  In the periphery of the substrate 6120, an input terminal 6125 for inputting a signal from an external circuit to the scan line driver circuit 6122, an input terminal 6126 for inputting a signal from the external circuit to the signal line driver circuit 6123, and a signal to the monitor circuit 6124 are input. An input terminal 6129 is provided.

  In order to cause the light-emitting element provided in the pixel 6130 to emit light, power needs to be supplied from an external circuit. A power supply line 6132 provided in the pixel portion 6121 is connected to an external circuit at an input terminal 6127. Since resistance loss occurs in the power supply line 6132 due to the length of the wiring, the input terminal 6127 is preferably provided at a plurality of locations around the substrate 6120. The input terminals 6127 are provided at both ends of the substrate 6120 and are arranged so that luminance unevenness is not noticeable in the plane of the pixel portion 6121. That is, it prevents the one side from being bright and the other side from being dark in the screen. In addition, the electrode on the side opposite to the electrode connected to the power supply line 6132 of the light-emitting element including the pair of electrodes is formed as a common electrode shared by the plurality of pixels 6130, and the resistance loss of this electrode is also reduced. For this purpose, a plurality of terminals 6128 are provided.

  Such a display panel is effective particularly when the screen size is increased because the power supply line is formed of a low resistance material such as Cu. For example, when the screen size is the 13-inch class, the length of the diagonal line is 340 mm, but when the screen size is the 60-inch class, the length is 1500 mm or more. In such a case, since the wiring resistance cannot be ignored, it is preferable to use a low resistance material such as Cu as the wiring. In consideration of wiring delay, signal lines and scanning lines may be formed in the same manner.

  An EL television receiver can be completed with the EL module having the panel configuration as described above. FIG. 62 is a block diagram illustrating a main configuration of an EL television receiver. A tuner 6201 receives a video signal and an audio signal. The video signal includes a video signal amplifying circuit 6202, a video signal processing circuit 6203 for converting a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and the video signal as input specifications of the drive circuit. Processing is performed by a control circuit 5906 for conversion. The control circuit 5906 outputs a signal to each of the scan line side and the signal line side. In the case of digital driving, a signal dividing circuit 5907 may be provided in front of the signal line driver circuit 5905 so that an input digital signal is divided into M pieces and supplied.

  Of the signals received by the tuner 6201, the audio signal is sent to the audio signal amplifier circuit 6204, and the output is supplied to the speaker 6206 through the audio signal processing circuit 6205. The control circuit 6207 receives control information on the receiving station (reception frequency) and volume from the input unit 6208 and sends a signal to the tuner 6201 and the audio signal processing circuit 6205.

  A television receiver can be completed by incorporating an EL module into a housing. A display portion is formed by the EL module. In addition, speakers, video input terminals, and the like are provided as appropriate.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

  As described above, by using the display device of the present invention and its driving method, the current flowing through the light-emitting element is determined in a manner that does not depend on the threshold voltage of the transistor, so that variations in the threshold voltage of the transistor can be compensated. it can. Accordingly, variation in luminance of the light emitting element can be reduced, and image quality can be improved.

  Note that the content described in this embodiment mode can be implemented by being freely combined with the content described in Embodiment Modes 1 to 12.

(Embodiment 14)
As an electronic device using the display device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproducing device (car audio, audio component, etc.), a personal computer, a game device, portable information A terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device (specifically, Digital Versatile Disc (DVD)) provided with a storage medium, and the image is displayed. And the like). Specific examples of these electronic devices are shown in FIGS.

  FIG. 63A illustrates a light-emitting device, which includes a housing 6301, a support base 6302, a display portion 6303, a speaker portion 6304, a video input terminal 6305, and the like. The present invention can be used for a display device included in the display portion 6303. According to the present invention, a clear image with reduced luminance variation can be viewed. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The light emitting device includes all display devices for displaying information such as for personal computers, for receiving TV broadcasts, and for displaying advertisements.

  FIG. 63B shows a digital still camera, which includes a main body 6306, a display portion 6307, an image receiving portion 6308, operation keys 6309, an external connection port 6310, a shutter 6311, and the like. The present invention can be used for a display device included in the display portion 6307, and according to the present invention, a clear image with reduced variation in luminance can be viewed.

  FIG. 63C illustrates a laptop personal computer, which includes a main body 6312, a housing 6313, a display portion 6314, a keyboard 6315, an external connection port 6316, a pointing device 6317, and the like. The present invention can be used for a display device included in the display portion 6314. According to the present invention, a clear image with reduced variation in luminance can be viewed.

  FIG. 63D illustrates a mobile computer, which includes a main body 6318, a display portion 6319, a switch 6320, operation keys 6321, an infrared port 6322, and the like. The present invention can be used for a display device included in the display portion 6319, and according to the present invention, a clear image with reduced variation in luminance can be viewed.

  FIG. 63E shows a portable image playback device (specifically, a DVD playback device) provided with a storage medium device, which includes a main body 6323, a housing 6324, a display portion A 6325, a display portion B 6326, a storage medium (such as a DVD). ) A reading unit 6327, an operation key 6328, a speaker unit 6329, and the like are included. The display portion A 6325 mainly displays image information, and the display portion B mainly displays character information. The present invention can be used for a display device included in the display portion A 6325 and the display portion B 6326. According to the present invention, a clear image with reduced luminance variation can be viewed. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  FIG. 63F illustrates a goggle type display (head mounted display), which includes a main body 6330, a display portion 6331, an arm portion 6332, and the like. The present invention can be used for a display device included in the display portion 6331, and according to the present invention, a clear image with reduced variation in luminance can be viewed.

  FIG. 63G illustrates a video camera, which includes a main body 6333, a display portion 6334, a housing 6335, an external connection port 6336, a remote control reception portion 6337, an image receiving portion 6338, a battery 6339, an audio input portion 6340, operation keys 6341, and the like. . The present invention can be used for a display device included in the display portion 6334, and according to the present invention, a clear image with reduced variation in luminance can be viewed.

  FIG. 63H illustrates a cellular phone, which includes a main body 6342, a housing 6343, a display portion 6344, an audio input portion 6345, an audio output portion 6346, operation keys 6347, an external connection port 6348, an antenna 6349, and the like. The present invention can be used for a display device constituting the display portion 6344. Note that the display portion 6344 can suppress current consumption of the mobile phone by displaying white characters on a black background. In addition, according to the present invention, it is possible to view a beautiful image with reduced luminance variation.

  Note that if a light emitting material having high light emission luminance is used, light including output image information can be enlarged and projected by a lens or the like and used for a front type or rear type projector.

  In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the response speed of the light emitting material is very high, the light emitting device is preferable for displaying moving images.

  In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to do.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the display device having any structure described in any of Embodiments 1 to 13 may be used for the electronic device of this embodiment.

FIG. 14 illustrates an example of a basic structure of a pixel in a display device of the present invention. FIG. 14 illustrates an example of a basic structure of a pixel in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. 6A and 6B illustrate an operation of a pixel circuit in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 14 illustrates an example of a layout of a pixel structure in a display device of the present invention. FIG. 6 illustrates a configuration example of a display device of the present invention. FIG. 11 illustrates a configuration example of a signal line driver circuit in a display device of the present invention. FIG. 11 illustrates a configuration example of a scan line driver circuit in a display device of the present invention. FIG. 6 illustrates a configuration example of a display device of the present invention. FIG. 6 illustrates a configuration example of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. 3A and 3B each illustrate a structure of a transistor used for a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 4A and 4B illustrate a method for manufacturing a transistor used in a display device of the present invention. 3A and 3B each illustrate a cross-sectional structure of a transistor used for a display device of the present invention. FIG. 6 is a top view of a transistor used for a display device of the present invention. FIG. 13 shows an example of a mask pattern of a transistor used for a display device of the present invention. FIG. 13 shows an example of a mask pattern of a transistor used for a display device of the present invention. FIG. 13 shows an example of a mask pattern of a transistor used for a display device of the present invention. The figure which shows an example of the hardware which controls the drive system of this invention. The figure which shows an example of the EL module using the drive system of this invention. FIG. 11 illustrates a configuration example of a display panel using the driving method of the present invention. FIG. 11 illustrates a configuration example of a display panel using the driving method of the present invention. FIG. 6 is a diagram showing an example of an EL television receiver using the driving method of the present invention. FIG. 11 is a diagram showing an example of an electronic device to which the driving method of the present invention is applied. The figure which shows the conventional pixel structure. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 11 illustrates an example of a pixel structure in a display device of the present invention. FIG. 14 illustrates an example of a structure of a display panel used in a display device of the present invention. FIG. 14 illustrates an example of a structure of a light-emitting element used for a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention. FIG. 14 illustrates an example of a structure of a display device of the present invention.

Explanation of symbols

101 first transistor 102 second transistor 103 storage capacitor 104 scanning line 105 first power supply line 106 second power supply line 107 capacitor line 108 light emitting element 115 capacitor line 201 first transistor 202 second transistor 203 storage capacitor 204 Scanning line 205 1st power supply line 206 2nd power supply line 207 Capacitance line 208 Light emitting element 301 1st transistor 302 2nd transistor 303 3rd transistor 304 4th transistor 305 5th transistor 306 1st Holding capacitor 307 Second holding capacitor 308 Signal line 309 First scanning line 310 Second scanning line 311 Third scanning line 312 Fourth scanning line 313 First power supply line 314 Second power supply line 315 Capacity line 316 Light-emitting element 901 First transistor 902 Second transistor 90 3rd transistor 904 4th transistor 905 5th transistor 906 1st storage capacitor 907 2nd storage capacitor 908 Signal line 909 1st scanning line 910 2nd scanning line 911 3rd scanning line 912 4th Scan line 913 First power line 914 Second power line 915 Capacitor line 916 Light emitting element 3617 Reference line 1901 Transistor 1902 Transistor 1903 Transistor 1904 Transistor 1905 Transistor 1906 Retention capacity 1907 Retention capacity 1908 Signal line 1909 First scan line 1910 Second scanning line 1911 Third scanning line 1912 Fourth scanning line 1913 Power supply line 1914 Power supply line 1916 Light emitting element 1923 Third transistor 1927 Second storage capacitor 1929 First scanning line 1930 Second scanning line 1931 First Scan line 1932 Fourth scan line 2101 Transistor 2102 Transistor 2103 Transistor 2104 Transistor 2105 Transistor 2106 Storage capacitor 2107 Storage capacitor 2108 Signal line 2109 First scan line 2110 Second scan line 2111 Third scan line 2112 Fourth Scan line 2113 Power line 2114 Power line 2116 Light emitting element 2123 Third transistor 2127 Second storage capacitor 2129 First scan line 2130 Second scan line 2131 Third scan line 2132 Fourth scan line 2136 Light emitting element 2149 1st scanning line 2317 6th transistor 2318 5th scanning line 3517 Reference line 3801 Pixel portion 3802 1st scanning line driving circuit 3803 2nd scanning line driving circuit 3804 3rd scanning line driving circuit 3805 4th Run Inspection line driving circuit 3806 Signal line driving circuit 3807 First scanning line 3808 Second scanning line 3809 Third scanning line 3810 Fourth scanning line 3811 Signal line 3812 Inverter 3901 Shift register 3902 First latch circuit 3903 Second Latch circuit 3904 amplifying circuit 3905 sampling circuit 4001 shift register 4002 amplifying circuit 4301 substrate 4302 base film 4303 pixel electrode 4304 first electrode 4305 wiring 4306 wiring 4307 N-type semiconductor layer 4308 N-type semiconductor layer 4309 semiconductor layer 4310 gate insulating film 4311 Insulating film 4312 Gate electrode 4313 Second electrode 4314 Interlayer insulating film 4315 Layer containing organic compound 4316 Counter electrode 4317 Light emitting element 4318 Drive transistor 4319 Capacitor element 4320 First electrode 440 1 substrate 4403 gate electrode 4404 first electrode 4405 gate insulating film 4406 semiconductor layer 4407 semiconductor layer 4408 N-type semiconductor layer 4409 N-type semiconductor layer 4410 N-type semiconductor layer 4411 wiring 4412 wiring 4413 conductive layer 4414 pixel electrode 4415 insulator 4416 organic Compound-containing layer 4417 Counter electrode 4418 Light-emitting element 4419 Drive transistor 4420 Capacitor element 4421 Capacitor element 4421 Capacitor element 4501 Insulator 4601 Substrate 4602 Insulating film 4603a Semiconductor film 4603b Semiconductor film 4604 Gate insulating film 4605 Gate electrode 4606 Insulating film 4607 Insulating Film 4608 Conductive film 4610a N-channel transistor 4610b P-channel transistor 4621a Insulating film 4621b Insulating film 4623 Insulating film 4624 Insulating film 46 26 Insulating film 4627a Insulating film 4627b Insulating film 4651a End portion 4651b End portion 4651a End portion 4552b End portion 4653a End portion 4653b End portion 4723 Insulating film 5301 N-channel transistor 5302 N-channel transistor 5303 P-channel transistor 5304 Capacitor element 5305 Resistor Element 5402 Second conductive layer 5403 First conductive layer 5404 Wiring 5405 Semiconductor layer 5406 Impurity region 5407 Impurity region 5408 Insulating layer 5409 Gate electrode 5410 Impurity region 5411 Impurity region 5412 Impurity region 5510 Semiconductor layer 5511 Semiconductor layer 5530 Mask pattern 5612 Gate wiring 5613 Gate wiring 5614 Gate wiring 5631 Mask pattern 5715 Wiring 5716 Wiring 5717 Wiring 5718 Wiring 5719 Line 5720 Wiring 5721 N-channel transistor 5722 N-channel transistor 5723 N-channel transistor 5724 N-channel transistor 5725 P-channel transistor 5726 P-channel transistor 5727 Inverter 5728 Inverter 5732 Mask pattern 5801 Substrate 5802 Peripheral circuit board 5803 Signal 5804 Pixel Section 5805 Scanning line driving circuit 5806 Signal line driving circuit 5807 Connection board 5808 Controller 5809 Memory 5810 Memory 5901 Display panel 5902 Circuit board 5903 Pixel section 5904 Scanning line driving circuit 5905 Signal line driving circuit 5906 Control circuit 5907 Signal division circuit 5908 Connection wiring 6010 Substrate 6011 Pixel portion 6012a FPC
6012b FPC
6012c FPC
6012d FPC
6012e FPC
6012f FPC
6012g FPC
6012h FPC
6013a IC chip 6013b IC chip 6013c IC chip 6013d IC chip 6013e IC chip 6013f IC chip 6013g IC chip 6013h IC chip 6120 Substrate 6121 Pixel portion 6122 Scan line driver circuit 6123 Signal line driver circuit 6124 Monitor circuit 6125 Input terminal 6126 Input terminal 6127 Input Terminal 6128 Terminal 6129 Input terminal 6130 Pixel 6131 Signal line 6132 Power line 6133 Scanning line 6201 Tuner 6202 Video signal amplifier circuit 6203 Video signal processor circuit 6204 Audio signal amplifier circuit 6205 Audio signal processor circuit 6206 Speaker 6207 Control circuit 6208 Input unit 6301 Case 6302 Support base 6303 Display unit 6304 Speaker unit 6305 Video input terminal 6306 Main body 6307 Table Display unit 6308 Image receiving unit 6309 Operation key 6310 External connection port 6311 Shutter 6312 Main body 6313 Housing 6314 Display unit 6315 Keyboard 6316 External connection port 6317 Pointing device 6318 Main body 6319 Display unit 6320 Switch 6321 Operation key 6322 Infrared port 6323 Main body 6324 Housing 6325 Display part A
6326 Display B
6327 Reading unit 6328 Operation key 6329 Speaker unit 6330 Main unit 6331 Display unit 6332 Arm unit 6333 Main unit 6334 Display unit 6335 External connection port 6337 Remote control reception unit 6338 Image receiving unit 6339 Battery input unit 6341 Operation key 6342 Main unit 6343 Case 6344 Display unit 6345 Audio input unit 6346 Audio output unit 6347 Operation key 6348 External connection port 6349 Antenna 6401 Driving transistor 6402 Switching transistor 6403 Retention capacitor 6404 Signal line 6405 Scan line 6406 First power line 6407 Second power line 6408 Light emitting element 6411 Light emitting element 6701 Signal line driver circuit 6702 Pixel portion 6703 First scanning line driver circuit 6704 Sealing substrate 6705 Seal Material 6706 Second scanning line driving circuit 6707 Space 6708 Wiring 6709 FPC
6710 substrate 6711 switching transistor 6712 driving transistor 6713 first electrode 6714 insulator 6716 layer containing organic compound 6717 second electrode 6718 light-emitting element 6719 IC chip 6720 IC chip 6721 transistor 6722 transistor 6801 substrate 6802 anode 6803 hole injection Layer 6804 Hole transport layer 6805 Light emitting layer 6806 Electron transport layer 6807 Electron injection layer 6808 Cathode 6900 Substrate 6901 Driving transistor 6902 First electrode 6903 Layer containing an organic compound 6904 Second electrode 7000 Substrate 7001 Driving transistor 7002 Base film 7003 First electrode 7004 Layer 7005 containing organic compound Second electrode 7006R Red color filter 7006G Green color filter 70 6B Blue color filter 7007 Black matrix 7101 Substrate 7102 Base film 7103 Channel formation region 7104 LDD region 7105 Impurity region 7106 Channel formation region 7107 LDD region 7108 Impurity region 7109 Gate insulating film 7110 Gate electrode 7111 Upper electrode 7112 Interlayer insulating film 7113 Wiring 7114 Pixel electrode 7115 Insulator 7116 Layer containing organic compound 7117 Counter electrode 7118 Driving transistor 7119 Capacitor element 7120 Light emitting element 7121 Region 7122 Second upper electrode 7123 Capacitor element 7201 Substrate 7202 Base film 7203 Channel formation region 7204 LDD region 7205 Impurity region 7206 Gate insulating film 7207 Gate electrode 7208 First electrode 7209 First interlayer insulating film 7210 Wiring 7 211 Second electrode 7212 Second interlayer insulating film 7213 Pixel electrode 7214 Third electrode 7216 Layer containing organic compound 7217 Counter electrode 7218 Driving transistor 7219 Capacitor element 7220 Light emitting element 7301 Substrate 7302 Base film 7303 Gate electrode 7304 First Electrode 7305 gate insulating film 7306 channel forming region 7307 LDD region 7308 impurity region 7309 channel forming region 7310 LDD region 7311 impurity region 7312 first interlayer insulating film 7313 wiring 7314 third electrode 7315 opening 7316 second interlayer insulating film 7317 Pixel electrode 7318 Insulator 7319 Organic compound layer 7320 Counter electrode 7321 Light-emitting element 7322 Driver transistor 7323 Capacitor element 7324 Fourth electrode 7325 Capacitor element

Claims (12)

A transistor, a first switch, a second switch, a third switch, a fourth switch, and the semiconductor layer, and the insulating film on the semiconductor layer, and a conductive layer on said insulating film, said A semiconductor device comprising: a second insulating film on a conductive layer; a second conductive layer on the second insulating film; and a third conductive layer on the second insulating film ,
A period in which the first switch is on and the second switch is off;
The transistor is a P-channel type,
P-channel transistors are used as the first switch, the second switch, the third switch, and the fourth switch,
One of a source and a drain of the transistor is electrically connected to the first wiring;
A gate of the transistor is electrically connected to the conductive layer;
A first terminal of the first switch is electrically connected to a gate of the transistor;
A second terminal of the first switch is electrically connected to the other of the source and the drain of the transistor;
A first terminal of the second switch is electrically connected to the other of the source and the drain of the transistor;
A second terminal of the second switch is electrically connected to the pixel electrode;
A first terminal of the third switch is electrically connected to a second wiring;
A second terminal of the third switch is electrically connected to the semiconductor layer;
A first terminal of the fourth switch is electrically connected to a third wiring;
A second terminal of the fourth switch is electrically connected to the semiconductor layer;
The conductive layer has a region functioning as a gate electrode of the transistor,
The second conductive layer is electrically connected to the conductive layer;
The third conductive layer is electrically connected to the semiconductor layer;
A first terminal of the first switch is electrically connected to the conductive layer via the second conductive layer;
A second terminal of the fourth switch is electrically connected to the semiconductor layer through the third conductive layer;
The first wiring has a function of supplying a first potential input to one of a source and a drain of the transistor,
The second wiring has a function of supplying a video signal;
The semiconductor device, wherein the third wiring has a function of supplying a second potential input to the semiconductor layer. A transistor, a first switch, a second switch, a third switch, a fourth switch, and the semiconductor layer, and the insulating film on the semiconductor layer, and a conductive layer on said insulating film, said A semiconductor device comprising: a second insulating film on a conductive layer; a second conductive layer on the second insulating film; and a third conductive layer on the second insulating film ,
A period in which the first switch is on and the second switch is off;
The transistor is a P-channel type,
P-channel transistors are used as the first switch, the second switch, the third switch, and the fourth switch,
One of a source and a drain of the transistor is electrically connected to the first wiring;
A gate of the transistor is electrically connected to the conductive layer;
A first terminal of the first switch is electrically connected to a gate of the transistor;
A second terminal of the first switch is electrically connected to the other of the source and the drain of the transistor;
A first terminal of the second switch is electrically connected to the other of the source and the drain of the transistor;
A second terminal of the second switch is electrically connected to the pixel electrode;
A first terminal of the third switch is electrically connected to a second wiring;
A second terminal of the third switch is electrically connected to the semiconductor layer;
A first terminal of the fourth switch is electrically connected to a third wiring;
A second terminal of the fourth switch is electrically connected to the semiconductor layer;
The conductive layer has a region functioning as a gate electrode of the transistor,
The second conductive layer is electrically connected to the conductive layer;
The third conductive layer is electrically connected to the semiconductor layer;
A first terminal of the first switch is electrically connected to the conductive layer via the second conductive layer;
A second terminal of the fourth switch is electrically connected to the semiconductor layer through the third conductive layer;
The first wiring has a function as a power line,
The second wiring has a function as a signal line,
The semiconductor device, wherein the third wiring has a function as a power supply line. In claim 1 or claim 2,
The pixel electrode includes a region overlapping with the semiconductor layer, the insulating film, and the conductive layer. In any one of Claims 1 thru | or 3 ,
The channel width of the transistor is larger than the channel width of the transistor used for the first switch,
The channel width of the transistor is larger than the channel width of the transistor used for the second switch,
A semiconductor device, wherein a channel width of the transistor is larger than a channel width of a transistor used for the third switch. In any one of Claims 1 thru | or 4 ,
Having a fifth switch;
A first terminal of the fifth switch is electrically connected to the third wiring;
The semiconductor device, wherein the second terminal of the fifth switch is electrically connected to the other of the source and the drain of the transistor. A transistor, a first switch, a second switch, a third switch, a fourth switch, and the semiconductor layer, and the insulating film on the semiconductor layer, and a conductive layer on said insulating film, said A display device comprising: a second insulating film on a conductive layer; a second conductive layer on the second insulating film; and a third conductive layer on the second insulating film ,
A period in which the first switch is on and the second switch is off;
The transistor is a P-channel type,
P-channel transistors are used as the first switch, the second switch, the third switch, and the fourth switch,
One of a source and a drain of the transistor is electrically connected to the first wiring;
A gate of the transistor is electrically connected to the conductive layer;
A first terminal of the first switch is electrically connected to a gate of the transistor;
A second terminal of the first switch is electrically connected to the other of the source and the drain of the transistor;
A first terminal of the second switch is electrically connected to the other of the source and the drain of the transistor;
A second terminal of the second switch is electrically connected to the light emitting element;
A first terminal of the third switch is electrically connected to a second wiring;
A second terminal of the third switch is electrically connected to the semiconductor layer;
A first terminal of the fourth switch is electrically connected to a third wiring;
A second terminal of the fourth switch is electrically connected to the semiconductor layer;
The conductive layer has a region functioning as a gate electrode of the transistor,
The second conductive layer is electrically connected to the conductive layer;
The third conductive layer is electrically connected to the semiconductor layer;
A first terminal of the first switch is electrically connected to the conductive layer via the second conductive layer;
A second terminal of the fourth switch is electrically connected to the semiconductor layer through the third conductive layer;
The first wiring has a function of supplying a first potential input to one of a source and a drain of the transistor,
The second wiring has a function of supplying a video signal;
The display device, wherein the third wiring has a function of supplying a second potential input to the semiconductor layer. A transistor, a first switch, a second switch, a third switch, a fourth switch, and the semiconductor layer, and the insulating film on the semiconductor layer, and a conductive layer on said insulating film, said A display device comprising: a second insulating film on a conductive layer; a second conductive layer on the second insulating film; and a third conductive layer on the second insulating film ,
A period in which the first switch is on and the second switch is off;
The transistor is a P-channel type,
P-channel transistors are used as the first switch, the second switch, the third switch, and the fourth switch,
One of a source and a drain of the transistor is electrically connected to the first wiring;
A gate of the transistor is electrically connected to the conductive layer;
A first terminal of the first switch is electrically connected to a gate of the transistor;
A second terminal of the first switch is electrically connected to the other of the source and the drain of the transistor;
A first terminal of the second switch is electrically connected to the other of the source and the drain of the transistor;
A second terminal of the second switch is electrically connected to the light emitting element;
A first terminal of the third switch is electrically connected to a second wiring;
A second terminal of the third switch is electrically connected to the semiconductor layer;
A first terminal of the fourth switch is electrically connected to a third wiring;
A second terminal of the fourth switch is electrically connected to the semiconductor layer;
The conductive layer has a region functioning as a gate electrode of the transistor,
The second conductive layer is electrically connected to the conductive layer;
The third conductive layer is electrically connected to the semiconductor layer;
A first terminal of the first switch is electrically connected to the conductive layer via the second conductive layer;
A second terminal of the fourth switch is electrically connected to the semiconductor layer through the third conductive layer;
The first wiring has a function as a power line,
The second wiring has a function as a signal line,
The display device, wherein the third wiring has a function as a power supply line. In claim 6 or claim 7 ,
One display electrode of the light-emitting element includes a region overlapping with the semiconductor layer, the insulating film, and the conductive layer. In any one of Claims 6 to 8 ,
The channel width of the transistor is larger than the channel width of the transistor used for the first switch,
The channel width of the transistor is larger than the channel width of the transistor used for the second switch,
A display device, wherein a channel width of the transistor is larger than a channel width of a transistor used for the third switch. In any one of Claims 6 thru | or 9 ,
Having a fifth switch;
A first terminal of the fifth switch is electrically connected to the third wiring;
The display device, wherein the second terminal of the fifth switch is electrically connected to the other of the source and the drain of the transistor. A display module comprising the semiconductor device according to any one of claims 1 to 5 or the display device according to any one of claims 6 to 11 and an FPC. An electronic apparatus comprising: the display module according to claim 1 1, an operation switch, the.

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