JP5646764B2 - Control system and method reconfigurable during operation - Google Patents

Description

  The present invention relates to a control system and method, and more particularly to a control system and method that can be reconfigured during operation.

  Devices such as robots use a servo motor for operation. The operation of the apparatus can be controlled by controlling the servo motor.

  Generally, operation control is performed using a master controller and a slave controller. The master controller transmits a control signal to each slave controller, and the slave controller controls the corresponding servo motor by the control signal. The master controller can be connected to a plurality of slave controllers, and each slave controller controls a corresponding servo motor.

  The slave controller is generally equipped with a functional board package that matches the operation of the servo motor. However, there is a restriction that the slave controller can control only the corresponding servo motor. That is, there is a problem that the slave controller must be replaced when changing the servo motor to another model.

  The present invention provides a reconfigurable control system and method capable of reconfiguring the structure of a gate array (FPGA: Field Programmable Gate Array) while changing the control method of the apparatus while maintaining the control of the apparatus. The purpose is to do.

  According to one aspect of the present invention, a master controller that generates a bitstream including reconfiguration information according to a user's command and a first slave controller, the first slave controller including the reconfiguration A first dynamic reconfiguration module that is a gate array (FPGA: Field Programmable Gate Array) that is reconfigured based on information and calculates a control value; and a static reconfiguration that is a gate array that controls the operation of the target device based on the control value. Reconfiguration during operation, comprising: a configuration module; and a controller configured to reconfigure one or more of the first dynamic reconfiguration module and the static reconfiguration module with the reconfiguration information A possible control system is provided.

  The control unit can reconfigure the gate array structure of the dynamic reconfiguration module independently of the operation of the static reconfiguration module.

  The slave controller further includes a second dynamic reconfiguration module that is a gate array that is reconfigured by the reconfiguration information and calculates a control value, and the control unit specifies a capacity of the reconfiguration information. If the second dynamic reconfiguration module is reconfigured according to the reconfiguration information, the first dynamic reconfiguration module is reconfigured until the reconfiguration of the second dynamic reconfiguration module is completed. Operation of the configuration module can be maintained.

  In addition, when the reconfiguration of the second dynamic reconfiguration module is completed, the control unit can stop the operation of the first dynamic reconfiguration module.

  The master controller includes a reconfiguration library storage unit that stores function information indicating a connection relationship between the gates of the first dynamic reconfiguration module or the static reconfiguration module, and the function according to the instruction. A reconfiguration information combining unit that extracts information and combines the extracted function information to generate the reconfiguration information, and an entry management unit that generates a bitstream including the reconfiguration information can be included.

  In addition, when the slave communication unit further transmits the bit stream to the first slave controller, and the entry management unit generates reconfiguration time information that is a time point when the bit stream according to the command is transmitted, the slave The communication unit can transmit the bit stream to the first slave controller when the predetermined period arrives or when the bit stream is generated based on the reconfiguration time information.

  The apparatus further includes a second slave controller that is a controller having the same configuration as the first slave controller, and the master controller corresponds to each of the first slave controller and the second slave controller. The bitstream including reconfiguration information can be generated.

  The master controller, the first slave controller, and the second slave controller can be connected by a network having a double ring structure.

  When the target device is changed, the static reconfiguration module may be a gate array reconfigured by the reconfiguration information.

  According to another aspect of the present invention, in a method in which a reconfigurable control system controls the operation of a target device, a step of generating a bitstream including reconfiguration information according to a user command, and the reconfiguration information Reconfiguring a first gate array (FPGA: Field Programmable Gate Array) that is reconstructed by calculating the control value, calculating a control value using the reconfigured gate array, and the target device And transmitting the control value to a second gate array that controls the operation of the control method.

  The step of reconfiguring the first gate array may be performed independently of the operation of the second gate array.

  When the capacity of the reconfiguration information is greater than or equal to a specified value, the third gate array includes a step of reconfiguring a third gate array that is reconfigured by the reconfiguration information and calculates a control value. The operation of the first gate array can be maintained until the reconfiguration is completed.

  The method may further include a step of stopping the operation of the first gate array when the reconfiguration of the third gate array is completed.

  In addition, the step of generating the bitstream may include the function from a storage space of the control system that stores function information indicating a connection relationship between the gates of the first gate array or the second gate array according to the instruction. The method may include a step of extracting information, a step of generating the reconstruction information by combining the extracted function information, and a step of generating a bitstream including the reconstruction information.

It is drawing which shows a control system. It is drawing which shows the structure of the bit stream which the master controller of a control system produces | generates. It is a block diagram which shows notionally the structure of a master controller. 6 is a diagram illustrating a process in which a master controller generates reconfiguration information. It is a block diagram which shows simply the function part which comprises a 1st slave controller. It is a flowchart which shows the process in which a control system controls operation of a servomotor.

  FIG. 1 illustrates a control system that can be reconfigured during operation according to an embodiment of the present invention.

  Referring to FIG. 1, the control system according to an embodiment of the present invention includes a master controller 101, a first slave controller 102, and a second slave controller 103. Although two slave controllers are shown in FIG. 1, the control system according to the embodiment of the present invention can include various numbers of slave controllers depending on the environment to which the present invention is applied. Each slave controller can be connected to each servo motor and one or more sensors that sense acceleration, heat generation, and the like of the servo motor.

  The master controller 101 receives a command related to an operation to be controlled from an input device such as a PC (not shown). At this time, the command received from the input device is a signal indicating an operation command according to one of the servo motor operation patterns. The master controller 101 performs one or more re-orders instructing the reconfiguration of the field programmable gate array (FPGA) provided in each slave controller so that the servo motor operates according to the pattern corresponding to the received command. Configuration information can be stored matching the received instruction. For example, the master controller 101 can generate a bitstream including instructions received from the input device and reconstruction information that matches the instructions.

  For example, as shown in FIG. 1, when there are two slave controllers 102 and 103, the master controller 101 transmits the first reconfiguration information corresponding to the first slave controller 102 and the second slave controller 103. A bitstream can be generated including one or more of the corresponding second reconstruction information.

  Hereinafter, the structure of the bit stream will be described in detail with reference to FIG.

  FIG. 2 is a diagram illustrating a structure of a bit stream generated by a master controller of a control system according to an embodiment of the present invention.

  The master controller 101 controls the servo motors connected to the first slave controller 102 and the second slave controller 103 according to the command received from the input device, respectively. A bit stream including reconfiguration information that instructs reconfiguration of the FPGA provided in the two-slave controller 103 is generated.

    At this time, the master controller 101 makes it easy for each slave controller to extract the reconfiguration information so that the reconfiguration information is positioned after the slave identification information that is information that can identify each slave controller in the bitstream. Can be.

  For example, the first slave identification information 210 and the first reconfiguration information 220 shown in FIG. 2 are the slave identification information and the reconfiguration information corresponding to the first slave controller 102, and the second slave identification information 230 and the first reconfiguration information 220 are the same. The 2 reconfiguration information 240 is slave identification information and reconfiguration information corresponding to the second slave controller 103. The first slave controller 102 searches the first slave identification information 210 included in the bitstream, and the data from after the first slave identification information 210 to before the next slave identification information is the first reconfiguration information. 220, and the first reconstruction information 220 can be extracted from the bitstream.

  Referring to FIG. 1 again, the master controller 101 can periodically generate a plurality of bit streams for instructions received from the input device.

  For example, it is assumed that the command received from the input device is a command for instructing to alternately perform the servo motor operation and stop processes at predetermined intervals. In this case, the master controller 101 generates a bit stream including reconfiguration information for operating the servo motor and a bit stream including reconfiguration information for stopping the servo motor at predetermined intervals. It can be generated alternately. Hereinafter, the configuration of the master controller 101 will be described in detail with reference to FIG.

  FIG. 3 is a block diagram conceptually showing the structure of the master controller. Referring to FIG. 3, the master controller 101 includes a host communication unit 310, a reconfiguration information combination unit 320, a reconfiguration library storage unit 330, an entry management unit 340, and a slave communication unit 350.

  The host communication unit 310 receives a user's command from the input device via the network. The host communication unit 310 transmits the received command to the reconfiguration information combination unit 320.

  The reconfiguration information combination unit 320 extracts one or more function information stored in the reconfiguration library storage unit according to an instruction received from the host communication unit 310, and generates reconfiguration information by combining the extracted function information. .

  Here, the function information according to the embodiment of the present invention can include information on the connection relationship between the gates of the FPGA of the slave controller, and can be expressed by various methods such as a bit string. The FPGA according to the embodiment of the present invention can perform a specific function when reconfigured by function information. The process of generating the reconfiguration information will be described in detail with reference to FIG. 4 later. At this time, the reconfiguration information combination unit 320 transmits the generated reconfiguration information to the entry management unit 340.

  The entry management unit 340 generates reconstruction time information and reconstruction mode information based on the reconstruction information received from the reconstruction information combination unit 320.

  Here, the reconfiguration time information is information indicating whether the time point when the bit stream including the reconfiguration information is transmitted is transmitted immediately or when the slave communication unit 350 periodically transmits the bit stream. It is.

  Here, the reconfiguration mode information is information indicating whether or not each slave controller that has received the bitstream reconfigures the FPGA.

  The entry management unit 340 inserts the reconfiguration mode information into the reconfiguration information, generates a bitstream including each reconfiguration information and slave identification information, and transmits the bit stream together with the reconfiguration time information to the slave communication unit 350.

  The slave communication unit 350 transmits the bit stream to the first slave controller 102 or the second slave controller 103 according to the reconfiguration time information. That is, when the reconfiguration time information indicates that the bit stream is transmitted immediately, the slave communication unit 350 immediately transmits the bit stream to the slave controller, and the reconfiguration time information indicates that the bit stream is transmitted according to the transmission cycle. When indicating transmission, the bit stream is transmitted when the transmission period designated by the slave communication unit 350 arrives.

  Referring to FIG. 1 again, the master controller 101 transmits the generated bit stream to the first slave controller 102. At this time, the master controller 101 can be connected to the first slave controller 102 and the second slave controller 103 in a double ring structure. That is, there may be a case where the second slave controller 103 cannot receive the bit stream transmitted from the master controller 101 to the first slave controller 102. In this case, the master controller 101 can transmit the generated bit stream to the second slave controller 103 using the double ring structure. Therefore, according to the embodiment of the present invention, even if a part of the network among the master controller 101, the first slave controller 102, and the second slave controller 103 is disconnected, it can operate normally. .

  The first slave controller 102 extracts reconfiguration information from the bit stream received from the master controller 101, reconfigures the FPGA based on the reconfiguration information, and controls the servo motor using the reconfigured FPGA. The structure of the first slave controller 102 will be described later with reference to FIG.

  FIG. 4 is a diagram illustrating a process of generating reconfiguration information of the master controller.

  Referring to FIG. 4, the reconfiguration information combination unit 320 of the master controller 101 receives a command from the input device. The reconfiguration information combination unit 320 extracts necessary function information from the reconfiguration library storage unit 330 in accordance with the received command. The reconfiguration library storage unit 330 stores one or more pieces of function information, and the reconfiguration information combination unit 320 stores in advance a list of function information necessary for reconfiguration of the FPGA by each command that can be received from the user. can do. Therefore, when the reconfiguration information combination unit 320 receives an instruction, the reconfiguration information combination unit 320 searches a list of function information that matches the instruction, extracts function information included in the searched list from the reconfiguration library storage unit 330, and receives function information. Are combined to generate reconfiguration information.

  For example, the reconfiguration library storage unit 330 has function information regarding an algorithm performed by the slave controller, function information indicating a function of receiving data from a sensor that performs a sensing function regarding the servo motor, and a function of actually controlling the motor drive. Function information can be stored. The reconfiguration information combination unit 320 receives the instruction 1 from the input device 410 and searches the list of function information stored by matching with the instruction 1. The reconfiguration information combination unit 320 confirms that the function information included in the list of function information is the algorithm 1, the sensor input 1, and the motor drive 2, and extracts each function information from the reconfiguration library storage unit 330. The reconfiguration information combination unit 320 combines the extracted function information to generate reconfiguration information 420 corresponding to the instruction 1. The reconfiguration information combination unit 320 can transmit the reconfiguration information 420 to the entry management unit 340.

  The master controller 101 described above has been described that the function information is extracted from the reconfiguration information combination unit 320 and is combined to generate the reconfiguration information. However, the reconfiguration information combination unit 320 has the reconfiguration information corresponding to each command in advance. Information itself can be stored, and when the reconfiguration information combination unit 320 receives an instruction, reconfiguration information corresponding to the instruction can be transmitted to the entry management unit 340. Therefore, the master controller 101 can extract the reconfiguration information and transmit it to the entry management unit 340 without performing a process of combining separate function information.

  FIG. 5 is a block diagram simply showing functional units constituting the first slave controller. Referring to FIG. 5, the first slave controller 102 includes a control unit 510 and a reconfiguration unit 520.

  The control unit 510 receives a bit stream from the master controller 101 and extracts reconfiguration information from the bit stream. The control unit 510 confirms whether or not the reconfiguration mode information included in the reconfiguration information indicates FPGA reconfiguration. If the reconfiguration mode information does not indicate FPGA reconfiguration, the control unit 510 does not perform the FPGA reconfiguration process. When the reconfiguration mode information indicates FPGA reconfiguration, the control unit 510 reconfigures the gate array structure of the reconfiguration unit 520 based on the reconfiguration information. For example, the reconfiguration information indicates an FPGA structure that receives data from a sensor related to a servo motor from a sensor, calculates the received data using a predetermined algorithm, and controls the servo motor according to the calculated result. In this case, the control unit 510 controls the reconfiguration unit 520 to reconfigure the FPGA according to the reconfiguration information.

  At this time, the control unit 510 described above has decided to perform the reconfiguration process according to the reconfiguration mode information, but according to another embodiment of the present invention, the control unit 510 transmits the bit stream to the slave controller. Whether or not to perform FPGA reconfiguration can be determined based on whether or not corresponding reconfiguration information is included.

  The reconfiguration unit 520 includes a static reconfiguration module 523 configured with an FPGA, a first dynamic reconfiguration module 526, and a second dynamic reconfiguration module 529. The static reconfiguration module 523 is a module for controlling the operation of the servo motor, and is based on a signal received from the dynamic reconfiguration module, that is, the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529. The servo motor can be controlled to perform rotational acceleration, reverse rotational acceleration, stop, and the like. Since the static reconfiguration module 523 directly controls the operation of the servo motor, reconfiguration is not performed while the first slave controller 102 is controlling the servo motor. However, the static reconfiguration module 523 can perform reconfiguration when the servo motor is replaced with another type of device. More specifically, when the user commands control of another replaced model device via the input device, the master controller 101 reconfigures the static reconfiguration unit 523 so as to correspond to the command. A bit stream including reconfiguration information indicating the configuration can be transmitted to the control unit 510 of the first slave controller 102, for example. Then, the control unit 510 reconfigures the gate array structure of the static reconfiguration unit 523 based on the reconfiguration information included in the bitstream so that the replaced device of another model can be controlled.

  The first dynamic reconfiguration module 526 reconfigures the FPGA independently of the static reconfiguration module 523 under the control of the control unit 510. In other words, the first dynamic reconfiguration module 526 is reconfigured regardless of whether the static reconfiguration module 523 is currently controlling the servomotor and the reconfigured state.

  For example, the dynamic reconfiguration module 526. When the rotation speed of the servo motor is received from the sensor that detects the rotation speed of the servo motor and the rotation speed is equal to or higher than the specified speed, the calculation is performed for the rotation speed of the servo motor according to a predetermined algorithm. It can be carried out. The dynamic reconfiguration module 323 can transmit the control value that is the result of the operation to the static reconfiguration module 523. Then, the static reconfiguration module 323 can adjust the rotation speed at a speed according to the received control value.

  In another example of the reconfiguration process of the first dynamic reconfiguration module 526, data is sequentially received from the first sensor, the second sensor, and the third sensor to control the servo motor. It is assumed that the master controller 101 generates a bit stream related to this. In this case, the control unit 510 can receive the first bit stream from the master controller 101. At this time, the first bit stream includes reconstruction information indicating an FPGA structure that receives data from the first sensor and performs an operation through a first algorithm designated in advance. Next, the control unit 510. The first dynamic reconfiguration module 526 is controlled to reconfigure the FPGA structure according to the reconfiguration information. At this time, the first static reconfiguration module 523 may continue the servo motor control process. After completing the reconfiguration, the dynamic reconfiguration module 526 receives data from the first sensor according to the FPGA structure, and calculates a control value that is a value calculated through the first algorithm. The dynamic reconfiguration module 526 transmits the control value to the static reconfiguration module 523. The static reconfiguration module 523 continues to control the servo motor according to the control value.

  Thereafter, the controller 510 can receive the second bit stream from the master controller 101. At this time, the second bit stream includes reconfiguration information indicating an FPGA structure that receives data from the second sensor and performs an operation through the first algorithm. Next, the first dynamic reconfiguration module 526 is reconfigured into an FPGA structure that receives data from the second sensor through the above-described process, and performs an operation. Further, the static reconfiguration module 523 continues to control the servo motor with the control value.

  Thereafter, the control unit 510 can receive the third bit stream from the master controller 101. At this time, the third bit stream includes reconfiguration information indicating an FPGA structure that receives data from the third sensor and performs an operation through the first algorithm. Next, the first dynamic reconfiguration module 526 is reconfigured into an FPGA structure that receives data from the third sensor through the above-described process, and performs an operation. Further, the static reconfiguration module 523 continues to control the servo motor with the control value.

  Therefore, it is possible to perform a function of sequentially receiving data from the first sensor, the second sensor, and the third sensor.

  When it is necessary to perform a process of sequentially receiving data from each sensor, the conventional motion controller must include all modules that receive data from each sensor, and thus the circuit of the motion controller is configured. The size had to increase. The first slave controller 510 uses one of the dynamic reconfiguration modules 526 from each sensor to control the servo motor while maintaining control of the servo motor using the static reconfiguration module 523. Data can be received sequentially. Therefore, the control system described above can be realized with a relatively small size as compared with the conventional operation controller.

  At this time, the functions of the static reconfiguration module 523 and the first dynamic reconfiguration module 526 described above are merely examples, and are not limited to the functions described above. That is, the functions of the static reconfiguration module 523 and the first dynamic reconfiguration module 526 may be changed according to the bitstream reconfiguration information received by the control unit 510.

  The second dynamic reconfiguration module 529 is a module having the same configuration as the first dynamic reconfiguration module 526, and is reconfigured in the same manner as the above-described reconfiguration process of the first dynamic reconfiguration module 526. Can do.

  According to another embodiment of the present invention, the controller 510 determines the FPGA structure of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 according to the capacity of the reconfiguration information extracted from the bitstream. Can be reconfigured.

  For example, assuming that the first dynamic reconfiguration module 526 is currently operating, the controller 510 determines that the second dynamic reconfiguration that is not currently operating when the capacity of the reconfiguration information is greater than or equal to the specified capacity. The FPGA of the configuration module 529 is reconfigured with the reconfiguration information. After the reconfiguration is completed, the second dynamic reconfiguration module 529 transmits a reconfiguration completion signal notifying that the reconfiguration is completed to the control unit 510. When receiving the reconfiguration completion signal, the controller 510 transmits an operation stop request for requesting the first dynamic reconfiguration module 526 currently operating to stop the operation. The first dynamic reconfiguration module 526 stops the operation in response to the operation stop request. At this time, the second dynamic reconfiguration module 529 in which the FPGA structure is reconfigured by the reconfiguration information performs an operation, and the operation result is transmitted to the static reconfiguration module 523. The static reconfiguration module 423 can control the servo motor upon receiving the calculation result input from the second dynamic reconfiguration module 526.

  Although it has been described that the control unit 510 described above determines that the capacity of the reconfiguration information of the bitstream received from the master controller 101 is equal to or greater than the specified value, the entry management of the master controller 101 is determined according to the implementation method. The unit 340 can determine that the capacity of the reconstruction information is equal to or greater than the specified value, and can insert information based on this capacity into the header of the reconstruction information. At this time, the control unit 510 can confirm the information from the header of the reconfiguration information and perform the reconfiguration process of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529.

  FIG. 6 is a flowchart showing a process in which the control system controls the operation of the servo motor.

  Referring to FIG. 6, in step 610, the master controller 101 receives a command from the input device.

  In step 620, the master controller 101 generates a bit stream for controlling the servo motor according to the command received from step 610. At this time, the master controller 101 generates a bit stream including reconfiguration information indicating the FPGA structure of the slave controller required to control the servo motor according to the command. The master controller 101 transmits the generated bit stream to the first slave controller.

  In step 630, the first slave controller 102 extracts reconfiguration information from the received bitstream. At this time, the first slave controller can transmit the bit stream to the second slave controller 103 after extracting the reconfiguration information. The second slave controller 103 that has received the bitstream can perform the same process as the operation of the first slave controller 102 after step 630.

  In step 640, the first slave controller 102 reconfigures the structure of the reconfiguration unit, which is an FPGA module, based on the reconfiguration information. At this time, when the first slave controller 102 reconfigures the first dynamic reconfiguration module 526 that currently controls the servo motor among the plurality of dynamic reconfiguration modules based on the reconfiguration information, When the controller 102 has to interrupt the control of the servo motor, the configuration of the second dynamic reconfiguration module 529 is reconfigured. When the reconfiguration of the second dynamic reconfiguration module 529 is completed, the first slave controller 102 interrupts the operation of the first dynamic reconfiguration module 526, and the second dynamic reconfiguration module 529 and the static reconfiguration module 523 can be used to control the servo motor. Further, the first slave controller 102 can independently reconfigure the static reconfiguration module 523, the first dynamic reconfiguration module 526, and the second dynamic reconfiguration module 529 based on the reconfiguration information. That is, when the reconfiguration information indicates only the structure for the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529, the first slave controller 102 determines that the static reconfiguration module 523 is a servo motor. The first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 can be reconfigured while controlling.

  In step 650, the first slave controller 102 controls the operation of the servo motor using the reconfiguration unit reconfigured from step 640.

  Although the above-described control system has been described as controlling a servo motor, it is apparent that the reconfiguration information can be configured to be suitable for other devices and devices other than the servo motor can be controlled.

  In the foregoing, the embodiments of the present invention have been mainly described. Many embodiments other than those described above are within the scope of the claims of the present invention. Those skilled in the art to which the present invention pertains can understand that the present invention can be realized in a modified form without departing from the essential characteristics of the present invention. Accordingly, the disclosed embodiments are to be considered in an illustrative rather than a restrictive perspective. The scope of the present invention is shown not by the above description but by the claims, and any difference within the equivalent scope should be construed as being included in the present invention.

  The control system and method according to the embodiment of the present invention can flexibly control various devices by reconfiguring the gate array structure according to user input.

  In the control system and method according to the embodiment of the present invention, the size of the control device can be reduced by reconfiguring the structure of the gate array and controlling the device using the reconfigured gate array. it can.

Claims (8)

A master controller for generating a bitstream including reconfiguration information according to a user's instruction;
A first slave controller,
The first slave controller is
A first dynamic reconfiguration module which is a gate array (FPGA: Field Programmable Gate Array) that is reconfigured by the reconfiguration information and calculates a control value;
A static reconfiguration module that is a gate array that controls the operation of the target device according to the control value;
A controller configured to reconfigure one or more of the first dynamic reconfiguration module and the static reconfiguration module with the reconfiguration information;
Only including,
The first slave controller is
A second dynamic reconfiguration module that is a gate array that is reconfigured by the reconfiguration information and calculates a control value;
The controller is
If the capacity of the reconfiguration information is greater than or equal to a specified value, control is performed to reconfigure the second dynamic reconfiguration module according to the reconfiguration information, and reconfiguration of the second dynamic reconfiguration module is performed. Maintaining operation of the first dynamic reconfiguration module until completion, a reconfigurable control system during operation. The operation of claim 1 , wherein the controller reconfigures the gate array structure of the first and second dynamic reconfiguration modules independently of the operation of the static reconfiguration module. Reconfigurable control system. The controller is
The control system capable of being reconfigured during operation according to claim 2 , wherein when the reconfiguration of the second dynamic reconfiguration module is completed, the operation of the first dynamic reconfiguration module is stopped. A master controller for generating a bitstream including reconfiguration information according to a user's instruction;
A first slave controller,
The first slave controller is
A first dynamic reconfiguration module which is a gate array (FPGA: Field Programmable Gate Array) that is reconfigured by the reconfiguration information and calculates a control value;
A static reconfiguration module that is a gate array that controls the operation of the target device according to the control value;
A controller configured to reconfigure one or more of the first dynamic reconfiguration module and the static reconfiguration module with the reconfiguration information;
Including
The master controller is
A reconfiguration library storage unit that stores function information indicating a connection relationship between the gates of the first dynamic reconfiguration module or the static reconfiguration module;
Reconstructing information combining unit that extracts the function information according to the instruction and generates the reconstructing information by combining the extracted function information;
An entry management unit for generating a bitstream including the reconstruction information;
Dynamic Sakuchu reconfigurable control systems that comprising a. A slave communication unit for transmitting the bit stream to the first slave controller;
When the entry management unit generates reconfiguration time information that is a time point at which the bit stream is transmitted by the command, the slave communication unit is configured to receive a time point determined by the reconfiguration time information or the bit 5. The reconfigurable control system according to claim 4 , wherein the bit stream is transmitted to the first slave controller when a stream is generated. A master controller for generating a bitstream including reconfiguration information according to a user's instruction;
A first slave controller,
The first slave controller is
A first dynamic reconfiguration module which is a gate array (FPGA: Field Programmable Gate Array) that is reconfigured by the reconfiguration information and calculates a control value;
A static reconfiguration module that is a gate array that controls the operation of the target device according to the control value;
A controller configured to reconfigure one or more of the first dynamic reconfiguration module and the static reconfiguration module with the reconfiguration information;
A second slave controller that is a controller having the same configuration as the first slave controller;
Including
The master controller, the first slave controller, and the second slave controller of the reconfigurable control the dynamic Sakuchu you and generating a bitstream including the reconfiguration information corresponding to each system. The control system capable of being reconfigured during operation according to claim 6 , wherein the master controller, the first slave controller, and the second slave controller are connected by a network having a double ring structure. . When the target device is changed,
The control system capable of being reconfigured during operation according to claim 1, wherein the static reconfiguration module is a gate array reconfigured according to the reconfiguration information.

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