JP5375021B2 - Clock recovery system and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock reproducing system and method which generate a stabler reproducing clock by synchronizing a clock for reproducing received data with a transmission side in a communication system. <P>SOLUTION: A receiving part 12 of the clock reproducing system reproduces a stable clock 154 by: allowing a time stamp extracting part 34 to extract a video image system time stamp 134 and network system time stamp 136 in a received packet 132 so as to store the same in a memory 36; calculating a network clock 146 of a receiving side by a counter 38 so as to obtain a network system time stamp 148 of the receiving side; allowing a frequency deviation detecting part 40 to detect frequency deviation 150 based on the time stamps 136 and 148; allowing a read timing generation part 42 to generate a read timing signal 140 in response to the frequency deviation 150; and controlling the timing for reading the video image system time stamp 142 from the memory 36. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a clock recovery system and method for synchronizing a clock for reproducing data on the receiving side with the transmitting side when transmitting a communication signal indicating data such as video or audio in the communication system.

  Conventionally, when a communication signal indicating data such as predetermined video or audio is transmitted in a communication system, it is necessary on the receiving side to synchronize the clock for reproducing the data with the clock on the transmitting side.

  For example, as shown in Non-Patent Document 1, in the MPEG (Moving Picture Experts Group) -2 system recommended by the International Telecommunication Union (ITU), when transmitting a video signal, an audio signal, or data, It is standardized to integrate and synchronize each signal. In this system, for example, when a TV signal is broadcast or communicated and transmitted in real time, an MPEG-2 transport stream (TS) defined here is generally used.

  As described above, when a video signal is transmitted in MPEG-2 TS and used for broadcasting or communication, in order to reproduce the signal continuously and stably on the receiving side, a clock related to the reproduction of the video signal on the receiving side is used. It is necessary to synchronize the signal with the clock signal on the transmission side. According to the MPEG-2 TS regulations, time information called PCR (Program Clock Reference) can be multiplexed and transmitted on a video signal, and a clock synchronized with the PCR can be reproduced on the receiving side.

  Non-patent documents 2 and 3 stipulate that HDTV (High Definition Television) signals are compressed and transmitted via an IP network such as the Internet. When transmitting a video signal using a communication line, it is necessary to maintain a high-quality signal, especially in broadcasting signal transmission, so it is necessary to reproduce a clock synchronized with the transmission side on the reception side. Some communication systems transmit signals together with clock information on the transmission side.

  For example, in Non-Patent Document 2, 148.5 MHz clock information is extracted from a digital video signal (SDI: Serial Digital Interface) to be transmitted, the clock information is transmitted as an IP packet together with the video signal, and synchronized on the receiving side. It is described that the clock is regenerated.

  In these communication systems, even if the clock information related to the video signal is transmitted via a network such as the Internet, if the network clock is asynchronous between the transmission side and the reception side, the clock frequency is accurately set on the reception side. It becomes difficult to reproduce.

  On the other hand, in Non-Patent Document 4, the transmission side device and the reception side device transmit and receive signals via a predetermined network, and input a common reference clock using ISDN or a radio timepiece. Has been used to achieve stable clock recovery.

Furthermore, the source clock recovery circuit described in Patent Document 1 generates a video time stamp on the transmission side based on the network clock, and regenerates the clock based on the time stamp on the reception side. On the side, the received data is accumulated in the data buffer, a threshold value is determined according to the occupation amount of the data buffer, and the generation interval of the reference pulse of the phase locked loop for regenerating the source clock is changed by this threshold value. Therefore, even when the network clock is asynchronous between the transmission side and the reception side, the clock synchronized with the input signal can be reproduced.
JP-A-6-303254 ISO / IEC 13818-1: 2000 (E), Information technology-Generic coding of moving pictures and associated audio information: Systems RFC (Request For Comments) 3497 (RTP Payload Format for Society of Motion Picture and Television Engineers (SMPTE) 292M Video) Internet <URL: http://www.ietf.org/rfc/rfc3497.txt> Pro-MPEG Code of Practice # 4 release1, July 2004 (Transmission of High Bit Rate Studio Streams over IP Networks) HDTV MPEG-2 High Multiplex Transmission Technology, NTT Technical Journal 2005.7, p.43-46

  However, in the method shown in Non-Patent Document 4, a stable clock can be recovered. However, since it is necessary to input a common reference clock to the transmission side and the reception side, reception and processing of the reception clock are required. It is necessary to provide a special additional mechanism and circuit.

  Further, in the circuit described in Patent Document 1, it is not necessary to input a common clock, but the remaining amount of the data buffer is monitored and the threshold value is controlled to correct the clock regeneration control voltage. Furthermore, since no special correction is performed within this threshold value range, an accurate frequency deviation cannot be detected, and a clock having sufficient stability cannot be reproduced.

  The present invention eliminates the disadvantages of the prior art, and can regenerate a stable clock with a simpler configuration regardless of whether the network clock is synchronized between the transmission side and the reception side. It is an object to provide a system and method.

  In order to solve the above-described problems, the present invention receives a digital communication signal transmitted from a transmission unit via a predetermined network, and receives the digital communication signal that is synchronized with the digital communication signal by the reception unit. In this clock recovery system, the transmission unit generates a data time stamp based on a recovered clock of data transmitted by the digital communication signal, and generates a first network time stamp based on a network clock on the transmitting side. The data time stamp is added to the digital communication signal as time information, the first network time stamp is added to the digital communication signal as frequency information, and the receiving unit receives the data time from the received digital communication signal. Stamp and first network time star According to the first network time stamp and the second network time stamp, the time stamp extracting means for extracting the time stamp, the time stamp generating means for generating the second network time stamp based on the network clock on the receiving side, It comprises frequency deviation detecting means for detecting the frequency deviation of the network clock on the transmitting side and the receiving side, and read timing generating means for reading out this data time stamp based on this frequency deviation.

  In addition, the receiving unit receives a digital communication signal transmitted from the transmitting unit via a predetermined network, and the receiving unit reproduces a clock synchronized with the digital communication signal. A data time stamp is generated based on a reproduction clock of data transmitted by the digital communication signal, a first network time stamp is generated based on a network clock on the transmission side, and the data time stamp is used as time information to generate the digital time stamp. A transmission step of adding the first network time stamp to the digital communication signal as frequency information, and adding the first network time stamp to the digital communication signal; and receiving the digital communication signal from the transmission unit and synchronizing to the digital communication signal Including a receiving step for regenerating the received clock. The time stamp extracting step for extracting the data time stamp and the first network time stamp from the digital communication signal, and the time stamp generating step for generating the second network time stamp based on the network clock on the receiving side, A frequency deviation detecting step for detecting a frequency deviation of the network clock on the transmitting side and the receiving side according to the first network time stamp and the second network time stamp, and reading out the data time stamp based on the frequency deviation And a read timing generation step, wherein a reproduction clock is generated based on the data time stamp read by the read timing generation step.

  According to the clock recovery system of the present invention, when a transmission unit transmits a packet indicating a video signal, a video system time stamp and a network system time stamp which is frequency information are added to the packet and transmitted. When receiving such a packet, extract the time stamp from this packet and store it in the time stamp storage memory while counting the network clock on the receiving side and the counter value of the network time stamp on the transmitting side and the network clock on the receiving side By detecting the frequency deviation based on the frequency deviation and controlling the timing to read the time stamp from the time stamp storage memory according to this frequency deviation, it is possible to absorb problems such as packet fluctuations and jitter generated on the transmission side or transmission path. And play a stable clock. That.

  As described above, in the clock recovery system of the present invention, even when the network clocks on the transmission side and the reception side are asynchronous, a common reference clock is input to the transmission side and the reception side, and equipment for the reference clock is provided. The clock frequency of the transmitted packet can be accurately reproduced on the receiving side.

  In particular, in the clock recovery system according to the present invention, the receiving unit detects a difference between the network time stamp on the transmission side and the network time stamp on the reception side, accumulates the difference value, and averages the difference value. By applying low-pass filter processing, etc., it is possible to smooth the jitter and fluctuations of the packet reception timing and extract the frequency deviation component, so the frequency deviation of the network clock between the transmission side and the reception side can be accurately It can be detected, and a more stable clock can be regenerated by periodically correcting the regenerated clock with a phase synchronization circuit.

  Next, an embodiment of a clock recovery system according to the present invention will be described in detail with reference to the accompanying drawings. For example, the clock recovery system includes a transmission unit 12 that transmits a digital communication signal and a reception unit 32 that receives the digital communication signal transmitted from the transmission unit 12.

  As shown in FIG. 1, the transmission unit 12 performs clock extraction on the communication signal to be transmitted by the equalizer unit 14, counts the extracted clock by the video system clock counter 16, and displays video according to the count value. The system time stamp generation unit 18 generates a video system time stamp, and the network clock counter 20 counts the network clock on the transmission side, and the network system time stamp generation unit 22 generates a network system time stamp according to the count value. The IP packet generator 24 generates an IP packet based on the time stamp and the communication signal, and transmits the IP packet to a predetermined network 26.

  Further, as shown in FIG. 2, the receiving unit 32 receives an IP packet from a predetermined network 26, and the time stamp extracting unit 34 extracts the time stamp from the IP packet and stores it in the time stamp storage memory 36. In addition, the network clock on the receiving side is counted by the network system clock counter 38, and the frequency deviation is detected by the frequency deviation detecting unit 40 based on these time stamp and count value. The reception unit controls the timing at which the read timing generation unit 42 reads the time stamp from the memory 36 according to the frequency deviation, and adjusts the output of the time stamp read from the memory 36 in this way by the time stamp register 44. To the phase synchronization circuit 46.

  In the present embodiment, the transmission unit 12 includes an equalizer unit 14, a video system clock counter 16, a video system time stamp generation unit 18, a network system clock counter 20, a network system time stamp generation unit 22, and an IP packet generation unit 24. However, any other configuration may be used as long as it transmits an IP packet having a video time stamp and a network time stamp.

  For example, the transmission unit 12 may be configured to transmit an SDI (Serial Digital Interface) signal, which is a digitized video signal, as an IP packet as the communication signal 102 to be transmitted.

  The equalizer unit 14 performs an equalizer process, a serial / parallel conversion process, and a clock extraction process on the communication signal 102, and supplies the parallelized communication signal 104 to the IP packet generation unit 24 after these processes. The extracted video system clock signal 106 is supplied to the video system clock counter 16. The equalizer unit 14 may be configured by a commercially available integrated circuit (IC). Further, these processes in the equalizer unit 14 may be configured as independent units.

  The video system clock counter 16 generates time information from the input clock. In this embodiment, the video system clock counter 16 counts the video system parallel clock signal 106 obtained by the equalizer unit 14 and outputs the count value 108 to the video system. This is supplied to the video time stamp generator 18 as clock information.

  The video time stamp generation unit 18 is provided to superimpose time information on an IP packet. In this embodiment, the IP packet generation unit 24 uses the count value 108 of the video clock counter 16 as the video time stamp 110. For example, the video time stamp 110 is output to the IP packet generation unit 24 in accordance with the network clock signal 112.

  The network system clock counter 20 generates network frequency information on the transmission side. In this embodiment, the network system clock counter 20 counts the network system clock signal 112 which is a reference clock signal according to the network on the transmission side, and the count value 114 is supplied to the network time stamp generator 22 as network clock information.

  The network system time stamp generation unit 22 is provided to superimpose the frequency information of the transmission side network on the IP packet. In this embodiment, the network system clock counter 20 count value 114 is used as the network system time stamp 116 as an IP address. For example, a network time stamp 116 is output to the IP packet generation unit 24 in accordance with the network clock signal 112.

  The IP packet generation unit 24 generates an IP packet 118 corresponding to the communication signal 102 to be transmitted by the transmission unit 12 and transmits the IP packet 118 toward the predetermined network 26. The IP packet 118 is generated by superimposing the frequency information. For example, the IP time stamp 110 and the network time stamp 116 are added to the communication signal 104 to generate the IP packet 118.

  In the transmission unit 12 of this embodiment, the video signal is used as data to be transmitted, the video system clock counter 16 generates a video system time stamp based on the reproduction clock of the video signal, and the IP packet generation unit 24 Although the system time stamp is added to the IP packet, the transmission unit 12 of the present invention generates a data time stamp based on the reproduction clock of other data, and the IP packet generation unit 24 adds the data time stamp to the IP packet. It may be added to the packet and transmitted.

  In the present embodiment, the reception unit 32 includes a time stamp extraction unit 34, a time stamp storage memory 36, a network clock counter 38, a frequency deviation detection unit 40, a read timing generation unit 42, a time stamp register 44, and a phase synchronization circuit 46. However, as long as it controls the supply timing of the video time stamp in accordance with the frequency deviation of the network time stamp on the transmission side and the reception side, it may be realized by any other configuration. .

  In this embodiment, the configuration as shown in FIG. 2 for reproducing the clock will be described with respect to the receiving unit 32, and the video signal processing will be omitted, but it can be applied to any receiving unit having any video signal processing.

  The time stamp extracting unit 34 extracts the video time stamp 134 and the network time stamp 136 from the IP packet 132 received by the receiving unit 32 via the predetermined network 26, and stores the video time stamp 134 as a time stamp. Then, the network time stamp 136 is supplied to the time stamp storage memory 36 and the frequency deviation detector 40.

  In addition, the time stamp extraction unit 34 detects an enable signal 138 for controlling writing of the time stamp in the memory 36 from the IP packet 132 and supplies it to the time stamp storage memory 36 and the frequency deviation detection unit 40. For example, the extraction unit 34 may detect the time stamp position based on the header of the IP packet 132 and extract the time stamp values 134 and 136, and is enabled from the time stamp position information obtained in the processing. A signal 138 can be generated.

  The time stamp storage memory 36 stores the transmission-side video time stamp 134 and network time stamp 136 extracted by the time stamp extraction unit 34. The storage memory 36 may be one that writes and reads time stamps in FIFO format, for example.

  The time stamp storage memory 36 of the present embodiment writes the time stamps 134 and 136 in response to the enable signal 138 from the time stamp extraction unit 34, and the video system in accordance with the read timing signal 140 from the read timing generation unit 42. The time stamp 142 and the network time stamp 144 may be read and supplied to the time stamp register 44 and the read timing generation unit 42, respectively.

  The network system clock counter 38 generates network frequency information on the receiving side. In this embodiment, the network system clock counter 38 counts the network system clock signal 146, which is a reference clock signal according to the network on the receiving side. 148 is supplied to the frequency deviation detector 40 as a network time stamp on the receiving side. The counter 38 may start counting the clock signal 146 in response to the start of reception of the IP packet 132 by the receiving unit 32.

  The frequency deviation detection unit 40 detects a frequency deviation based on the network time stamps 136 and 148 on the transmission side and the reception side, and supplies a frequency deviation value 150 used for correcting the read timing signal 140 to the read timing generation unit 42. Is. Although the network clocks on the transmission side and the reception side have substantially the same frequency, they may not be completely synchronized. As shown in FIG. 3, the network time stamp 136 on the transmission side and the network system clock counter value on the reception side Since fluctuations may occur between the time stamps 148, the frequency deviation detector 40 averages and removes fluctuations between these time stamps, and detects frequency deviations.

  The detection unit 40 of the present embodiment detects, for example, the arrival timings of the network time stamps 136 and 148 on the transmission side and the reception side according to the enable signal 138, and compares these time stamps 136 and 148 to obtain a difference value. And the difference value is accumulated, and the difference value is averaged or subjected to low-pass filter processing to smooth the jitter and fluctuation of the packet reception timing and extract the frequency deviation component. .

  For example, the detection unit 40 calculates the period deviation ΔT based on the time stamps 136 and 148 on the assumption that the frequency deviation Δf is calculated as 1 / ΔT using the period deviation ΔT. Each time the time stamps 136 and 148 are input, the detection unit 40 detects a period deviation ΔT (n) including fluctuations in the transmission network time stamp acquisition interval, and Δ detected during a predetermined unit period. Periodic deviation ΔT can be obtained by averaging T (n) and removing fluctuations.

  By multiplying the period deviation ΔT by the frequency of the network clock 146 on the receiving side, the network clock deviation N per unit period can be calculated, and when the number of packets per unit period is M, The interval at which the read timing is shifted by one clock is every M / N packet. For example, the frequency deviation detection unit 40 supplies information indicating whether or not to shift the read timing to the read timing generation unit 42 as the frequency deviation value 150 in accordance with the input of the enable signal 138, and in particular, shift of the read timing. May be issued at every shift interval M / N.

  Further, the frequency deviation detecting unit 40 can issue any one of the period deviation ΔT, the network clock deviation N, and the shift interval M / N as the frequency deviation value 150. In this case, the enable signal is issued by issuing the deviation value 150. The input of 138 may be indicated to the read timing generation unit.

  The read timing generation unit 42 generates a read timing signal 140 for controlling the timing for reading the network timestamp 144 on the transmission side from the time stamp storage memory 36. From the time stamp storage memory 36 according to the timing signal 140, The video system time stamp 142 can be read out and input to the time stamp register 44, and the video system time stamp 152 can be read out from the time stamp register 44 and input to the phase synchronization circuit 46.

  In this embodiment, the read timing generation unit 42 may generate a read timing signal 140 indicating the timing at which the transmission-side network system time stamp 144 is synchronized with the reception-side network clock 148. According to the frequency deviation value 150, the read timing can be periodically controlled to adjust the frequency deviation component of the read timing signal 140.

  For example, the generation unit 42 obtains the shift interval M / N of the transmission side network clock based on the frequency deviation value 150, and delays and stops the periodic read timing of the time stamp 142 for each shift interval M / N. Alternatively, by generating the timing signal 140 early, it is possible to correct a shift due to a frequency deviation between the transmission side and the reception side.

  In addition, the read timing generation unit 42 uses the timing signal 140 to store the time stamp one stage before the video time stamp stored at the head of the time stamp storage memory 36 in accordance with the timing signal 140, for example. And may control the register 44.

  For example, the read timing generation unit 42 causes the phase comparator 46 to output the video system time stamp 152 already held in the time stamp register 44 and the video system time stamp 142 stored at the head of the time stamp storage memory 36. The memory 36 and the register 44 can be controlled by the timing signal 140 so that the register 44 can read the data. Further, the generation unit 42 controls the register 44 by the timing signal 140 so that the video time stamp 152 of the same time as the time stamp 142 corresponding to the timing signal 140 is output from the register 44 to the phase comparator 46. Can do.

  Further, when the read timing generation unit 42 of the present embodiment receives the frequency deviation value 150 instructing a shift when the network system time stamp 144 has not been received at the time of activation or reception start, the network system on the transmission side Regardless of the time stamp 144, the network clock 148 on the receiving side, and the frequency deviation value 150, the network time stamp 144 may be forcibly received from the time stamp storage memory 36 by forcibly issuing the timing signal 140.

  The time stamp register 44 temporarily holds the video time stamp 142 read from the time stamp storage memory 36.

  The time stamp register 44 of this embodiment is already held in accordance with the timing at which the transmission-side network system time stamp 144 is synchronized with the network clock 148 on the reception side, that is, the read timing signal 140 by the read timing generation unit 42. The current time stamp 152 is output to the phase comparator 46, and the video time stamp 142 is read from the memory 36 and held. For example, the register 44 can output the video time stamp 142 of the same time as the time stamp corresponding to the timing signal 140 to the phase comparator 46 in response to the timing signal 140.

  As shown in FIG. 4, a phase locked loop (PLL) circuit 46 inputs a video time stamp 152 from the time stamp register 44 to a phase comparator 48, and outputs the comparison result by the comparator 48 as D / A converter 50 converts the signal into an analog signal, and an oscillator 52 oscillates an electric signal having a frequency corresponding to the analog signal to generate a reproduction clock 154. The counter 54 counts the electric signal, The count value is used as a comparison target in the comparator 48.

  The phase comparator 48 compares the phase of the video time stamp 152 and the count value 156 of the counter 54 to obtain the phase difference 158. For example, the phase comparator 48 subtracts the video time stamp 152 and the count value 156, and The subtraction result is supplied as a phase difference 158 to the D / A converter 50.

  The D / A converter 50 converts the phase difference 158 into a voltage value 160 and supplies it to the oscillator 52. In this embodiment, the converter 50 converts the phase difference 158 of the digital signal into the voltage value 160 of the analog signal. However, as long as the converter 50 can obtain a voltage value 160 suitable for the oscillator 52 according to the phase difference 158. Good.

  The oscillator 52 is a variable frequency oscillator that outputs a frequency signal 154 indicating an oscillation frequency corresponding to the input voltage value 160, and the frequency signal 154 from the oscillator 52 becomes a reproduction clock signal of the receiving unit 32. The oscillator 52 may be, for example, a crystal oscillator such as a voltage controlled crystal oscillator (VCXO).

  The counter 54 is a counter that counts the frequency signal 154 output from the oscillator 52. For example, the counter 54 may divide and count the frequency signal 154 and supply the count value 156 to the phase comparator 48. In the phase synchronization circuit 46 using the frequency dividing counter 54, the video time stamp 152 and the frequency signal count value 156 obtained by dividing the reproduction clock signal 154 are synchronized, that is, the reproduction clock signal 154 is a video time stamp. The frequency is controlled by multiplying 152 by the frequency division number.

  The phase synchronization circuit 46 of the present embodiment is controlled so that the received video system time stamp 152 and the count value 156 corresponding to the oscillation signal 154 have the same phase. Then, by subtracting the count value 156 and controlling the frequency of the oscillation signal 154 in the oscillator 52 so that the subtraction result 158 becomes 0, the oscillation signal 154 that is the video system clock on the receiving side, that is, the reproduction clock signal 154 Are reproduced so as to be synchronized with the video signal on the transmission side.

  Next, an operation example related to IP packet transmission by the transmission unit 12 of the clock recovery system in the present embodiment will be described.

  In the present embodiment, an SDI signal of a digital video signal is applied as the communication signal 102 to be transmitted by the transmitter 12, and an HD-SDI (High Definition Serial Digital Interface) which is an SDI signal of HDTV (High Definition Television), for example. ) Signal can be applied.

  This HD-SDI signal is a 1.485 / 1.001 GHz or 1.485 GHz serial signal. For example, a 1.485 / 1.001 GHz signal is generally adopted in digital television broadcasting. Further, the HD-SDI signal is a video signal composed of a luminance signal and a color difference signal, and each 10 bits may be digitized at 74.25 / 1.001 MHz and multiplexed into one and serialized.

  In this embodiment, the network system clock signal 112 is input to each unit of the transmission unit 12 as a reference clock signal on the transmission side, and for example, IP packet transmission is performed using a plurality of Ethernet 1000BASE-T as communication lines. A network clock signal 112 having a clock rate of 125 MHz is used.

  In the transmission unit 12 of the present embodiment, first, the HD-SDI signal 102 to be transmitted is input to the equalizer unit 14, and equalization processing, serial / parallel conversion, and clock extraction are performed. As a result, a 20-bit video signal 104 composed of a luminance signal and a color difference signal is obtained as a parallel communication signal 104 and supplied to the IP packet generator 24, and a 148.5 / 1.001 MHz clock signal 106 is extracted. It is supplied to the video system clock counter 16.

  The clock signal 106 is counted by the counter 16, and as a result, a 32-bit counter value 108 is obtained and supplied to the video time stamp generator 18. In the generation unit 18, the counter value 108 is supplied to the IP packet generation unit 24 as the video system time stamp 110 in accordance with the network system clock signal 112.

  In this embodiment, the network system clock signal 112 is counted by the network system clock counter 20 and the count value 114 is supplied to the network system time stamp generator 22. In the generation unit 22, similarly to the generation unit 18, the counter value 114 is supplied to the IP packet generation unit 24 as the network system time stamp 116 according to the network system clock signal 112.

  The IP packet generator 24 generates an IP packet 118 based on the video signal 104. Further, as shown in FIG. 5, a video time stamp 110 and a network time stamp 116 are added to the IP packet 118. Is multiplexed.

  As described above, according to the transmission unit 12 of the present embodiment, even when the transmission side and the reception side network clocks are asynchronous in transmission using a communication line such as Ethernet, the frequency information of the transmission side network clock is packetized. Therefore, on the receiving side, it is possible to synchronize the clock between them using the frequency information of the network clock on the transmitting side.

  For example, when transmitting a packet by the ProMPEG method, the transmission unit 12 can multiplex network time stamps by expanding the header area using an RTP extension header and a header length, as shown in FIG.

  Next, an operation related to clock recovery by the receiving unit 32 of the clock recovery system in the present embodiment will be described with reference to the timing chart of FIG.

  In the present embodiment, each unit in the receiving unit 32 operates according to the network system clock signal 146 which is a reference clock signal on the receiving side, and the IP packet 132 transmitted from the transmitting unit 12 is received via the predetermined network 26. Then, the data is input to the time stamp extraction unit 34.

  When the IP packet 132 is referred to in the time stamp extraction unit 34, the video time stamp 134, the network time stamp 136, and the write enable signal 138 are extracted and sent to the time stamp storage memory 36. The extracted network time stamp 136 and enable signal 138 are also supplied to the frequency deviation detector 40.

  In this time stamp extraction unit 34, for example, as shown in FIG. 6, video time stamps 134 indicating VT1, VT2, VT3 and VT4 are extracted at times t202, t204, t206 and t208, respectively, and nt1, nt2 , Nt3 and nt4 are extracted, and an enable signal 138 indicating an enable state at a low level is extracted at each time.

  In the time stamp storage memory 36, the time stamps 134 and 136 are stored in response to the write enable signal 138, for example, when the enable signal 138 is at a low level as shown in FIG.

  Meanwhile, in the receiving unit 32, the network clock signal 146 is counted by the network clock counter 38, and the count value 148 is supplied to the frequency deviation detecting unit 40 and the read timing generating unit 42 as needed. The count value 148 becomes nc1, nc2, nc3, and nc4 at times t202, t204, t206, and t208, respectively, for example, as shown in FIG.

  Further, since the count value 148 indicates a network time stamp on the receiving side, the frequency deviation detecting unit 40 inputs the network time stamp 136 on the transmitting side and the network time stamp 148 on the receiving side. It will be.

  Here, the frequency deviation detection unit 40 detects the frequency deviation between the network time stamps 136 and 148 on the transmission side and the reception side, and supplies the frequency deviation value 150 to the read timing generation unit 42.

  For example, in the frequency deviation detection unit 40, a shift instruction indicating whether or not to shift the read timing is issued as the frequency deviation value 150 and supplied to the read timing generation unit 42. In order to detect the packet interval for shifting the read timing by one clock, the detection unit 40 detects the period deviation ΔT, calculates the network clock deviation N per unit period, and calculates the number M of packets per unit period. To detect the shift interval M / N. In this embodiment, assuming that the unit period and the number M of packets in that period are predetermined, the detection unit 40 detects the period deviation ΔT.

  In the frequency deviation detection unit 40 of the present embodiment, when the enable signal 138 is at a low level, the transmission side and reception side network time stamps 136 and 148 are determined. For example, at time t202, the network time stamp 136 indicating nt1 and nc1 respectively. And 148, and at time t204, time stamps 136 and 148 respectively indicating nt2 and nc2 are input to the detector 40, the fluctuation ΔT2 of the time stamp acquisition interval is equal to the time stamp nt1 and the time stamp previously input. Using nc1, it is calculated by the formula ((nt2-nt1)-(nc2-nc1)) / (nc2-nc1).

  Similarly, when time stamps 136 and 148 respectively indicating nt3 and nc3 are input to the detection unit 40 at time t206, fluctuation ΔT3 = ((nt3-nt2)-(nc3-nc2)) / (nc3- nc2) is calculated, and when time stamps 136 and 148 respectively indicating nt4 and nc4 are input to the detection unit 40 at time t208, fluctuation ΔT4 = ((nt4-nt3)-(nc4-nc3)) / ( nc4-nc3) is calculated.

  Thus, in the frequency deviation detection unit 40 of the present embodiment, the previously input time stamps 136 and 148 are nt (n-1) and nc (n-1), and the current time stamps 136 and 148 are nt ( n) and nc (n), the fluctuation ΔT (n) of the time stamp acquisition interval is expressed by the formula ((nt (n) -nt (n-1))-(nc (n) -nc (n- 1))) / (nc (n) -nc (n-1)). Further, the detected fluctuation ΔT (n) may be accumulated in the frequency deviation detection unit 40, and is averaged for each predetermined averaging number n. For example, the equation (ΔT (1) + ΔT (2) A period fluctuation ΔT is detected by averaging with + ΔT (3) +... + ΔT (n)) / n.

  Further, in the read timing generation unit 42, when the value obtained by adjusting the reception side network clock 148 according to the frequency deviation value 150 is equal to the transmission side network time stamp 144, a read timing signal 140 instructing reading is generated, The time stamp storage memory 36 is supplied. In the memory 36, the first time stamp 142 among the stored time stamps is read according to the timing signal 140 and supplied to the time stamp register 44.

  For example, an operation example of reading the video time stamp 142 when the correction based on the frequency deviation is not considered, that is, when the network clocks on the transmission side and the reception side are completely synchronized will be described with reference to the timing chart of FIG. .

  In the operation example of FIG. 7, at the time t212, the transmission side network time stamp 144 indicating nt11 is input to the read timing generation unit 42, and the video time stamp VT11 corresponding to this network time stamp nt11 is the time stamp register 44. Is entered.

  Next, when the read timing generation unit 42 proceeds to time t214 and the reception-side network clock counter value 148 becomes equal to nt11, a read timing signal 140 for instructing reading is generated and supplied to the time stamp storage memory 36.

  At this time, in the memory 36, the first time stamp 142 of the stored time stamps, that is, the time stamp nt12 next to the time stamp nt11 is read out according to the timing signal 140 and read as the network time stamp signal 144. It is supplied to the timing generator 42. At the same time, the video time stamp VT12 corresponding to the network time stamp nt12 is read from the memory 36 and supplied to the time stamp register 44 as the video time stamp signal 134.

  The timing signal 140 is also supplied to the time stamp register 44. In this register 44, the video time stamp VT11 is read out according to the timing signal 140 and output as the video time stamp signal 152 for phase synchronization. It is supplied to the circuit 46.

  Next, the read timing generation unit 42 generates the read timing signal 140 at time t216 when the network clock counter value 148 becomes equal to nt12. The network time stamp nt13 next to the time stamp nt12 is obtained from the time stamp storage memory 36. It is read out and supplied to the generating unit 42 as a time stamp signal 144. The video time stamp VT13 corresponding to the time stamp nt13 is read from the memory 36 and supplied to the time stamp register 44 as a time stamp signal 134. Further, in this register 44, the video time stamp VT12 is read in accordance with the timing signal 140 and supplied to the phase synchronization circuit 46 as the time stamp signal 152.

  Similarly, the read timing generation unit 42 generates the read timing signal 140 at the time t218 when the network clock counter value 148 becomes equal to nt13. The network time stamp nt14 next to the time stamp nt13 is the time stamp storage memory 36. Is supplied to the generating unit 42. The video time stamp VT14 corresponding to the time stamp nt14 is read from the memory 36 and supplied to the time stamp register 44. Further, in this register 44, the video time stamp VT13 is read and supplied to the phase synchronization circuit 46.

  On the other hand, an example of the operation of reading the video time stamp 142 when considering correction by frequency deviation, that is, when the network clocks of the transmission side and the reception side are not synchronized will be described with reference to the timing chart of FIG. In this operation example, it is assumed that the interval M / N for shifting the read timing has already been detected.

  In the operation example of FIG. 8, at the time t222, the transmission side network time stamp 144 indicating nt21 is input to the read timing generation unit 42, and the video time stamp VT21 corresponding to this network time stamp nt21 is the time stamp register 44. Is entered.

  Next, the read timing generation unit 42 proceeds to time t224, and when the reception-side network clock counter value 148 becomes equal to nt21, the read timing signal 140 is generated in the same manner as the operation example at time t214 shown in FIG. The network time stamp nt22 next to the time stamp nt21 is read from the time stamp storage memory 36 and supplied to the generating unit 42. The video time stamp VT22 corresponding to the time stamp nt22 is read from the memory 36 and supplied to the time stamp register 44. Further, in this register 44, the video time stamp VT21 is read and supplied to the phase synchronization circuit 46.

  Further, in this embodiment, it is assumed that the shift interval M / N elapses when the time t226 is further advanced, and at this time, the frequency deviation detection unit 40 issues a frequency deviation value 150 instructing the shift of the read timing and reads out. It is supplied to the timing generator 42.

  In the read timing generation unit 42, the network clock counter value 148 is originally equal to nt22 at time t228, but in this embodiment, this counter value is determined according to the frequency deviation value 150 indicating the shift instruction at time t226. 148 is advanced to be equal to nt22, and a read timing signal 140 is generated and supplied to the time stamp storage memory 36.

  At this time, in the memory 36, the time stamp nt23 next to the network time stamp nt22 is read in accordance with the timing signal 140 and supplied to the read timing generation unit 42 as the time stamp signal 144. At the same time, the video time stamp VT22 corresponding to the network time stamp nt23 is read from the memory 36 and supplied to the time stamp register 44 as the time stamp signal 134.

  Further, in the time stamp register 44, the video time stamp VT22 is read according to the timing signal 140 and supplied to the phase synchronization circuit 46 as the time stamp signal 152.

  In this way, in the read timing generation unit 42, as shown in FIG. 9, the comparison value 170 obtained by adjusting the frequency of the network clock counter value 148 for each shift interval M / N is compared with the transmission side network time stamp 144, and the comparison is made. A read timing signal 140 is generated according to the result. Further, in the receiving unit 32 of the present embodiment, among the video system time stamps 152 output from the time stamp register 44, it corresponds to the transmission side network time stamp 144 particularly at the time of frequency adjustment by the generating unit 42, that is, at the counter discontinuity point. The video time stamps 172, 174, and 176 to be operated may be PLL controlled by the phase synchronization circuit 46.

  This video time stamp 152 is compared with, for example, the frequency-divided signal 156 in the phase comparator 48, and a phase difference 158 as a result of the comparison is supplied to the D / A converter 50. The voltage is converted to a voltage value 160 by the A converter 50 and supplied to the oscillator 52.

  In the oscillator 52, an oscillation frequency 154 is generated according to the voltage value 160, and the frequency signal 154 is output as a reproduction clock signal of the reception unit 32.

  Further, the recovered clock signal 154 is frequency-divided at a predetermined frequency dividing rate by the frequency dividing counter 54, and the resulting frequency-divided signal 156 is supplied to the phase comparator 48.

  As described above, the phase difference 158 by the phase comparator 48 is used as a parameter for adjusting the frequency-divided signal 156 so that the frequency-divided signal 156 is in phase with the video time stamp 152, that is, synchronized.

It is a block diagram which shows one Example of the transmission part of the clock reproduction | regeneration system based on this invention. It is a block diagram which shows one Example of the receiving part of the clock reproduction | regeneration system based on this invention. 3 is a graph schematically showing fluctuations of a network clock generated between a transmission side and a reception side in the reception unit of the embodiment shown in FIG. 2. It is a block diagram which shows the example of the phase-locked loop circuit in the receiving part of the Example shown in FIG. FIG. 3 is a schematic diagram illustrating an example of a packet on which a network time stamp is superimposed in the transmission unit of the embodiment illustrated in FIG. 1. 3 is a timing chart for explaining an operation procedure of time stamp input in the receiving unit of the embodiment shown in FIG. 3 is a timing chart illustrating an operation procedure for reading a time stamp when the network clock is synchronized in the receiving unit of the embodiment illustrated in FIG. 2. 3 is a timing chart illustrating an operation procedure for reading a time stamp when the network clock is not synchronized in the receiving unit of the embodiment illustrated in FIG. 2. FIG. 3 is a graph schematically showing a network clock for correcting time stamp read timing in the receiving unit of the embodiment shown in FIG. 2. FIG.

Explanation of symbols

12 Transmitter
14 Equalizer section
16 Video clock counter
18 Video time stamp generator
20 Network clock counter
22 Network time stamp generator
24 IP packet generator 24
26 network
32 Receiver
34 Time stamp extractor
36 Time stamp storage memory
38 Network clock counter
40 Frequency deviation detector
42 Read timing generator
44 Time stamp register
46 Phase synchronization circuit

Claims (4)

In a clock recovery system in which a receiving unit receives a digital communication signal transmitted from a transmitting unit via a predetermined network and regenerates a clock synchronized with the digital communication signal in the receiving unit.
The transmission unit generates a data time stamp based on a reproduction clock of data transmitted by the digital communication signal, generates a first network time stamp based on a network clock on the transmitting side, and sets the data time stamp to a time Adding to the digital communication signal as information, adding a first network time stamp to the digital communication signal as frequency information,
The receiving unit extracts time stamp extraction means for extracting the data time stamp and the first network time stamp from the received digital communication signal;
A time stamp generating means for generating a second network time stamp based on a network clock on the receiving side;
Frequency deviation detecting means for detecting the frequency deviation of the network clock on the transmission side and the reception side according to the first network time stamp and the second network time stamp;
Look including a read timing generating means for reading based on the data time stamp to the frequency deviation,
The receiving unit includes phase synchronization means for generating a reproduction clock by performing phase synchronization control on the data time stamp read by the read timing generation means,
The clock reproduction is characterized in that the reception unit controls the output of the reproduction clock by the phase synchronization means only when the read timing generation means corrects the read timing of the data time stamp based on the frequency deviation. system.   2. The clock recovery system according to claim 1, wherein the system applies a video signal as data to be transmitted by the digital communication signal, and applies a video time stamp as the data time stamp. . In a clock recovery method in which a reception unit receives a digital communication signal transmitted from a transmission unit via a predetermined network and recovers a clock synchronized with the digital communication signal in the reception unit, the method includes:
The transmitting unit generates a data time stamp based on a reproduction clock of data transmitted by the digital communication signal, generates a first network time stamp based on a network clock on the transmitting side, and sets the data time stamp to a time Adding to the digital communication signal as information, and adding a first network time stamp as frequency information to the digital communication signal;
The receiving unit includes a receiving step of receiving the digital communication signal from the transmitting unit and reproducing a clock synchronized with the digital communication signal;
The receiving step includes a time stamp extracting step of extracting the data time stamp and a first network time stamp from the digital communication signal;
A time stamp generating step for generating a second network time stamp based on a network clock on the receiving side;
A frequency deviation detecting step of detecting a frequency deviation of the network clock on the transmitting side and the receiving side according to the first network time stamp and the second network time stamp;
A read timing generation step of reading the data time stamp based on the frequency deviation,
Generating a recovered clock based on the data time stamp read by the read timing generation step ;
The reception step includes a phase synchronization step of generating a reproduction clock by performing phase synchronization control on the data time stamp read by the read timing generation step,
The clock recovery system, wherein the recovery clock is output controlled by the phase synchronization step only when the read timing generation step corrects the read timing of the data time stamp based on the frequency deviation . 4. The clock recovery method according to claim 3 , wherein the method applies a video signal as data transmitted by the digital communication signal and applies a video time stamp as the data time stamp. .

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