JP5233174B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having normally-off characteristics while using a two-dimensional electron gas layer (2DEG layer) as a carrier conduction path.

  The conventional semiconductor device having a heterojunction for generating a two-dimensional electron gas layer serving as a carrier conduction path has several problems.

  FIG. 6A shows a conventional semiconductor device 611 having a general configuration that functions as a HEMT (High Electron Mobility Transistor) as a semiconductor device having a heterojunction.

  As illustrated, the semiconductor device 611 includes a first semiconductor layer 131, a second semiconductor layer 133, a source electrode 151, a gate electrode 153, a drain electrode 155, and a gate insulating film 157.

  The first semiconductor layer 131 is made of, for example, GaN. The second semiconductor layer 133 is made of, for example, AlGaN having a larger band gap than the first semiconductor layer 131 and a lattice constant smaller than that of the first semiconductor layer 131. Thus, both layers form a heterointerface 135. At the same time, a two-dimensional electron gas layer (2DEG layer) 137 is generated on the first semiconductor layer 131 side of the interface based on spontaneous polarization and piezoelectric polarization of the first semiconductor layer 131 and the second semiconductor layer 133. The second semiconductor layer 133 functions as an electron supply layer, and the first semiconductor layer 131 functions as an electron transit layer.

  The source electrode 151, the gate electrode 153, and the drain electrode 155 are formed on the upper surface of the second semiconductor layer 133. However, the source electrode 151 and the drain electrode 155 are both in ohmic junction (low resistance junction) with the second semiconductor layer 133, whereas the gate electrode 153 has a gate between the second semiconductor layer 133 and the gate electrode 153. An insulating film 157 is provided.

  When the semiconductor device 611 is operated as a HEMT, typically, the source electrode 151 is grounded and a positive voltage is applied to the drain electrode 155.

In this state, when no voltage is applied to the gate electrode 153, it is desired that the current _IDS flowing between the drain electrode 155 and the source electrode 151 becomes zero.

Further, when applying a positive voltage V _GS to the gate electrode 153, I _DS increases, and it is further desired that I _DS can be changed by changing V _GS . This is because the semiconductor device 611 ideally operates as a voltage control transistor if it can be done in this way.

However, actually, if a voltage is not applied to the gate electrode 153, the current _IDS flows between the source electrode 151 and the drain electrode 155. This is a phenomenon known as a so-called normally-on characteristic. That is, the operation of the semiconductor device 611, as indicated by the solid line 721 in FIG. _7, even _{V GS} = 0 _{I DS} does not become 0, a predetermined positive value _{I DS,} becomes to _ON. In order to set I _DS = 0, it is necessary to apply a predetermined negative voltage V _{GS, OFF} to the gate electrode 153.

Therefore, in order to perform an ideal operation as a transistor, firstly _{, a} depletion layer is generated by applying the above-described predetermined negative voltage V _{GS, OFF} to the gate electrode 153 in advance, so that the source electrode 151 and the drain electrode The current path to 155 is cut off, and the drain-source current I _DS is controlled by the gate voltage V _GS with reference to the voltage.

  However, continuing to apply a negative potential to the gate electrode 153 in order to turn off the HEMT has a drawback that the electrical circuit around the semiconductor device becomes complicated as a whole, resulting in the appearance of noise sources and an increase in cost. is there.

  Another technique for realizing normally-off is to thin the electron supply layer (see, for example, Patent Document 1). Specifically, as in the semiconductor device 613 illustrated in FIG. 6B, the vicinity of the gate formation portion on the upper surface of the second semiconductor layer 133 that is the electron supply layer is formed as a recess (concave portion), and the lower portion of the gate electrode 153 is formed. A so-called recess gate that makes an electron supply layer thin is known.

  The semiconductor device 613 has the same configuration as the semiconductor device 611 shown in FIG. 6A described above except that the recess 691 is provided.

The electrical characteristics of the semiconductor device 613 are as indicated by a one-dot chain line 723 in FIG. In the semiconductor device 613, a recess 691 is provided immediately below the gate electrode 153, and the second semiconductor layer 133 that is an electron supply layer is partially thinned. This weakens the electric field due to piezo polarization and spontaneous polarization based on the heterojunction between the electron supply layer and the electron transit layer, and reduces the concentration of the two-dimensional electron gas layer. Then, the pinch-off voltage immediately below the gate electrode 153 increases. Therefore, even if no voltage is applied to the gate electrode 153, the two-dimensional electron gas layer immediately below the gate electrode 153 disappears and is depleted. Therefore, a normally-off characteristic is obtained in which I _DS = 0 when V _GS = 0.

However, in the semiconductor device 613, since the electron supply layer is thinned, an electric field generated by piezoelectric polarization and spontaneous polarization caused by the second semiconductor layer 133 that is an electron supply layer and the first semiconductor layer 131 that is an electron transit layer is weak. Thus, the concentration or thickness of the 2DEG layer 137 decreases. Therefore, the channel becomes narrow for electrons as carriers. This adversely affects the performance as a HEMT. For example, by channel becomes narrower, the maximum value, i.e. the saturation current value of the current I _DS which can flow between the drain and the source decreases.

Generally, in the HEMT of the conduction path of the carrier of the 2DEG layer of the hetero interface, the maximum value of the current I _DS which can flow between the drain and the source is limited by the amount in the width of the conduction path. That is, as indicated by a solid line 721 in FIG. 7, even when a gate voltage V _GS greater than a certain value is applied, the current I _DS does not increase beyond a certain value I _{DS, S.}

In the semiconductor device 613 having a channel narrowed as a recess gate, the saturation current value is lowered as indicated by I _{DS and S1 in} FIG. 7 as compared with the saturation current values I _{DS and S} of the general semiconductor device 611. This means that the performance as a HEMT is low.

  After all, the general semiconductor device 611 has a defect of having a normally-on characteristic. On the other hand, the semiconductor device 613 has successfully obtained a normally-off characteristic by providing a recess gate, but has a decrease in saturation current value. It can be said that the price was paid.

In addition, as the HEMT, it is desirable that a large drain-source current I _DS flows with a small gate application voltage V _GS . In other words, the drain-source resistance should be small. However, in the semiconductor device 613 in which the channel is narrowed by employing the recess gate, the drain-source resistance (channel layer resistance) increases because the two-dimensional electron gas layer immediately below the gate electrode 153 disappears.
JP 2005-183733 A

  The development of a HEMT that has both the easy acquisition of normally-off characteristics and the prevention of lowering of the saturation current value, which has the electrical characteristics indicated by the dotted line 725 in FIG. 7, is awaited.

  Furthermore, it is preferable that the ratio of the drain-source current increase to the gate voltage increase is large. That is, in FIG. 7, it is desirable that the slope 735 of the dotted line 725 is larger than the slope 731 of the solid line 721.

  The present invention has been made in view of the above circumstances, and realizes a HEMT having a normally-off characteristic with a simple mechanism, no reduction in saturation current value, and good drain-source current characteristics with respect to gate voltage. An object of the present invention is to provide a semiconductor device capable of performing

To achieve the above object, a semiconductor device according to the present onset Ming,
A second semiconductor layer formed on the first semiconductor layer so as to form a two-dimensional electron gas layer on the first semiconductor layer side of the heterointerface by forming a heterointerface with the first semiconductor layer; A semiconductor substrate, and a semiconductor substrate that is formed with a step in the thickness direction and exposed laterally;
A first electrode formed in a portion of the upper surface of the second semiconductor layer at a higher position due to the step, and a Schottky junction with the semiconductor substrate;
An insulating film that continuously covers the exposed portion on the side of the semiconductor substrate from the exposed portion on the side surface of the first electrode through the interface between the exposed portion on the side surface of the first electrode and the exposed portion on the side of the semiconductor substrate. When,
A second electrode formed across the interface between the exposed portion on the side surface of the first electrode and the exposed portion on the side of the semiconductor substrate via the insulating film;
A third electrode formed at a position spaced apart from the first electrode and the second electrode and in low resistance contact with the upper surface of the semiconductor substrate;
Is provided.

  The second electrode may also be formed on a portion of the upper surface of the second semiconductor layer that is lower than the step.

At the interface between the exposed portion on the side surface of the first electrode and the exposed portion on the side of the semiconductor substrate, from the exposed portion on the side surface of the first electrode to the exposed portion of the second semiconductor layer on the side of the semiconductor substrate. It is desirable to be flat.

  The first semiconductor layer and the second semiconductor layer are made of, for example, different nitride compound semiconductors.

  According to the present invention, the semiconductor device has a normally-off characteristic, does not cause a decrease in the saturation current value, and becomes a HEMT having a good drain-source current characteristic with respect to the gate voltage.

(Embodiment 1)
The semiconductor device according to this embodiment is a HEMT. FIG. 1A is a schematic diagram of a cross section of the semiconductor device 111.

  As shown in FIG. 1, the semiconductor device 111 includes a first semiconductor layer 131, a second semiconductor layer 133, a source electrode 151, a gate electrode 153, a drain electrode 155, and a gate insulating film 157.

  The first semiconductor layer 131 is made of, for example, a nitride compound semiconductor GaN having a thickness of 1 to 3 μm and functions as an electron transit layer. The second semiconductor layer 133 is made of a nitride compound semiconductor AlGaN having a thickness smaller than that of the first semiconductor layer 131, for example, 5 to 50 nm (more preferably 5 to 30 nm), and functions as an electron supply layer.

  The first semiconductor layer 131 and the second semiconductor layer 133 are different types of nitride compound semiconductors, and are configured such that the band gap energy of the second semiconductor layer 133 is larger than that of the first semiconductor layer 131. ing. Therefore, both layers form a heterointerface 135, and the first semiconductor layer in the vicinity of the interface is formed by piezoelectric polarization between the first semiconductor layer 131 and the second semiconductor layer 133 or by the spontaneous polarization of the second semiconductor layer 133. A 2DEG layer 137 is formed on the 131 side.

  The source electrode 151 may be formed on the upper surface of the second semiconductor layer 133. However, the source electrode 151 is a recess engraved until reaching the heterointerface 135, more preferably reaching the 2DEG layer 137 as shown in FIG. It is preferable to be arranged so as to be embedded in. When arranged in such a manner, the source electrode 151 contacts the 2DEG layer 137 as indicated by a circle 171 in the figure, so that the on-resistance can be reduced.

  The source electrode 151 is made of Ni / Au. Since Ni / Au has a large work function, the source electrode 151 forms a Schottky junction with the first semiconductor layer 131, and the source electrode 151 forms a Schottky junction with the second semiconductor layer 133. Further, the source electrode 151 also forms a Schottky junction with the 2DEG layer 137.

  The gate electrode 153 is made of Al, and is mainly formed on the upper surface of the second semiconductor layer 133 with the gate insulating film 157 interposed between the upper surface of the second semiconductor layer 133. However, at that time, the gate electrode 153 and the gate insulating film 157 are formed so that the contact portion 171 between the source electrode 151 and the 2DEG layer 137 (first semiconductor layer 131) is located immediately below the gate electrode 153 and the gate insulating film 157.

  That is, as shown in FIG. 1A, the gate electrode 153 and the gate insulating film 157 are generally formed on the upper surface of the second semiconductor layer 133, but a part of them is formed between the second semiconductor layer 133 and the source electrode 151. It extends to the upper surface of the source electrode 151 beyond (through) the interface. Here, it is desirable that the contact portion 171 is located closer to the gate electrode 153 than the dotted line 161 in the drawing representing the lower end of the stretching.

  The drain electrode 155 is separated from the source electrode 151 and the gate electrode 153 and is made of Ti / Al. Since Ti / Al has a small work function, the drain electrode 155 and the second semiconductor layer 133 are in ohmic contact (low resistance contact) by performing an annealing process. The gate electrode 153 is positioned between the drain electrode 155 and the source electrode 151 when the semiconductor device 111 is viewed from above.

  Hereinafter, how the semiconductor device 111 operates as a HEMT will be described.

  In accordance with a normal procedure for operating the semiconductor device 111 having the 2DEG layer 137 as a HEMT, the source electrode 151 is grounded and a positive voltage is applied to the drain electrode 155.

  In the conventional HEMT, the source electrode is also in ohmic contact with the semiconductor layer like the drain electrode, the 2DEG layer is not cut off, and the current path between the drain electrode and the source electrode is in a conductive state. A current flows from the drain electrode to the source electrode (normally on characteristics).

  The normally-on characteristic is an undesirable property for a transistor. In order to overcome this problem, conventionally, two major measures have been taken.

  One is to apply a negative potential to the gate electrode in advance. However, continuing to apply a negative potential to the gate electrode in order to turn off the HEMT has a drawback that the electrical circuit around the semiconductor device becomes complicated as a whole.

  The other is to provide a recess (recess) in the electron supply layer directly under the gate electrode and thin the electron supply layer directly under the gate electrode, thereby increasing the pinch-off voltage of the portion and depleting it. . However, when the electron supply layer is thinned, the electric field generated by piezo polarization at the heterointerface is weakened, and the concentration of the two-dimensional electron gas layer is reduced. This means that the conduction channel becomes narrower for electrons as carriers. That is, the HEMT has a low performance in which the channel layer resistance increases and the saturation current value decreases.

  In the semiconductor device 111 according to this embodiment, even if the source electrode 151 is grounded and a positive voltage is applied to the drain resistor 155, the source electrode 151 forms a Schottky junction with both the second semiconductor layer 133 and the 2DEG layer 137. In addition, since this voltage is a reverse voltage with respect to the Schottky junction, a depletion layer is generated at the interface between the source electrode 151 and the 2DEG layer 137 (or the second semiconductor layer 133) in contact therewith. The source electrode 151 and the 2DEG layer 137 are electrically cut off and no current flows.

  As described above, in the semiconductor device 111 according to the present embodiment, the normally-off characteristic was easily obtained unlike the conventional semiconductor device.

FIG. 3A shows the energy state of electrons when no voltage is applied to the gate electrode 153 in the semiconductor device 111 according to the present embodiment. In order to facilitate understanding, the band structure of the first semiconductor layer 131 is replaced with a band structure of a two-dimensional electron gas layer. A sufficiently thick Schottky barrier exists at the interface (contact portion 171) between the source electrode (Fermi energy E _f ) and the two-dimensional electron gas layer (conduction electron energy E _c ). Therefore, electrons on the source electrode side are bounced back to the barrier (or cannot get over the barrier) and cannot reach the two-dimensional electron gas layer 137. Therefore, no current flows between the drain electrode 155 and the source electrode 151.

  Next, a positive potential is applied to the gate electrode 153. As shown in FIG. 1A, since the contact portion 171 between the source electrode 151 and the 2DEG layer 137 exists immediately below the gate electrode 153, the Schottky barrier existing in the contact portion 171 is separated from the gate electrode 153. Remarkably affected by the electric field. Then, as shown in FIG. 3 (b), the Schottky barrier in the contact portion 171 is thinned by the electric field, so that the tunnel effect becomes significant, and electrons flow from the source electrode 151 to the 2DEG layer 137. It is taken into the drain electrode 155. That is, the HEMT can be turned on by applying the gate voltage.

  Here, it is desirable to generate an electric field in a direction perpendicular to the 2DEG layer 137 in order to sufficiently exhibit the above-described effect. Therefore, it is preferable to make the height of the lower surface of the gate electrode 153 constant, and in order to do so, the upper surface of the source electrode 151 and the upper surface of the second semiconductor layer 133 are preferably the same height. . That is, it is desirable that the upper surface of the source electrode 155 and the upper surface of the second semiconductor layer 133 are connected flatly without a step. Here, the term “flatness” as used herein includes not only strict flatness but also flatness within a range of inevitable variations in manufacturing a semiconductor device.

In this embodiment, the higher the positive potential applied to the gate electrode 153, the thinner the Schottky barrier, so that the drain-source current _IDS increases (dotted line 725 in FIG. 7).

Further, in this embodiment, unlike the conventional semiconductor device 613 shown in FIG. 6B, the portion of the second semiconductor layer 133 immediately below the gate electrode 153 is not thinned, and the source electrode 151 is an electron. Due to the fact that the 2DEG layer 137 which is the conductive channel of the 2DEG layer is in direct contact with the contact portion 171, the source resistance becomes almost zero. Therefore, the drain-source resistance value (ON resistance) is smaller than the conventional semiconductor device 611 shown in FIG. 6A and 613 shown in FIG. 6B. Therefore, as shown in FIG. 7, the amount of change in drain-source current I _DS (inclination 735 in FIG. 7) with respect to the amount of change in gate voltage V _GS is the conventional semiconductor device (inclination 731 in FIG. 7). Bigger than that. That is, the HEMT has good drain-source current characteristics with respect to the gate voltage.

  Also, in the semiconductor device 111 according to the present embodiment, unlike the conventional semiconductor device 613, the portion immediately below the gate electrode 153 in the second semiconductor layer 133 that is an electron supply layer is not particularly thinned. . On the right side of the contact portion 171, that is, on the drain electrode 155 side, the second semiconductor layer 133, that is, the electron supply layer having a sufficient thickness is formed on the heterointerface 135 as in the conventional semiconductor device 611. Therefore, the problem of a decrease in saturation current is less likely to occur than in the conventional semiconductor device 613.

  Therefore, the semiconductor device 111 according to the present embodiment has a normally-off characteristic, does not cause a decrease in saturation current value, and has a low electrical resistance due to a low resistance between the drain and the source. It is a superior HEMT.

In an environment where HEMT is actually used, spike-like sudden electrical noise is often generated. At that time, the HEMT having a normally-off characteristic by a conventional Schottky junction may be turned on / off by mistake every time such noise is generated. In order to prevent this, in the semiconductor device 111 according to the present embodiment, the thickness of the gate insulating film 157 is increased so that it is turned on only when the gate voltage V _GS exceeds a positive value. That's fine. That is, as indicated by the white arrow in FIG. 7, the line representing the electrical characteristics of the HEMT according to this example can be easily translated in the + X-axis direction by increasing the thickness of the gate insulating film 157. In addition, the degree of such parallel movement is larger as the gate insulating film 157 is thicker. Therefore, after considering the magnitude of the above-described sudden electrical noise, the thickness of the gate insulating film 157 may be adjusted so that the gate electrode V _GS is turned on only when the gate voltage V _GS is higher than that. As described above, the HEMT according to the present embodiment can flexibly cope with a situation where noise is present while obtaining a normally-off characteristic.

(Embodiment 2)
The semiconductor device 113 (FIG. 1B) according to the present embodiment is an improvement of the HEMT according to the first embodiment in three respects.

  The first improvement is that the overlap between the gate electrode 153 and the source electrode 151 when the semiconductor device 113 is viewed from directly above is increased. Thus, the source electrode 151 and the 2DEG layer 137 surely have the contact portion 171 below the gate electrode 153, so that the operation as a HEMT having normally-off characteristics is ensured.

  The second improvement is that when the source electrode 151 is embedded in the semiconductor layer, the electrode penetrates through the 2DEG layer 137 and reaches a sufficiently deep portion of the first semiconductor layer 131. As a result, the source electrode 151 and the 2DEG layer 137 are in surface contact with each other at the contact portion 171, so that the operation as a HEMT having normally-off characteristics is ensured and the drain-source current characteristics with respect to the gate voltage. Can be further improved.

  The third improvement is that the drain electrode 155 is buried in a trench dug so as to penetrate the 2DEG layer 137 and reach a sufficiently deep portion of the first semiconductor layer 131. As a result, the drain electrode 155 is in direct contact with the 2DEG layer 137, so that the on-resistance can be reduced. Therefore, it is possible to further improve the characteristics of the drain-source current with respect to changes in the gate voltage.

  Of these three improvements, only one may be applied, or any two may be applied in combination.

(Embodiment 3)
The semiconductor device 211 according to the present embodiment is a modification of the HEMT according to the first embodiment from the viewpoint of ease of manufacture (FIG. 2A).

  In the HEMT according to the present embodiment, a groove dug in the first semiconductor layer 133 to bury the source electrode 151 has a taper in which the groove width becomes narrower in the depth direction. Since the groove does not have to be dug perpendicularly to the upper surface of the second semiconductor layer as in the first embodiment, the manufacture is facilitated.

  In order for the semiconductor device 113 according to the present embodiment to sufficiently exhibit the effect, the gate electrode 153 is formed from the upper surface of the second semiconductor layer 133 to the second semiconductor layer 133 as in the case of the semiconductor device 111 according to the first embodiment. The contact portion 171 between the source electrode 151 and the 2DEG layer 137 is preferably located immediately below the gate electrode 153, extending beyond the interface between the source electrode 151 and the upper surface of the source electrode 151.

(Embodiment 4)
In the same way as the third embodiment is a simplification of the first embodiment, the semiconductor device 213 according to the present embodiment makes it easier to manufacture the semiconductor device 113 according to the second embodiment. That is, the drain electrode 155 is formed so as to be embedded in a groove formed with a taper similar to the groove for embedding the source electrode 151 in the third embodiment (FIG. 2B). As in the case of the third embodiment, there is a merit that manufacturing is easy.

(Embodiment 5)
Unlike the first to fourth embodiments, the semiconductor device according to the present embodiment does not focus on the interface in the thickness direction between the source electrode 151 and the second semiconductor layer 133, but instead of the source electrode 151 and the second semiconductor layer 133. Focusing on the interface in the width direction (lateral direction), the HEMT can easily obtain normally-off characteristics and good electrical characteristics without bringing the source electrode 151 into contact with the 2DEG layer 137.

  FIG. 4A is a schematic cross-sectional view of the semiconductor device 411 according to this embodiment. Unlike the first to fourth embodiments, the source electrode 151 is provided on the upper surface of the second semiconductor layer 133 without being embedded in the first semiconductor layer 131 or the second semiconductor layer 133.

  In forming the source electrode 151 in this way, the source electrode 151 and the first electrode 151 are formed in comparison with the case where the source electrode 151 is embedded in the first semiconductor layer 131 or the second semiconductor layer 133 (the first to fourth embodiments). There are advantages such as improvement in adhesion between the semiconductor layer 131 and adhesion between the source electrode 151 and the second semiconductor layer 133.

  In providing the source electrode 151 on the upper surface of the second semiconductor layer 133, the second semiconductor layer 133 is formed thicker than usual in the lower portion of the region where the source electrode 151 is provided.

  Here, in the second semiconductor layer 133, a thick portion at a lower portion of a region where the source electrode 151 is provided is referred to as a first portion 133A, and the other portion is referred to as a second portion 133B. The upper side of the one-dot chain line in the horizontal direction of FIG. 4A is the first portion 133A, and the lower side is the second portion 133B. Note that the first portion 133A may be doped with an n-type impurity to form a contact layer.

  Note that the formation of the second semiconductor layer 133 partially thick in this way is, from a relative point of view, by recessing a region of the upper surface of the second semiconductor layer 133 where the source electrode 151 is not formed. It can be said that this is the same as the above-described conventional method (FIG. 6B) for obtaining normally-off characteristics (as a recess).

However, in the present embodiment, the thickness of the second semiconductor layer 133 as the electron supply layer is first ensured as usual over the entire range, and is particularly thick only in the range where the source electrode 151 is formed. In addition, the second semiconductor layer 133 is formed so as to expose a side surface with a step in the thickness direction. Therefore, unlike the conventional recessed gate structure in which the electron supply layer directly under the gate electrode must be made to have a thickness of about several atomic layers or less by dry etching, normally-off characteristics can be obtained more reliably and manufacturing is easy. Yield is expected to improve. Further, the above-described decrease in the saturation current value due to the recess, which is represented by IDS _{and S1} in FIG. 7, does not occur in the semiconductor device 411 according to the present embodiment.

  In addition to the thickness of the second semiconductor layer 133 below the source electrode 151, the thickness of the source electrode 151 itself is added, and a step is generated on the upper surface of the second semiconductor layer 133. The gate electrode 153 includes the interface between the source electrode 151 and the second semiconductor layer 133 from at least the side wall surface of the source electrode 151 formed on the upper surface of the second semiconductor layer 133 with the gate insulating film 157. It is formed so as to cover a range over a part of the exposed second semiconductor layer 133. As shown in the drawing, it is desirable that the cross sections of the gate electrode 153 and the gate insulating film 157 extend to the upper surface of the source electrode 151, resulting in a stepped shape.

  In FIG. 4A, horizontal dotted lines 461 and 463 and vertical dotted lines 465 and 467 are for the following explanation.

  The upper surface of the gate electrode 153 needs to be positioned higher than the interface between the source electrode 151 and the first portion 133A of the second semiconductor layer 133, for example, above the plane indicated by the dotted line 461 in the drawing. The lower surface of the gate electrode 153 needs to be positioned lower than the interface between the source electrode 151 and the first portion 133A of the second semiconductor layer 133, for example, below the plane indicated by the dotted line 463 in the drawing. The gate electrode 153 becomes a side wall end on the drain electrode 155 side from a dotted line 465 corresponding to a side wall end on the source electrode 151 side of a portion where the first portion 133A of the second semiconductor layer 133 and the gate insulating film 157 are in contact with each other. It is desirable to extend to the dotted line 467.

  In the HEMT according to this embodiment, two regions are important in the operation. One is a region indicated by an ellipse 471 sandwiched between a dotted line 461 and a dotted line 463 including the interface between the source electrode 151 and the second semiconductor layer 133. In this region, the mechanism of expression of the electrical characteristics characteristic of the present invention is the same as in the first to fourth embodiments. Another important area is an area indicated by an ellipse 473 between the dotted lines 465 and 467 in the 2DEG layer 137. The mechanism of the expression of electrical characteristics characteristic of the present invention in this region will be described later.

  A Schottky electrode is employed as the source electrode 151, and the semiconductor device 411 according to the present embodiment acquires normally-off characteristics. The first portion 133A of the second semiconductor layer 133 in the present embodiment plays a role of a current path to the 2DEG layer 137 (FIG. 1A) of the first embodiment. The operation / effect in the embodiment is the same as the operation / effect in the first embodiment.

  The gate electrode 153 spans the interface between the source electrode 151 and the first portion 133A of the second semiconductor layer 133 so as to cross the side surface of the source electrode 151 and the side surface of the first portion 133A of the second semiconductor layer 133. The gate insulating film 157 is interposed therebetween.

  The operation of the semiconductor device 411 according to this embodiment as a HEMT will be described with reference to a schematic diagram of electron energy shown in FIG. First, when the source electrode 151 is grounded and a voltage is applied to the drain electrode 155, a reverse bias is applied between the source electrode 151 and the second semiconductor layer 133.

  When no voltage is applied to the gate electrode 153, a reverse bias is applied between the source electrode 151 and the second semiconductor layer 133 as described above, and no current flows between the drain and the source. In consideration of the two regions indicated by the ellipse 471 and the ellipse 473 in FIG. 4A, this state is represented as a schematic diagram of electron energy as shown in FIG. 5A.

  A thick Schottky barrier exists at the interface between the region 471, that is, the source electrode 151 and the electron supply layer (second semiconductor layer 133).

  On the other hand, an energy barrier exists at the interface 473 between the electron supply layer (second semiconductor layer 133) and the 2DEG layer 137 (or the first semiconductor layer 131).

  Therefore, as shown in FIG. 5A, electrons inside the source electrode 151 cannot reach the 2DEG layer 137. Therefore, no current flows inside the semiconductor device 411. That is, the semiconductor device 411 has normally-off characteristics.

  Here, when a positive voltage is applied to the gate electrode 153, both the region 471 and the region 473 are affected by the electric field from the gate electrode 153. In particular, since the electric field due to the voltage applied to the gate electrode 153 is generated in the direction perpendicular to the interface included in the region 471 and the interface included in the region 473, the influence of the voltage applied to the gate electrode 153 is large.

  Note that in order to generate an electric field in a direction perpendicular to the interface included in the region 471, a portion from the exposed portion of the side surface of the source electrode 151 to the exposed portion of the side surface of the second semiconductor layer 133 is desirably flat. In the present embodiment, etching is performed using the source electrode 151 as a mask so as to expose the side surface of the second semiconductor layer 133, and then the gate insulating film 157 and the gate electrode 153 are stacked and easily subjected to predetermined patterning. The above structure can be formed.

  The state of electron energy when a positive voltage is applied to the gate electrode 153 is as shown in FIG. First, the Schottky barrier at the interface between the region 471, that is, the source electrode 151 and the electron supply layer (second semiconductor layer 133) is caused by the electric field mainly from the portion surrounded by the dotted line 461 and the dotted line 463 of the gate electrode 153. As shown by the upward white arrow (1) in the figure, it becomes thinner. Further, the 2DEG layer 137 is lowered by an electric field mainly from a portion surrounded by the dotted line 465 and the dotted line 467 of the gate electrode 153, as indicated by a left-pointed white arrow (2) in the drawing.

  Thus, the tunnel effect is likely to occur due to the combination of the thin Schottky barrier and the low Schottky barrier. That is, electrons reach the 2DEG layer 137 from the source electrode 151. In this way, in the semiconductor device 411 according to this embodiment, a current flows between the source electrode 151 and the drain electrode 155 to be turned on.

If the voltage applied to the gate electrode 153 is increased, the Schottky barrier becomes thinner and lower, so that the tunnel effect is more likely to occur. As a result, the current flowing through the semiconductor device 411 increases. In this way, the drain-source current I _DS can be controlled by controlling the gate voltage V _GS .

(Embodiment 6)
FIG. 4B shows a schematic cross-sectional view of the semiconductor device 413 according to this embodiment. In the fifth embodiment, the first portion 133A is formed in the region where the source electrode 151 is provided on the upper surface of the second portion 133B of the second semiconductor layer 133, and a step is provided in the second semiconductor layer 133. In this embodiment, a recess or groove is provided, and the gate electrode 153 is embedded in the recess or groove via the gate insulating film 157.

  The thickness of the second semiconductor layer 133 is adjusted over the entire surface to match the thickness of the thickened portion of the second semiconductor layer 133 of the semiconductor device 411 according to the fifth embodiment. That is, the second semiconductor layer 133 is thicker than the conventional general semiconductor device 611 (FIG. 6A).

  Therefore, if the gate electrode 153 is formed as it is on the upper surface of the second semiconductor layer 133, the distance between the lower surface of the gate electrode 153 and the 2DEG layer 137 is too long compared to the conventional semiconductor device, and thus the gate voltage. It becomes difficult to control the thickness of the Schottky barrier on the upper surface of the 2DEG layer (interface 473 in the figure) by application.

  Therefore, in the present embodiment, a recess or groove having a sufficient depth is dug in the upper surface of the second semiconductor layer 133, and a part of the gate electrode 153 is placed along the gate insulating film 157 under the second semiconductor layer 133. It is embedded inside 133. Thereby, the distance between the lower surface of the gate electrode 153 and the upper surface of the 2DEG layer 137 is shortened, and the Schottky barrier existing at the interface 473 can be controlled.

  Therefore, the semiconductor device 413 also has interfaces 471 and 473 similar to those of the fifth embodiment. Therefore, it can be operated similarly to the fifth embodiment.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation and application are possible. For example, in Embodiments 1 to 6, a known substrate for epitaxially growing a semiconductor layer is provided under the first semiconductor layer 131, and further, a buffer layer is provided between the substrate and the first semiconductor layer 131. Or you may.

  The above-described configuration of the semiconductor device is an example and is not limited. Although the nitride compound semiconductor has been described as an example of the first semiconductor layer 131 and the second semiconductor layer 133, other III-V group compound semiconductors such as GaAs may be used. Further, a contact layer to which an n-type impurity is added may be inserted between the second semiconductor layer 133 and the drain electrode 155 or between the second semiconductor layer 133 and the source electrode 151. Alternatively, an AlN layer may be sandwiched between the first semiconductor layer 131 and the second semiconductor layer 133. A substrate including these is called a semiconductor substrate. The semiconductor device according to the present invention includes the entire semiconductor substrate.

  In Embodiments 1 to 4, the source electrode 151 does not have to be formed thick until the recess is completely filled. Similarly, in the fifth and sixth embodiments, a step may be provided in the gate electrode 153 so as to match the step of the gate insulating film 157.

It is a cross-sectional schematic diagram which shows the structure of the semiconductor device which functions as HEMT based on Embodiment 1 and Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows the structure of the semiconductor device which functions as HEMT based on Embodiment 3 and Embodiment 4 of this invention. It is a schematic diagram which shows the relationship between the electron energy and the Schottky barrier in the first to fourth embodiments of the present invention. It is a cross-sectional schematic diagram which shows the structure of the semiconductor device which functions as HEMT based on Embodiment 5 and Embodiment 6 of this invention. It is a schematic diagram which shows the relationship between electron energy and a Schottky barrier in Embodiment 5 and Embodiment 6 of this invention. It is a cross-sectional schematic diagram which shows the structure of the conventional common semiconductor device which functions as HEMT. It is a figure which shows the electrical property of HEMT.

Explanation of symbols

111 Semiconductor Device According to First Embodiment 113 Semiconductor Device According to Second Embodiment 131 First Semiconductor Layer 133 Second Semiconductor Layer 133A First Part of Second Semiconductor Layer 133B Second Part of Second Semiconductor Layer 135 Heterointerface 137 Two-dimensional electron gas layer 151 Source electrode 153 Gate electrode 155 Drain electrode 157 Gate insulating film 171 Contact portion between source electrode and two-dimensional electron gas layer 211 Semiconductor device according to Embodiment 3 213 Semiconductor device according to Embodiment 4 411 Embodiment Semiconductor device according to 5 413 Semiconductor device according to the sixth embodiment 471 Region including interface between source electrode and second semiconductor layer 473 Region that is part of 2DEG layer

Claims (4)

A second semiconductor layer formed on the first semiconductor layer so as to form a two-dimensional electron gas layer on the first semiconductor layer side of the heterointerface by forming a heterointerface with the first semiconductor layer; A semiconductor substrate, and a semiconductor substrate that is formed with a step in the thickness direction and exposed laterally;
A first electrode formed in a portion of the upper surface of the second semiconductor layer at a higher position due to the step, and a Schottky junction with the semiconductor substrate;
An insulating film that continuously covers the exposed portion on the side of the semiconductor substrate from the exposed portion on the side surface of the first electrode through the interface between the exposed portion on the side surface of the first electrode and the exposed portion on the side of the semiconductor substrate. When,
A second electrode formed across the interface between the exposed portion on the side surface of the first electrode and the exposed portion on the side of the semiconductor substrate via the insulating film;
A third electrode formed at a position spaced apart from the first electrode and the second electrode and in low resistance contact with the upper surface of the semiconductor substrate;
A semiconductor device comprising: Of the upper surface of the second semiconductor layer, the second electrode is also formed on the lower portion of the step.
The semiconductor device according to claim 1 . At the interface between the exposed portion on the side surface of the first electrode and the exposed portion on the side of the semiconductor substrate, from the exposed portion on the side surface of the first electrode to the exposed portion of the second semiconductor layer on the side of the semiconductor substrate. Flat,
The semiconductor device according to claim 1 or 2, characterized in that. The first semiconductor layer and the second semiconductor layer are composed of different nitride compound semiconductors,
The semiconductor device according to any one of claims 1 to 3 characterized in that.

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