JP5298185B2 - I2C monitoring sequential read data storage device - Google Patents

Abstract

Provided is an I2C monitor sequential read data storage device capable of dealing with various read schemes in highly versatile manner. The I2C monitor sequential read data storage device acquires communication data through an I2C interface between a master circuit and a slave circuit and is equipped with an address counter for counting the number of addresse equivalents of the slave circuit. When acquiring a byte address for specifying a predetermined region of the slave circuit, the I2C monitor sequential read data storage device sets the acquired byte address as an initial value of the address counter.

Description

  The present invention relates to an I2C monitoring sequential read data storage device capable of supporting a plurality of reading methods.

  A transmission device that monitors and controls using an I2C interface such as an optical module or LSI is composed of a plurality of units, and each unit is an EEPROM in which physical inventory information (hereinafter referred to as PI information) of each unit is stored. Is provided. The transmission apparatus reads PI information from the EEPROM of each unit via the I2C interface.

  When the unit is mounted on the transmission apparatus, the transmission apparatus reads and controls PI information stored in advance in the EEPROM of the unit via the I2C interface, and acquires the PI information. For example, when the unit is a transponder, the PI information is information unique to the unit such as wavelength information handled by the transponder.

  When the unit is replaced to upgrade the version, the transmission apparatus reads the PI information of the replaced unit through the I2C interface. At this time, the I2C monitoring sequential read data storage device connected to the I2C interface acquires and stores necessary I2C communication data (typically PI information) between the transmission device and the unit. The PI information and the like stored in the I2C monitoring sequential read data storage device is used when required by other units.

  If the transmission device is the master side and the unit's EEPROM is the slave side, the read method using the I2C interface between them is a sequential read method with a relatively short read time, a random read method specifying address information, or a sequential random read method. Etc. are used.

  Communication processing means that realizes a read method with a short transmission time in addition to a read method that specifies address information in order to shorten the time required for initial setting of the system and to provide flexibility of the communication processing means, For example, it is disclosed in Patent Document 1 below.

Japanese Patent Laid-Open No. 8-316973

  If the I2C monitoring sequential read data storage device only supports a single I2C read method, for example, if the read method using the I2C interface between the transmission device and the unit is different, the communication data cannot be read, It becomes impossible to acquire desired information held in the EEPROM or the like in the unit.

  Therefore, an I2C monitoring sequential read data storage device that can cope with various read methods using an I2C interface between the master circuit side and the slave circuit side with high versatility is expected.

  The present invention has been made in view of the above-described problems. I2C monitoring sequential read data storage that can cope with various read methods using an I2C interface between a master circuit side and a slave circuit side with high versatility. An object is to provide an apparatus.

  An I2C monitoring sequential read data storage device according to the present invention is an I2C monitoring sequential read data storage device that acquires communication data via an I2C interface between a master circuit and a slave circuit, and counts the address equivalent number of the slave circuit. When an address counter is provided and a byte address specifying a predetermined area of the slave circuit is acquired, the acquired byte address is set as an initial value of the address counter.

  The I2C monitoring sequential read data storage device according to the present invention preferably includes a byte address register for temporarily storing the acquired byte address, and when the slave circuit returns a normal signal for reception of the byte address, the byte address register The byte address temporarily stored in may be used as the initial value of the address counter.

  The I2C monitoring sequential read data storage device according to the present invention more preferably stores the acquired communication data when the slave circuit that has received the device address or byte address specifying the slave circuit returns an abnormal signal. It does not have to be.

  The I2C monitoring sequential read data storage device according to the present invention preferably further includes an acknowledge register for temporarily storing a reply signal of a slave circuit that has received a device address or byte address for specifying the slave circuit, and a counter value of the address counter. And a decoder unit that outputs timing for storing communication data acquired by decoding the data, and when the return signal input from the ACK register is an abnormal signal, the decoder does not store the acquired communication data The unit may not output the timing for storing the communication data.

  Further, the I2C monitoring sequential read data storage device according to the present invention is more preferably initialized even when the slave circuit receiving the device address or the byte address specifying the slave circuit returns an abnormal signal. Good.

  Further, the I2C monitoring sequential read data storage device according to the present invention preferably further detects a termination signal for ending the communication between the master circuit and the slave circuit, and detects the N2 detection that initializes the I2C monitoring sequential read data storage device. The Nac detection unit may initialize the I2C monitoring sequential read data storage device when the return signal input from the acknack register is an abnormal signal.

  In the I2C monitoring sequential read data storage device according to the present invention, more preferably, a plurality of slave circuits are connected via an I2C interface, and the I2C monitoring sequential read data storage device specifies a slave circuit that is an information acquisition target. An expected device address value may be set in advance, and communication data of the slave circuit corresponding to the expected device address value may be stored.

  Further, the I2C monitoring sequential read data storage device according to the present invention is more preferably an I2C monitoring sequential read data storage device, wherein an expected value storage unit that stores in advance a device address expected value that specifies a slave circuit that is an information acquisition target; A device address expected value stored in the expected value storage unit and a device address expected value comparing unit that compares the acquired device address, and the device address expected value comparing unit includes the device address expected value and the acquired device address. May be output from the initialization signal of the I2C monitoring sequential read data storage device.

  The I2C monitoring sequential read data storage device according to the present invention preferably initializes the address counter only when the I2C monitoring sequential read data storage device is turned on so that the address counter matches the address count of the slave circuit. May be used.

  Further, in the I2C monitoring sequential read data storage device according to the present invention, it is more preferable that the restart is transmitted from the master circuit to the slave circuit even when the address counter acquires the start signal transmitted from the master circuit to the slave circuit. Even if the signal is acquired, it may not be initialized in either case.

  In the I2C monitoring sequential read data storage device according to the present invention, the slave circuit is preferably an EEPROM, and the I2C monitoring sequential read data storage device is stored in a predetermined area of the EEPROM read by the master circuit via the I2C interface. A storage unit that acquires and stores the processed data may be provided.

  In the I2C monitoring sequential read data storage device according to the present invention, more preferably, the read method of the I2C interface may be any one or more of a random read method, a sequential read method, and a sequential random read method. .

  It is possible to provide an I2C monitoring sequential read data storage device that can cope with various read methods with high versatility.

It is a conceptual diagram which illustrates the structure of the communication apparatus between a master circuit and a slave circuit. It is a figure which illustrates the structure outline | summary of the I2C monitoring sequential read data storage device corresponding to a sequential read system. It is a timing chart conceptual diagram which shows the outline | summary of the operation processing of an I2C monitoring sequential read data storage device. It is a conceptual diagram explaining three types of I2C communication systems. It is a conceptual diagram explaining the structure of the I2C monitoring sequential read data storage device concerning 1st embodiment. It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device in the case of a sequential random system. It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device in the case of a sequential random system. It is a conceptual diagram which illustrates the structure of an I2C monitoring sequential read data storage device. It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device. It is a block diagram which illustrates notionally the structural example of an I2C monitoring sequential read data storage device. It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device. It is a figure which illustrates notionally the structure outline | summary of an I2C monitoring sequential read data storage device. It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device. It is a conceptual diagram which illustrates the structure of an I2C monitoring sequential read data storage device. It is a conceptual diagram which illustrates the structure of an I2C monitoring sequential read data storage device.

Explanation of symbols

  100..Master circuit-slave circuit communication device 110.Master circuit 120.Slave circuit 130.I2C monitoring sequential read data storage device 140.I2C interface 150.Communication unit.

  A circuit that controls I2C is a master circuit, and a circuit that is controlled by I2C is a slave circuit. The slave circuit is typically a memory such as an EEPROM. The master circuit and slave circuit connected by the I2C interface may require data written in the slave circuit in a unit other than the master circuit.

  In such a case, it is preferable to acquire necessary data by monitoring the I2C interface without affecting the existing master circuit and slave circuit. The I2C monitoring read data storage device retrieves read data (also referred to as read data) when the master circuit performs read control on the slave circuit via the I2C interface. Accordingly, each embodiment will be described after the I2C reading method such as the sequential read method is described in detail.

  FIG. 1 is a conceptual diagram illustrating the configuration of a master circuit-slave circuit communication device 100. As shown in FIG. 1, the slave circuit 120 and the master circuit 110 are connected via an I2C interface 140. The I2C interface 140 includes a serial data (appropriately referred to as SDA or sda) connection line 140a and a serial clock (appropriately also referred to as SCL or scl) connection line 140b, which are connected so as to enable bidirectional communication. The

  Further, the I2C monitoring sequential read data storage device 130 is connected to the serial data connection line 140a and the serial clock connection line 140b so that the communication data of the serial data connection line 140a and the serial clock connection line 140b are respectively branched and input. Is done. The serial data connection line 140a typically transmits various information such as PI information read from the slave circuit 120 as communication data. The serial clock connection line 140b typically transmits a clock signal for synchronization between the slave circuit 120 and the master circuit 110.

  In the master circuit-slave circuit communication device 100 shown in FIG. 1, the I2C monitoring sequential read data storage device 130 transmits communication data between the slave circuit 120 and the master circuit 110 as necessary by the connection configuration described above. You can get it.

  Typically, if the slave circuit 100 is an EEPROM in which PI information is stored in advance, when the master circuit 110 reads and controls the PI information of the EEPROM, the I2C monitoring sequential read data storage device 130 passes through the I2C interface. The read PI information can be acquired and stored.

  The I2C monitoring sequential read data storage device 130 can read all data such as all PI information in the slave circuit 120 collectively in a relatively short time by one read control by reading by the sequential read method. It is. A read circuit corresponding to the sequential read method tends to be frequently used because the circuit scale can be made relatively simple and small and can be made inexpensive.

  In FIG. 1, the master circuit 110 and the I2C monitoring sequential read data storage device 130 are described as being provided in the communication unit 150, but the arrangement position of the I2C monitoring sequential read data storage device 130 is limited to this. Is not to be done. For example, the slave circuit 120 and the I2C monitoring sequential read data storage device 130 may be configured in the same unit so that the unit in which the slave circuit 120 is disposed has the function.

  Here, an outline of the configuration of the I2C monitoring sequential read data storage device 130 (1) corresponding to the sequential read method will be described. FIG. 2 is a diagram illustrating an outline of the configuration of the I2C monitoring sequential read data storage device 130 (1) that supports only the sequential read method.

  As shown in FIG. 2, the I2C monitoring sequential read data storage device 130 (1) detects that the communication start signal between the master circuit 110 and the slave circuit 120 is input from the serial data connection line 140a. The unit 210 is provided. Further, the I2C monitoring sequential read data storage device 130 (1) confirms that a communication end signal (also referred to as “nack“ Nack ”) between the master circuit 110 and the slave circuit 120 is input from the serial data connection line 140a. A nack (also referred to as “Nack”) detection unit 220 for detection is provided.

  When the start detection unit 210 detects the start signal, the set / reset unit 230 outputs an “enable” signal to the bit counter 240, and the bit counter 240 initialized by the “enable” signal starts counting up. Further, the set / reset unit 230 disables the bit counter 240 when the Nack detection unit 220 detects a communication end signal. When the next “Start” is detected, the entire I2C monitoring sequential data storage device 130 is initialized. When the entire I2C monitoring sequential read data storage device 130 (1) is initialized, the counter values of various counters provided in the I2C monitoring sequential read data storage device 130 (1) are typically reset to zero.

  When the bit counter 240 counts a total of 9 bits from 0 to 8, the byte counter 250 counts up one byte at a time from the initial value zero. Typically, 8 bits out of a total of 9 bits counted by the bit counter 240 are read data or the like, and 1 bit out of a total of 9 bits counted by the bit counter 240 is a master circuit for receiving read data. An ACK (also referred to as “Ack”) signal or a NACK signal, which is a reply from 110. The byte counter 250 is reset to zero by a communication start “Start” or a communication restart “Re Start”.

  Further, the first decoder unit 260 detects the timing of “read bit” that the master circuit 110 instructs the slave circuit 120 to read from the counter value of the byte counter 250 and the like.

  The second decoder unit 270 receives the data read from the slave circuit 120 (also referred to as “read data”) based on the counter value of the byte counter 250, and the master circuit 110 sends an acknowledgment signal to the slave circuit 120. Detect the notification timing.

  When the second decoder section 270 detects the timing of the ACK signal after “read data”, an “enable” signal is output to the address counter 290, and the address counter 290 starts counting up. The third decoder unit 2a0 detects the timing at which the read data is stored in the storage unit 2b from the counter value of the address counter 290. The address counter 290 counts up the number corresponding to the address of the slave circuit 120.

  The serial / parallel conversion unit 280 performs parallel conversion on communication data (typically, data read from the EEPROM) input from the serial data connection line 140a. The storage unit 2b stores the data converted in parallel by the serial / parallel conversion unit 280 at the timing detected by the third decoder unit 2a0.

  The storage unit 2b typically stores “read data 0”, “read data 1”,..., “Read data” sequentially acquired every 8 bits, respectively, in order as a register 2b0, a register 2b1, and a register 2bn (n Is an arbitrary natural number, typically 255), and is stored by the trigger input from the third decoder unit 2a0.

  A clock signal is input to the bit counter 240, the byte counter 250, the serial / parallel converter 280, and the address counter 290 from the serial clock connection line 140b. That is, the I2C monitoring sequential read data storage device 130 (1) performs operation processing in synchronization with the master circuit 110 and the slave circuit 120.

  FIG. 3 is a timing chart conceptual diagram showing an outline of operation processing of the I2C monitoring sequential read data storage device 130 (1). FIG. 3 illustrates a chart when the memory capacity of the slave circuit 120 is 256 bytes.

  In FIG. 3, when the start detection unit 210 detects a communication start signal, the set / reset unit 230 outputs an “enable” signal. The bit counter 240 is reset to zero by the “enable” signal and starts counting up. Further, “read data0” input from the serial data connection line 140a is stored in the register 2b0 at a timing instructed by the third decoder unit 2a0.

  On the other hand, when the second decoder unit 270 detects the timing of the Ack signal after “read data 0”, the address counter 290 starts counting up sequentially. In the sequential method, the address counter 290 sequentially counts up to 255 bytes so as to be delayed by 1 byte with respect to the count value of the byte counter 250 thereafter. That is, when the count value of the address counter 290 is 1, “read data1” is stored in the register 2b1 at a timing instructed by the third decoder unit 2a0. When the count value of the address counter 290 is 255, “read data 255” is stored in the register 2b255 at the timing indicated by the third decoder unit 2a0.

  Further, when the Nack detection unit 220 detects a Nack signal instructing the end of communication, the “enable” output of the set reset unit 230 is stopped, and the count up of the bit counter 240 is stopped. When the count-up of the bit counter 240 is stopped, the operation process of the I2C monitoring sequential read data storage device 130 (1) is stopped.

  FIG. 4 is a conceptual diagram illustrating three types of I2C communication methods. FIG. 4A is a conceptual diagram illustrating I2C communication between the master circuit 110 and the slave circuit 120 for the random read method. FIG. 4B is a conceptual diagram illustrating I2C communication between the master circuit 110 and the slave circuit 120 in the sequential read method. FIG. 4C is a conceptual diagram illustrating I2C communication between the master circuit 110 and the slave circuit 120 in the sequential random read method.

  As shown in FIG. 4A, in the random read method, the master circuit 110 transmits a communication start signal “Start” and “Device add + Write” obtained by adding a write signal to a device address that identifies the slave circuit 120. Is done.

  When the slave circuit 120 correctly receives “Device add + Write”, the slave circuit 120 returns “Ack” to the master circuit 110. If the slave circuit 120 does not correctly receive “Device add + Write”, it returns “Nack” to the master circuit 110. The case where “Device add + Write” is not correctly received includes, for example, the case where there is no slave circuit 120 corresponding to the instructed device address.

  Here, since “Nack” returned from the slave circuit 120 is different from the communication end signal, the Nack detection unit 220 does not detect it, and the operation and processing of the I2C monitoring sequential read data storage device 130 (1) are not detected. Never ends.

  Next, the master circuit 110 transmits a byte address “Byte add” designating a specific area of the slave circuit 120. The byte address is typically an address where information to be read from the EEPROM is stored.

  When the slave circuit 120 correctly receives “Byte add”, the slave circuit 120 returns Ack to the master circuit 110. If the slave circuit 120 does not correctly receive “Byte add”, it returns Nack to the master circuit 110. The case where “Byte add” is not correctly received includes, for example, the case where there is no memory area corresponding to the designated byte address.

  Next, a communication restart signal “Re Start” and “Device add + Read” obtained by adding a read signal to the device address that identifies the slave circuit 120 are transmitted from the master circuit 110.

  When the slave circuit 120 correctly receives “Device add + Read”, the slave circuit 120 returns Ack to the master circuit 110. If the slave circuit 120 does not correctly receive “Device add + Read”, it returns Nack to the master circuit 110. Further, the slave circuit 120 transmits “Read data” obtained by reading the information stored in the designated byte address to the master circuit 110.

  Finally, the master circuit 110 transmits “Nack” instructing the end of communication to the slave circuit 120, and communication between the master circuit 110 and the slave circuit 120 is ended. In the random read method, for each piece of information to be read, information for specifying the slave circuit 120 in which the information to be read is stored (corresponding to “Device add”) and information for specifying the storage location (“Byte”). add ") is instructed by the master circuit 110. Thereby, the master circuit 110 can read desired information in an arbitrary order. The above is an outline of the random read type I2C communication.

  Also, as shown in FIG. 4B, in the sequential read method, the communication start signal “Start” from the master circuit 110 and “Device add + Read” obtained by adding a read signal to the device address that identifies the slave circuit 120; Is sent.

  When the slave circuit 120 correctly receives “Device add + Read”, it returns “Ack” to the master circuit 110. If the slave circuit 120 does not correctly receive “Device add + Read”, it returns “Nack” to the master circuit 110. The case where “Device add + Read” is not correctly received includes, for example, the case where there is no slave circuit 120 corresponding to the instructed device address.

  In the sequential read method, the master circuit 110 does not need to transmit a byte address “Byte add” that designates a specific area of the slave circuit 120. The master circuit 110 typically reads all the information stored in the EEPROM sequentially from the first address.

  The designated slave circuit 120 transmits “Read data” obtained by reading the stored information to the master circuit 110. If the master circuit 110 correctly receives “Read data”, the master circuit 110 returns “Ack” to the slave circuit 120. Thereafter, the slave circuit 120 sequentially transmits “Read data” obtained by sequentially reading stored information to the master circuit 110. Also, the master circuit 110 returns “Ack” to the slave circuit 120 every time “Read data” is correctly received.

  Finally, the master circuit 110 transmits “Nack” instructing the end of communication to the slave circuit 120, and communication between the master circuit 110 and the slave circuit 120 is ended. In the sequential read method, it is not necessary for the master circuit 110 to instruct information specifying the storage location (corresponding to “Byte add”) for each piece of information to be read. Thereby, the master circuit 110 can read desired information relatively quickly. The above is an outline of the sequential read type I2C communication.

  Further, as shown in FIG. 4C, in the sequential random read system, the front stage is a random read system and the rear stage is a sequential read system. That is, since the reading method is a continuous connection of both, detailed description is avoided here in order to avoid duplication of explanation.

  In the sequential random read method, the sequential read method sequentially reads from the specific area corresponding to the byte address read last when the random read method is completed.

(First embodiment)
FIG. 5 is a conceptual diagram illustrating the configuration of the I2C monitoring sequential read data storage device 130 (2) according to the first embodiment. The I2C monitoring sequential read data storage device 130 (2) loads the byte address “Byte add” designating a specific area of the slave circuit 120 as an initial value of the address counter 290 (2). Thereby, it is possible to cope with any of the I2C reading methods of the sequential read method, the random read method, and the sequential random read method.

  In FIG. 5, the same parts as those already described in FIG. 2 are denoted by the same reference numerals, and the description is avoided here to avoid duplication of explanation, and the I2C monitoring sequential read data storage device The structure etc. which differ from 130 (1) are demonstrated.

  The I2C monitoring sequential read data storage device 130 (2) includes a byte address decoder unit 510 that detects the timing at which a byte address is transmitted from the master circuit 110. In addition, the I2C monitoring sequential read data storage device 130 (2) includes a byte address ack decoder unit 520 that detects timing at which “Ack” for byte address reception is transmitted from the slave circuit 120.

  The byte address decoder unit 510 and the byte address ACK decoder unit 520 receive the count values of the bit counter 240 (2) and the byte counter 250 (2), respectively, and the bit counter 240 (2) and the byte counter 250 (2 ) And the respective timings are detected based on the count values.

  The I2C monitoring sequential read data storage device 130 (2) includes a byte address register 530 that temporarily stores a byte address “Byte add” transmitted from the master circuit 110. The byte address register 530 acquires and stores the byte address “Byte add” converted in parallel by the serial / parallel converter 280 (2) at the timing detected by the byte address decoder 510.

  The address counter 290 (2) loads (also referred to as acquisition) the byte address “Byte add” stored in the byte address register 530 as an initial value at the timing detected by the byte address ack decoder unit 520. After that, the address counter 290 (2) starts counting up sequentially from the loaded byte address “Byte add” when the second decoder unit 270 (2) detects the “Ack” signal timing after “read data”. To do.

  Since the I2C monitoring sequential read data storage device 130 (2) has the configuration of the I2C monitoring sequential read data storage device 130 (1), the I2C monitoring sequential read data storage device 130 (2) can support the sequential method.

  FIG. 6 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (2) in the case of the random method. FIG. 6 shows an example in which the byte address “Byte add” instructed from the master circuit 110 is “7”.

  In FIG. 6, when the start detection unit 210 (2) detects the communication start signal “Start” from the master circuit 110, the set reset unit 230 (2) outputs an “enable” signal to the bit counter 240 (2). , The bit counter 240 (2) is initialized by the “enable” signal and starts counting up.

  When the byte address ack decoder 520 detects the timing at which “Ack” for byte address reception is transmitted from the slave circuit 120, the byte address “Byte add = 7” temporarily stored in the byte address register 530 is stored in the address counter. 290 (2) is loaded as an initial value.

  The read data “Read data” read from the byte address “Byte add = 7” of the slave circuit 120 is converted in parallel by the serial / parallel converter 280 (2), and then the third decoder 2a0 (2 ) Detects the timing at which the data read from the counter value of the address counter 290 (2) is stored in the storage unit 2b (2), the data is stored in the register 2b7 (2) corresponding to the byte address “Byte add = 7”. Is done.

  FIG. 7 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (2) in the case of the sequential random method. FIG. 7 shows an example in which the byte address “Byte add” reads the equivalent of 10 bytes from “7”.

  In FIG. 7, when the start detection unit 210 (2) detects the communication start signal “Start” from the master circuit 110, the set / reset unit 230 (2) outputs an “enable” signal to the bit counter 240 (2). , The bit counter 240 (2) is initialized to zero by the “enable” signal, and starts counting up at the rising edge of the clock “scl”. The byte counter 250 (2) is reset to zero by the communication start “Start” or the communication restart “Re Start”.

  When the byte address ack decoder 520 detects the timing at which “Ack” for byte address reception is transmitted from the slave circuit 120, the byte address “Byte add = 7” temporarily stored in the byte address register 530 is stored in the address counter. 290 (2) is loaded as an initial value “7”.

  The read data “Read data” read from the byte address “Byte add = 7” of the slave circuit 120 is converted in parallel by the serial / parallel converter 280 (2), and then the third decoder 2a0 (2 ) Detects the timing at which the data read from the counter value of the address counter 290 (2) is stored in the storage unit 2b (2), the data is stored in the register 2b7 (2) corresponding to the byte address “Byte add = 7”. Is done. This is the chart corresponding to the random method in the sequential random method. Thereafter, the chart corresponds to the sequential method in the sequential random method.

  When the second decoder unit 270 (2) detects the “Ack” signal timing after “read data” read from the byte address “Byte add = 7”, the second decoder unit 270 (2) detects the address counter 290. “Enable” is output to (2). The address counter 290 (2) to which “enable” is input starts counting up sequentially from the initial values 7 to 16 already loaded.

  Thereafter, as described in the sequential method, the I2C monitoring sequential read data storage device 130 (2) sequentially acquires “read data8”, “read data9”,..., “Read data16” sequentially in the register 2b8. , Registers 2b9,... Are stored in the register 2b16 by a trigger input from the third decoder unit 2a0 (2). The address counter 290 counts up the number corresponding to the address of the slave circuit 120.

  When the Nack detection unit 220 (2) detects “Nack” instructing the end of communication transmitted from the master circuit 110 to the slave circuit 120, the operation and processing of the I2C monitoring sequential read data storage device 130 (2) Ends.

(Second embodiment)
The I2C monitoring sequential read data storage device 130 (3) according to the second embodiment monitors the responses “Ack” and “Nack” from the slave circuit 120 after receiving the device address “Device add” or the byte address “Byte add”. To do.

  If either of the reply from the slave circuit 120 after receiving the device address “Device add” or the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, then the I2C monitoring sequential The read data storage device 130 (3) does not store “Read data” read from the slave circuit 120.

  If either the reply from the slave circuit 120 after receiving the device address “Device add” or the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the device address “Device add” is received. "At least one of the reply from the slave circuit 120 after reception or the reply from the slave circuit 120 after reception of the byte address" Byte add "is not normally received. It is considered that the reliability of the read data “Read data” read from “add” decreases.

  As a result, the I2C monitoring sequential read data storage device 130 (3) stores only the read data “Read data” with high reliability, so that the reliability of the stored “Read data” can be improved. it can.

  FIGS. 8 and 14 are conceptual diagrams illustrating the configuration of the I2C monitoring sequential read data storage device 130 (3). If the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the I2C monitoring sequential read data storage device 130 (3) illustrated in FIG. 8 reads “Read” read from the slave circuit 120. In this example, “data” is not stored.

  In FIG. 8, the same components as those of the already described I2C monitoring sequential read data storage device 130 (2) are denoted by corresponding reference numerals, and detailed description is avoided here in order to avoid duplication of explanation. .

  As shown in FIG. 8, the I2C monitoring sequential read data storage device 130 (3) includes an acknowledgment register 810 that temporarily stores “Ack” or “Nack” after receiving the byte address “Byte add”.

  The ACK register 810 receives the trigger from the byte address ACK decoder unit 520 (2) that detects the timing at which “Ack” or “Nack” is transmitted from the slave circuit 120 in response to the byte address reception. The “Ack” or “Nack” converted in parallel in (3) is temporarily stored.

  Further, if the temporarily stored information is “Nack”, the acknack register 810 masks the trigger output of the third decoder unit 2a0 (3). When the trigger output of the third decoder unit 2a0 (3) is masked, the storage unit 2b (3) does not store “Read data” because the timing for storing the acquired “Read data” is not given.

  The I2C monitoring sequential read data storage device 130 (3) is replaced with a byte address ack decoder unit 520 (2) that detects the timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120. Alternatively, a device address ack decoder unit that detects the timing at which “Ack” or “Nack” for device address reception is transmitted from the slave circuit 120 may be provided together with the byte address ack decoder unit 520 (2).

  Further, the I2C monitoring sequential read data storage device 130 (6) shown in FIG. 14 returns a response from the slave circuit 120 after receiving the device address “Device add” or from the slave circuit 120 after receiving the byte address “Byte add”. If at least one of the replies is “Nack”, the “Read data” read from the slave circuit 120 is not stored. Thereby, the I2C monitoring sequential read data storage device 130 (6) can hold storage data with higher reliability.

  The I2C monitoring sequential read data storage device 130 (6) replaces the byte address ack decoder unit 520 (2) included in the I2C monitoring sequential read data storage device 130 (3), and a byte address device address ack decoder unit 520 (5). Is provided.

  The byte address device address ack decoder unit 520 (5) has a timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120, and “Ack” or “Nack” for device address reception is the slave circuit 120. And the timing transmitted from.

  The ACKNACK register 810 is “Ack” or “Nack” converted in parallel by the serial / parallel converter 280 (3) in response to a trigger input from the byte address device address ACK decoder 520 (5) that has detected the above timing. Is temporarily stored.

  Further, in the I2C monitoring sequential read data storage device 130 (6), the acknowledgment register 810 masks the trigger output of the third decoder unit 2a0 (3) if the temporarily stored information is “Nack”. When the trigger output of the third decoder unit 2a0 (3) is masked, the storage unit 2b (3) does not store “Read data” because the timing for storing the acquired “Read data” is not given.

  FIG. 9 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (6) when the byte address is “7” in the random read method. As illustrated in FIG. 9, the I2C monitoring sequential read data storage device 130 (6) receives “Device add + Write” in which the write signal is added to the device address that specifies the slave circuit 120 and the reply after receiving “Nack”. The acknowledge register 810 masks the third decoder unit 2a0 (3).

  When the acknowledge register 810 masks the third decoder unit 2a0 (3), the storage unit 2b (3) is not given a timing to store the read “Read data 7”, and therefore “Read data 7” is stored in the register 2b7 ( It will not be stored in 3).

  The remaining operations and processing of the I2C monitoring sequential read data storage device 130 (6) in FIG. 9 are already described in FIG. 6 as operations and processing of the I2C monitoring sequential read data storage device 130 (2). Therefore, in order to avoid duplication of explanation, it will not be described in detail here.

  Further, the I2C monitoring sequential read data storage device 130 (6), if the reply after receiving “Device add + Read” obtained by adding a read signal to the device address specifying the slave circuit 120 is “Nack”, the acknowledge register 810. Masks the third decoder section 2a0 (3). That is, “Device add” in the second embodiment is included in both cases of “Device add + Read” and “Device add + Write”.

(Third embodiment)
The I2C monitoring sequential read data storage device 130 (4) described in the third embodiment is the same as the I2C monitoring sequential read data storage device 130 (3), 130 (6) described in the second embodiment. Instead of the register 810 (2) masking the third decoder unit 2a0 (4), the ACKNACK register 810 (2) adds the I2C monitoring sequential read data storage device 130 (4) to the Nack detection unit 220 (4) End the operation and control.

  That is, when the Nack register 810 (2) temporarily stores “Nack”, the Nack detection unit 220 (4) performs the same reset operation as when the communication end signal “Nack” is detected. 4), and the I2C communication monitoring operation ends.

  As a result, the I2C monitoring sequential read data storage device 130 (4) stops acquiring “Read data” in a situation where there may be an abnormality in the monitored I2C communication, so that data with low reliability is acquired. It is preferable because it is neither stored nor stored. In other words, for example, PI information stored in the I2C monitoring sequential read data storage device 130 (4) is only extremely reliable information.

  If either the reply from the slave circuit 120 after receiving the device address “Device add” or the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the device address “Device add” is received. "I2C monitoring sequential read data where at least one of the reply from the slave circuit 120 after reception or the reply from the slave circuit 120 after reception of the byte address" Byte add "is not normally received. Since the storage device 130 (4) stores only the read data “Read data” with high reliability, it is possible to improve the reliability of the stored “Read data”.

  FIGS. 10 and 15 are block diagrams conceptually illustrating a configuration example of the I2C monitoring sequential read data storage device 130 (4). If the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the I2C monitoring sequential read data storage device 130 (3) shown in FIG. This is a configuration example waiting for “Start”.

  In FIG. 10, the same components as those of the already described I2C monitoring sequential read data storage device 130 (3) are denoted by the corresponding reference numerals, and detailed description is avoided here to avoid duplication of explanation. .

  As illustrated in FIG. 10, the I2C monitoring sequential read data storage device 130 (4) includes an acknowledgment register 810 (2) that temporarily stores “Ack” or “Nack” after receiving the byte address “Byte add”.

  The ACKNACK register 810 (2) receives serial or parallel data in response to a trigger input from the byte address ACK decoder unit 520 (3) that detects the timing at which “Ack” or “Nack” is transmitted from the slave circuit 120 in response to byte address reception. The “Ack” or “Nack” converted in parallel by the conversion unit 280 (4) is temporarily stored.

  Further, if the temporarily stored information is “Nack”, the acknowledge register 810 (2) outputs a signal to the Nack detection unit 220 (4). Receiving the signal output, the Nack detector 220 (4) causes the set / reset unit 230 (4) to output an initialization signal. The bit counter 240 (4) to which the initialization signal of the set / reset unit 230 (4) is input stops counting up.

  Note that the I2C monitoring sequential read data storage device 130 (4) is replaced with a byte address ack decoder unit 520 (3) that detects the timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120. Alternatively, a device address ack decoder unit that detects the timing at which “Ack” or “Nack” for device address reception is transmitted from the slave circuit 120 may be provided together with the byte address ack decoder unit 520 (3).

  Further, the I2C monitoring sequential read data storage device 130 (7) shown in FIG. 15 receives a reply from the slave circuit 120 after receiving the device address “Device add” or the slave circuit 120 after receiving the byte address “Byte add”. If at least one of the replies is “Nack”, the I2C monitoring operation is stopped and the communication start signal “Start” is waited. As a result, the I2C monitoring sequential read data storage device 130 (7) can hold storage data with higher reliability.

  The I2C monitoring sequential read data storage device 130 (7) replaces the byte address ack decoder unit 520 (3) provided in the I2C monitoring sequential read data storage device 130 (4), and a byte address device address ack decoder unit 520 (6). Is provided.

  The byte address device address ack decoder unit 520 (6) has a timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120, and “Ack” or “Nack” for device address reception is the slave circuit 120. And the timing transmitted from.

  The ACK register 810 (2) receives “Ack” converted in parallel by the serial / parallel conversion unit 280 (4) in response to a trigger input from the byte address device address ACK decoder unit 520 (6) that has detected the timing described above. “Nack” is temporarily stored.

  If the information temporarily stored in the ACKNACK register 810 (2) is “Nack”, the I2C monitoring sequential read data storage device 130 (7) ends the I2C monitoring operation and waits for “Start”.

  FIG. 11 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (7) when the byte address is “7” in the random read method. As shown in FIG. 11, the I2C monitoring sequential read data storage device 130 (7), if the reply after receiving the device address “Device add” specifying the slave circuit 120 is “Nack”, the acknowledge register 810 ( 2) causes the set reset unit 230 (4) to output the same output as when the Nack detection unit 220 (4) detects the communication end signal “Nack”.

  That is, the Nack detection unit 220 (4) causes the set / reset unit 230 (4) to stop outputting the “enable” signal to stop the count up of the bit counter 240 (4).

  The remaining operations and processing of the I2C monitoring sequential read data storage device 130 (7) in FIG. 11 are already described in FIG. 6 as operations and processing of the I2C monitoring sequential read data storage device 130 (2). Therefore, in order to avoid duplication of explanation, it will not be described in detail here.

  Further, the I2C monitoring sequential read data storage device 130 (7) performs the I2C monitoring control operation if the reply after receiving “Device add + Read” obtained by adding a read signal to the device address specifying the slave circuit 120 is “Nack”. To stop. That is, “Device add” in the third embodiment is included in both cases of “Device add + Read” and “Device add + Write”.

(Fourth embodiment)
The I2C monitoring sequential read data storage device 130 (5) according to the fourth embodiment includes a slave circuit 120 that is an information acquisition target when a plurality of slave circuits 120 are I2C connected to a single master circuit 110. The expected value to be identified is compared with the acquired device address “Device add”.

  The I2C monitoring sequential read data storage device 130 (5) becomes an information acquisition target only when the expected value for specifying the slave circuit 120 that is the information acquisition target matches the acquired device address “Device add”. PI information of a specific slave circuit 120 is acquired.

  As a result, the I2C monitoring sequential read data storage device 130 (5) can acquire PI information and the like of the desired slave circuit 120 even when there are a plurality of slave circuits 120 in the connected I2C interface 140. It becomes possible.

  FIG. 12 is a diagram conceptually illustrating a configuration outline of the I2C monitoring sequential read data storage device 130 (5). In FIG. 12, the same parts as those already described in the above-described embodiment are denoted by the corresponding reference numerals, and detailed description is avoided here in order to avoid duplication of explanation.

  As illustrated in FIG. 12, the I2C monitoring sequential read data storage device 130 (5) includes a device address decoder unit 1210 that detects the timing at which the device address “Device add” is transmitted from the master circuit 110. The device address decoder 1210 detects the timing at which the device address “Device add” is transmitted from the master circuit 110 based on the counter values of the bit counter 240 (5) and the byte counter 250 (5).

  The I2C monitoring sequential read data storage device 130 (5) is a device address register that temporarily stores the device address “Device add” input from the serial data connection line 140a with the timing detected by the device address decoder unit 1210 as a trigger. 1220. The device address “Device add” temporarily stored in the device address register 1220 is data converted in parallel by the serial / parallel converter 280 (5).

  The I2C monitoring sequential read data storage device 130 (5) also compares a device address “Device add” temporarily stored in the device address register 1220 with a preset expected value, a device address expected value comparison unit. 1230.

  The expected device address comparison unit 1230 includes an expected value storage unit 1231 that stores a device address “Device add” corresponding to a specific slave circuit 120 that is an information acquisition target as an expected value. The expected value stored in the expected value storage unit 1231 may be set in advance by an operator or the like.

  If the device address expected value comparison unit 1230 compares the device address “Device add” with the expected value, and if they match, the I2C monitoring sequential read data storage device 130 (5) continues the processing and reads “Read data”. ”And memorize.

  When the device address expected value comparison unit 1230 compares the device address “Device add” with the expected value, and does not match, the device address expected value comparison unit 1230 sends a mismatch signal to the Nack detection unit 220 (5). Output. When a mismatch signal is input from the device address expected value comparison unit 1230, the Nack detection unit 220 (5) receives the I2C monitoring sequential read data storage device 130 (5) in the same manner as when the communication end signal “Nack” is detected. To stop the monitoring operation.

  In FIG. 12, the Nack detection unit 220 (5) that has received the mismatch signal causes the set / reset unit 230 (5) to output an initialization signal. The bit counter 240 (5) to which the initialization signal of the set / reset unit 230 (5) is input stops counting up. The initialization signal of the set / reset unit 230 (5) typically corresponds to a process of lowering the “enable” flag for the bit counter 240 (5).

  FIG. 13 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (5). FIG. 13 shows an example in which the byte address “Byte add” is “7”.

  As illustrated in FIG. 13, the expected value storage unit 1230 stores an expected value “A0h” corresponding to the device address of the slave circuit 120 that is an information acquisition target in advance. The device address “Device add” acquired by the I2C monitoring sequential read data storage device 130 (5) from the serial data connection line 140a is “C0h”, and a trigger from the device address decoder unit 1210 causes the device address register 1220 to store “ “C0h” is temporarily stored.

  The device address expected value comparison unit 1230 compares “C0h” stored in the device address register 1220 with the expected value “A0h” stored in advance in the expected value storage unit 1230. The device address expected value comparison unit 1230 outputs a mismatch signal to the Nack detection unit 220 (5) because the comparison result does not match.

  The Nack detection unit 220 (5) sends a trigger to reset the set reset unit 230 (5), and the set reset unit 230 (5) lowers the “enable” flag output to the bit counter 240 (5). As a result, the bit counter 240 (5) stops counting up and enters a communication start “Start” waiting state. In this case, the I2C monitoring sequential read data storage device 130 (5) does not operate until the next communication start signal “Start” is acquired.

  Thus, the I2C monitoring sequential read data storage device 130 (5) can extract normal read data even when a plurality of slave circuits 120 are connected.

(Fifth embodiment)
The I2C monitoring sequential read data storage device 130 (8) described in the fifth embodiment has the same configuration as the configuration of the I2C monitoring sequential read data storage device 130 (2) illustrated in FIG. 5 described in the first embodiment. Become.

  However, in the I2C monitoring sequential read data storage device 130 (8), the address counter 290 (2) is reset to zero only when the I2C monitoring sequential read data storage device 130 (8) is powered on (powered on). And

  Since the address counter 290 (2) is not reset except when the power is turned on, the I2C monitoring sequential read data storage device 130 (8) always holds the counter value of the address counter 290 (2) during the I2C monitoring operation. The value coincides with the byte address “Byte add” of the slave circuit 120.

  Therefore, the I2C monitoring sequential read data storage device 130 (8) always holds the same read address as that of the slave circuit 120 and acquires normal read data even when accessed alternately by various read methods. Can remember.

  The I2C monitoring sequential read data storage device 130 (8) is typically suitable when a read process is performed by the sequential read method after the random read method. After the communication between the master circuit 110 and the slave circuit 120 by the random method is completed, the last read byte address by the random method is held on the slave circuit 120 side. The slave circuit 120 only initializes the read address to zero when the power is turned on, and the last read address remains as long as the power is turned on.

  On the other hand, the I2C monitoring sequential read data storage device 130 (8) is not initialized by the communication end signal “Nack” at the time when reading by the random method is completed, and the address counter 290 (2) is based on the random method. Holds the read address at the end of the read.

  As a result, the read address held by the slave circuit 120 matches the read address held by the I2C monitoring sequential read data storage device 130 (8), and both hold even if the sequential method is subsequently shifted. It is possible to sequentially read from the address.

  Here, if the I2C monitoring sequential read data storage device 130 (8) is initialized by the communication end signal “Nack” at the time when reading by the random method is completed, the address counter 290 (2) is randomly set. The counter value becomes zero without holding the read address at the time when reading by the method is completed. In this case, the read address held by the slave circuit 120 is the last address at the time when the random read is completed. That is, if the state is shifted to the sequential read method in this state, the initial value of the read address is different between the I2C monitoring sequential read data storage device 130 (8) and the slave circuit 120, so the I2C monitoring sequential read data storage device. 130 (8) cannot acquire accurate information.

  The I2C monitoring sequential read data storage device 130 (8) described in the fifth embodiment includes a power-on reset of the address counter 290 (2) or a unit in which the I2C monitoring sequential read data storage device 130 (8) is incorporated. Since it is only at reset (however, the read target slave circuit 120 is not reset by resetting the unit), so even if I2C communication of various methods is continued, the desired information is obtained accurately. It is preferable because it can be stored.

  The configurations of the I2C monitoring sequential read data storage device 130 (1) to the I2C monitoring sequential read data storage device 130 (8) illustrated in the first to fifth embodiments will be described in each embodiment. The configuration is not limited, and the configuration can be changed as appropriate within the obvious range.

  The operations and processes of the I2C monitoring sequential read data storage device 130 (1) to the I2C monitoring sequential read data storage device 130 (8) illustrated in the first to fifth embodiments are respectively performed. It is not limited to the description in the form, and its operation and processing can be changed as appropriate within the obvious range.

  The present invention can be used for an apparatus for monitoring communication data between a master circuit and a slave circuit that communicate via an I2C interface.

Claims (12)

In an I2C monitoring sequential read data storage device for acquiring communication data between a master circuit and a slave circuit via an I2C interface,
An address counter for counting the number of addresses corresponding to the slave circuit;
An I2C monitoring sequential read data storage device characterized in that, when a byte address specifying a predetermined area of the slave circuit is acquired, the acquired byte address is used as an initial value of the address counter. The I2C monitoring sequential read data storage device according to claim 1,
A byte address register for temporarily storing the acquired byte address;
When the slave circuit returns a normal signal for reception of the byte address, the byte address temporarily stored in the byte address register is used as an initial value of the address counter. I2C monitoring sequential read data storage apparatus. In the I2C monitoring sequential read data storage device according to claim 1 or 2,
When the slave circuit that has received the device address or the byte address specifying the slave circuit has returned an abnormal signal,
An I2C monitoring sequential read data storage device characterized by not storing the acquired communication data. The I2C monitoring sequential read data storage device according to any one of claims 1 to 3,
An acknowledge register that temporarily stores a reply signal of the slave circuit that has received the device address or the byte address that identifies the slave circuit, and a timing for storing the acquired communication data by decoding the counter value of the address counter An output decoder unit,
The decoder unit does not output a timing for storing the communication data so as not to store the acquired communication data when the reply signal input from the acknack register is an abnormal signal. I2C monitoring sequential read data storage device. In the I2C monitoring sequential read data storage device according to claim 3 or 4,
When the slave circuit that has received the device address or the byte address specifying the slave circuit has returned the abnormal signal,
An I2C monitoring sequential read data storage device characterized by being initialized. The I2C monitoring sequential read data storage device according to claim 4,
A detection unit that initializes the I2C monitoring sequential read data storage device when detecting an end signal for ending communication between the master circuit and the slave circuit;
The I2C monitoring sequential read data storage device, wherein the Nack detection unit initializes the I2C monitoring sequential read data storage device when the reply signal input from the acknack register is an abnormal signal. In the I2C monitoring sequential read data storage device according to claim 1 or 2,
A plurality of the slave circuits are connected via the I2C interface;
An I2C monitoring sequential read data storage device is characterized in that a device address expected value for specifying the slave circuit to be acquired information is preset, and communication data of the slave circuit corresponding to the device address expected value is stored. I2C monitoring sequential read data storage device. The I2C monitoring sequential read data storage device according to claim 7,
An I2C monitoring sequential read data storage device includes an expected value storage unit that stores in advance a device address expected value that identifies the slave circuit that is an information acquisition target;
A device address expected value comparison unit that compares the expected device address value stored in the expected value storage unit with the acquired device address; and
The device address expected value comparison unit outputs an initialization signal of an I2C monitoring sequential read data storage device when the device address expected value is different from the acquired device address. I2C monitoring sequential read data Storage device. In the I2C monitoring sequential read data storage device according to claim 1 or 2,
The I2C monitoring sequential read data storage device, wherein the address counter is initialized only when the I2C monitoring sequential read data storage device is turned on so that the address counter matches the address count of the slave circuit. . The I2C monitoring sequential read data storage device according to claim 9,
The address counter is initial in both cases when a start signal transmitted from the master circuit to the slave circuit is acquired and when a restart signal transmitted from the master circuit to the slave circuit is acquired. An I2C monitoring sequential read data storage device, characterized in that: The I2C monitoring sequential read data storage device according to any one of claims 1 to 10,
The slave circuit is an EEPROM;
The I2C monitoring sequential read data storage device includes a storage unit that acquires and stores data stored in the predetermined area of the EEPROM read by the master circuit via the I2C interface. Sequential read data storage device. The I2C monitoring sequential read data storage device according to any one of claims 1 to 11,
The I2C monitoring sequential read data storage device is characterized in that the read method of the I2C interface is at least one of a random read method, a sequential read method, and a sequential random read method.

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