JP5070511B2 - Serial data transmission device using magnetic coupling of inductor pair - Google Patents
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本発明は、高速シリアルデータ伝送装置に関し、特にインダクタ対の磁気結合を利用することで、低消費電力及び電磁干渉（Ｅｌｅｃｔｒｏｍａｇｎｅｔｉｃ Ｉｎｔｅｒｆｅｒｅｎｃｅ；ＥＭＩ）の低減を同時に実現できるシリアルデータ伝送装置に関する。 The present invention relates to a high-speed serial data transmission apparatus, and more particularly to a serial data transmission apparatus that can simultaneously realize low power consumption and reduction of electromagnetic interference (EMI) by using magnetic coupling of an inductor pair.
数１００Ｍｂｐｓから１Ｇｂｐｓ程度までの伝送速度で、且つ、低消費電力分野向けのシリアルインタフェースの規格にＬＶＤＳ（Ｌｏｗ Ｖｏｌｔａｇｅ Ｄｉｆｆｅｒｅｎｔｉａｌ Ｓｉｇｎａｌｉｎｇ：小振幅差動信号、例えば特許文献１参照）がある。そのブロック図を図１０に示す。ＬＶＤＳでは、送信回路のドライバ回路５０で差動伝送線路５３上の電流の向きを切り替えて送信信号を作る。受信回路５１では、差動伝送線路５３の終端抵抗を用いて電流−電圧変換を行って、受信信号を得る。従って、受信信号の感度に相当する伝達インピーダンスは終端抵抗そのものであり、感度を上げて低消費電力化を狙うには、終端抵抗を大きくする必要がある。 LVDS (Low Voltage Differential Signaling: see, for example, Patent Document 1) is a serial interface standard for a low power consumption field at a transmission speed of several hundred Mbps to about 1 Gbps. The block diagram is shown in FIG. In LVDS, the driver circuit 50 of the transmission circuit switches the direction of the current on the differential transmission line 53 to generate a transmission signal. In the receiving circuit 51, current-voltage conversion is performed using a termination resistor of the differential transmission line 53 to obtain a received signal. Therefore, the transfer impedance corresponding to the sensitivity of the received signal is the termination resistance itself, and it is necessary to increase the termination resistance in order to increase the sensitivity and reduce power consumption.
一方、伝送線路による高速信号伝送では、反射による誤り率の低下を抑えるため、伝送線路の特性インピーダンスと終端抵抗を整合させる必要がある。そのため、終端抵抗の上限は伝送線路の特性インピーダンスで制限される。プリント配線基板上の伝送線路の特性インピーダンスは、マイクロストリップ等の構造から２００Ω程度が上限である。一方、差動信号伝送はＥＭＩ低減に有効とされるが、それは、伝送線路の構造において差動線路間が密に結合している場合に限られる。大きな特性インピーダンスを得るためには、差動線路間を離して疎にしなければならず、結果としてＥＭＩを劣化させる。ＥＭＩの低減には、差動線路間をより密にすることが重要であるが、これは特性インピーダンスの低下につながり、ＬＶＤＳのような終端抵抗で伝達インピーダンス、即ち受信感度が定まる装置構成の場合、低消費電力化とＥＭＩの低減は相反する要求である。 On the other hand, in high-speed signal transmission using a transmission line, it is necessary to match the characteristic impedance of the transmission line and the termination resistance in order to suppress a decrease in error rate due to reflection. Therefore, the upper limit of the termination resistance is limited by the characteristic impedance of the transmission line. The upper limit of the characteristic impedance of the transmission line on the printed wiring board is about 200Ω due to the structure of a microstrip or the like. On the other hand, differential signal transmission is effective in reducing EMI, but it is limited to the case where the differential lines are tightly coupled in the structure of the transmission line. In order to obtain a large characteristic impedance, the differential lines must be separated and made sparse, resulting in degradation of EMI. In order to reduce EMI, it is important to make the differential lines denser, but this leads to a decrease in characteristic impedance. In the case of a device configuration in which transfer impedance, that is, reception sensitivity is determined by a terminating resistor such as LVDS. Lowering power consumption and reducing EMI are conflicting requirements.
本発明では、ＬＶＤＳ方式で原理的に生じる低消費電力化とＥＭＩの低減に関するトレードオフを解消する。即ち、本発明は、低消費電力化とＥＭＩの低減を同時に実現できる高速シリアルデータ伝送装置を提供することを目的とする。 The present invention eliminates the trade-off related to low power consumption and EMI reduction that occur in principle in the LVDS system. That is, an object of the present invention is to provide a high-speed serial data transmission apparatus that can simultaneously realize low power consumption and EMI reduction.
上記目的を達成するための本発明に係るシリアルデータ伝送装置は、送信回路を第１半導体チップ内に集積してなる第１半導体集積回路と受信回路を第２半導体チップ内に集積してなる第２半導体集積回路を備え、前記第１半導体集積回路と前記第２半導体集積回路が伝送線路を介して相互に接続されてなるシリアルデータ伝送装置であって、前記受信回路と前記伝送線路間が受信側インダクタ対の電磁結合によって非接触に接続し、前記送信回路と前記伝送線路間が送信側インダクタ対の電磁結合によって非接触に接続し、前記送信回路側から前記送信側インダクタ対の一次側インダクタの自己共振による減衰振動パルスを利用して前記伝送線路に送信信号を出力し、前記受信回路が、前記伝送線路から前記受信側インダクタ対を介して受信した減衰振動パルスの立ち上がりエッジまたは立ち下がりエッジを検出して単安定な受信検出パルスを発生する回路を備え、タイミングクロックなしに受信信号を非同期検出することを第１の特徴とする。ここで、前記自己共振は、前記送信側インダクタ対の１次側インダクタのインダクタンス、寄生容量、及び、寄生抵抗による自己共振である。 In order to achieve the above object, a serial data transmission apparatus according to the present invention includes a first semiconductor integrated circuit in which a transmission circuit is integrated in a first semiconductor chip and a reception circuit in an integration of a second semiconductor chip. A serial data transmission device comprising two semiconductor integrated circuits, wherein the first semiconductor integrated circuit and the second semiconductor integrated circuit are connected to each other via a transmission line, wherein the reception circuit and the transmission line receive between Non-contact connection by electromagnetic coupling of the side inductor pair, and non-contact connection between the transmission circuit and the transmission line by electromagnetic coupling of the transmission side inductor pair, and a primary side inductor of the transmission side inductor pair from the transmission circuit side receiving of using the damped oscillation pulse by self-resonance outputs the transmission signal to said transmission line, said receiving circuit via the receiving-side inductor pair from said transmission line It detects a rising or falling edge of the damped oscillation pulse comprises a circuit for generating a single stable receiving detection pulses, the first feature to asynchronously detect the received signals without timing clock. Here, the self-resonance is self-resonance due to the inductance, parasitic capacitance, and parasitic resistance of the primary inductor of the transmission-side inductor pair.
尚、上記第１の特徴のシリアルデータ伝送装置は、好ましくは、前記受信側インダクタ対が前記第２半導体チップ内に形成され構成されているか、或いは、前記受信側インダクタ対の１次側インダクタが前記第２半導体チップ内に形成され、前記受信側インダクタ対の２次側インダクタが前記第２半導体集積回路のパッケージ基板または前記第２半導体集積回路を搭載するプリント配線基板上に形成され構成されている。 In the serial data transmission device of the first feature, preferably, the reception-side inductor pair is formed and configured in the second semiconductor chip, or the primary-side inductor of the reception-side inductor pair is Formed in the second semiconductor chip, and a secondary inductor of the receiving inductor pair is formed on a package substrate of the second semiconductor integrated circuit or a printed wiring board on which the second semiconductor integrated circuit is mounted. Yes.
尚、上記第１の特徴のシリアルデータ伝送装置は、好ましくは、前記送信側インダクタ対が前記第１半導体チップ内に形成され、前記受信側インダクタ対が前記第２半導体チップ内に形成され構成されているか、或いは、前記送信側インダクタ対の１次側インダクタが前記第１半導体チップ内に形成され、前記送信側インダクタ対の２次側インダクタが前記第１半導体集積回路のパッケージ基板または前記第１半導体集積回路を搭載するプリント配線基板上に形成され、前記受信側インダクタ対の１次側インダクタが前記第２半導体チップ内に形成され、前記受信側インダクタ対の２次側インダクタが前記第２半導体集積回路のパッケージ基板または前記第２半導体集積回路を搭載するプリント配線基板上に形成され構成されている。 In the serial data transmission device of the first feature, preferably, the transmission-side inductor pair is formed in the first semiconductor chip, and the reception-side inductor pair is formed in the second semiconductor chip. Alternatively, a primary inductor of the transmission inductor pair is formed in the first semiconductor chip, and a secondary inductor of the transmission inductor pair is a package substrate of the first semiconductor integrated circuit or the first Formed on a printed wiring board on which a semiconductor integrated circuit is mounted, a primary inductor of the receiving inductor pair is formed in the second semiconductor chip, and a secondary inductor of the receiving inductor pair is the second semiconductor; An integrated circuit package substrate or a printed wiring board on which the second semiconductor integrated circuit is mounted is formed.
更に、当該第１の特徴のシリアルデータ伝送装置において、前記送信回路から前記送信側インダクタ対の１次側インダクタに入力される電流パルスの立ち上がり時における前記送信側インダクタ対の２次側インダクタで発生する前記減衰振動パルスの立ち上がり時ピークと、前記電流パルスの立ち下がり時における前記送信側インダクタ対の２次側インダクタで発生する前記減衰振動パルスの立ち下がり時ピークが同極性で重なり合って前記送信信号の信号振幅が増大するように、前記送信パルスのパルス幅が設定されていることが好ましい。 Further, in the serial data transmission apparatus of the first aspect, the secondary side inductor of the transmitting-side inductor pair at the rising edge of current pulse input from the transmitting circuit to the primary side inductor of the transmitting-side inductor pairs The rising peak of the damped oscillation pulse generated and the falling peak of the damped oscillation pulse generated in the secondary inductor of the transmitting-side inductor pair at the falling edge of the current pulse overlap with the same polarity and overlap the transmission. The pulse width of the transmission pulse is preferably set so that the signal amplitude of the signal increases.
上記第１の特徴のシリアルデータ伝送装置は、更に、前記第１半導体チップ内と前記第２半導体チップ内の夫々に、前記送信回路と前記受信回路が切り替え動作可能に集積されてなり、前記第１半導体集積回路と前記第２半導体集積回路が夫々、送受信回路として機能することを第２の特徴とする。 In the serial data transmission device of the first feature, the transmission circuit and the reception circuit are further integrated in the first semiconductor chip and the second semiconductor chip so as to be capable of switching operation. A second feature is that each of the first semiconductor integrated circuit and the second semiconductor integrated circuit functions as a transmission / reception circuit.
上記何れかの特徴のシリアルデータ伝送装置は、更に、前記受信回路が、前記受信側インダクタ対を介して受信した減衰振動パルスの立ち上がりまたは立ち下がりエッジを検出した後、前記受信側インダクタ対の前記受信回路側に接続する１次側インダクタの両端を前記受信検出パルスの発生期間中に一時的に短絡して符号間干渉を抑制する回路を備えることが好ましい。
Any of the above serial data transmission apparatus features are further pre Symbol receiver circuit, after detecting the rising or falling edge of the damped oscillation pulse received via the reception-side inductor pair, the receiving side inductor pairs It is preferable to provide a circuit that suppresses intersymbol interference by temporarily shorting both ends of the primary inductor connected to the reception circuit side during the generation period of the reception detection pulse.
ＬＶＤＳ方式では、入力インピーダンスと伝達インピーダンスが等しいために、低消費電力化とＥＭＩの低減の両立が困難であった。上記何れかの特徴のシリアルデータ伝送装置によれば、少なくとも受信回路と伝送線路間が、受信側インダクタ対の電磁結合により非接触に結合しているので、入力インピーダンスと伝達インピーダンスを独立に設計できるため、低消費電力化とＥＭＩの低減を同時に実現できる。即ち、ＥＭＩの低減のため入力インピーダンスを低く保ったまま、受信感度を上げるべく伝達インピーダンスを大きくすることができる。 In the LVDS system, since the input impedance and the transfer impedance are equal, it is difficult to achieve both low power consumption and EMI reduction. According to the serial data transmission device having any of the above characteristics, at least the receiving circuit and the transmission line are coupled in a non-contact manner by electromagnetic coupling of the receiving inductor pair, so that the input impedance and the transfer impedance can be designed independently. Therefore, low power consumption and EMI reduction can be realized at the same time. That is, the transmission impedance can be increased to increase the reception sensitivity while keeping the input impedance low to reduce the EMI.
また、ＬＶＤＳでは電源から直流的に送信電流が流れているが、更に、送信回路と伝送線路間も送信側インダクタ対の電磁結合により非接触に結合することで、電源からの送信電流はパルス的に流れ、且つ、パルス幅も短いため、平均電源電流を極めて小さくできる。また、送信側インダクタ対は同相差動変換器としても動作しており、その同相除去比は非常に大きい。そのため、ＥＭＩが生じるもうひとつの原因である同相信号が伝送線路上に伝わることがなく、ＥＭＩ低減に非常に有効である。加えて、非接触接続のため、ＩＣチップに静電気破壊防止回路（ＥＳＤ保護回路）が必要なく、広帯域化が実現できる。 In LVDS, a transmission current flows from a power source in a DC manner. Furthermore, the transmission current from the power source is pulse-like by coupling the transmission circuit and the transmission line in a non-contact manner by electromagnetic coupling of the transmission-side inductor pair. In addition, since the pulse width is short, the average power supply current can be made extremely small. The transmission-side inductor pair also operates as a common-mode differential converter, and its common-mode rejection ratio is very large. For this reason, the in-phase signal, which is another cause of EMI, is not transmitted on the transmission line, which is very effective in reducing EMI. In addition, because of the non-contact connection, the IC chip does not require an electrostatic breakdown prevention circuit (ESD protection circuit), and a wide band can be realized.
次に、本発明に係るシリアルデータ伝送装置（適宜、「本発明装置」と称する）の一実施形態における構成及び動作について、図面を参照して説明する。 Next, the configuration and operation of an embodiment of a serial data transmission apparatus according to the present invention (referred to as “the present invention apparatus” as appropriate) will be described with reference to the drawings.
図１に、本発明装置の概略の構成例を模式的に示す。図１に示すように、本発明装置１は、プリント配線基板２上の離間した位置に夫々フリップチップ実装された第１半導体集積回路１０と第２半導体集積回路２０を備え、第１半導体集積回路１０と第２半導体集積回路２０が、プリント配線基板２上に形成された２本のストリップ線路からなる伝送線路３を介して相互に接続されて構成される。 FIG. 1 schematically shows a schematic configuration example of the apparatus of the present invention. As shown in FIG. 1, the device 1 of the present invention includes a first semiconductor integrated circuit 10 and a second semiconductor integrated circuit 20 which are flip-chip mounted at spaced positions on a printed wiring board 2, respectively. 10 and the second semiconductor integrated circuit 20 are connected to each other via a transmission line 3 formed of two strip lines formed on the printed wiring board 2.
また、図２に、本発明装置１の概略のブロック構成を模式的に示す。図２に示すように、第１半導体集積回路１０は、シリアルデータの送信回路１１と１対の送信側インダクタ対（トランス）１２、１３を共通の第１半導体チップ内に集積して構成されている。また、第２半導体集積回路２０は、シリアルデータの受信回路２１と１対の受信側インダクタ対（トランス）２２、２３を共通の第２半導体チップ内に集積して構成されている。送信側インダクタ対の１次側インダクタ１２は送信回路１１に接続し、送信側インダクタ対の２次側インダクタ１３は第１半導体チップの２つの電極パッド１４、１５に接続し、当該２つの電極パッド１４、１５が夫々伝送線路３の送信側の２つの終端部とフリップチップ実装により電気的に接続している。また、受信側インダクタ対の１次側インダクタ２２は受信回路２１に接続し、受信側インダクタ対の２次側インダクタ２３は第２半導体チップの２つの電極パッド２４、２５に接続し、当該２つの電極パッド２４、２５が夫々伝送線路３の受信側の２つの終端部とフリップチップ実装により電気的に接続している。これにより、送信回路１１と伝送線路３間が送信側インダクタ対１２、１３の電磁結合（トランス結合）によって、受信回路２１と伝送線路３間が受信側インダクタ対２２、２３の電磁結合（トランス結合）によって非接触に接続している。これにより、本発明装置１によって第１半導体集積回路１０と第２半導体集積回路２０間のポイント−ポイント接続のチップ間伝送網が構築される。 FIG. 2 schematically shows a schematic block configuration of the device 1 of the present invention. As shown in FIG. 2, the first semiconductor integrated circuit 10 is configured by integrating a serial data transmission circuit 11 and a pair of transmission-side inductor pairs (transformers) 12 and 13 in a common first semiconductor chip. Yes. The second semiconductor integrated circuit 20 is formed by integrating a serial data receiving circuit 21 and a pair of receiving inductor pairs (transformers) 22 and 23 in a common second semiconductor chip. The primary inductor 12 of the transmission inductor pair is connected to the transmission circuit 11, and the secondary inductor 13 of the transmission inductor pair is connected to the two electrode pads 14 and 15 of the first semiconductor chip. 14 and 15 are electrically connected to the two terminal portions on the transmission side of the transmission line 3 by flip chip mounting. The primary inductor 22 of the receiving inductor pair is connected to the receiving circuit 21, and the secondary inductor 23 of the receiving inductor pair is connected to the two electrode pads 24, 25 of the second semiconductor chip. The electrode pads 24 and 25 are electrically connected to the two terminal portions on the receiving side of the transmission line 3 by flip chip mounting. As a result, the transmission circuit 11 and the transmission line 3 are electromagnetically coupled (transformer coupling) between the transmission-side inductor pairs 12 and 13, and the reception circuit 21 and the transmission line 3 are electromagnetically coupled (transformer coupling) between the reception-side inductor pairs 22 and 23. ) Contactlessly connected. As a result, a point-to-point connection interchip transmission network between the first semiconductor integrated circuit 10 and the second semiconductor integrated circuit 20 is constructed by the device 1 of the present invention.
送信側インダクタ対１２、１３と受信側インダクタ対２２、２３は、夫々第１半導体チップと第２半導体チップにおいて夫々の金属配線層を用いて形成される。図３に示すように、例えば、多層金属配線を利用する場合には、送信側インダクタ対の２次側インダクタ１３が最上層の金属配線を用いて開ループ或いはスパイラル状に形成され、送信側インダクタ対の１次側インダクタ１２が最上層より下位の１層以上の金属配線を用いて、２次側インダクタ１３の下方に開ループ或いはスパイラル状に形成される。受信側インダクタ対２２、２３についても送信側インダクタ対１２、１３と同様に形成される。このように半導体チップの金属配線層を用いて形成された各インダクタ対は、半導体製造技術による加工精度で実現できるため、インダクタ素子としての再現性が良く、また、１次側と２次側インダクタ間に１に近い理想的な結合係数が得られる。 The transmission-side inductor pairs 12 and 13 and the reception-side inductor pairs 22 and 23 are formed using respective metal wiring layers in the first semiconductor chip and the second semiconductor chip, respectively. As shown in FIG. 3, for example, when using multilayer metal wiring, the secondary inductor 13 of the transmission-side inductor pair is formed in an open loop or spiral using the uppermost metal wiring, and the transmission-side inductor is formed. The paired primary inductors 12 are formed in an open loop or spiral shape below the secondary inductor 13 using one or more layers of metal wiring lower than the uppermost layer. The reception-side inductor pairs 22 and 23 are formed in the same manner as the transmission-side inductor pairs 12 and 13. Thus, each inductor pair formed using the metal wiring layer of the semiconductor chip can be realized with processing accuracy by semiconductor manufacturing technology, so that the reproducibility as an inductor element is good, and the primary side and secondary side inductors are also provided. An ideal coupling coefficient close to 1 is obtained in between.
図４に、第１半導体集積回路１０の送信回路１１の回路構成例を、送信側インダクタ対１２、１３の等価回路とともに示す。図４中のＣとＲは、１次側インダクタ１２の寄生容量、寄生抵抗であり、インダクタンスＬと寄生抵抗Ｒと寄生容量Ｃの直並列回路によって１次側インダクタ１２の等価回路が表される。１次側インダクタ１２の一方端１２ａは電源に接続され、他方端１２ｂはスイッチとして動作するＮＭＯＳＦＥＴ１６を介して接地される。ＮＭＯＳＦＥＴ１６をオンオフすることで、１次側インダクタ１２に流れる電流を制御する。 FIG. 4 shows a circuit configuration example of the transmission circuit 11 of the first semiconductor integrated circuit 10 together with equivalent circuits of the transmission-side inductor pairs 12 and 13. C and R in FIG. 4 are the parasitic capacitance and parasitic resistance of the primary inductor 12, and an equivalent circuit of the primary inductor 12 is represented by a series-parallel circuit of the inductance L, the parasitic resistance R, and the parasitic capacitance C. . One end 12a of the primary inductor 12 is connected to a power source, and the other end 12b is grounded via an NMOSFET 16 that operates as a switch. By turning the NMOSFET 16 on and off, the current flowing through the primary inductor 12 is controlled.
ＮＭＯＳＦＥＴ１６のゲート端子１７に入力する送信パルスＶｉｎを図５上段の電圧波形で制御した場合を考える。１次側及び２次側の自己インダクタンスを夫々Ｌ１、Ｌ２とする。Ｌ２＝Ｌ１／ｎ２（ｎは巻き線比、ｎ＞５程度）を実現すると、ＮＭＯＳＦＥＴ１６をオンした場合の１次側インダクタ１２に流れる電流ｉ１Ｔ（ｔ）は、以下の数１で表される。 Consider a case where the transmission pulse Vin input to the gate terminal 17 of the NMOSFET 16 is controlled by the voltage waveform in the upper stage of FIG. Let L1 and L2 be self-inductances on the primary side and the secondary side, respectively. When L2 = L1 / n 2 (n is the winding ratio, n> 5), the current i 1T (t) flowing through the primary inductor 12 when the NMOSFET 16 is turned on is expressed by the following equation ( 1 ). The
但し、Ｅ、Ｒ、Ｒｏｎ、ｔは、夫々、電源電圧、１次側インダクタ１２の寄生抵抗、ＮＭＯＳＦＥＴ１６のオン抵抗、時間を表す。１次側インダクタ１２に流れる電流ｉ１Ｔ（ｔ）の電流波形を図５中段に示す。図５中段に示すように、ＮＭＯＳＦＥＴ１６をオンすると、１次側インダクタ電流ｉ１Ｔ（ｔ）は時間ｔの経過とともにＥ／（Ｒ＋Ｒｏｎ）で表される電流値に飽和する。引き続き、ＭＯＳＦＥＴ８をオフすると、２次側インダクタ１３に流れる電流ｉ２Ｔ（ｔ）は、以下の数２で表される。 However, E, R, Ron, and t represent the power supply voltage, the parasitic resistance of the primary inductor 12, the on-resistance of the NMOSFET 16, and the time, respectively. The current waveform of the current i 1T (t) flowing through the primary inductor 12 is shown in the middle part of FIG. As shown in the middle part of FIG. 5, when the NMOSFET 16 is turned on, the primary inductor current i 1T (t) saturates to a current value represented by E / (R + Ron) as time t elapses. Subsequently, when the MOSFET 8 is turned off, the current i 2T (t) flowing through the secondary inductor 13 is expressed by the following formula 2.
但し、ｋ、ＲＴＬ、Ｃ、ｔｏｆｆは、夫々、送信側インダクタ対１２、１３間の結合係数、伝送線路３の特性インピーダンス、１次側インダクタ１２の寄生容量、ＮＭＯＳＦＥＴ１６がオフした時刻を表す。２次側インダクタ電流ｉ２Ｔ（ｔ）の電流波形を図５下段に示す。図５下段に示すように、２次側インダクタ１３に誘導される電流は減衰振動波形であり、その周波数ω０は１次側インダクタ１２の自己共振周波数に等しい。 Here, k, R TL , C, and t off represent the coupling coefficient between the transmission-side inductor pairs 12 and 13, the characteristic impedance of the transmission line 3, the parasitic capacitance of the primary-side inductor 12, and the time when the NMOSFET 16 is turned off, respectively. . The current waveform of the secondary inductor current i 2T (t) is shown in the lower part of FIG. As shown in the lower part of FIG. 5, the current induced in the secondary inductor 13 is a damped oscillation waveform, and its frequency ω 0 is equal to the self-resonant frequency of the primary inductor 12.
また、以上の解析から１次側インダクタ電流ｉ１Ｔ（ｔ）は飽和電流値Ｅ／（Ｒ＋Ｒｏｎ）に達すれば十分であり、言い換えれば、飽和電流値に達した以降に電源から供給される電力は伝送線路３上には伝達されず、ＮＭＯＳＦＥＴ１６のオン抵抗及び１次側インダクタ１２の寄生抵抗Ｒで無駄に消費される。電力効率を考えると、飽和電流値に達するまでの短パルスでＮＭＯＳＦＥＴ１６のゲート電圧を制御することで、電流が流れる時間を小さくして、消費電力を抑えることができる。 From the above analysis, it is sufficient that the primary inductor current i 1T (t) reaches the saturation current value E / (R + Ron). In other words, the power supplied from the power source after reaching the saturation current value is It is not transmitted onto the transmission line 3 and is wasted due to the on-resistance of the NMOSFET 16 and the parasitic resistance R of the primary-side inductor 12. Considering the power efficiency, by controlling the gate voltage of the NMOSFET 16 with a short pulse until the saturation current value is reached, the time during which the current flows can be shortened and the power consumption can be suppressed.
更に、図６に示すように、ＮＭＯＳＦＥＴ１６のゲート端子１７に入力する送信パルスＶｉｎ（図６上段）のパルス幅を共振周波数の周期の１／２に設定し、送信パルスＶｉｎの立ち上がり時と立ち下がり時（つまり、１次側インダクタ電流ｉ１Ｔ（ｔ）の立ち上がり時と立ち下がり時）における２次側インダクタ１３の端子間の減衰振動パルスＶ２Ｔ（図６下段）の電圧波形の同極性のピークを重ね合わせることにより、大きな信号振幅を得ることができる。つまり、立ち上がり時ピークと立ち下がり時ピークの重ね合わせにより、送信側インダクタ対に流れる電流を抑えたまま伝送線路３の受信端での受信信号振幅を大きくできるため、低消費電力化が図れる。尚、図６中段には、２次側インダクタ電流ｉ２Ｔ（ｔ）を示す。 Further, as shown in FIG. 6, the pulse width of the transmission pulse Vin (upper stage in FIG. 6) input to the gate terminal 17 of the NMOSFET 16 is set to ½ of the period of the resonance frequency, and the rising and falling edges of the transmission pulse Vin. Peak of the same polarity of the voltage waveform of the damped oscillation pulse V 2T (lower stage in FIG. 6) between the terminals of the secondary inductor 13 at the time (that is, when the primary inductor current i 1T (t) rises and falls) A large signal amplitude can be obtained by superimposing. In other words, by superimposing the rising peak and the falling peak, the received signal amplitude at the receiving end of the transmission line 3 can be increased while suppressing the current flowing through the transmitting inductor pair, so that power consumption can be reduced. In the middle part of FIG. 6, secondary inductor current i 2T (t) is shown.
図７に、受信側インダクタ対２２、２３の等価回路を示す。送信側インダクタ対と同様に、図７中のＣとＲは、１次側インダクタ２２の寄生容量、寄生抵抗であり、インダクタンスＬと寄生抵抗Ｒと寄生容量Ｃの直並列回路によって１次側インダクタ２２の等価回路が表される。巻き線比ｎ、受信側インダクタ対２２、２３間の結合係数ｋ、及び、各回路定数Ｌ，Ｃ，Ｒは、送信側インダクタ対と同じである場合を想定する。電流源１２は伝送線路３上を伝播してきた電流パルスｉＴＬをモデル化している。解析を簡単にするため電流パルスｉＴＬをステップパルスで近似すると、１次側インダクタ２２の両端（オープン端）に生じる受信電圧Ｖ１Ｒ（ｔ）は、以下の数３で表される。 FIG. 7 shows an equivalent circuit of the receiving-side inductor pair 22, 23. Similarly to the transmitting-side inductor pair, C and R in FIG. 7 are the parasitic capacitance and parasitic resistance of the primary-side inductor 22, and the primary-side inductor is constituted by a series-parallel circuit of the inductance L, the parasitic resistance R, and the parasitic capacitance C. 22 equivalent circuits are represented. It is assumed that the winding ratio n, the coupling coefficient k between the receiving-side inductor pairs 22 and 23, and the circuit constants L, C, and R are the same as those of the transmitting-side inductor pair. The current source 12 models the current pulse i TL that has propagated on the transmission line 3. When the current pulse i TL is approximated by a step pulse in order to simplify the analysis, the received voltage V 1R (t) generated at both ends (open end) of the primary inductor 22 is expressed by the following Equation 3.
送信側インダクタ対の１次側インダクタ１２に流れる電流ｉ１Ｔ（ｔ）と受信側インダクタ対の１次側インダクタ２２に生じる受信電圧波形Ｖ１Ｒ（ｔ）の振幅比が等価的な伝達インピーダンスＺｅｑである。以上の結果から、この伝達インピーダンスＺｅｑを導出すると、以下の数４に示すようになる。 A transfer impedance Z eq in which the amplitude ratio of the current i 1T (t) flowing in the primary inductor 12 of the transmitting inductor pair and the received voltage waveform V 1R (t) generated in the primary inductor 22 of the receiving inductor pair is equivalent. It is. From this result, when the transfer impedance Z eq is derived, the following equation 4 is obtained.
一方、図８に示す受信側インダクタ対２２、２３の伝送線路３側から見た入力インピーダンスＺｉｎは、以下の数５に示すようになる。 On the other hand, the input impedance Z in viewed from the transmission line 3 side of the receiving-side inductor pair 22 and 23 shown in FIG.
尚、入力インピーダンスＺｉｎに虚数部を生じるが、数５の第２式で表される係数ｍを大きく設計することで、実数部に対する相対値を小さくできる。以上のように、本発明装置では、受信感度である伝達インピーダンスＺｅｑと入力インピーダンスＺｉｎを独立に設計可能である。 Although an imaginary part is generated in the input impedance Z in , the relative value with respect to the real part can be reduced by designing the coefficient m expressed by the second equation of Formula 5 to be large. As described above, in the device of the present invention, the transfer impedance Z eq and the input impedance Z in which are reception sensitivities can be designed independently.
送信側及び受信側インダクタ対の等価回路における上記の各パラメータ値は電磁界シミュレータを用いることによって解析することができる。受信側インダクタ対の入力インピーダンスＺｉｎが自己共振周波数ω０上で、Ｒ＋ｊＸ＝３８＋１５ｊ［Ω］であるような伝送回路のシミュレーション結果を、図９の左列に示す。伝送線路３はプリント配線基板２上の長さ３０ｃｍの差動伝送線路をモデル化している。図９左列の最上段から順番に、送信回路１１のＮＭＯＳＦＥＴ１６のゲート入力信号（送信パルス）Ｖｉｎ、送信側インダクタ対の１次側インダクタ電流ｉ１Ｔ（ｔ）、送信側インダクタ対の２次側インダクタ電流ｉ２Ｔ（ｔ）、受信側インダクタ対の１次側での受信電圧波形Ｖ１Ｒ（ｔ）を表す。シミュレーション結果から伝達インピーダンスＺｅｑは２００Ωであり、入力インピーダンスＺｉｎと伝達インピーダンスＺｅｑが独立に実現されていることがわかる。即ち、入力インピーダンスが３８Ωとなり、伝達インピーダンスが２００Ωとなる。従って、伝送線路３の特性インピーダンスを３８Ωと小さく設定でき、差動線路間を密に接近させＥＭＩを低く抑えることができる。一方、受信感度である伝達インピーダンスは２００Ωと大きく、送信電流を小さく抑えても、大きな受信電圧信号が得られるため、低消費電力化も同時に実現できる。 Each parameter value in the equivalent circuit of the transmission side and reception side inductor pair can be analyzed by using an electromagnetic field simulator. The simulation result of the transmission circuit in which the input impedance Z in of the receiving-side inductor pair is R + jX = 38 + 15j [Ω] on the self-resonant frequency ω 0 is shown in the left column of FIG. The transmission line 3 models a differential transmission line having a length of 30 cm on the printed wiring board 2. The gate input signal (transmission pulse) Vin of the NMOSFET 16 of the transmission circuit 11, the primary side inductor current i 1T (t) of the transmission side inductor pair, and the secondary side of the transmission side inductor pair in order from the top row in the left column of FIG. The inductor current i 2T (t) and the reception voltage waveform V 1R (t) on the primary side of the reception-side inductor pair are represented. The simulation result shows that the transfer impedance Z eq is 200Ω, and the input impedance Z in and the transfer impedance Z eq are realized independently. That is, the input impedance is 38Ω and the transfer impedance is 200Ω. Therefore, the characteristic impedance of the transmission line 3 can be set as small as 38Ω, and the differential lines can be closely approached to keep the EMI low. On the other hand, the transmission impedance, which is the reception sensitivity, is as large as 200Ω, and even if the transmission current is kept small, a large reception voltage signal can be obtained.
図９左列の受信電圧波形Ｖ１Ｒ（ｔ）に注目すると、最大振幅に比して、０．３倍程度の反射波形が生じている。減衰振動パルスの振動周波数上でインピーダンス整合しているが、減衰振動パルスのパワースペクトラムが広がりを持つので、整合条件は完全には満たされていないためである。反射信号を抑えるには、図９右列の上部の回路図に示すように、数Ω程度の抵抗を直列に挿入する。このような低抵抗は、２次側インダクタ２３と電極パッド２４、２５間に形成する配線抵抗によって容易に実現できる。５Ωの抵抗を挿入した場合のシミュレーション結果を図９右列の各段に示す。伝達インピーダンスＺｅｑは１６０Ωに低下するが、反射信号は０．１倍未満に抑制されている。 When attention is paid to the reception voltage waveform V 1R (t) in the left column of FIG. 9, a reflection waveform about 0.3 times as large as the maximum amplitude is generated. This is because the impedance matching is performed on the vibration frequency of the damped vibration pulse, but the power condition of the damped vibration pulse has a spread, and the matching condition is not completely satisfied. In order to suppress the reflected signal, a resistance of about several Ω is inserted in series as shown in the upper circuit diagram of the right column of FIG. Such a low resistance can be easily realized by a wiring resistance formed between the secondary inductor 23 and the electrode pads 24 and 25. The simulation result when a 5Ω resistor is inserted is shown in each stage in the right column of FIG. The transfer impedance Z eq is reduced to 160Ω, but the reflected signal is suppressed to less than 0.1 times.
１Ｇｂｐｓの伝送速度を仮定した場合のＬＶＤＳと本発明装置１の送信回路１１が必要とする平均電源電流の比較を行う。先のシミュレーションから、本発明装置１における送信パルスを含む１ｎｓの時間範囲で電源電流を平均化すると、０．４ｍＡであった。即ち、１Ｇｂｐｓの伝送速度では、送信回路は平均０．４ｍＡの電源電流を必要とする。これに対して、ＬＶＤＳの規格では、最も小さい場合でも、送信回路は３．５ｍＡの電源電流が必要である。一方、受信電圧信号に注目すると、ＬＶＤＳの場合は３．５ｍＡの送信電流に対して ３５０ｍＶである。図９に示すように、本発明装置１では、明らかに３５０ｍＶ以上の振幅が得られているにも拘らず、送信電流は９分の１に低減できている。本発明装置１では、送信電流は送信側インダクタ対の１次側インダクタに流れる電流であり、図９に示すように、この電流はパルス幅０．２５ｎｓのパルス電流である。伝達インピーダンスは２００Ωであり、ＬＶＤＳの規格である１００Ωに対して２倍の改善に留まるが、ＬＶＤＳの送信電流が直流的に常に流れているのに対して、本発明装置１ではパルス幅０．２５ｎｓのパルス電流を１ｎｓの時間範囲で平均化できるため、全体として９分の１に低減できる。 A comparison is made between the LVDS assuming a transmission rate of 1 Gbps and the average power supply current required by the transmission circuit 11 of the device 1 of the present invention. From the previous simulation, when the power supply current was averaged in the time range of 1 ns including the transmission pulse in the device 1 of the present invention, it was 0.4 mA. That is, at a transmission rate of 1 Gbps, the transmission circuit requires an average power supply current of 0.4 mA. On the other hand, according to the LVDS standard, the transmission circuit requires a power supply current of 3.5 mA even in the smallest case. On the other hand, paying attention to the reception voltage signal, in the case of LVDS, it is 350 mV for a transmission current of 3.5 mA. As shown in FIG. 9, in the device 1 of the present invention, the transmission current can be reduced to 1/9 although the amplitude of 350 mV or more is clearly obtained. In the device 1 of the present invention, the transmission current is a current flowing through the primary inductor of the transmission inductor pair, and as shown in FIG. 9, this current is a pulse current having a pulse width of 0.25 ns. The transfer impedance is 200Ω, which is only twice as good as the LVDS standard of 100Ω. However, the transmission current of the LVDS always flows in a direct current, whereas the device 1 of the present invention has a pulse width of 0. Since the pulse current of 25 ns can be averaged over a time range of 1 ns, it can be reduced to 1/9 as a whole.
次に、ＥＭＩについてＬＶＤＳと本発明装置１の比較を行う。図１０に示すようなＬＶＤＳのドライバ回路５０を駆動するためには、相補的にゲートを制御する差動制御信号５２が必要である。図１１に示すように、これらの差動制御信号にペア内スキューが生じる、或いは、エッジレートが不揃いになると差動伝送線路上に同相信号が重畳する。差動伝送線路上の同相信号は大きな遠方電磁界を生じさせ、ＥＭＩを劣化させる。本発明装置１の場合、図４に示すように、送信回路１１の制御信号（入力パルスＶｉｎ）はシングルエンドであり、原理的にペア内スキューやエッジレートの不揃いが生じない。斯かるシングルエンドのドライバにも拘らず、伝送線路３上に同相信号が重畳しないのは、送信側インダクタ対が同相差動変換器として動作しており、更に、その同相除去比が極めて大きいからである。即ち、本発明装置１はＥＭＩを劣化させる同相信号の除去能力が高く、ＥＭＩ低減に大きな効果がある。 Next, the LVDS and the device 1 of the present invention are compared for EMI. In order to drive the LVDS driver circuit 50 as shown in FIG. 10, a differential control signal 52 for controlling the gates in a complementary manner is required. As shown in FIG. 11, in-pair skew occurs in these differential control signals, or in-phase signals are superimposed on the differential transmission line when the edge rates are not uniform. The in-phase signal on the differential transmission line creates a large far electromagnetic field and degrades EMI. In the case of the device 1 of the present invention, as shown in FIG. 4, the control signal (input pulse Vin) of the transmission circuit 11 is single-ended, and in principle there is no in-pair skew or uneven edge rate. In spite of such a single-ended driver, the common-mode signal is not superimposed on the transmission line 3 because the transmission-side inductor pair operates as a common-mode differential converter, and the common-mode rejection ratio is extremely large. Because. That is, the device 1 of the present invention has a high ability to remove in-phase signals that degrade EMI, and has a great effect on EMI reduction.
次に、第２半導体集積回路２０の受信回路２１の回路構成例とその回路動作について説明する。 Next, a circuit configuration example and circuit operation of the receiving circuit 21 of the second semiconductor integrated circuit 20 will be described.
受信側インダクタ対２２，２３を介して受信回路２１に入力される受信電圧波形は数ＧＨｚの振動減衰波形である。従って、図１２に示すように、通常のラッチ・コンパレータ５４で信号検出を行う場合、タイミング精度は、伝送速度とは無関係に減衰振動波形の周波数で定まり、タイミングクロックに対するタイミング余裕Ｔｍが狭くタイミング設計は非常に難しい。そこで、本実施形態では、信号検出にタイミングクロックを必要としない非同期検出法を導入する。即ち、受信回路２１を図１３に示す回路構成とし、受信した減衰振動パルスをタイミングクロックなしに電源電圧レベルの振幅のパルス列に再生する。 The reception voltage waveform input to the reception circuit 21 via the reception-side inductor pair 22 and 23 is a vibration attenuation waveform of several GHz. Therefore, as shown in FIG. 12, when signal detection is performed by a normal latch / comparator 54, the timing accuracy is determined by the frequency of the damped oscillation waveform regardless of the transmission speed, and the timing margin Tm with respect to the timing clock is narrow. Is very difficult. Therefore, in this embodiment, an asynchronous detection method that does not require a timing clock for signal detection is introduced. That is, the receiving circuit 21 has the circuit configuration shown in FIG. 13, and the received damped oscillation pulse is reproduced into a pulse train having an amplitude of the power supply voltage level without a timing clock.
以下、図１３に示す受信回路２１の回路動作を説明する。動作時の各節点の電圧波形を図１４に示す。受信側インダクタ対の１次側インダクタ２２の一方端を接地すると、他方端に中心電位０Ｖの減衰振動パルスＶ１Ｒが励起される。この減衰振動パルスＶ１Ｒを、コンデンサＣｃ、抵抗Ｒｏ、及び、バイアス回路３０によってレベルシフトして、中心電位がＶｂｎの振動波形Ｖ３Ｒ（図１４上段）をＮＭＯＳＦＥＴ３１のゲート端子に入力する。図１５に、バイアス回路３０の回路構成例を示す。図１５に示すバイアス回路３０の出力Ｂｉａｓ−ｐが抵抗Ｒｏに接続している。尚、図１５中のＰＭＯＳＦＥＴ３７は、バイアス動作中はオフしている。 Hereinafter, the circuit operation of the receiving circuit 21 shown in FIG. 13 will be described. FIG. 14 shows the voltage waveform at each node during operation. Grounding the one end of the receiving inductor pair of the primary inductor 22, damped oscillation pulse V 1R central potential 0V is excited at the other end. The level of the damped oscillation pulse V 1R is shifted by the capacitor Cc, the resistor Ro, and the bias circuit 30, and the oscillation waveform V 3R (upper stage in FIG. 14) whose center potential is Vbn is input to the gate terminal of the NMOSFET 31. FIG. 15 shows a circuit configuration example of the bias circuit 30. The output Bias-p of the bias circuit 30 shown in FIG. 15 is connected to the resistor Ro. Note that the PMOSFET 37 in FIG. 15 is off during the bias operation.
図１３の受信回路２１において、ＮＭＯＳＦＥＴ３１のドレイン端子にＰＭＯＳＦＥＴ３３のドレイン端子が接続して中間ノードＮ１となり、ＮＭＯＳＦＥＴ３１のソース端子を接地し、ＰＭＯＳＦＥＴ３３のソース端子を電源に接続して、中間ノードＮ１をダイナミックに充放電されるノードとする。中間ノードＮ１が電源電圧ＶＤＤに充電されている場合に、ＮＭＯＳＦＥＴ３１のゲート端子に入力する振動波形Ｖ３ＲによってＮＭＯＳＦＥＴ３１が導通して、中間ノードＮ１が接地電圧（０Ｖ）まで放電される。中間ノードＮ１の当該電源電圧ＶＤＤから接地電圧までの電圧遷移が２段のインバータで構成される遅延回路３２を介して一定時間遅延してＰＭＯＳＦＥＴ３３のゲート端子に伝達する（図１４中段の電圧パルスＶ４Ｒ）。そうすると、ＰＭＯＳＦＥＴ３３が導通して、再び中間ノードＮ１が電源電圧ＶＤＤに充電される。以上の自己プリチャージ動作により受信した減衰振動パルスＶ１Ｒを、例えばノードＮ２において電源電圧レベルの振幅の電圧パルスＶ５Ｒとして再生できる（図１４下段）。 In the receiving circuit 21 of FIG. 13, the drain terminal of the PMOSFET 33 is connected to the drain terminal of the NMOSFET 31 to become the intermediate node N1, the source terminal of the NMOSFET 31 is grounded, the source terminal of the PMOSFET 33 is connected to the power source, and the intermediate node N1 is dynamically The node is charged and discharged. If the intermediate node N1 is charged to the power supply voltage VDD, and conducts the NMOSFET 31 by the vibration waveform V 3R inputted to the gate terminal of the NMOSFET 31, the intermediate node N1 is discharged to the ground voltage (0V). A voltage transition from the power supply voltage VDD to the ground voltage at the intermediate node N1 is delayed for a predetermined time through a delay circuit 32 formed of a two-stage inverter and transmitted to the gate terminal of the PMOSFET 33 (the voltage pulse V in the middle stage in FIG. 14). 4R ). As a result, the PMOSFET 33 becomes conductive, and the intermediate node N1 is charged to the power supply voltage VDD again. The damped oscillation pulse V 1R received by the above self-precharge operation can be reproduced as, for example, the voltage pulse V 5R having the amplitude of the power supply voltage level at the node N2 (lower stage in FIG. 14).
図１３に示す受信回路２１において、符号間干渉を抑制するために受信した振動波形Ｖ１Ｒの減衰率が大きくなるように、中間ノードＮ１の放電により上記自己プリチャージ動作を開始した後、受信側インダクタ対の１次側インダクタ２２の両端を短絡することで保持している電磁エネルギーを開放する。具体的には、１次側インダクタ２２の両端に接続するＮＭＯＳＦＥＴ３４のゲート端子に再生された電圧パルスＶ５Ｒと同相のパルス信号を例えばノードＮ３から入力する。 In the receiving circuit 21 shown in FIG. 13, after the self-precharge operation is started by discharging the intermediate node N1 so that the attenuation rate of the vibration waveform V1R received in order to suppress intersymbol interference is increased, The stored electromagnetic energy is released by short-circuiting both ends of the primary inductor 22 of the inductor pair. Specifically, a pulse signal having the same phase as that of the regenerated voltage pulse V 5R is inputted to the gate terminal of the NMOSFET 34 connected to both ends of the primary side inductor 22 from, for example, the node N3.
ここで、図１３のＮＭＯＳＦＥＴ３１のリーク電流により中間ノードＮ１が徐々に放電して、振動波形Ｖ３Ｒを誤検出して電圧パルスＶ５Ｒを発生する虞がある。従って、本実施形態では、例えば図１６に示すようなリーク電流補償回路３５を中間ノードＮ１に接続して、当該リーク電流による放電を防止している。 Here, there is a possibility that the intermediate node N1 is gradually discharged due to the leakage current of the NMOSFET 31 in FIG. 13, and the oscillation waveform V 3R is erroneously detected to generate the voltage pulse V 5R . Therefore, in this embodiment, for example, a leakage current compensation circuit 35 as shown in FIG. 16 is connected to the intermediate node N1 to prevent discharge due to the leakage current.
また、本発明装置１では、送信回路１１と伝送線路３間及び受信回路２１と伝送線路３間がインダクタ対によるトランス結合であるため、シリアルデータの伝送はパルス伝送が基本となる。図１３に示すように、送信回路１１のＮＭＯＳＦＥＴ１６のゲート端子１７に入力する前に、ＮＲＺ信号をパルス変換回路１８でパルス信号に変換する。図１７に示すように、パルス変換回路１８は、ＮＲＺ信号が立ち上がり時に２回、立ち下がり時に１回、夫々短パルスを出力する。図１８に、当該パルス信号に変換する回路構成例を示す。 In the device 1 of the present invention, the transmission between the transmission circuit 11 and the transmission line 3 and the reception circuit 21 and the transmission line 3 are transformer-coupled by an inductor pair, so that serial data transmission is based on pulse transmission. As shown in FIG. 13, the NRZ signal is converted into a pulse signal by the pulse conversion circuit 18 before being input to the gate terminal 17 of the NMOSFET 16 of the transmission circuit 11. As shown in FIG. 17, the pulse conversion circuit 18 outputs a short pulse twice when the NRZ signal rises and once when it falls. FIG. 18 shows a circuit configuration example for conversion into the pulse signal.
一方、受信回路２１側では、再生したパルス信号Ｖ５ＲをＮＲＺ信号ＶＮＲＺに変換するために逆変換回路３６を設けている。図１９に示すように、逆変換回路３６では、パルス信号Ｖ５Ｒにおいて短パルスが２回連続する場合に高レベルを出力し、１回だけの場合に低レベルを出力する。斯かる逆変換処理により送信時のＮＲＺ信号が再現できる。図２０に、再生したパルス信号Ｖ５ＲをＮＲＺ信号ＶＮＲＺに逆変換する回路構成例を示す。 On the other hand, on the receiving circuit 21 side, an inverse conversion circuit 36 is provided to convert the reproduced pulse signal V 5R into the NRZ signal V NRZ . As shown in FIG. 19, the inverse conversion circuit 36 outputs a high level when the short pulse continues twice in the pulse signal V 5R , and outputs a low level only once. The NRZ signal at the time of transmission can be reproduced by such inverse conversion processing. FIG. 20 shows a circuit configuration example for inversely converting the regenerated pulse signal V 5R into the NRZ signal V NRZ .
次に、本発明に係るシリアルデータ伝送装置の別実施形態について説明する。 Next, another embodiment of the serial data transmission apparatus according to the present invention will be described.
〈１〉上記実施形態では、図２に示すように、送信側インダクタ対１２、１３と受信側インダクタ対２２、２３は、夫々の半導体チップ内に１次側と２次側の両方のインダクタを形成する構成を例示したが、各インダクタ対の伝送線路３と接続する２次側インダクタを夫々、半導体チップ外に取り出して形成するようにしても構わない。 <1> In the above-described embodiment, as shown in FIG. 2, the transmission-side inductor pairs 12 and 13 and the reception-side inductor pairs 22 and 23 include both primary-side and secondary-side inductors in the respective semiconductor chips. Although the structure to be formed has been illustrated, the secondary inductors connected to the transmission line 3 of each inductor pair may be formed outside the semiconductor chip.
例えば、図２１に模式的に示すように、各２次側インダクタ１３，２３を、夫々プリント配線基板２上に形成する。ここで、２次側インダクタ１３，２３の各一方端を１本の伝送線路３に接続し、各他方端を夫々接地するようにしても良い。尚、送信側インダクタ対の１次側インダクタ１２は、送信回路１１とともに第１半導体チップ内に集積し、受信側インダクタ対の１次側インダクタ２２は、受信回路２１とともに第２半導体チップ内に集積する。つまり、第１半導体集積回路１０は、シリアルデータの送信回路１１と送信側インダクタ対の１次側インダクタ１２を共通の第１半導体チップ内に集積して構成され、第２半導体集積回路２０は、シリアルデータの受信回路２１と受信側インダクタ対の１次側インダクタ２２を共通の第２半導体チップ内に集積して構成されている。第１半導体集積回路１０と第２半導体集積回路２０は、夫々プリント配線基板２上に、フリップチップ実装または接着剤等で貼付されるが、このとき、送信側インダクタ対の第１半導体チップ側の１次側インダクタ１２とプリント配線基板２側の２次側インダクタ１３が対向して重なり合うように位置合わせし、受信側インダクタ対の第２半導体チップ側の１次側インダクタ２２とプリント配線基板２側の２次側インダクタ２３が対向して重なり合うように位置合わせする。 For example, as schematically shown in FIG. 21, the secondary inductors 13 and 23 are respectively formed on the printed wiring board 2. Here, each one end of the secondary inductors 13 and 23 may be connected to one transmission line 3 and each other end may be grounded. The primary inductor 12 of the transmitting inductor pair is integrated with the transmitting circuit 11 in the first semiconductor chip, and the primary inductor 22 of the receiving inductor pair is integrated with the receiving circuit 21 in the second semiconductor chip. To do. That is, the first semiconductor integrated circuit 10 is configured by integrating the serial data transmitting circuit 11 and the primary inductor 12 of the transmitting inductor pair in a common first semiconductor chip, and the second semiconductor integrated circuit 20 includes: The serial data receiving circuit 21 and the primary side inductor 22 of the receiving side inductor pair are integrated in a common second semiconductor chip. The first semiconductor integrated circuit 10 and the second semiconductor integrated circuit 20 are attached to the printed wiring board 2 by flip chip mounting or adhesive, respectively. At this time, the first semiconductor chip side of the transmission side inductor pair is attached. The primary-side inductor 12 and the secondary-side inductor 13 on the printed wiring board 2 side are aligned so as to oppose each other, and the primary-side inductor 22 on the second semiconductor chip side of the receiving-side inductor pair and the printed-wiring board 2 side The secondary inductors 23 are aligned so as to overlap each other.
本別実施形態では、フリップチップ実装で必要なバンプ形成やバンプ・パッド間の接合が、少なくとも伝送線路３に対して不要となるため、実装作業が簡単化できる。 In the present alternative embodiment, bump formation and bump-pad bonding necessary for flip-chip mounting are not required at least for the transmission line 3, so that the mounting operation can be simplified.
更に、第１半導体集積回路１０と第２半導体集積回路２０を個別のパッケージに実装してからプリント配線基板２上に搭載するようにしてもよい。この場合には、各２次側インダクタ１３，２３を、夫々のパッケージ基板に上記要領で形成するようにしても構わない。 Further, the first semiconductor integrated circuit 10 and the second semiconductor integrated circuit 20 may be mounted on the printed wiring board 2 after being mounted in separate packages. In this case, the secondary inductors 13 and 23 may be formed on the respective package substrates as described above.
〈２〉上記実施形態では、第１半導体集積回路１０内に送信回路１１に設け、第２半導体集積回路２０内に受信回路２１を設け、第１半導体集積回路１０側から第２半導体集積回路２０に伝送線路３を介して一方向にシリアルデータ伝送する場合を想定したが、送信回路１１と受信回路２１を一体化した送受信回路４０を、第１半導体集積回路１０と第２半導体集積回路２０内に夫々集積するのも好ましい。これにより、第１半導体集積回路１０と第２半導体集積回路２０間で双方向のシリアルデータ伝送が可能となる。 <2> In the above embodiment, the transmission circuit 11 is provided in the first semiconductor integrated circuit 10, the reception circuit 21 is provided in the second semiconductor integrated circuit 20, and the second semiconductor integrated circuit 20 is provided from the first semiconductor integrated circuit 10 side. However, the transmission / reception circuit 40 in which the transmission circuit 11 and the reception circuit 21 are integrated in the first semiconductor integrated circuit 10 and the second semiconductor integrated circuit 20 is assumed. It is also preferable to accumulate in each. Thereby, bidirectional serial data transmission between the first semiconductor integrated circuit 10 and the second semiconductor integrated circuit 20 becomes possible.
具体的には、図２２に示すように、送受信回路４０内に、ＰＭＯＳＦＥＴ４１を１次側インダクタＬの一方端と電源の間に追加し、送信回路部分と受信回路部分を切り替えて活性化させる切り替え信号Ｔｘ／Ｒｘを用いて、ＰＭＯＳＦＥＴ４１とパルス変換回路１８を切り替え信号Ｔｘ／Ｒｘで送信動作時にのみ活性化させ、バイアス回路３０を切り替え信号Ｔｘ／Ｒｘで受信動作時にのみ活性化させる構成とすることで、送信回路部分と受信回路部分を切り替え動作可能に構成する。図２２中の１次側インダクタＬは、送信回路１１として機能する場合は、送信側インダクタ対の１次側インダクタ１２となり、受信回路２１として機能する場合は、受信側インダクタ対の１次側インダクタ２２となる。尚、送信回路１１と受信回路２１を一体化して送受信回路４０とする回路構成は、図２２に示す回路構成に限定されるものではない。 Specifically, as shown in FIG. 22, a PMOSFET 41 is added between the one end of the primary inductor L and the power source in the transmission / reception circuit 40, and switching is performed by switching between the transmission circuit portion and the reception circuit portion. Using the signal Tx / Rx, the PMOSFET 41 and the pulse conversion circuit 18 are activated only during the transmission operation with the switching signal Tx / Rx, and the bias circuit 30 is activated only during the reception operation with the switching signal Tx / Rx. Thus, the transmission circuit portion and the reception circuit portion are configured to be switchable. When the primary inductor L in FIG. 22 functions as the transmission circuit 11, it becomes the primary inductor 12 of the transmission inductor pair, and when it functions as the reception circuit 21, the primary inductor of the reception inductor pair. 22 The circuit configuration in which the transmission circuit 11 and the reception circuit 21 are integrated to form the transmission / reception circuit 40 is not limited to the circuit configuration shown in FIG.
〈３〉上記実施形態では、送信回路１１と伝送線路３間、及び、受信回路２１と伝送線路３間の両方をインダクタ対によるトランス結合で非接触接続としたが、図２３に示すように、受信回路２１と伝送線路３間だけをトランス結合による非接触接続とし、送信回路１１と伝送線路３間はＬＶＤＳのように電流を直接切り替える方式にすることも可能である。 <3> In the above embodiment, both the transmission circuit 11 and the transmission line 3 and between the reception circuit 21 and the transmission line 3 are non-contact connected by transformer coupling using an inductor pair, but as shown in FIG. It is also possible to adopt a system in which only the reception circuit 21 and the transmission line 3 are contactlessly connected by transformer coupling, and the current is directly switched between the transmission circuit 11 and the transmission line 3 like LVDS.
〈４〉上記実施形態では、伝送線路３は、プリント配線基板２上に形成されたストリップ線路を想定したが、ストリップ線路に限定されるものではなく、例えば同軸ケーブルであっても構わない。 <4> In the above embodiment, the transmission line 3 is assumed to be a strip line formed on the printed wiring board 2, but is not limited to a strip line, and may be a coaxial cable, for example.
本発明に係るシリアルデータ伝送装置は、プリント配線基板上のストリップ線路や同軸線路等の伝送線路で結合された半導体集積回路間の高速シリアルデータ伝送に利用でき、特に、高速性とともに、低消費電力化とＥＭＩの低減に有効である。従って、低消費電力化と同時にＥＭＩの低減が重要な携帯電話等では、装置内の大容量データ伝送、例えば画像データ伝送等に対して大いに有用である。 The serial data transmission device according to the present invention can be used for high-speed serial data transmission between semiconductor integrated circuits coupled by a transmission line such as a strip line or a coaxial line on a printed wiring board, and in particular, high speed and low power consumption. This is effective for reducing the EMI and EMI. Therefore, in a cellular phone or the like in which reduction of EMI is important at the same time as reducing power consumption, it is very useful for large-capacity data transmission in the apparatus, for example, image data transmission.
１： 本発明に係るシリアルデータ伝送装置
２： プリント配線基板
３： 伝送線路
１２： 伝送される電流パルスをモデル化した電流源
１０： 第１半導体集積回路
１１： 送信回路
１２： 送信側インダクタ対の１次側インダクタ
１２ａ： 送信側インダクタ対の１次側インダクタの一方端
１２ｂ： 送信側インダクタ対の１次側インダクタの他方端
１３： 送信側インダクタ対の２次側インダクタ
１４： 第１半導体チップの電極パッド
１５： 第１半導体チップの電極パッド
１６： 送信回路の駆動用ＮＭＯＳＦＥＴ
１７： 送信回路のＮＭＯＳＦＥＴのゲート端子
１８： パルス変換回路
２０： 第２半導体集積回路
２１： 受信回路
２２： 受信側インダクタ対の１次側インダクタ
２３： 受信側インダクタ対の２次側インダクタ
２４： 第２半導体チップの電極パッド
２５： 第２半導体チップの電極パッド
３０： バイアス回路
３１： 受信回路の受信電圧波形検出用のＮＭＯＳＦＥＴ
３２： 受信回路の自己プリチャージ動作用の遅延回路
３３： 受信回路の自己プリチャージ動作用のＰＭＯＳＦＥＴ
３４： 符号間干渉を抑制するためのＮＭＯＳＦＥＴ
３５： リーク電流補償回路
３６： 逆変換回路
３７： バイアス回路内のモード切替用のＰＭＯＳＦＥＴ
４０： 送受信回路
４１： 送受信回路の送受信を切替用のＰＭＯＳＦＥＴ
５０： ＬＶＤＳのドライバ回路
５１： ＬＶＤＳの受信回路
５２： ＬＶＤＳの差動制御信号
５３： 差動伝送線路
５４： ラッチ・コンパレータ
Ｂｉａｓ−ｎ： バイアス回路の中間電圧出力
Ｂｉａｓ−ｐ： バイアス回路の中間電圧出力
Ｃ： １次側インダクタの寄生容量
Ｃｃ： 受信回路のレベルシフト用コンデンサ
Ｉ１Ｔ： 送信側インダクタ対の１次側インダクタ電流
Ｉ２Ｔ： 送信側インダクタ対の２次側インダクタ電流
Ｌ： １次側インダクタのインダクタンス
Ｎ１〜Ｎ３： 受信回路内のノード
Ｒ： １次側インダクタの寄生抵抗
Ｒｏ： 受信回路のレベルシフト用抵抗
Ｔｍ： タイミング余裕
Ｔｘ／Ｒｘ： 切り替え信号
ＶＤＤ： 電源電圧
Ｖｉｎ： 送信パルス
Ｖ２Ｔ： 送信側インダクタ対の２次側インダクタの端子間に生じる減衰振動パルス
Ｖ１Ｒ： 受信側インダクタ対の１次側インダクタの端子間に生じる受信電圧
Ｖ３Ｒ： レベルシフト後の受信電圧
Ｖ４Ｒ： 自己プリチャージを起動する電圧パルス
Ｖ５Ｒ： 再現された電圧パルス
ＶＮＲＺ： 再生されたＮＲＺ信号
1: Serial data transmission apparatus according to the present invention 2: Printed wiring board 3: Transmission line 12: Current source modeling current pulse to be transmitted 10: First semiconductor integrated circuit 11: Transmission circuit 12: Transmission side inductor pair Primary inductor 12a: One end of primary inductor of transmitter inductor pair 12b: Other end of primary inductor of transmitter inductor pair 13: Secondary inductor of transmitter inductor pair 14: First semiconductor chip Electrode pad 15: Electrode pad of first semiconductor chip 16: NMOSFET for driving transmission circuit
17: Gate terminal of NMOSFET of transmission circuit 18: Pulse conversion circuit 20: Second semiconductor integrated circuit 21: Reception circuit 22: Primary inductor of reception inductor pair 23: Secondary inductor of reception inductor pair 24: Second 2 Electrode pad of semiconductor chip 25: Electrode pad of second semiconductor chip 30: Bias circuit 31: NMOSFET for detecting received voltage waveform of receiving circuit
32: Delay circuit for self-precharge operation of receiver circuit 33: PMOSFET for self-precharge operation of receiver circuit
34: NMOSFET for suppressing intersymbol interference
35: Leakage current compensation circuit 36: Inverse conversion circuit 37: PMOSFET for mode switching in the bias circuit
40: Transmission / reception circuit 41: PMOSFET for switching transmission / reception of the transmission / reception circuit
50: Driver circuit of LVDS 51: Receiver circuit of LVDS 52: Differential control signal of LVDS 53: Differential transmission line 54: Latch comparator Bias-n: Intermediate voltage output of bias circuit Bias-p: Intermediate voltage of bias circuit Output C: Parasitic capacitance of primary inductor Cc: Capacitor for level shift of receiver circuit I 1T : Primary inductor current of transmitter inductor pair I 2T : Secondary inductor current of transmitter inductor pair L: Primary side Inductor inductances N1 to N3: Nodes in the receiving circuit R: Parasitic resistance of the primary inductor Ro: Level shift resistance of the receiving circuit Tm: Timing margin Tx / Rx: Switching signal VDD: Power supply voltage Vin: Transmission pulse V 2T : Generated between the terminals of the secondary inductor of the transmitting inductor pair Damped oscillation pulse V 1R: receiving voltage generated between the first primary inductor terminal of the reception side inductor pair V 3R: reception voltage V 4R after the level shift: Self precharge voltage start pulse V 5R: voltage pulses reproduced V NRZ : Regenerated NRZ signal
Claims (9)
前記受信回路と前記伝送線路間が受信側インダクタ対の電磁結合によって非接触に接続し、
前記送信回路と前記伝送線路間が送信側インダクタ対の電磁結合によって非接触に接続し、
前記送信回路側から前記送信側インダクタ対の一次側インダクタの自己共振による減衰振動パルスを利用して前記伝送線路に送信信号を出力し、
前記受信回路が、前記伝送線路から前記受信側インダクタ対を介して受信した減衰振動パルスの立ち上がりエッジまたは立ち下がりエッジを検出して単安定な受信検出パルスを発生する回路を備え、タイミングクロックなしに受信信号を非同期検出することを特徴とするシリアルデータ伝送装置。 A first semiconductor integrated circuit in which a transmission circuit is integrated in a first semiconductor chip; and a second semiconductor integrated circuit in which a reception circuit is integrated in a second semiconductor chip. The first semiconductor integrated circuit and the second semiconductor integrated circuit A serial data transmission device in which semiconductor integrated circuits are connected to each other via a transmission line,
The receiving circuit and the transmission line are connected in a non-contact manner by electromagnetic coupling of a receiving inductor pair,
The transmission circuit and the transmission line are connected in a non-contact manner by electromagnetic coupling of a transmission-side inductor pair,
Output a transmission signal to the transmission line using a damped oscillation pulse due to self-resonance of the primary inductor of the transmission inductor pair from the transmission circuit side ,
The reception circuit includes a circuit that generates a monostable reception detection pulse by detecting a rising edge or a falling edge of a damped oscillation pulse received from the transmission line via the reception-side inductor pair, and without a timing clock. A serial data transmission device characterized in that a received signal is detected asynchronously .
前記受信側インダクタ対の１次側インダクタが前記第２半導体チップ内に形成され、前記受信側インダクタ対の２次側インダクタが前記第２半導体集積回路のパッケージ基板または前記第２半導体集積回路を搭載するプリント配線基板上に形成されていることを特徴とする請求項１又は２に記載のシリアルデータ伝送装置。 A primary inductor of the transmitting inductor pair is formed in the first semiconductor chip, and a secondary inductor of the transmitting inductor pair is mounted with the package substrate of the first semiconductor integrated circuit or the first semiconductor integrated circuit. Formed on the printed wiring board
The primary inductor of the receiving inductor pair is formed in the second semiconductor chip, and the secondary inductor of the receiving inductor pair is mounted with the package substrate of the second semiconductor integrated circuit or the second semiconductor integrated circuit. The serial data transmission device according to claim 1 , wherein the serial data transmission device is formed on a printed wiring board.
前記第１半導体集積回路と前記第２半導体集積回路が夫々、送受信回路として機能することを特徴とする請求項１〜７の何れか１項に記載のシリアルデータ伝送装置。 In the first semiconductor chip and the second semiconductor chip, the transmission circuit and the reception circuit are integrated so as to be capable of switching operation, respectively.
Wherein the first semiconductor integrated circuit the second semiconductor integrated circuit are respectively serial data transmission apparatus according to any one of claim 1 to 7, characterized in that it functions as a transceiver circuit.
After the receiving circuit detects the rising or falling edge of the damped oscillation pulse received through the receiving-side inductor pair, both ends of the primary-side inductor connected to the receiving circuit side of the receiving-side inductor pair are connected to the receiving-side inductor pair. The serial data transmission device according to claim 1, further comprising a circuit that temporarily short-circuits during generation of the reception detection pulse to suppress intersymbol interference.
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| JP2006293338A JP5070511B2 (en) | 2006-10-27 | 2006-10-27 | Serial data transmission device using magnetic coupling of inductor pair |
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| JP5496541B2 (en) | 2009-04-20 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP5562459B2 (en) * | 2013-02-27 | 2014-07-30 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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