JP5068921B2 - Nanotube films and products - Google Patents

Abstract

Nanotube films and articles and methods of making the same are disclosed. A conductive article includes an aggregate of nanotube segments in which the nanotube segments contact other nanotube segments to define a plurality of conductive pathways along the article. The nanotube segments may be single walled carbon nanotubes, or multi-walled carbon nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. The articles so formed may be disposed on substrates, and may form an electrical network of nanotubes within the article itself. Conductive articles may be made on a substrate by forming a nanotube fabric on the substrate, and defining a pattern within the fabric in which the pattern corresponds to the conductive article. The nanotube fabric may be formed by growing the nanotube fabric on the substrate using a catalyst, for example, in which the catalyst is a gas phase catalyst, or in which the catalyst is a metallic gas phase catalyst. The nanotube fabric may be formed by depositing a solution of suspended nanotubes on the substrate. The deposited solution may be spun to create a spin-coating of the solution. The solution may be deposited by dipping the substrate into the solution. The nanotube fabric is formed by spraying an aerosol having nanotubes onto a surface of the substrate.

Description

This application is related to the following applications, all of which are assigned to the assignee of the present application, and all of which are incorporated by reference in their entirety. That is, those applications are
An electromechanical memory array (US patent application Ser. No. 09 / 915,093 filed on Jul. 25, 2001) using nanotube ribbons and methods of making them,
An electromechanical memory having a cell selection circuit constructed by nanotube technology (US patent application Ser. No. 09 / 915,173 filed on Jul. 25, 2001);
Hybrid circuit with nanotube electromechanical memory (U.S. patent application Ser. No. 09 / 91,095 filed Jul. 25, 2001).

  The present invention relates generally to carbon nanotube films, woven fabrics, layers, products, and more particularly to producing conductive products from carbon nanotube films, woven fabrics or layers for various uses in circuits and the like.

  Reliable manufacturing of conductive ultrathin metal layers and electrodes in the 10 nm regime is a problem. For example, S.M. Wolf, “Silicon Processing for the VLSI Era”, Volume 2, “Process Integration” (S. Wolf, Silicon Processing for the VLSI era; Volume 2-Process Integration) (Lattice Press, Sunset Beach, 1990) Press, Sunset Beach, 1990. Metal films in this size regime are usually discontinuous and do not become conductive over microscopic distances. Such films of 10 nm or less are susceptible to thermal damage due to currents that render them unsuitable for applications such as electrical interconnections in semiconductor devices.The thin metal phase resulting from their low thermal conductivity Interconnect damage due to heat is one of the main factors that hinder significant downsizing and improved performance of highly integrated semiconductor devices.

  Conventional interconnect technology has a tendency to suffer from thermal damage and metal diffusion, which in particular affects the performance of semiconductor devices, from degradation of its electrical characteristics. These effects are even more pronounced due to dimensional reduction in current generation for 0.18 μm and 0.13 μm structures, for example, due to metal diffusion through the ultrathin gate oxide layer.

  Accordingly, there is a need in the art for conductive elements that may work well in contexts with high current densities or in extreme thermal conditions. This includes circuit contexts with very small feature sizes, but also includes other high current density extreme thermal environment contexts. There is also a need for conductive elements that are less likely to diffuse undesirable amounts of contaminants into other circuit elements.

  The present invention provides nanotube films and products and methods for making them. Under one aspect of the invention, a conductive product includes a collection of nanotube segments in contact with other nanotube segments to define a plurality of conductive paths along the product.

  Under other aspects of the invention, the nanotube segments can be single-walled carbon nanotubes or multi-walled carbon nanotubes. The various segments can have different lengths and can include segments having a length that is shorter than the length of the product.

The product so formed can be placed on a substrate to form an electrical network of nanotubes within the product itself.
Under another aspect of the present invention, a nanotube woven fabric is formed on the substrate, and the pattern is formed on one substrate by defining a pattern within the woven fabric corresponding to the conductive product. It can be made up.

  According to another aspect of the present invention, the nanotube woven fabric is formed on the substrate using a single catalyst in which the catalyst is a gas phase catalyst or the catalyst is a metal gas phase catalyst. It is formed by growing.

  According to another aspect of the present invention, the nanotube woven fabric is formed by depositing a solution of nanotubes suspended on one substrate. The deposited solution can be spun to create a spin coating of the solution.

  Under another aspect of the present invention, the solution can be deposited by immersing the substrate in the solution.

According to another aspect of the present invention, the nanotube woven fabric is formed by spraying an aerosol having nanotubes on the surface of the substrate. The present invention provides a method for producing a film of conductive nanotubes. Under one aspect of the invention, a substrate is provided to grow nanotube growth and a vapor phase catalyst is introduced. A carbon source is also introduced to grow a single layer of nanotubes that is substantially parallel to the major surface of the substrate.

  Under another aspect of the invention, the vapor phase catalyst is a metallocene.

  Under another aspect of the invention, the conductive product forms a nanotube woven fabric on the substrate, the pattern defining a pattern in the woven fabric corresponding to the conductive product, It is made up on one substrate by removing a portion of the woven fabric so that the patterned woven fabric remains on the substrate to form a conductive product.

  Under another aspect of the invention, the conductive product provides a substrate, introduces a vapor phase catalyst to grow nanotube growth, and is substantially parallel to the major surface of the substrate. It is built on one substrate by introducing a carbon source to grow one phase of the nanotube.

  Under another aspect of the invention, a conductive product provides a substrate to grow nanotubes that are substantially parallel to the major surface of the substrate that is within the region defined by the pattern. It is then fabricated on a single substrate by supplying a patterned layer of material, supplying a catalyst to grow nanotube growth, and supplying a carbon source.

Under another aspect of the invention, the material patterned layer is an insulator or semiconductor, and the nanotubes are grown on the patterned material.
Under another aspect of the invention, the patterned layer is a patterned metal layer and the nanotubes are grown in other areas that are not the patterned metal layer.

  A new electromechanical memory array in which an electromechanical memory cell operating similar to the NTWCM device disclosed in WO 01/03208, which is incorporated herein by reference in its entirety, is created and for manufacturing the same Various methods are disclosed. However, unlike the NTWCM device disclosed in WO 01/03208, new ribbons or belts made from nanotube matting layers or nanotube nonwovens are used as conductive elements. At various points in this disclosure, the ribbon is referred to as a trace or as a conductive product. In one example, the ribbon is suspended and in another example, the ribbon is placed on a single substrate. In one example, the ribbon is used to deflect to a specific state under electrical control, and in other examples, the ribbon does not move but simply carries current or voltage. in use. The new nanotube belt structure is easier to build with the desired values of integration and scale (in the number of devices being manufactured) and the geometric pattern is considered to be more easily controlled. It is done. It is believed that the new nanotube ribbon can more easily support high current densities without experiencing with metal traces or suffering from the problems outlined above.

  Under certain embodiments of the present invention, the conductive product can be made from a woven nanotube fabric, layer or film. Carbon nanotubes having a small tube diameter of 1 nm are conductors that can support very high current densities. For example, Z. Yao, C.I. L. Kane, C.I. Dekker, Phys. Rev. Lett. 84, 2941 (2000). These carbon nanotubes also have the highest thermal conductivity known to be. Regarding this, for example, S.M. Berber, Y.M. -K. Kwon, D.C. Tomanek, Phys. Rev. Lett. 84, 4613 (2000). These carbon nanotubes are thermally and chemically stable. Regarding this, for example, P.I. M.M. Ajayan, T .; W. Ebesen, Rep. Prog. Phys. 60, 1025 (1997). However, the use of individual nanotubes is problematic because it is difficult to grow individual nanotubes with appropriately controlled directions, lengths, and the like. By creating traces from a nanotube woven fabric, many if not all of the benefits of individual nanotubes can be retained. Furthermore, traces made from nanotube woven fabrics have benefits not found in individual nanotubes. For example, because the trace consists of many nanotubes in the aggregate, the trace does not fail as a result of individual nanotube failure or breakage. Instead, there are many alternative paths through which electrons can travel within a certain trace. In fact, a trace made from a nanotube woven fabric creates its own electrical network of individual nanotubes within its defined trace. Furthermore, by using nanotube fabrics, layers, or films, the technology can be used to create such traces.

Nanotube Ribbon Crossbar Memory (NTRCM)
Since the new nanotube belt crossbar memory device works similarly to NTWCM, the description of their architecture and principle of operation is short. For a more complete description and background reference can be made to WO 01/03208.

  FIG. 1 illustrates and describes an exemplary electromechanical memory array 100 constructed in accordance with the principles of the preferred embodiment of the present invention. The array has a plurality of non-volatile memory cells 103 that can be in an “on” state 105 or an “off” state 106. Although the actual number of such cells is not critical to understanding the present invention, the technology supports devices that have the same or greater information storage capability as modern non-volatile circuit devices. It is possible.

  Each memory cell 103 includes an electrical trace or wiring, for example, a nanotube ribbon 101 suspended by one or more supports 102 overlying 104.

  Each intersection of the ribbon 101 and a wiring, eg 104, forms a crossbar connection and defines a memory cell. Under certain embodiments, each cell applies current or voltage to an electrode 112 that is in electrical communication with the ribbon 101, or through an electrode (not shown) that is in communication with a trace or wiring 104. Thus, reading and writing are performed. The support 102 is made from a layer 108 of silicon nitride (Si3N4). Underneath the layer 108 is a gate oxide layer 109 that separates the n-doped silicon trace 104 from the underlying silicon wafer 110.

  Referring to FIGS. 1-2B together, junction 106 illustrates the cell in a first physical and electrical state in which the nanotube ribbon 101 is separated from a corresponding trace 104. Junction 105 illustrates the cell in a second physical and electrical state in which the nanotube ribbon 101 is deflected toward a corresponding trace 104. In the first state, the bond is an open circuit and may be sensed on either the ribbon 101 or the trace 104 when so addressed. In the second state, the junction is a rectifying junction (eg, Schottky or PN) and may be sensed, such as on either the tube 101 or the trace 104, when so addressed. is there.

  Under certain embodiments, the nanotube ribbon 101 can be held in place on the support by friction. Under other embodiments, the ribbon can be held by other means, such as by securing the ribbon to the support using any of a variety of techniques. This friction can be increased by using chemical interactions involving covalent bonds by using carbon compounds such as pyrene or other chemically reactive species. Vapor deposited or spin coated materials such as metals, semiconductors, or insulators, particularly silicon, titanium, silicon oxide, or polyimide, can also be added to increase its pinning strength. The nanotube ribbon or each nanotube can also be pinned to the surface by using wafer bonding. In this regard, R.A. J. et al. Chen et al., “Noncovalent Sidewall Functionalization of Single-Walled Carbon Nanotubes for Protein Immobilization”, J. et al. Am. Chem. Soc. , 123, 2001, 3838-39 and for exemplary techniques for pinning and coating nanotubes with metal, see Dai et al., Appl. Phys. Lett. 77, 2000, 3015-17. For various technologies, refer to WO01 / 03208.

  As illustrated and described in FIGS. 2A-B, under certain preferred embodiments, the nanotube ribbon 101 has a width of about 180 nm, relative to a suitably manufactured silicon nitride support 102. It is pinned. The local area of the trace 104 under the ribbon 101 forms an n-doped silicon electrode and is located near the support 102 and is preferably not wider than the belt, eg 180 nm. The relative separation band 208 from the top of the support 102 to which the belt 101 is attached to the electrode 206 to the deflection position should be approximately 5 to 50 nm in size (see FIG. 2B). The size of the separation band 208 is designed to be compatible with the electromechanical switching capability of the memory device. For this embodiment, the 5-50 nm separation band is suitable for certain embodiments utilizing ribbon 101 made of carbon nanotubes, but other separation bands are preferred for other materials. It is thought that it will become something. This magnitude results from the interaction (interplay) between strain energy and adhesion energy of the deflected nanotube. These characteristic dimensions are suggested from the viewpoint of the latest manufacturing technology. Other embodiments can be manufactured with smaller (or larger) dimensions that reflect the capabilities of the manufacturing facility.

  The nanotube ribbon 101 of certain embodiments is formed of entangled or matted nanotube nonwoven fabrics (more are described below). The switching parameters of the ribbon are similar to those of each nanotube. Thus, the expected switching time and voltage of the ribbon should be approximately equal to the same time and voltage as the nanotube. Unlike the prior art, which relies on the directed growth or chemical self-assembly of each nanotube, the preferred embodiment of the present invention utilizes manufacturing techniques including thin films and lithography. This method of manufacture is useful for production on large surfaces, especially on at least 6 inch wafers. (In contrast, it is currently impossible to grow each nanotube over distances that are less than a millimeter.) The ribbon provides redundancy in the conduction path accommodated by the ribbon. Should show improved fault tolerance on each nanotube (if individual nanotubes break other tubes in the rib, provide a conduction path, while only a single nanotube If used, the cell will fail). Furthermore, since the ribbon can be made to have a larger cross-sectional area than individual nanotubes, the resistance of the ribbon should be significantly lower than that for individual nanotubes, and therefore , Its impedance is reduced.

  FIG. 3 illustrates and describes one method of manufacturing a particular embodiment of the NTRCM device 100. The first intermediate structure 302 is made or supplied. In the illustrated and described embodiment, the structure 302 includes a silicon substrate 110 having an insulating layer 109 (such as silicon dioxide) and a silicon nitride layer (Si 3 N 4) 108 defining a plurality of supports 102. In this example, many other arrangements, such as multiple columns, are possible, but the support 102 is formed by a patterned array of silicon nitride. Conductive traces 104 extend between the supports 102. In this example, the trace 104 is illustrated as being essentially in contact with the support 102, but other arrangements are possible for other geometric patterns. For example, a space may exist between the trace 104 and the support 102, and the trace 104 may be shaped as a wire or have a non-quadratic cross section including a triangle or trapezoid. A sacrificial layer 304 is disposed on the trace 104 so as to define a planar surface 306 on the top surface of the support 102. This planar surface facilitates the growth of the matted nanotube layer of certain embodiments, as described below.

  Once such structure 302 is created or delivered, the top surface 306 receives a catalyst 308. For example, under certain embodiments, a catalytic metal 308 that includes iron (Fe), molybdenum (Mo), cobalt, or other metal may be spin coated or other application technique to create a second intermediate structure 310. Is applied.

  The nanotube matting layer 312 is then grown into a single-walled carbon nanotube (SWNT) nonwoven to form a third intermediate structure 314. For example, the second intermediate structure 310 is placed in an oven while a gas containing an inert gas such as a carbon source, hydrogen, argon or nitrogen is flowed over the top surface, and also at a high temperature (eg, , About 800-1200 ° C.). This environment facilitates the formation or growth of the matted layer or film 312 of single wall carbon nanotubes. The layer 312 is originally one nanotube thick, and the various tubes are bonded together by van der Waals forces. Despite this relatively frequent growth due to the propensity of the material to grow, sometimes one nanotube can grow to another. Under some embodiments (not shown), the catalyst 308 is used to grow the nanotubes at a specific density, either at a higher density or at a lower density, as desired. It can be patterned to help. The catalyst composition and density conditions, growth environment and time are appropriately controlled, and the nanotubes can be made to be evenly distributed over a given field that is originally a single wall of nanotubes. Suitable growth includes, but is not limited to, catalyst composition and concentration, functionalization of the underlying surface, spin coating parameters (length and RPM), growth time, temperature, and gas concentration. Parameter control is required.

  The photoresist can then be applied to the layer 312 and patterned to define a ribbon within the matted layer of the nanotubes 312. The ribbon pattern intersects with the underlying trace 104 (eg, orthogonal). The photoresist is removed to leave a ribbon 101 of nonwoven nanotubes lying on the planar surface 306 to form a fourth intermediate structure 318.

  The fourth intermediate structure 318 has an underlying portion 320 of the sacrificial layer 304 that is exposed as shown. The structure 318 is then treated with an acid such as HF and includes the portion under the ribbon 101, and thus is an array of ribbons 101 suspended above the trace 104 and supported by the support 102. 322 is formed and the sacrificial layer 304 is removed.

  Subsequent metallization can be used to form the addressing electrodes illustrated in FIG.

  One aspect of the above technique is that conventional techniques such as lithographic patterning can be used in various growth, patterning and etching operations. At present, this can include feature dimensions (eg, ribbon 101 width) as low as about 180 nm to 130 nm, but the physical properties of the components are smaller if manufacturing capability allows. Even feature dimensions are acceptable.

  As explained below, there are many possible ways to create the above-described intermediate structures or similar structures described above. FIG. 4 illustrates one method for creating the first intermediate structure 302, for example.

  The silicon wafer 400 is provided with an oxide layer 402. The oxide layer is preferably several nanometers thick but can be as large as 1 μm. A silicon nitride (Si 3 N 4) layer 404 is disposed on top of the oxide surface 402. The silicon nitride layer is preferably at least 30 nm thick.

  Silicon nitride layer 404 is subsequently patterned and etched to create cavities 406 to form support structure 407. Using the latest technology, the width of the cavity can be reduced to about 180 nm or even smaller. The remaining silicon nitride material defines the support 102 (eg, as a row or possibly a column).

  An n-doped silicon covering 408 is then deposited to fill the cavity 406. The covering 408 for the exemplary embodiment can be about 1 μm thick, but can be as thin as 30 nm.

  The covering 408 is subsequently processed, for example, by self-planarization or annealing of a thick silicon layer to produce the planar surface 306 discussed above to form the structure 411. In the case of self-planarization, reactive ion etching (RIE) with endpoint detection (EPD) can be used until the top surface 410 of the etched silicon nitride is reached.

  The structure 411 is then oxidized to form and define a sacrificial layer 304 of SiO 2 to a depth of about 10-20 nm in the planar surface 306.

  The remaining unconverted portion of silicon forms trace 104.

  FIG. 5 illustrates another method that can be used to create the NTRCM device 100 of a particular embodiment. A support structure 407 described in connection with FIG. 4 is provided. The n-doped silicon layer 514 is then added using a CVD process, sputtering, or electroplating. Under certain embodiments, layer 514 is added to be approximately half the height of the Si 3 N 4 support 102.

  After the layer 514 is added, an annealing step is performed to create a planarized surface 306 to form the structure 411 as described above. The annealing step causes the silicon of layer 514 to flow into the cavity 406.

  As described in connection with FIG. 4, the structure 411 is then oxidized to form and define a sacrificial layer 304 of SiO 2 at a depth of about 10-20 nm in the planar surface 306.

FIG. 6 illustrates another approach for forming an alternative first intermediate structure 302 ′. In this embodiment, the silicon substrate 600 is covered by a layer 602 of silicon nitride having a height 604 of at least 30 nm.
The silicon nitride layer 602 is then patterned and etched to create spacing 606 and to define the support 102. The etching process exposes a portion 608 of the surface of the silicon substrate 600.

  The exposed silicon nitride 608 is oxidized to produce a silicon dioxide (SiO2) layer 610 having a thickness of a few nm. These layers 610 ultimately insulate the traces 104 in a manner similar to that performed by the insulating layer 109 for the structure 302 described above.

  Once the insulating layer 610 is created, the trace 104 can be created in any of a variety of ways. FIG. 6 illustrates the above processing steps of FIGS. 4-5 used to create such a trace to illustrate this point.

  FIG. 7 illustrates and describes another approach for forming the first intermediate structure 302. A silicon substrate 700 having a silicon dioxide layer 702 and a silicon nitride layer 704 accept a patterned photoresist layer 706. For example, a photoresist layer is spin coated on layer 704 and then exposed and developed by lithography.

  A reactive ion etch (RIE) or the like can then be used to etch the Si 3 N 4 layer to form the cavity 708 and define the support 102.

  Later, n-doped silicon 710 can be deposited in the cavity 708. Under a particular embodiment of silicon, the Si3N4 support 102 is deposited at a height approximately equal to the height 712.

  The photoresist 706 and silicon 710 on top of the photoresist 710 are then stripped to form the intermediate structure 411 as described above.

The structure 411 is then oxidized to produce the sacrificial SiO ₂ layer 304.

  FIG. 8 illustrates and describes another approach for forming the first intermediate structure 302. Under this approach, a starting structure 800 is provided having a lowest silicon layer 802 with a lowest silicon dioxide layer 804 on top of it. The second silicon layer 806 is on top of the layer 804, and the second silicon dioxide layer 808 is on top of the second silicon layer 806.

The top silicon dioxide (SiO ₂ ) layer 808 is patterned by photolithography to create an RIE mask 810. The mask is used to etch the exposed portion 812 of the second silicon layer 806 down to the first silicon dioxide layer 804. This etch creates a cavity 814 and also defines the trace 104.

The cavity 814 is filled and covered with silicon nitride (Si ₃ N ₄ ) 816.

The Si3N4 covering 816 is back-etched by RIE to the same height 818 as the rest of the SiO ₂ layer 806 covering the n-doped silicon electrode 104 (forming the sacrificial layer 304).

FIG. 9 illustrates and describes one approach for forming one alternative first intermediate structure 302 ″. Under this approach, a structure like 407 (shown in FIG. 4 but not shown in FIG. 9) is provided. In this example, the Si ₃ N ₃ support 102 has a height of about 30 nm. A thin layer of metal 902 is deposited on top of the Si ₃ N ₃ support 102 and on the bottom of the cavity 904 depicted by item 903, on top of the exposed portion SiO2. Metals 902 and 903 form temporary electrodes. The layer of n-doped silicon 906 can then be deposited by electroplating and by covering the electrode 903 until it reaches a height 908 on the top of the support 102 and contacts the electrode 902. Or it can be grown. The growth process can be controlled by the initiation of current flowing between the lower and upper metal electrodes 902, 903.

  The exposed metal electrode 902 can then be removed by wet chemical methods or dry chemical methods. This forms an intermediate structure 411 ′, such as the structure 411 described above, but with a buried electrode 903 as an artifact of the silicon growth process.

  The structure 411 ′ is then oxidized to form a sacrificial layer 304 on the exposed portion of silicon, as described above. For example, the layer 304 can be grown to a thickness of about 10 nm.

  FIG. 10 illustrates and describes another approach for forming the first intermediate structure 302. A silicon substrate 1002 having a layer of silicon dioxide 1004 on its top and a silicon (n-doped) second layer 1006 on top of the layer 1004 is used as a starting material. Mask layer 1008 is patterned by photolithography on top of layer 1006.

  The exposed portion 1010 of the n-doped silicon layer 1006 is chemically converted to the Si3N4 support 102 using nitridation techniques. The unconverted portion of layer 1006 forms trace 104.

  The mask 1008 is removed to form the structure 411 as described above.

  The exposed portion 1012 of the silicon surface is then oxidized to form the SiO 2 sacrificial layer 304.

  FIG. 11 illustrates one approach for forming one alternative first intermediate structure 302 ′ ″. Under this approach, the silicon substrate 1102 is layered with a thin film 1104 of Si3N4 as a starting material. On top of the silicon nitride layer 1104, n-doped silicon is added and patterned by lithography by RIE to form the traces 104.

  The surface of the trace 104 is oxidized to form the SiO2 layer 1106, which acts as an alternative form of the sacrificial layer 304 '.

  The structure is grown entirely with Si 3 N 41108 to perform a back etch to form a planar surface 306 and to form an alternative first intermediate structure 302 ′ ″. As will be apparent to those skilled in the art, under this approach, the trace 104 will be separated from the support 102 if the sacrificial layer is subsequently removed. Other modifications of this technique can be employed to create alternative cross sections of the trace 104. For example, the trace 104 can be created to have a circular top or to have a triangular or trapezoidal cross section. Further, the cross-section can have a triangular or other form with tapered sides.

  As described above, once a first intermediate structure, eg, 302, is formed, a matted nanotube layer 312 is provided on the planar surface 306 of the structure 302. In a preferred embodiment, the nonwoven layer 312 is grown on the structure by using a catalyst 308 and by controlling the growth environment. In other embodiments, the matted nanotube layer 312 is provided separately and can be applied directly onto the structure 302. Under this approach, structure 302 preferably includes the sacrificial layer to provide a planar surface to receive the individually grown fabric, but the sacrificial layer is not required under such an approach. it is conceivable that.

  Since the growth process brings the underside of these nanotubes into contact with the planar surface 306 of the intermediate structure 302, the nanotubes exhibit a “self-assembled” trait, as suggested by FIG. In particular, individual nanotubes tend to adhere to the surface they grow on whenever they are energetically suitable so that they form substantially as a “single wall”. Because some nanotubes can grow on top of another, the single wall is not considered complete. Each of the nanotubes is not “woven” with another, but adheres to another as a result of van der Waals forces. FIG. 12 is a schematic depiction of an actual nonwoven nanotube. Because of the small feature dimensions of the nanotubes, even the latest scanning electron microscopes cannot photograph real woven fabrics without lack of accuracy. Nanotubes have small feature dimensions of 1-2 nm, which are below the accuracy of a scanning electron microscope (SEM). FIG. 12 suggests, for example, the matting properties of the woven fabric. That is, although not clear from the figure, the woven fabric may have discontinuous small areas due to the absence of tubes. Each tube typically has a diameter of 1-2 nm (thus defining a woven fabric layer of about 1-2 nm), but has a length of a few microns and can be as long as 200 microns. . The tubes bend and sometimes cross each other. The tubes are attached to each other by van der Waals forces.

  In certain embodiments, the nanotubes grow substantially unrestricted in the x and y axis directions, but are substantially restricted in the z axis as a result of self-assembling traits (perpendicular to the page of FIG. 12). . In other embodiments, the above approach to the growing matted nanotube layer 312 can be supplemented by using field-oriented or flow-oriented growth techniques. Such replenishment may be used to tailor the growth further so that it is delayed in one plane axis (eg, the x-axis). This allows for further coverage of the desired area with a planar knitted monolayer coating of nanotubes with controllable density.

  A plan view of the matted nanotube layer 312 with the underlying silicon trace 104 is shown in FIG.

  As explained above, once the matted nanotube layer 312 is provided on the surface 306, the layer 312 defines a ribbon 101 of woven nanotube cloth that intersects the support 102. And patterned and etched. The sacrificial layer is then removed (eg, with an acid) to form the array 322 described above in connection with FIG. The matted layer of nanotubes 312 forms a non-woven, non-continuous film, etchant, and other chemicals diffuse between the respective nanotube “fibers” and laid under the sacrificial layer and the like. It is possible to reach the components more easily.

  Subsequent metallization can also be used to form the addressing electrodes illustrated in FIG. 1, for example 112, as outlined above. Other embodiments use nanotube technology to perform memory cell addressing instead of using metallized electrode 112 and addressing lines (not shown).

  More particularly, under the specific embodiments described above, nanotubes are used to form an NTRCM array. Particular embodiments use nanotube technology in either individual wiring or belt form to implement addressing logic to select the memory cell (s) for reading or writing operations. . This approach can further promote the integration of nanotube technology into system design and provide beneficial functionality for higher level system design. For example, under this approach, the memory architecture will not only store the memory contents in a non-volatile manner, but will uniquely store the last memory address.

  The nanotube-based memory cell has bistability characterized by a high ratio of resistance between the “0” and “1” states. Switching between these states is achieved by applying a specific voltage across the nanotube belt or wiring and the underlying trace, where at least one of the memory cell elements is a nanotube or nanotube ribbon. is there. In one approach, a “readout current” is applied and the voltage across this junction is measured by a “sense amplifier”. The reading is non-destructive, meaning that the cell maintains its state and is done by DRAM, so no white-black operation is required.

  FIG. 14 illustrates a branch binary selection system or decoder 1400. As described below, the decoder 1400 can be implemented with nanotube or nanotube ribbon technology. Furthermore, the decoder can be built on the same circuit components as a nanotube memory cell array, eg, NTRCM or NTWCM.

  The perpendicular intersection 1402 of the two lines 1404 and 1406, illustrated as a point, signifies the joining of two nanotubes or nanotube ribbons. In this respect, the interaction is similar to “pass transistors” found in CMOS and other technologies where the intersection can be opened or closed.

  Locations such as 1420 where single nanotubes or nanotube ribbons cross each other but are not intended to create a crossbar junction can be caused by lithographically patterned insulators between the components. It is possible to insulate.

  For purposes of clarity, the decoder illustrated and described is for a 3-bit binary address carried on addressing line 1408. With the value of encoding, the intersection (point) is switched to create a single path that passes through to select line 1418 by sensing current I.

  In order to use this technique, the “dual rail” representation 1408 of each bit of the binary address is externally finished so that each of the address bits 1410 is represented in a true and complementary form. Thus, line 1406 can be a logical true version of address line 1408a and line 1407 can be a logical supplement to address line 1408a. The voltage value of the expression 1408 matches the voltage value that required switching the crossbar junction to the “1” or “0” state as described above.

  Thus, the address 1408 can be used to supply a detection current I to a bit or a column of bits in an array, such as a nanotube or nanotube ribbon. Similarly, the same approach can be used to detect a particular array column (s) to read its detection value along with selecting a given trace, eg, a single row . This approach can therefore be used for X and / or Y decoding for both reading and writing operations.

  Certain embodiments of the present invention provide a hybrid technology circuit 1500 illustrated in FIG. The core memory cell array 1502 is constructed using NTWCM or NTRCM, and the core is a semiconductor circuit forming X and Y address decoders 1504 and 1506; X and Y buffers 1508 and 1510; control logic 1512 and output buffer 1514 Surrounded by The circuit surrounding the NTWCM or NWBCM core can be used for normal interface functions including supplying read current and detecting output voltage.

  In other embodiments, the X and Y address decoders 1504 and 1506 can be replaced by the nanotube wiring or belt addressing techniques discussed above. In such an embodiment, the core includes memory cells and addressing logic.

  In a particular embodiment, the hybrid circuit 1500 implements the surrounding circuit with a nanotube core (which simply has either memory cells or memory cells and addressing logic) and also uses a field programmable gate array. By doing so, it can be formed. The core and gate array circuit can be housed in a single physical package if desired. Alternatively, they can be packaged separately. For example, a sealed package nanotube circuit (with memory or memory and addressing logic) can be combined with a PLD / FPGA / ASIC containing the I / O interface logic. The resulting compact chipset provides access to the benefits of the NT memory for users of the product, but can be utilized on an as-needed basis by the manufacturer. Make the best use of the “off-the-shelf” technology.

  FIG. 16 illustrates one possible implementation 1600 of the hybrid technology. The FPGA chip 1602 containing the buffering and control logic (described above) is a single (possibly multiple layer) printed circuit board (PCB) for the nanotube (NT) chip 1606 containing the memory cells and addressing logic. ) Connected by performing a trace on 1604.

  This particular embodiment is suggested to be compliant with the PCI bus standard that is typical of today's personal computers. Other passive circuits such as capacitors, resistors, transformers, etc. (not shown) may also have been required to comply with the PCI standard. Front side bus speeds of 200 MHz to 400 MHz are annotated and suggest the type of external clock speed at which such chipsets operate. This speed is limited by the PCB interconnect and FPGA / PLD / ASIC speed, and by the chip package, not by the NT memory cell speed.

Carbon Nanotube Films, Layers, Woven Fabrics and Products The above embodiments of NTRCM and addressing lines use electrically conductive products made from nanotubes 312 such as those illustrated in FIGS. . The layer is believed to have a thickness of about 1 nm or less, ie, a given nanotube thickness. The nanotube matting layer 312 is grown or vapor-deposited on a surface such as the surface of a silicon wafer in order to form a continuous film having a predetermined density. The two-dimensional film can then be patterned to produce conductive lines or traces ranging in width from 1 nm (the smallest nanotube dimensions) to several hundred microns or more, depending on the application and context. . The pattern allows for the interconnection of various sized semiconductor devices such as transistors or memory elements, and ultimately the end-up (fanout) of bond pads or other interconnect materials or structures. It can be generated with multiple length and width dimensions. The nanotube interconnects can be metal interconnects when different materials need to be connected due to their intrinsic properties that allow easy contact with metals or semiconductor materials.

  The trace and conductive product can be used in other forms of the circuit. For example, nanotube traces can be used to have the ability to withstand high current densities and are typically very small sized traces (eg, a sub-10 nm regime). They can also be used to reduce the likelihood of contaminating other circuit features.

  FIG. 17 illustrates, for example, an exemplary use of a nanotube ribbon, trace, or conductive product on a substrate (by inspection, FIG. 17 is similar to FIG. 3, but in this example, The film 312 is grown on the substrate, not on the intermediate structure 310). In this example, the silicon substrate 110 has an oxide layer 109 similar to that shown in FIG. In order to facilitate the growth or deposition of the film 312, a planar surface (shown as 306 in FIG. 3 but not shown in FIG. 17) can be created. The film 312 with single and / or multi-walled nanotubes can then be grown on the combination, for example by spin coating, using chemical vapor deposition (CVD) or by vapor deposition. It is. The film 312 is originally one nanotube thick when single wall nanotubes are used, but can be substantially thicker up to 1000 nm, for example, when multiple wall nanotubes are used.

  When growing the film, a catalyst can be used as described above. However, the catalyst (shown as 308 in FIG. 3 but not shown in FIG. 17) need not be deposited directly on the surface of the substrate. That is, alternatively or additionally, it can be supplied in gaseous form as part of the CVD process. For example, gas phase metal species such as ferrocene can be used. Ferrocene and other gas phase metal species grow carbon nanotubes, as do other species including iron, molybdenum, tungsten, cobalt and other transition metals. These are all suitable for forming a catalyst in the gas phase. The metal vapor phase catalyst can be optimized or modified along with the appropriate temperature, pressure, surface preparation, and growth time to produce the nanotube matted layer 312.

  When the film 312 is deposited, pre-grown nanotubes can be used. For example, under certain embodiments of the present invention, the nanotubes are suspended in a solvent that is in a soluble or insoluble form to produce the nanotube film 312 and on the surface. Spin coated. In such an arrangement, the film can be one or more nanotubes thick depending on the spin profile and other process parameters. Suitable solvents include dimethylformamide, n-methylpyrrolidinone, n-methylformamide, orthodichlorobenzine, paradichlorobenzine, 1,2, with a suitable surfactant such as sodium dodecyl sulfate or TRITON X-100 or others. Contains dichloroethane, alcohol, and water. The nanotube concentration and deposition parameters such as surface functionalization, spin coating rate, temperature, pH, time, etc. can be adjusted as needed for controlled deposition of single or multiple layers of nanotubes.

  The nanotube film 312 can also be deposited by immersing the wafer or substrate in a solution of dissolved or suspended nanotubes. The film can also be formed by spraying the nanotubes on the surface in the form of an aerosol.

  Nanotubes are made to distribute evenly over a given field, which is essentially a single layer of nanotubes, when the state and density of the catalyst composition, growth environment, and time are properly controlled. be able to.

  In forming the nanotube matting layer 312, a photoresist layer is spin coated on the nanotube film 312 and patterned by exposure or the like to define conductive traces. In the example of FIG. 17, the trace is illustrated as a parallel straight trace, but the trace definition can take other forms. The definition trace can have a width of at least 1 nm and a maximum of 100 microns or more, depending on the type of device being interconnected.

  Once so defined, the exposed photoresist can be processed to remove some of the layer, but the trace 101 remains. Subsequent metallization can be used to form the addressing electrode or terminal extension interconnect structure shown in FIG.

  Referring to FIG. 18, the nanotube ribbon pattern 1802 can then be connected to other ribbons 101, metal traces (not shown) or electronic features 1806. For example, referring to the intermediate structure 1800, the nanotube trace 101 can be connected to a nanotube trace 1802 having different feature dimensions such as width. The trace 101 can also be connected to an element 112, which can be a metal contact or a bonding pad (not shown in a reduced scale in this figure). Referring to the intermediate structure 1804, the trace 1010 can be formed as an NTRCM cell, or with a semiconductor site, or can be connected to a memory element within 1804. Referring to the intermediate structure 1808, the trace can connect an electronic processing site or logic 1806. Although not necessarily drawn to scale, the trace 101 can also be connected to a bond pad, indicated by item 112.

  Although these interconnects can be originally formed by a single layer of nanotubes, multi-layer ribbons, matted layers can also be considered using appropriate growth conditions. This includes catalyst composition, underlying surface concentration, functionalization, spin coating parameters (length and RPM, eg, 40 seconds, 50-5000 rpm), growth time, temperature, and gas concentration. Although it is not necessarily limited to, control of the parameter containing them is needed.

  In one aspect of the above technique, the various growth, deposition, patterning, and etching operations can use conventional techniques such as lithography patterning. With this technique, the trace can be made to have a width of about 180 nm to 130 nm where it is narrow. However, the physical characteristics of the trace 101 are acceptable, even with smaller feature sizes, if allowed by manufacturing capability.

  Normal interconnects tend to fall into thermal damage and metal diffusion, which in particular erodes the performance of semiconductor devices, due to their reduced electrical properties. These effects are even more pronounced in dimensional reduction due to ultra-thin gate oxide layers, for example in current generation 0.18 μm and 0.13 μm structures due to metal diffusion. In contrast, the carbon nanotube ribbon 101 does not suffer from these problems. They are substantially more robust, have the highest known thermal conductivity, and do not fall into thermal failure. Furthermore, metals or dopant diffusion is unlikely to occur because they are built entirely with covalently bonded carbon atoms.

  FIG. 19 illustrates another approach for forming the first intermediate structure 302. A silicon substrate 1900 having a silicon dioxide layer 1902 receives a patterned photoresist layer 1904. For example, a photoresist layer can be spin coated on layer 1902 and then exposed and the retractable cavity 1906 and mask pattern 1908 developed by lithography.

  Thereafter, a sacrificial layer 1912 such as n-doped silicon or metal such as molybdenum, tungsten or tantalum 1910, aluminum oxide is deposited in the cavity 1906 and forms the corresponding features 1914 and 1916.

  The photoresist 1912, material 1914, and aluminum oxide (Al 2 O 3) 1916 are then stripped to form an intermediate structure 1918 with the electrode 104 and sacrificial layer 304 on top of the photoresist 1912. A spin-on-glass (SOG) such as a flowable oxide (FOX) is spin coated on the structure 1918 and 200-2000 nm high on top of the sacrificial layer 1912. Annealed using a gradient temperature protocol at 600 ° C. using standard techniques to form a SiO 2 layer 1920 on the substrate.

  Reactive ion etching (RIE) or the like can then be used to etch the SiO 2 layer 1920 to form the structure 302 with the support 102.

  The choice of electrode material is limited by the method by which the nanotubes are placed on the substrate surface. The three methods include spin coat catalyst based growth, gas phase catalyst assisted CVD, nanotube spin coating or direct deposition. As described above, for growth based on the catalyst, is the catalyst spin coated or is the substrate immersed in the catalyst material followed by a standard cleaning protocol? On the surface. In each of these cases, the nanotubes are then grown by a CVD (Chemical Vapor Deposition) process at 800 ° C. using a combination of hydrogen and a carbon-containing precursor gas as described above. . Therefore, electrode materials that are sufficiently robust to withstand the temperature, including molybdenum, tungsten, tantalum, germanium, copper, and alloys thereof are considered preferred. The electrode material can be constructed of a single or bundle of materials including silicon, tungsten, molybdenum, tantalum, copper, etc. The bundled electrode structure helps and can create sufficient Schottky barriers for each memory bit rectification.

  The nanotubes are required for growth that allows the use of electrode materials that dissolve at temperatures as low as less than 800 ° C. and substantially as low as 400 ° C. when grown using a gas phase catalyst such as ferrocene. It is possible to substantially consider substantially lower temperatures. Certain gas phase catalysts of interest may include cobalt, tungsten, molybdenum or rhenium metallocenes containing five six-membered rings. With appropriate knowledge of inorganic chemistry, these compounds can be synthesized and placed in the gas phase to act as nucleation sites on the substrate for nanotube growth using bubbles. Of course, such materials are believed to be essentially usable with typical CMOS processes known in the literature and are used by standard industrial manufacturing facilities.

  If nanotubes are deposited on the surface at room temperature by spin coating of nanotube solutions or suspensions, then the choice of electrode material is substantially expanded. In this case, there is no high temperature step, and any metal typically used without hindrance along with standard CMOS metallization conditions, especially aluminum and their alloys, would be acceptable.

The sacrificial layer 304 can be constructed of Al ₂ O ₃ , metal oxides, salts, metals and other materials. The intermediate structure 302, including SOG, SiO ₂ and other, in order to form the support 102 can be formed using various materials. A nanotube protocol low temperature spin coating is selected, which substantially stretches the material suitable for the sacrificial layer. This includes metals such as PMMA or other polymers, tungsten, chromium, aluminum, bismuth, and other transition and major group metals. Also included are semiconductors such as germanium and insulators such as salts, oxides and other chalcogenides.

The choice of material for the support layer is highly dependent on the method chosen for nanotube growth and other factors. If a low temperature process is chosen to place the nanotubes on the surface, it can be envisaged to use such materials as polymers such as Al ₂ O ₃ , silicon monoxide, semiconductors, insulators, and polyimides.

  The material selection process is limited to such materials that can be used without hindrance with the manufacturing process described above. It is well understood by those skilled in the art in selecting a particular electrode material that the sacrificial layer and support material are limited based on typical processing steps useful in semiconductor manufacturing. Similarly, if a particular sacrificial layer is selected, the choice of electrode and sacrificial layer material is appropriately limited. Further, in selecting a particular support material, the selection of the electrode and sacrificial layer material is similarly limited.

  FIG. 20 shows an atomic force microscope (AFM) image of an exemplary nanotube woven fabric 312. In this photograph, each nanotube is about 1.5 nm in diameter. (The image is fuzzy because of the inherent limitations of the microscope, but it is not caused by the actual organization of a given nanotube.) This image is an atomic force microscope (AFM) Is taken at the lateral resolution limit.

  Most of the disclosure is written as if the woven fabric was of the same type, eg, all single-walled nanotubes, but the woven fabric was all multi-walled or single and multi-walled It can also be configured in combination with a structure.

Other Embodiments Standard lithographic methods for defining regions where nanotubes are intended to grow planarly on the surface to facilitate the growth of interconnects or electrode materials. Can be used to form a pattern first. Such an approach has been used to pattern SiO ₂ structures that grow thick multi-wall vertical nanotubes. In a similar approach, the patterned SiO ₂ structure can be used to grow horizontal nanotube films with a thickness of 1-1000 nm to create structures of the above-described forms such as 101. . Other materials that provide nanotube growth, nucleation such as insulators, and support for metal oxides can be appropriately selected vapor phase metallocene or other vapor deposited to produce patterned nanotube ribbons It can be useful when used with metal precursors. The underlying patterned layer can also act as a sacrificial layer that forms suspended nanotubes upon removal. This method of growth represents a form of “positive” growth, whereby the nanotubes use a pre-patterned surface as a nucleation site.

  In yet another embodiment, a “negative” growth method can be considered, whereby the lithographically patterned substrate includes a metal or other material that does not support nanotube growth. If a suitable gas phase precursor such as a metallocene or similar compound is supplied, it is conceivable that the nanotubes are originally grown only in the region without the patterned material. By removing the underlying material, the suspended nanotube 101 or interconnect structure can be supplied when the patterned metal species is removed.

  In yet another embodiment, instead of using a wet chemical removal method of the sacrificial layer to suspend the nanotubes at a specific height above the electrode, a controlled etch of the electrode (ie, a 0.18 μm wide electrode) 15 nm etching) can be used. That is, for example, metal (eg, copper) and semiconductor (eg, silicon) electrodes can be etched at an etch rate of a few nanometers / second.

  In another embodiment, pinning the nanotubes onto the support is performed using a thin coating that is stacked to prevent the tube from slipping during operation. This opens a “window” just above the memory cell itself.

  The electrical properties of the layer and conductive product can be tuned by controlling the cross section of the nanotube ribbon. For example, the ribbon thickness can be increased for a given width and nanotube density. A higher cross-section will increase the number of conductive channels that lead to improved electrical properties.

  By the method for producing the nanotube ribbon, continuous conductivity can be realized even on the rough surface topology. In contrast, the typical deposition of metal electrodes would suffer from structural and thus electrical defects.

  Apart from carbon nanotubes, other materials with electronic and mechanical properties suitable for electromechanical switching are being considered. These materials are believed to have similar properties to carbon nanotubes, but have different tensile strengths that are likely to be reduced. The tensile strength and adhesion energy of the material must be within a range that allows the bistability of the joint and electromechanical switching properties to be within acceptable tolerances.

  In order to integrate CMOS logic for addressing, two approaches can be considered. In a first embodiment, the nanotube array is integrated before metallization, but integration is also performed after ion implantation and planarization of the CMOS logic device. The second method involves the growth of the nanotube array prior to the fabrication of the CMOS device including ion implantation and high temperature annealing steps. In completing these steps, the final metallization of both the nanotube ribbon and the CMOS device will proceed using standard and widely used protocols.

  An electrode made of n-doped silicon on top of certain metal or semiconductor lines can also be envisaged. This provides a rectifying junction in the ON state so that there are no multiple current paths.

  In addition to rectifying connections, there are other widely accepted and used methods to prevent crosstalk (ie, multiple current paths) from occurring in the crossbar array. A tunnel barrier on top of a static, lithographically produced electrode prevents the formation of an ohmic ON state. Although no leakage current at zero bias voltage occurs, a small bias voltage should be applied for charge carriers to overcome the tunnel between this barrier and the crossing line.

  In order to modify the interaction with the electrode surface, various methods of increasing the adhesion energy by using ions, sharing or other forces can be considered. These methods can be used to expand the range of bistability with these connections.

  Nanotubes can be functionalized with planar conjugated hydrocarbons such as pyrene that can help improve the internal adhesion between the nanotubes within the ribbon.

  Certain of the above aspects, such as the hybrid circuit and addressing nanotube technology, can be applied to individual nanotubes or nanotube ribbons (eg, directional growth technology, etc.).

  The scope of the invention is not limited to the embodiments described above, but is further defined by the appended claims, and these claims include modifications and improvements to those described above.

FIG. 1 illustrates and describes a nanotube belt crossbar memory device according to a particular embodiment of the present invention. FIG. 2A illustrates and describes two states of a memory cell according to a particular embodiment of the present invention. FIG. 2B illustrates and describes two states of a memory cell according to a particular embodiment of the present invention. FIG. 3 illustrates the operation of creating a memory device according to a particular embodiment of the present invention. FIG. 4 illustrates some forms of creating an intermediate structure used to build a memory device according to a particular embodiment of the present invention. FIG. 5 illustrates several forms of creating an intermediate structure used to build a memory device according to a particular embodiment of the present invention. FIG. 6 illustrates several forms of creating an intermediate structure that is used to create a memory device according to a particular embodiment of the present invention. FIG. 7 illustrates some forms of creating an intermediate structure used to build a memory device according to a particular embodiment of the present invention. FIG. 8 illustrates some forms of creating an intermediate structure used to build a memory device according to a particular embodiment of the present invention. FIG. 9 illustrates and describes several forms of creating an intermediate structure used to create a memory device according to a particular embodiment of the present invention. FIG. 10 illustrates several forms of creating an intermediate structure used to create a memory device according to a particular embodiment of the present invention. FIG. 11 illustrates some forms of creating an intermediate structure used to build a memory device according to a particular embodiment of the present invention. FIG. 12 illustrates and illustrates a non-woven nanotube, or matted nanotube layer, used to create a particular embodiment of the present invention. FIG. 13 illustrates and illustrates a matted nanotube layer associated with a hidden and lying trace of a particular embodiment of the present invention. FIG. 14 illustrates the steps of addressing the logic of a particular embodiment of the present invention. FIG. 15 illustrates a hybrid technology embodiment of the present invention where the memory core uses nanotube technology. FIG. 16 illustrates a hybrid technology embodiment of the present invention where the memory core and addressing lines use nanotube ribbon technology. FIG. 17 illustrates the operation of creating a conductive product according to a particular embodiment of the present invention. FIG. 18 illustrates and describes how a conductive product according to a particular embodiment of the present invention is used to connect electrical components. FIG. 19 illustrates and describes one method of creating an intermediate structure according to a particular embodiment of the present invention. FIG. 20 illustrates and illustrates a non-woven nanotube woven or matted nanotube used to make certain embodiments of the present invention.

Claims (15)

An assembly comprising a substrate and conductive traces mounted on the substrate, the sheet-like structure extending in a plane ,
An assembly wherein the conductive trace includes a patterned non-woven mass of nanotubes by lithographic patterning to provide a plurality of conductive paths along the conductive trace.   The assembly of claim 1, wherein the nanotubes comprise single-walled carbon nanotubes.   The assembly of claim 1, wherein the nanotube comprises a multi-wall nanotube.   The assembly of claim 1, wherein the nanotubes have different lengths.   The assembly of claim 1, wherein the nanotubes comprise nanotubes having a length less than the length of the trace. An assembly comprising a substrate and conductive traces mounted on the substrate, the sheet-like structure extending in a plane ,
The patterned non-woven mass of nanotubes by lithographic patterning, wherein the conductive traces form an electrical network of nanotubes in contact with other nanotubes to provide a plurality of conductive paths along the conductive traces An assembly characterized by comprising:   The assembly of claim 6 wherein the nanotubes comprise single wall carbon nanotubes.   The assembly of claim 6, wherein the nanotubes comprise multi-walled nanotubes.   7. An assembly according to claim 6, wherein the nanotubes have different lengths.   7. The assembly of claim 6, wherein the nanotube comprises a nanotube having a length that is less than the length of the trace. An assembly comprising a substrate and conductive traces that are planar sheet-like structures ,
The conductive trace is provided on the substrate, and the conductive trace is a non-woven mass of nanotubes patterned by lithographic patterning to provide a plurality of conductive paths along the conductive trace. An assembly characterized by comprising: An assembly comprising a substrate, at least one metal electrode, and conductive traces that are planar sheet-like structures ,
The conductive trace is provided on the substrate, and the conductive trace is a non-woven mass of nanotubes patterned by lithographic patterning to provide a plurality of conductive paths along the conductive trace. Contains
The assembly wherein the metal electrode is provided on at least a portion of the conductive trace, the metal electrode being formed by a metallization process. A wafer substrate structure having a non-woven fabric of nanotubes, which is a planar extending sheet-like structure patterned by lithography patterning on a wafer substrate, wherein the nanotubes are arranged according to the intrinsic self-assembly characteristics of the nanotubes Wafer substrate structure characterized by being made. A wafer substrate structure having a non-woven fabric of nanotubes, which is a sheet-like structure extending in a plane, patterned by lithography patterning on a wafer substrate, wherein the non-woven fabric is a single layer of nanotubes Wafer substrate structure. A wafer substrate structure having a non-woven fabric of nanotubes, which is a planar sheet-like structure patterned by lithography patterning on a wafer substrate, the non-woven fabric having controlled density nanotubes A wafer substrate structure characterized by comprising:

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