JP5063100B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a floating gate and a control gate.

  2. Description of the Related Art A semiconductor device includes a non-volatile memory including a stacked gate having a control gate and a floating gate. The floating gate is provided on the semiconductor substrate via a tunnel oxide film, and a control gate is provided on the floating gate via an insulating film. The control gate has, for example, a WSi (tungsten silicide) layer and a polysilicon (polycrystalline silicon) layer, and the floating gate has, for example, a polysilicon layer.

As a method for forming the stack gate structure, a method combining dry etching and wet etching has been proposed (see, for example, Patent Document 1). According to this method, first, rough patterning of the stack gate structure is performed by dry etching. Thereafter, the polysilicon remaining between the floating gates adjacent to each other is removed by wet etching, and a short circuit between the floating gates is prevented.
Japanese Patent Laid-Open No. 2002-9040

  In the wet etching, not only the polysilicon remaining between adjacent floating gates is removed, but also the side walls of the stack gate are etched. For this reason, the width dimension of the control gate portion in the stack gate is reduced, and the coupling ratio K is reduced.

Here, the coupling ratio K is K = C ₂ / (C ₁ + C ₂ ). C ₁ is a capacitance between the semiconductor substrate and the floating gate, and C ₂ is a capacitance between the floating gate and the control gate. When the control gate voltage is V _CG , the floating gate voltage is V _FG = K · V _CG . Therefore, when the coupling ratio decreases, the floating gate voltage V _FG decreases. As a result, it becomes necessary to apply a high voltage to the control gate.

  The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing a decrease in the coupling ratio K when the side wall of the stack gate is etched. And

  According to one embodiment of the present invention, there is provided a semiconductor device manufacturing method including the following steps.

First, a first silicon layer in a polycrystalline state provided on the substrate, an insulating layer provided on the first silicon layer, and a second silicon layer in an amorphous state provided on the insulating layer A laminated film is formed. The laminated film is patterned to form a laminated body including a floating gate having a first silicon layer, an intergate insulating film having an insulating layer, and a control gate having a second silicon layer. The side walls of this laminate are etched under etching conditions in which the etching rate of polycrystalline silicon is faster than the etching rate of amorphous silicon. The laminated film is formed by depositing a first silicon layer in an amorphous state on a substrate, a heat treatment step for crystallizing the first silicon layer from an amorphous state to a polycrystalline state, and a crystallized first step. Depositing a second silicon layer in an amorphous state on one silicon layer.

  According to another embodiment of the present invention, there is provided a semiconductor device manufacturing method comprising the following steps.

  First, a first silicon layer provided on a substrate and containing an impurity element which is a donor or an acceptor, an insulating layer provided on the first silicon layer, and a first silicon layer provided on the insulating layer A laminated film having a second silicon layer having a higher impurity element content concentration is formed. The laminated film is patterned to form a laminated body including a floating gate having a first silicon layer, an intergate insulating film having an insulating layer, and a control gate having a second silicon layer. A second silicon oxide film is formed on the sidewall of the stacked body by oxidizing the exposed surface of the first silicon layer, and thicker than the first silicon oxide film by oxidizing the exposed surface of the second silicon layer. Is formed. A silicon oxide etching process is performed in which the second silicon layer is covered with the silicon oxide film on the side wall, and the side wall is etched so that the first silicon layer is exposed. After this silicon oxide etching step, the sidewall is etched under etching conditions in which the etching rate of silicon is higher than the etching rate of silicon oxide.

  According to one embodiment of the present invention, the sidewall of the stacked body including the floating gate having the first silicon layer in the polycrystalline state and the control gate having the second silicon layer in the amorphous state is etched. This etching is performed under the condition that the etching rate of polycrystalline silicon is higher than the etching rate of amorphous silicon. Therefore, the first silicon layer portion of the floating gate can be selectively etched on the side wall of the stacked body rather than the second silicon layer portion of the control gate. Thereby, the fall of a coupling ratio can be suppressed.

  According to another embodiment of the present invention, a floating gate having a first silicon layer containing an impurity element that is a donor or an acceptor, and the impurity element is contained at a higher concentration than the first silicon layer. The sidewall of the stack including the control gate having the second silicon layer is oxidized. Therefore, a thicker silicon oxide film is formed in the second silicon layer portion on the side wall of the stacked body. Since the thickness difference of the silicon oxide film occurs in this way, the sidewall is etched so that the second silicon layer is covered with the silicon oxide film and the first silicon layer is exposed on the sidewall of the stacked body. it can. After this, the sidewall is etched under etching conditions in which the etching rate of silicon is higher than the etching rate of silicon oxide, so that the floating gate portion is selectively etched rather than the control gate portion on the sidewall of the stacked body. Can do. Therefore, a reduction in coupling ratio can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking a NAND flash memory as an example of a semiconductor device. Needless to say, the present invention is not limited to the NAND type but can be applied to other types of semiconductor devices such as an AND type, an OR type, a NOR type, and a DINOR type.

(Embodiment 1)
FIG. 1 is a diagram showing a schematic circuit configuration of the semiconductor device according to the first embodiment. Referring to FIG. 1, a plurality of memory cells MC are arranged in a matrix in a memory cell array of a NAND flash memory. Each control gate of the memory cells MC arranged in the row direction (horizontal direction in the figure) is connected to a word line WL extending in the row direction. A plurality of memory cells MC arranged in the column direction (vertical direction in the figure) are connected in series.

  The bit line side select transistor SG1 is connected to one end of the memory cell MC group connected in series, and the source line side select transistor SG2 is connected to the other side. The source of the bit line side select transistor SG1 is connected to the bit line BL which is a data line, and the source of the source line side select transistor SG2 is connected to the common source line CS.

  The gates of the bit line side select transistors SG1 arranged in the row direction are connected to a bit line side select gate line BSG extending in the row direction. Each gate of the source line side select transistors SG2 arranged in the row direction is connected to a source line side select gate line SSG extending in the row direction.

  FIG. 2 is a schematic plan view showing a planar layout in the memory cell array of the semiconductor device according to the first embodiment of the present invention. 3 is a schematic sectional view taken along line III-III in FIG. 2, and FIG. 4 is a schematic sectional view taken along line IV-IV in FIG.

  Referring mainly to FIG. 2, a plurality of memory cells MC are arranged in a matrix on the surface of p-type silicon substrate SB. A word line WL (FIG. 1) integrated with the control gate CG of each memory cell MC extends in the row direction (vertical direction in FIG. 2). The active region in which the source / drain region 2 of each memory cell MC is formed extends in the column direction (lateral direction in FIG. 2).

  Referring mainly to FIG. 4, a groove 1 a is formed on the surface of the silicon substrate SB, and the groove 1 a is filled with a buried insulating layer 3. The trench 1a and the buried insulating layer 3 constitute STI (Shallow Trench Isolation). The active region of the silicon substrate SB is surrounded by this STI.

  Referring mainly to FIG. 3, each of the plurality of memory cells MC includes a pair of n-type source / drain regions 2, a gate insulating layer 4, a floating gate FG, an inter-gate insulating film GI, a control And a gate CG. A pair of source / drain regions 2 are formed at a distance from each other on the surface of the active region. Floating gate FG is located on a region sandwiched between a pair of source / drain regions 2 via gate insulating layer 4. The control gate CG is formed on the floating gate FG via an inter-gate insulating film GI. An inorganic film 6 is formed on the control gate CG.

  The floating gate FG is formed of a first silicon layer S1p having a thickness of 20 nm made of polycrystalline silicon. This silicon contains an impurity element which is a donor or an acceptor.

  The control gate CG has a multilayer structure. The lower layer side of the multilayer structure is a polycrystalline second silicon layer S2p containing an impurity element which is a donor or acceptor, and the upper layer side is a tungsten silicide layer 5.

  The inter-gate insulating film GI is formed of an insulating layer IL such as an oxynitride film (ONO (Oxide-Nitride-Oxide) film) having a thickness of 10 nm.

  A thin oxide film not shown in FIG. 3 is formed on the outermost surfaces of the floating gate FG and the control gate CG.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
5 to 18 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. 5 (a) to 18 (a) show cross sections corresponding to the broken lines in FIG. 3, and FIGS. 5 (b) to 18 (b) show cross sections corresponding to the line IV-IV in FIG. Show.

  Referring to FIGS. 5A and 5B, after the trench 1a is selectively formed on the surface of the p-type silicon substrate SB, the buried insulating layer 3 is formed so as to be buried in the trench 1a. . The trench 1a and the buried insulating layer 3 form an STI for isolating the active region.

  6A and 6B, a silicon oxide film, for example, is formed as a gate insulating layer 4 on the surface of the active region of the silicon substrate SB by a thermal oxidation method.

7A and 7B, the amorphous first silicon layer S1a containing phosphorus (P) at a concentration of 2 × 10 ²⁰ atoms / cm ³ on the gate insulating layer 4 is 20 nm. Deposited in film thickness. Note that the silicon substrate SB is heated to 520 ° C. during the deposition.

  Referring mainly to FIGS. 8A and 8B, the amorphous first silicon layer S1a is selectively etched using a photoresist pattern (not shown) formed by photolithography as a mask. Removed. As a result, the amorphous first silicon layer S1a is patterned, and the length of the floating gate FG in the row direction (lateral direction in FIG. 4) is defined. Thereafter, the photoresist pattern (not shown) is removed.

  Referring mainly to FIGS. 9A and 9B, a heat treatment step is performed in which silicon substrate SB is heated to 1000 ° C. As a result, the amorphous first silicon layer S1a (FIG. 8) is crystallized and changed to the polycrystalline first silicon layer S1p. Further, during this heat treatment step, that is, while the silicon substrate SB is heated to 1000 ° C., an oxynitride film is deposited to a thickness of 10 nm as the insulating layer IL.

Referring to FIGS. 10A and 10B, the amorphous second silicon layer S2a containing phosphorus (P) at a concentration of 2 × 10 ²⁰ atoms / cm ³ is 100 nm on the insulating layer IL. Deposited in thickness. Note that the silicon substrate SB is heated to 520 ° C. during the deposition.

  Referring to FIGS. 11A and 11B, a tungsten silicide layer 5 is deposited to a thickness of 100 nm on the amorphous second silicon layer S2a. Note that the silicon substrate SB is heated to 550 ° C. during the deposition. As a result, a stacked film SF including the polycrystalline first silicon layer S1p, the insulating layer IL, the amorphous second silicon layer S2a, and the tungsten silicide layer 5 is formed on the substrate SB. Subsequently, an inorganic film 6 such as a TEOS (Tetra Ethyl Ortho Silicate) oxide film is deposited to a thickness of 100 nm on the stacked film SF. During this deposition, the silicon substrate SB is heated to 680 ° C.

  Referring to FIGS. 12A and 12B, a photoresist 7 patterned by photolithography is formed on the inorganic film 6. Subsequently, anisotropic dry etching is performed using the photoresist 7 as a mask, and the inorganic film 6 is patterned. Note that the photoresist 7 remaining after the etching is removed by ashing.

  Referring to FIGS. 13A and 13B, the pattern of the inorganic film 6 is formed by the above patterning. Subsequently, anisotropic dry etching of the laminated film SF is performed using the inorganic film 6 as a mask.

  Referring to FIGS. 14A and 14B, patterning of the tungsten silicide layer 5, the amorphous second silicon layer S2a, the insulating layer IL, and the polycrystalline first silicon layer S1p is continuously performed by this dry etching. Done. By this patterning, the control gate CG having the tungsten silicide layer 5 and the amorphous second silicon layer S2a is formed. Further, an inter-gate insulating film GI is formed from the insulating layer IL. A floating gate FG is formed from the first silicon layer S1p. As a result, a stacked body LB including the floating gate FG, the intergate insulating film GI, and the control gate CG is formed.

  In the stage immediately after the dry etching, there may be residual silicon RS remaining between the floating gates FG adjacent to each other because the first silicon layer S1p is not completely etched.

  Subsequently, ashing is performed. The side wall of the stacked body LB is in a state in which a side wall deposit 8 made of an oxide formed by ashing or a polymer adhered during the dry etching is formed. The side wall deposits 8 are removed by a 30-second cleaning process with hydrofluoric acid having a concentration of 0.3% by weight.

  Referring to FIGS. 15A and 15B, the first silicon layer S1p and the second silicon layer S2a are exposed on the side wall of the stacked body LB by the above processing.

  Referring mainly to FIGS. 16A and 16B, a sidewall etching process is performed in which the sidewall of the stacked body LB is wet-etched. As an etching condition, a condition is selected in which the etching rate of polycrystalline silicon is higher than the etching rate of amorphous silicon. For this reason, the progress of etching for polycrystalline silicon (arrow Ep in the figure) proceeds more than the progress of etching for amorphous silicon (arrow Ea in the figure).

  As a result of this wet etching, the dimension in the width direction (lateral direction in the figure) of the first silicon layer S1p in the polycrystalline state is smaller than the dimension in the width direction (lateral direction in the figure) of the second silicon layer S2a in the amorphous state. Become. Further, the remaining silicon RS (FIG. 15) is removed.

  As an etching solution, a mixed chemical solution (APM (Ammonia-Hydrogen Peroxide-Water Mixture)) of ammonia water, hydrogen peroxide water, and pure water can be used. The mixing ratio of the aqueous ammonia and the aqueous hydrogen peroxide is set so that the etching action by ammonia is stronger than the oxidizing action by hydrogen peroxide (ammonia rich). For example, etching is performed at 70 ° C. for 10 minutes using an etching solution in which ammonia water having a concentration of 29% by weight, hydrogen peroxide solution having a concentration of 30% by weight, and pure water are mixed at a ratio of 5: 2: 500. Can do.

  Referring to FIGS. 17A and 17B, source / drain regions 2 are formed so as to sandwich each floating gate FG by ion implantation or the like.

  Referring mainly to FIGS. 18A and 18B, oxide film 9 is formed on the side walls of floating gate FG and control gate CG by, for example, ISSG (In Situ Steam Generation) at 1000 ° C. At this time, the second silicon layer S2a (FIG. 17) in the amorphous state is crystallized due to the high temperature and changes to the second silicon layer S2p in the polycrystalline state. Thereby, the semiconductor device (FIGS. 3 and 4) is manufactured.

  According to the semiconductor device manufacturing method of the present embodiment, as shown in FIG. 15, the floating gate FG having the polycrystalline first silicon layer S1p and the control gate CG having the amorphous second silicon layer S2a. Is formed. Therefore, as shown in FIG. 16, the stacked body LB is etched under the etching conditions in which the etching speed of polycrystalline silicon (arrow Ep in the figure) is higher than the etching speed of amorphous silicon (arrow Ea in the figure). By etching the side walls of the film, selective etching can be performed. This etching suppresses the reduction in the width direction (lateral direction in FIG. 16) dimension of the second silicon layer S2a portion of the control gate CG, while suppressing the decrease in the width direction (lateral direction in FIG. (Direction) dimension can be reduced. For this reason, it is possible to remove the residual silicon RS (FIG. 15) while suppressing a decrease in the coupling ratio K.

Further, by etching the side wall of the stacked body LB, it is possible to widen the interval between the adjacent floating gates FG while suppressing a decrease in the coupling ratio K. Therefore, it is possible to prevent a problem caused by the adjacent floating gates interfering with each other without the side effect of lowering the floating gate voltage V _FG . Note that examples of defects include a shift of the threshold voltage Vth at the time of reading from the memory and erroneous extraction of electrons (adjacent word disturb) from the floating gate FG.

  Further, as shown in FIG. 7, the silicon layer constituting at least a part of the floating gate FG is first deposited as an amorphous first silicon layer S1a. For this reason, the temperature of the silicon substrate SB during the deposition process can be lowered as compared with the case where polycrystalline silicon is deposited.

  As shown in FIG. 9, the insulating layer IL is formed when the amorphous first silicon layer S1a (FIG. 8) is crystallized into the polycrystalline first silicon layer S1p by heat treatment. For this reason, when the insulating layer IL needs to be formed at a high temperature, the heat treatment of the first silicon layer S1a and the formation of the insulating layer IL can be performed only by raising the temperature of the silicon substrate SB once. it can.

(Embodiment 2)
Although the present embodiment differs from the first embodiment in the manufacturing method, the configuration of the semiconductor device (FIGS. 1 to 4) is the same. For this reason, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted. A method for manufacturing the semiconductor device of the present embodiment will be described below.

  19 and 20 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. 19 (a) and 20 (a) show a cross section corresponding to the broken line portion of FIG. 3, and FIGS. 19 (b) and 20 (b) show a cross section corresponding to the IV-IV line of FIG. Show.

Referring to FIGS. 19A and 19B, the first silicon layer S1p in a polycrystalline state containing phosphorus (P) at a concentration of 2 × 10 ²⁰ atoms / cm ³ on the gate insulating layer 4 is 20 nm. Deposited with a film thickness of Note that the silicon substrate SB is heated to 1000 ° C. during the deposition.

  Referring mainly to FIGS. 20A and 20B, the polycrystalline first silicon layer S1p is selectively formed using a photoresist pattern (not shown) formed by photolithography as a mask. Etched away. As a result, the polycrystalline first silicon layer S1p is patterned, and the length of the floating gate FG in the row direction (lateral direction in FIG. 4) is defined. Thereafter, the photoresist pattern (not shown) is removed.

  Subsequent steps are performed in the same manner as the steps after FIG. 9 in the method of manufacturing the semiconductor device of the first embodiment, and thus description thereof is omitted.

  According to the manufacturing method of the semiconductor device of the present embodiment, as shown in FIG. 19, the first silicon layer S1p is deposited not in the amorphous state but in the polycrystalline state. Therefore, it is not necessary to perform heat treatment for changing the amorphous state to the polycrystalline state thereafter.

(Embodiment 3)
The planar layout of the semiconductor device of the present embodiment is the same as the planar layout (FIG. 2) of the first embodiment described above. For this reason, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted.

  21 and 22 are schematic cross-sectional views of the semiconductor device according to the third embodiment of the present invention. Each of FIGS. 21 and 22 corresponds to a position along each of the III-III line and the IV-IV line in FIG. 2.

  Referring to FIGS. 21 and 22, floating gate FG is formed of a first silicon layer SLp in a polycrystalline state having a thickness of 20 nm. This silicon contains an impurity element which is a donor or an acceptor.

  The control gate CG has a multilayer structure. The lower layer side of the multilayer structure is a polycrystalline second silicon layer SHp, and the upper layer side is a tungsten silicide layer 5. The second silicon layer SHp contains the above-described impurity element at a higher concentration than the first silicon layer SLp.

  A method for manufacturing the semiconductor device of the present embodiment will be described below. Since the process up to the step of FIG. 6 in the method for manufacturing the semiconductor device of the first embodiment is performed in the same manner in the method for manufacturing the semiconductor device of the present embodiment, the description thereof is omitted.

  23 to 35 are schematic cross-sectional views illustrating the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps. 23 (a) to 35 (a) show cross sections corresponding to the broken lines in FIG. 21, and FIGS. 23 (b) to 35 (b) are cross sections corresponding to the line IV-IV in FIG. FIG. 22 shows a cross section corresponding to FIG.

Referring to FIGS. 23A and 23B, the first silicon layer SLa in an amorphous state containing phosphorus (P) at a concentration of 2 × 10 ²⁰ atoms / cm ³ on the gate insulating layer 4 has a thickness of 20 nm. Deposited in film thickness. Note that the silicon substrate SB is heated to 520 ° C. during the deposition.

  Referring mainly to FIGS. 24A and 24B, the amorphous first silicon layer SLa is selectively etched using a photoresist pattern (not shown) formed by photolithography as a mask. Removed. As a result, the amorphous first silicon layer SLa is patterned, and the length of the floating gate FG in the row direction (lateral direction in FIG. 22) is defined. Thereafter, the photoresist pattern (not shown) is removed.

  Referring to FIGS. 25A and 25B, a heat treatment step is performed in which silicon substrate SB is heated to 1000 ° C. Thereby, the first silicon layer SLa in the amorphous state is crystallized and changed to the first silicon layer SLp in the polycrystalline state. Further, during this heat treatment step, that is, while the silicon substrate SB is heated to 1000 ° C., an oxynitride film is deposited to a thickness of 10 nm as the insulating layer IL.

Referring to FIGS. 26A and 26B, a film having an amorphous second silicon layer SHa containing 100 nm of phosphorus (P) at a concentration of 4 × 10 ²⁰ atoms / cm ³ on insulating layer IL. Deposited in thickness. Note that the silicon substrate SB is heated to 520 ° C. during the deposition.

  Referring to FIGS. 27A and 27B, a tungsten silicide layer 5 is deposited to a thickness of 100 nm on the amorphous second silicon layer SHa. Note that the silicon substrate SB is heated to 550 ° C. during the deposition. Thus, the first silicon layer SLp containing the impurity element which is a donor or acceptor, the insulating layer IL, and the second silicon layer containing the impurity element at a higher concentration than the first silicon layer SLp on the substrate SB. A stacked film SF3 having SHa and the tungsten silicide layer 5 is formed.

  Subsequently, an inorganic film 6 such as a TEOS oxide film is deposited on the stacked film SF3 to a thickness of 100 nm. During this deposition, the silicon substrate SB is heated to 680 ° C.

  Referring to FIGS. 28A and 28B, heat treatment is performed at a temperature of 1000 ° C. for 60 seconds in a nitrogen atmosphere. Thereby, the inorganic film 6 such as the TEOS oxide film is baked. In addition, the amorphous second silicon layer SHa is crystallized and changed to a polycrystalline second silicon layer SHp. As a result, both the first and second silicon layers SLp and SHp are in a polycrystalline state.

  Referring to FIGS. 29A and 29B, a photoresist 7 patterned by a photoengraving technique is formed on the inorganic film 6. Subsequently, anisotropic dry etching is performed using the photoresist 7 as a mask, and the inorganic film 6 is patterned. Note that the photoresist 7 remaining after the etching is removed by ashing.

  Referring to FIGS. 30A and 30B, the pattern of the inorganic film 6 is formed by the above patterning. Subsequently, anisotropic dry etching of the laminated film SF3 is performed using the inorganic film 6 as a mask.

  Referring to FIGS. 31A and 31B, patterning of tungsten silicide layer 5, polycrystalline second silicon layer SHp, insulating layer IL, and polycrystalline first silicon layer SLp is performed by this dry etching. Done continuously. By this patterning, a control gate CG having the tungsten silicide layer 5 and the second silicon layer SHp is formed. Further, an inter-gate insulating film GI is formed from the insulating layer IL. A floating gate FG is formed from the first silicon layer SLp. As a result, a stacked body LB including the floating gate FG, the intergate insulating film GI, and the control gate CG is formed.

  In the stage immediately after this dry etching, there may be residual silicon RS remaining between the floating gates FG adjacent to each other because the first silicon layer SLp is not completely etched.

  Subsequently, an oxidization process for oxidizing the exposed surfaces of the first and second silicon layers SLp and SHp is performed on the sidewalls of the stacked body LB by ashing. Thereby, on the side wall of the stacked body LB, the first silicon oxide film OL is formed on the surface of the first silicon layer SLp, and the second silicon oxide film OH is formed on the surface of the second silicon layer SHp. Here, the dimension DH in the thickness direction (lateral direction in the figure) of the second silicon oxide film OH is larger than the dimension DL in the thickness direction (lateral direction in the figure) of the first silicon oxide film OL. This is because the concentration of the impurity element which is a donor or acceptor contained in silicon is higher in the second silicon layer SHp than in the first silicon layer SLp.

  Subsequently, a silicon oxide etching step for removing a part of the second silicon oxide film OH and the first silicon oxide film OL is performed. By this step, the silicon oxide film is etched by not less than the thickness dimension DL and less than the thickness dimension DH on the side wall of the stacked body LB.

  As an etching condition, for example, wet etching for 10 seconds with a hydrofluoric acid having a concentration of 0.3% by weight can be performed. In addition to hydrofluoric acid, an aqueous ammonium fluoride solution can also be used.

  Referring to FIGS. 32A and 32B, as a result of the etching, the second silicon layer SHp is covered with the second silicon oxide film OH on the side wall of the stacked body LB, and the first silicon layer SLp is formed. Is exposed.

  Subsequently, a silicon etching process is performed in which the sidewalls of the stacked body LB are wet-etched under etching conditions in which the etching rate of silicon is higher than the etching rate of silicon oxide. As the etchant, an etchant containing an alkali having an OH group can be used. Specifically, ammonia, TMAH (Tetra Methyl Ammonium Hydroxide), potassium hydroxide, or the like can be used.

  Further, in order to suppress the surface roughness (etching unevenness) of silicon during etching, an oxidizing agent (an aqueous solution having an oxidizing power with respect to silicon) is added to the etching solution. As the oxidizing agent, hydrogen peroxide water, ozone water, or the like can be used. However, the addition amount is within a range where the oxidizing action by the oxidizing agent does not become stronger than the etching action of silicon by the alkali.

  Specifically, ammonia water having a concentration of 29% by weight, hydrogen peroxide solution having a concentration of 30% by weight, and pure water mixed at 5: 2: 500 at 70 ° C., 10 ° C. The silicon etching process can be performed by wet etching for a minute.

  Referring to FIGS. 33A and 33B, as a result of this etching, the width direction of the first silicon layer SLp (lateral direction in the figure) is the same as the width direction of the second silicon layer SHp (lateral direction in the figure). ) Is smaller than the dimension. Further, the remaining silicon RS (FIG. 15) is removed.

  Referring to FIGS. 34A and 34B, source / drain regions 2 are formed so as to sandwich each floating gate FG by ion implantation or the like.

  Referring to FIGS. 35A and 35B, oxide film 9 is formed on the sidewalls of floating gate FG and control gate CG by, for example, 1000 ° C. ISSG. Thereby, the semiconductor device shown in FIGS. 21 and 22 is manufactured.

  In the above manufacturing method, the first silicon layer SLa (FIG. 23) and the second silicon layer SHa (FIG. 26) are deposited in a state containing phosphorus (P). Instead, phosphorus (P) may be contained in silicon by ion implantation after deposition. Further, by increasing the temperature of the substrate SB during the deposition, silicon may be deposited in a polycrystalline state instead of an amorphous state.

  As the impurity element, a donor or acceptor (boron (B), arsenic (As), or the like) for silicon other than phosphorus (P) can be used.

  In addition, the oxidation process for oxidizing the exposed surfaces of the first and second silicon layers SLp and SHp on the side wall of the stacked body LB is not limited to that by ashing. For example, the oxidation process can be performed using an aqueous solution in which oxygen is dissolved, ozone water, hydrogen peroxide water, or the like. Alternatively, the oxidation step can be performed by leaving in the air or an oxygen atmosphere.

  According to the manufacturing method of the semiconductor device of the present embodiment, as shown in FIG. 31, the floating gate FG having the first silicon layer SLp containing the impurity element and the second silicon containing the impurity element having a higher concentration. A control gate CG having the layer SHp is formed. For this reason, the second silicon layer SHp portion on the side wall of the stacked body LB is more easily oxidized than the first silicon layer portion SLp portion. As a result, the thickness dimension DH of the second silicon oxide film OH formed in the second silicon layer SHp part becomes larger than the thickness dimension DL of the first silicon oxide film OL formed in the first silicon layer SLp part. For this reason, the second silicon layer SHp is covered with the second silicon oxide film OH and the first silicon layer SLp is exposed on the sidewall of the stacked body LB by wet etching that removes silicon oxide by a thickness dimension DL or more and less than DH. It can be made the state.

  Thereafter, the sidewall of the stacked body LB is etched under an etching condition in which the etching rate of silicon is higher than the etching rate of silicon oxide, so that the second silicon layer SHp portion is etched as compared with the first silicon layer SLp portion. Can be suppressed. Therefore, as shown in FIG. 33, the width direction of the first silicon layer SLp portion of the floating gate FG is suppressed while suppressing the reduction in the width direction (lateral direction in the drawing) dimension of the second silicon layer SHp portion of the control gate CG. The horizontal dimension in the figure can be reduced. For this reason, it is possible to remove the remaining silicon RS (FIG. 32) while suppressing a decrease in the coupling ratio K.

  Further, by etching the side wall of the stacked body LB, the gap between the adjacent floating gates FG can be widened while suppressing the decrease in the coupling ratio K as in the first embodiment.

  Note that in the silicon oxide etching step (steps from FIG. 31 to FIG. 32), silicon oxide can be etched by using an etchant containing hydrofluoric acid or ammonium fluoride as an etchant.

  Further, in the silicon etching step (steps from FIG. 32 to FIG. 33), the etching solution containing an alkaline aqueous solution and an oxidizing agent aqueous solution is used, so that silicon can be etched with little unevenness.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a method of manufacturing a semiconductor device having a floating gate and a control gate.

It is a figure which shows the typical circuit structure of the semiconductor device in Embodiment 1 of this invention. 1 is a schematic plan view showing a planar layout in a memory cell array of a semiconductor device in Embodiment 1 of the present invention. It is a schematic sectional drawing which follows the III-III line of FIG. It is a schematic sectional drawing in alignment with the IV-IV line of FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 10th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 11th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 12th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 13th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 14th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 10th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 11th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 12th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic sectional drawing which shows the 13th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention.

Explanation of symbols

  FG floating gate, GI inter-gate insulating film, CG control gate, IL insulating layer, LB stack, S1p polycrystalline first silicon layer, S2a amorphous second silicon layer, SB substrate.

Claims (5)

A laminated film having a polycrystalline first silicon layer provided on a substrate, an insulating layer provided on the first silicon layer, and an amorphous second silicon layer provided on the insulating layer Laminating process to form,
Patterning the laminated film to form a laminated body including a floating gate having the first silicon layer, an intergate insulating film having the insulating layer, and a control gate having the second silicon layer;
A side wall etching step for etching the side wall of the laminate under an etching condition in which the etching rate of polycrystalline silicon is faster than the etching rate of amorphous silicon ,
The laminating step
Depositing the first silicon layer in an amorphous state on the substrate;
A heat treatment step of crystallizing the first silicon layer from an amorphous state to a polycrystalline state;
Depositing the second silicon layer in an amorphous state on the crystallized first silicon layer . In the heat treatment step, wherein said that the insulating layer is formed on the first silicon layer, a method of manufacturing a semiconductor device according to claim 1. A first silicon layer containing an impurity element which is a donor or an acceptor provided on the substrate; an insulating layer provided on the first silicon layer; and an insulating layer provided on the insulating layer, from the first silicon layer Forming a laminated film having a second silicon layer having a high concentration of the impurity element,
Patterning the laminated film to form a laminated body including a floating gate having the first silicon layer, an intergate insulating film having the insulating layer, and a control gate having the second silicon layer;
A first silicon oxide film is formed on the side wall of the stacked body by oxidizing the exposed surface of the first silicon layer, and a second thicker than the first silicon oxide film is formed by oxidizing the exposed surface of the second silicon layer. Forming a silicon oxide film;
A silicon oxide etching step of etching the sidewall so that the second silicon layer is covered with the silicon oxide film on the sidewall and the first silicon layer is exposed;
A method of manufacturing a semiconductor device, comprising: a silicon etching step that etches the sidewall under etching conditions in which a silicon etching rate is higher than a silicon oxide etching rate after the silicon oxide etching step. 4. The method of manufacturing a semiconductor device according to claim 3 , wherein the silicon oxide etching step is wet etching using an etchant containing hydrofluoric acid or ammonium fluoride. Method for producing the silicon etching step, characterized in that it is a wet etching using an etchant containing an alkali aqueous solution and oxidizing agent solution, the semiconductor device according to claim 3 or 4.

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