[go: up one dir, main page]

JP4994691B2 - Crystal oscillator for surface mounting - Google Patents

Crystal oscillator for surface mounting Download PDF

Info

Publication number
JP4994691B2
JP4994691B2 JP2006100025A JP2006100025A JP4994691B2 JP 4994691 B2 JP4994691 B2 JP 4994691B2 JP 2006100025 A JP2006100025 A JP 2006100025A JP 2006100025 A JP2006100025 A JP 2006100025A JP 4994691 B2 JP4994691 B2 JP 4994691B2
Authority
JP
Japan
Prior art keywords
ceramic
terminals
chip
pair
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006100025A
Other languages
Japanese (ja)
Other versions
JP2007184890A (en
Inventor
貢一 守谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nihon Dempa Kogyo Co Ltd
Original Assignee
Nihon Dempa Kogyo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nihon Dempa Kogyo Co Ltd filed Critical Nihon Dempa Kogyo Co Ltd
Priority to JP2006100025A priority Critical patent/JP4994691B2/en
Priority to US11/606,511 priority patent/US7602107B2/en
Publication of JP2007184890A publication Critical patent/JP2007184890A/en
Priority to US12/584,155 priority patent/US7932786B2/en
Priority to US12/584,168 priority patent/US8008980B2/en
Application granted granted Critical
Publication of JP4994691B2 publication Critical patent/JP4994691B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Oscillators With Electromechanical Resonators (AREA)

Description

本発明は表面実装用の水晶発振器(以下、表面実装発振器とする）を技術分野とし、特にＩＣチップの接続を確実にして小型で安価な表面実装発振器に関する。   The present invention relates to a surface mount crystal oscillator (hereinafter referred to as a surface mount oscillator), and more particularly to a small and inexpensive surface mount oscillator that ensures connection of an IC chip.

（発明の背景）
表面実装発振器は小型・軽量であることから、特に携帯電話を代表としてコンパクトな移動型の電子機器に、周波数や時間の基準源として内蔵される。このようなものの一つに、本出願人による表面実装発振器がある（特許文献１参照）。 (Background of the Invention)
Since surface-mounted oscillators are small and lightweight, they are built in as a reference source for frequency and time in compact mobile electronic devices such as mobile phones. One of such devices is a surface mount oscillator by the present applicant (see Patent Document 1).

（従来技術の一例）
第４図は一従来例を説明する表面実装発振器の図で、同図（ａ）は断面図、同図（ｂ）はＩＣチップの回路機能面（一主面）の図、同図（ｃ）は水晶片の平面図である。 (Example of conventional technology)
FIG. 4 is a diagram of a surface-mount oscillator for explaining a conventional example . FIG. 4 (a) is a sectional view, FIG. 4 (b) is a diagram of a circuit function surface (one main surface) of the IC chip, and FIG. ) Is a plan view of the crystal piece.

表面実装発振器は密閉容器１内にＩＣチップ２と水晶片３とを収容してなる。密閉容器１はセラミック基板（実装基板）４と金属カバー５とからなる。セラミック基板４は矩形状とした平板状の第１セラミック４ａと開口部を有して凹部を形成する第２セラミック４ｂとを積層してなる。第１セラミック４ａは積層面側の表面（凹部底面）にＩＣチップ２と電気的に接続する回路端子６を有し、裏面の４角部に実装電極７を有する。   The surface mount oscillator includes an IC chip 2 and a crystal piece 3 housed in a sealed container 1. The sealed container 1 includes a ceramic substrate (mounting substrate) 4 and a metal cover 5. The ceramic substrate 4 is formed by laminating a flat plate-like first ceramic 4a having a rectangular shape and a second ceramic 4b having an opening and forming a recess. The first ceramic 4a has circuit terminals 6 that are electrically connected to the IC chip 2 on the surface on the laminated surface side (the bottom surface of the recess), and mounting electrodes 7 on the four corners on the back surface.

実装電極７はスルーホールによる側面電極７ｂ及び第１と第２セラミック４（ａｂ）との積層面を経て、ＩＣチップ２のＩＣ端子８が固着される回路端子６に電気的に接続する。側面電極７ｂは図示しないセット基板への実装時に半田フィレットを形成する。第２セラミック４ｂは周回する外周に封止用の金属膜９を有し、一端部両側に水晶保持端子１０を有する。金属カバー５は凹状とし、開口端面が第２セラミック４ｂの金属膜９上に接合される。例えば共晶合金ＡuＳn等の金属ロウ１１を用いた熱圧着によって接合される。   The mounting electrode 7 is electrically connected to the circuit terminal 6 to which the IC terminal 8 of the IC chip 2 is fixed through the side surface electrode 7b by the through hole and the laminated surface of the first and second ceramics 4 (ab). The side electrode 7b forms a solder fillet when mounted on a set substrate (not shown). The second ceramic 4b has a sealing metal film 9 on the outer periphery that circulates, and has crystal holding terminals 10 on both sides of one end. The metal cover 5 has a concave shape, and the opening end face is bonded onto the metal film 9 of the second ceramic 4b. For example, bonding is performed by thermocompression bonding using a metal braze 11 such as a eutectic alloy AuSn.

ＩＣチップ２は少なくとも発振回路を集積化し、回路機能面である一主面に複数のＩＣ端子８を有する。そして、第１セラミック４ａ上の回路端子６にバンプ１２を用いた超音波熱圧着によって固着される。これにより、ＩＣチップ２の各ＩＣ端子８と実装電極７及び水晶保持端子１０とが電気的に接続する。   The IC chip 2 integrates at least an oscillation circuit and has a plurality of IC terminals 8 on one main surface which is a circuit function surface. And it adheres to the circuit terminal 6 on the 1st ceramic 4a by ultrasonic thermocompression using the bump 12. FIG. Thereby, each IC terminal 8 of the IC chip 2 is electrically connected to the mounting electrode 7 and the crystal holding terminal 10.

ＩＣ端子８は少なくとも一対の水晶端子、及び電源、出力、アース、自動制御（ＡＦＣ）端子を有する。水晶片３は両主面に励振電極１３を有し、長さ方向の一端部両側に引出電極１４を延出する。そして、引出電極１４の延出した一端部両側が水晶保持端子１０に導電性接着剤１５等によって固着される。水晶保持端子１０はＩＣチップ２の水晶端子と電気的に接続する。電源、出力、アース、自動制御（ＡＦＣ）端子は実装電極７と電気的に接続する   The IC terminal 8 has at least a pair of crystal terminals and a power source, output, ground, and automatic control (AFC) terminal. The crystal piece 3 has excitation electrodes 13 on both main surfaces, and extends extraction electrodes 14 on both sides of one end in the length direction. Then, both ends of the extended end portion of the extraction electrode 14 are fixed to the crystal holding terminal 10 by the conductive adhesive 15 or the like. The crystal holding terminal 10 is electrically connected to the crystal terminal of the IC chip 2. Power supply, output, ground, automatic control (AFC) terminal is electrically connected to mounting electrode 7

このようなものでは、特に金属カバー５ａを凹状としてセラミック基板４の外周に接合するので、内積を大きくできる。逆に言えば、小型化を促進できる。例えば第５図に示したように、凹状とした積層セラミックからなる容器本体１に平板状の金属カバー５を接合した場合は、製造上の観点等から容器本体１の最上位層の枠幅は高さ寸法と同等以上にする必要がある。したがって、最上位層の枠幅ｄ２は必然的に大きくなる。ちなみに、容器本体１の最上位層の枠幅ｄ２を例えば0.35ｍｍとすると、金属カバー５の厚みｄ１は例えば0.08ｍｍとして格段に小さくできる。
特開２００３−３１８６９０号公報 実開平６−４８２１５号公報 特開平８−３０７１５３号公報 In such a case, since the metal cover 5a is formed in a concave shape and joined to the outer periphery of the ceramic substrate 4, the inner product can be increased. In other words, downsizing can be promoted. For example, as shown in FIG. 5, when a flat metal cover 5 is joined to a container body 1 made of a laminated ceramic having a concave shape, the frame width of the uppermost layer of the container body 1 is from the viewpoint of manufacturing. It must be equal to or higher than the height dimension. Accordingly, the frame width d2 of the uppermost layer is necessarily increased. Incidentally, when the frame width d2 of the uppermost layer of the container body 1 is set to 0.35 mm, for example, the thickness d1 of the metal cover 5 can be significantly reduced to 0.08 mm, for example.
JP 2003-318690 A Japanese Utility Model Publication No. 6-48215 JP-A-8-307153

（従来技術の問題点）
しかしながら、上記構成の表面実装発振器では、ＩＣチップ２を固着して水晶片３の一端部を固着することから、平板状の第１セラミック４ａと開口部を有する第２セラミック４ｂとを積層する。通常では、第６図（ａ）に示したように、予め電極パターンが形成されてシート状とした平板状の第１セラミック生地４Ａと開口部を有する第２セラミック生地４Ｂを積層する。そして、これらを一体的に焼成した後、分割線Ｘ−Ｘに沿って分割し、個々のセラミック基板４を得る。 (Problems of conventional technology)
However, in the surface mount oscillator having the above configuration, since the IC chip 2 is fixed and one end of the crystal piece 3 is fixed, the flat plate-like first ceramic 4a and the second ceramic 4b having an opening are laminated. Normally, as shown in FIG. 6 (a), a plate-like first ceramic cloth 4A having an electrode pattern formed in advance and made into a sheet shape and a second ceramic cloth 4B having an opening are laminated. And after baking these integrally, it divides | segments along the dividing line XX, and obtains each ceramic substrate 4. FIG.

この場合、積層されたシート状のセラミック生地の両主面側から楔状の分割溝１６を設け「第６図（ｂ）、同図（ａ）の○囲み部の一部拡大図」、セラミック基板４独立的にして焼成する。これにより、焼成後の分割を容易にする。しかし、この場合には、第１セラミック４ａは平板状として、第２セラミック４ｂは開口部を有して枠状とする。 In this case, wedge-shaped dividing grooves 16 are provided from both principal surface sides of the laminated sheet-like ceramic fabric, " FIG. 6 (b), partially enlarged view of the encircled portion in FIG. 6 (a)", ceramic substrate 4 Independent firing. This facilitates division after firing. However, in this case, the first ceramic 4a has a flat plate shape, and the second ceramic 4b has a frame shape with an opening.

したがって、焼成時には、セラミック生地からのバインダの蒸発に伴う収縮力が、特に第２セラミック４ｂによる枠部上端に集中して開口面積を小さくする方向の外力Ｐが発生する。したがって、第１セラミック４ａは凹面状に湾曲する。これにより、セラミック基板４は、特に凹部底面の平坦度（平面精度）悪化する問題があった。   Therefore, at the time of firing, an external force P is generated in a direction in which the contraction force accompanying the evaporation of the binder from the ceramic fabric is concentrated particularly on the upper end of the frame portion due to the second ceramic 4b to reduce the opening area. Accordingly, the first ceramic 4a is curved in a concave shape. Thereby, the ceramic substrate 4 has a problem that the flatness (planar accuracy) of the bottom surface of the recess is deteriorated.

このことから、実装基板４の凹部底面（第１セラミックの表面）に、バンプ１２を用いた超音波熱圧着によってＩＣチップ２を固着する場合、第６図（ｃ）に示したように平坦度に欠けた凹面部では充分な押圧力が加わらず、固着強度を小さくする問題があった。この場合、電気的接触が損なわれるとともに、衝撃に対して剥離を引き起こす弊害を招く。ちなみに、凹部底面の平坦度は10〜15μｍ以下が望まれる。 Therefore, when the IC chip 2 is fixed to the bottom surface of the recess (the surface of the first ceramic) of the mounting substrate 4 by ultrasonic thermocompression using the bumps 12, the flatness as shown in FIG. 6 (c) . There is a problem in that a sufficient pressing force is not applied to the concave surface portion lacking in the thickness and the fixing strength is reduced. In this case, the electrical contact is impaired, and a detrimental effect that causes peeling upon impact is caused. Incidentally, the flatness of the bottom surface of the recess is desired to be 10 to 15 μm or less.

（発明の目的）
本発明はセラミック基板の平坦度に優れてバンプを用いた超音波熱圧着による接合を確実にし、小型化に適した表面実装発振器を提供することを目的とする。 (Object of invention)
It is an object of the present invention to provide a surface mount oscillator that is excellent in flatness of a ceramic substrate, ensures bonding by ultrasonic thermocompression using a bump, and is suitable for miniaturization.

本発明は、特許請求の範囲（請求項１）に示したように、一主面の周回する外周に金属膜を有して他主面の４角部に実装電極を有する矩形状のセラミック基板と、前記金属膜に開口端面が固着された凹状の金属カバーとからなる密閉容器とを備え、前記セラミック基板の一主面上にはＩＣチップがバンプを用いた超音波熱圧着によって固着され、前記ＩＣチップの上方には前記ＩＣチップと板面が対向した水晶片が配置された表面実装用の水晶発振器であって、前記セラミック基板は少なくとも中央領域に両主面を有した平板状である構成とする。 According to the present invention, a rectangular ceramic substrate having a metal film on the outer periphery of one main surface and mounting electrodes at the four corners of the other main surface as shown in the claims (Claim 1) And a sealed container comprising a concave metal cover with an open end face fixed to the metal film, and an IC chip is fixed on one main surface of the ceramic substrate by ultrasonic thermocompression using a bump, A crystal oscillator for surface mounting in which a crystal piece whose plate surface is opposed to the IC chip is disposed above the IC chip, wherein the ceramic substrate is a flat plate having both main surfaces at least in a central region. The configuration.

このような構成であれば、セラミック基板は中央領域を平板状として凹部を有しないので、開口部を有するセラミックを要しない。したがって、例えば積層とした場合でも、中央領域を平板状とした第１と第２セラミックを積層するので、前述した焼成時の枠部の収縮力に伴う湾曲を防止して平坦度を維持する。無論、単板の場合でも同じである。このことから、バンプを用いた超音波熱圧着による接合を確実にする。   With such a configuration, the ceramic substrate does not need a ceramic having an opening because the central region is flat and does not have a recess. Therefore, for example, even in the case of lamination, the first and second ceramics having a flat central region are laminated, so that the flatness is maintained by preventing the bending due to the shrinkage force of the frame portion at the time of firing described above. Of course, the same applies to a single plate. This ensures bonding by ultrasonic thermocompression bonding using bumps.

（実施態様）
本発明の請求項２では、請求項１の前記セラミック基板は前記実装電極を有する第１セラミックと前記ＩＣチップの固着される第２セラミックとを積層してなり、前記第１セラミックにおける対向する少なくとも一組の両辺の中央部には外周が開放した切欠部を有し、前記切欠部によって露出した前記第２セラミックの積層面には温度補償データの書込表面端子が形成される。 (Embodiment)
According to claim 2 of the present invention, the ceramic substrate according to claim 1 is formed by laminating a second ceramic which is fixed in the first ceramic and the IC chip with the mounting electrode, at least facing in the first ceramic A center portion of both sides of the pair has a notch portion whose outer periphery is open, and a temperature compensation data writing surface terminal is formed on the laminated surface of the second ceramic exposed by the notch portion.

これによれば、温度補償データの書込表面端子は外周が開放した切欠部例えばコ字上に形成されるので、例えば特許文献３に示されるように中央領域に穴部設けたと合に比較し、書き込み用のプローブを当接しやすくする。この場合でも、請求項１と同様に中央領域を平板状とするので平坦度を維持する。この場合、切欠部を有するので焼成時に収縮力が作用するが、切欠部は外周領域なので全体的な湾曲に対する影響は小さい。なお、一組の対向する両辺のみならず、他組の両辺にも切欠部を設ければ、４個の書込端子を要する場合でも適用できる。 According to this, the temperature compensation data writing surface terminal is formed on a notch portion having an open outer periphery, for example, a U-shape, so that, for example, as shown in Patent Document 3, a hole portion is provided in the central region. , Make it easy to contact the writing probe. Even in this case, the flatness is maintained because the central region is flat like the first aspect. In this case, since the cutout portion is provided, a shrinkage force acts during firing, but since the cutout portion is an outer peripheral region, the influence on the overall curvature is small. Note that if notches are provided not only on one pair of opposing sides but also on both sides of the other set, the present invention can be applied even when four write terminals are required.

同請求項３では、前記セラミック基板は前記実装電極を有する第１セラミックと前記ＩＣチップの固着される第２セラミックとを積層してなり、前記第１セラミックの対向する一組の両辺の中央部には外周が開放した切欠部を有し、前記切欠部によって露出した前記第２セラミックの積層面には水晶片の検査端子が形成される。この場合でも、請求項２と同様な効果を奏する。
In the third aspect of the present invention, the ceramic substrate is formed by laminating a first ceramic having the mounting electrode and a second ceramic to which the IC chip is fixed, and a central portion of a pair of opposite sides of the first ceramic. Has a notch portion whose outer periphery is open, and an inspection terminal for a crystal piece is formed on the laminated surface of the second ceramic exposed by the notch portion. Even in this case, an effect similar to that of the second aspect is obtained.

同請求項４では、前記セラミック基板は前記実装電極を有する第１セラミックと前記ＩＣチップの固着される第２セラミックとを積層してなり、前記第１セラミックの各辺の中央部には外周が開放した切欠部を有し、前記切欠部によって露出した前記第２セラミックの積層面には、温度補償データの書込表面端子と水晶片の一対の検査端子が形成される。この場合でも請求項２と同様な効果を奏する。
According to the fourth aspect of the present invention, the ceramic substrate is formed by laminating a first ceramic having the mounting electrode and a second ceramic to which the IC chip is fixed, and an outer periphery is provided at a central portion of each side of the first ceramic. A temperature compensation data writing surface terminal and a pair of inspection terminals for a crystal piece are formed on the laminated surface of the second ceramic having an open notch and exposed by the notch. Even in this case, an effect similar to that of the second aspect is obtained.

（第１実施形態、請求項１〜４に相当）
第１図は本発明の第１実施形態を説明する図で、同図（ａ）は表面実装発振器の断面図、同図（ｂ）はセラミック基板の平面図である。なお、前従来例と同一部分には同番号を付与してその説明は簡略又は省略する。 (First embodiment , corresponding to claims 1 to 4 )
FIG. 1 is a diagram for explaining a first embodiment of the present invention. FIG. 1 (a) is a cross-sectional view of a surface mount oscillator, and FIG. 1 (b) is a plan view of a ceramic substrate. In addition, the same number is attached | subjected to the same part as a prior art example, and the description is simplified or abbreviate | omitted.

表面実装発振器は、前述したように、一主面の周回する外周に金属膜９を有する矩形状のセラミック基板４に、凹状の金属カバー５の開口端面を金属ロウ１１で接合した密閉容器１を備える。そして、密閉容器１内にＩＣチップ２と水晶片３とを収容してなる。水晶片３の長さはＩＣチップ２の同方向の長さよりも大きい。勿論、短くてもよい。但し、長い方が板面面積が大きいので設計を容易にする。   As described above, the surface-mount oscillator includes the sealed container 1 in which the opening end surface of the concave metal cover 5 is bonded to the rectangular ceramic substrate 4 having the metal film 9 on the outer periphery of one main surface by the metal brazing 11. Prepare. The IC chip 2 and the crystal piece 3 are accommodated in the sealed container 1. The length of the crystal piece 3 is larger than the length of the IC chip 2 in the same direction. Of course, it may be short. However, the longer one makes the design easier because the plate surface area is larger.

第1実施形態では、セラミック基板４は最小限の一層とし、両主面ともに水平面とした平板状とする。周回する金属膜９は例えば４角部の外周端から離間し、４角部の端面（側面）にはスルーホールによる側面電極７ｂが形成される。そして、セラミック基板４の一主面には回路端子６及び中継端子１７が形成される。   In the first embodiment, the ceramic substrate 4 is a minimum of one layer, and has a flat plate shape in which both main surfaces are horizontal surfaces. The circulating metal film 9 is separated from, for example, the outer peripheral ends of the four corners, and side electrodes 7b are formed by through holes on the end surfaces (side surfaces) of the four corners. Circuit terminals 6 and relay terminals 17 are formed on one main surface of the ceramic substrate 4.

回路端子６はＩＣチップ２のＩＣ端子に対応して長さ方向の両側に４個ずつの計８個が形成される。そして、前述のように、少なくとも一対の水晶端子６（Ｘ1、Ｘ2）、及び電源６（Ｖcc）、出力６（Ｖout）、アース６（Ｅ）、自動周波数制御６（ＡＦＣ）端子を有する。ここでのＩＣチップ２は、発振回路とともに温度補償機構を集積化し、温度補償データを書き込む２個の書込端子を有する。これに対応して、回路端子６は２個の書込端子６（Ｗ1、Ｗ2）を有する。   A total of eight circuit terminals 6 corresponding to the IC terminals of the IC chip 2 are formed, four on each side in the length direction. As described above, at least a pair of crystal terminals 6 (X1, X2), a power source 6 (Vcc), an output 6 (Vout), a ground 6 (E), and an automatic frequency control 6 (AFC) terminal are provided. The IC chip 2 here has a temperature compensation mechanism integrated with an oscillation circuit, and has two write terminals for writing temperature compensation data. Correspondingly, the circuit terminal 6 has two write terminals 6 (W1, W2).

中継端子１７はセラミック基板４の長さ方向の一端部両側に設けられ、回路端子６中の水晶端子６（Ｘ1、Ｘ2）に導電路１８によって電気的に接続する。セラミック基板４の他主面（外表面、底面）には、側面電極７ｂと接続した実装電極７を有する。そして、ＩＣ端子（回路端子６）中の電源６（Ｖcc）、出力６（Ｖout）、アース６（Ｅ）、自動周波数制御端子６（ＡＦＣ）と電気的に接続する。   The relay terminals 17 are provided on both sides of one end of the ceramic substrate 4 in the length direction, and are electrically connected to the crystal terminals 6 (X1, X2) in the circuit terminals 6 by conductive paths 18. The other main surface (outer surface, bottom surface) of the ceramic substrate 4 has mounting electrodes 7 connected to the side electrodes 7b. The power supply 6 (Vcc), output 6 (Vout), ground 6 (E), and automatic frequency control terminal 6 (AFC) in the IC terminal (circuit terminal 6) are electrically connected.

また、他主面には書込端子６（Ｗ1、Ｗ2）に接続した書込表面端子７（Ｗ1、Ｗ2)が設けられる。書込表面端子７（Ｗ1、Ｗ2)は、両長辺の実装電極７間の中央に設けられ、温度補償データの書き込み用のプローブが当接する。そして、実装電極７及び書込表面端子７（ａｂ）とこれに対応する各回路端子６とは、ビアホール１９及び一主面の導電路１８によって接続する。金属膜９は実装電極７中のアース端子７（Ｅ）にビアホール１９によって電気的に接続し、ケースアースとする。   The other main surface is provided with write surface terminals 7 (W1, W2) connected to the write terminals 6 (W1, W2). The writing surface terminal 7 (W1, W2) is provided at the center between the mounting electrodes 7 on both long sides, and a probe for writing temperature compensation data contacts. The mounting electrode 7 and the writing surface terminal 7 (ab) are connected to the corresponding circuit terminal 6 by the via hole 19 and the conductive path 18 on one main surface. The metal film 9 is electrically connected to the ground terminal 7 (E) in the mounting electrode 7 by a via hole 19 to form a case ground.

ビアホール１９は、回路下地パターン（回路端子６、中継端子１７、導電路１８及び実装電極７）を印刷によって形成時する際、印刷材を貫通孔に充填する。印刷材は例えばモリブテン（Ｍo）やタングステン（Ｗ）からなる。そして、セラミック生地とともに一体的に焼成した後、例えば回路パターン上にメッキによるニッケル（Ｎi）及び金（Ａu）を積層して形成される。これにより、貫通孔は閉塞されて密閉を維持する。   The via hole 19 fills the through hole with a printing material when the circuit base pattern (circuit terminal 6, relay terminal 17, conductive path 18 and mounting electrode 7) is formed by printing. The printing material is made of molybdenum (Mo) or tungsten (W), for example. Then, after integrally firing together with the ceramic fabric, for example, nickel (Ni) and gold (Au) by plating are laminated on the circuit pattern. Thereby, a through-hole is obstruct | occluded and a sealing is maintained.

ＩＣチップ２は従来同様にバンプ１２を用いた超音波熱圧着によって、各ＩＣ端子８が回路端子６に接続する。水晶片３はセラミック基板１と長さ方向が一致し、引出電極１４の延出した一端部両側が一対の金属性のサポータ２０に導電性接着剤によって接続して保持される。サポータ２０は両端側が同方向に折曲して一端側の折曲部が中継端子１７に接続し、他端側の折曲部が水晶片３の一端部両側を保持する。   In the IC chip 2, each IC terminal 8 is connected to the circuit terminal 6 by ultrasonic thermocompression using the bumps 12 as in the prior art. The crystal piece 3 has the same length direction as the ceramic substrate 1, and both ends of the extended end portion of the extraction electrode 14 are connected to and held by a pair of metallic supporters 20 with a conductive adhesive. The supporter 20 is bent at both ends in the same direction, the bent portion on one end side is connected to the relay terminal 17, and the bent portion on the other end side holds both sides of one end portion of the crystal piece 3.

このような構成であれば、セラミック基板４は両主面を水平面とした平板状とするので、従来例のように焼成時には開口部をもった第２セラミックによっての収縮による凹面とはならず、水平面を維持できる。したがって、バンプ１２を用いた超音波熱圧着によっての回路端子６への電気的接続を確実にする。   With such a configuration, the ceramic substrate 4 has a flat plate shape with both main surfaces as horizontal surfaces, so that it does not become a concave surface due to contraction by the second ceramic having an opening during firing, as in the conventional example, A horizontal plane can be maintained. Therefore, the electrical connection to the circuit terminal 6 is ensured by ultrasonic thermocompression bonding using the bumps 12.

また、金属カバー５とするので、従来同様に寸法を短縮して小型化を促進する。そして、セラミック基板４を平板状の単層として最小数なので、安価にできる。なお、底面に設けた書込表面端子７（Ｗ1、Ｗ2）は、セット基板に対する接続強度を高めるため、必要に応じて実装電極として適用できる。また、スルーホールによる４角部の側面電極７ｂ設けず、この分金属膜９を外周側に接近させて実質的な内積を大きくしてもよい。   Further, since the metal cover 5 is used, the size is shortened and the miniaturization is promoted as in the conventional case. Since the ceramic substrate 4 is the minimum number of flat single layers, the cost can be reduced. Note that the writing surface terminals 7 (W1, W2) provided on the bottom surface can be applied as mounting electrodes as necessary in order to increase the connection strength to the set substrate. Also, the substantial inner product may be increased by making the metal film 9 closer to the outer peripheral side without providing the side electrode 7b at the four corners by the through hole.

（第２実施形態、特に請求項２及び３に相当）
第２図は本発明の第２実施形態を説明する図で、同図（ａ）は表面実装発振器の断面図、同図（ｂ）は第１セラミックの平面図、同図（ｃ）は、表面実装発振器の底面図である。なお、第１実施形態と同一部分の説明は省略又は簡略する。 (Second embodiment, particularly equivalent to claims 2 and 3 )
FIG. 2 is a diagram for explaining a second embodiment of the present invention. FIG. 2 (a) is a sectional view of a surface mount oscillator, FIG. 2 (b) is a plan view of the first ceramic, and FIG. It is a bottom view of a surface mount oscillator. In addition, description of the same part as 1st Embodiment is abbreviate | omitted or simplified.

第２実施形態ではセラミック基板４を例えば二層とした第１と第２セラミック４（ａｂ）の積層基板とし、その他の構成は第１実施形態と概ね同一とする。ここでの、実装電極７が形成される第１セラミック４ａは対向する一組の両辺の中央部に外周が開放した例えばコ字状の切欠部２１を有し、中央領域を板状とする。ＩＣチップ２が固着される第２セラミック４ｂは全面的に平板状とする。 In the second embodiment, the ceramic substrate 4 is, for example, a laminated substrate of first and second ceramics 4 (ab) having two layers, and the other configurations are substantially the same as those of the first embodiment. Here, the first ceramic 4a on which the mounting electrode 7 is formed has, for example, a U-shaped cutout portion 21 whose outer periphery is open at the central portion of a pair of opposing sides, and the central region has a plate shape. The second ceramic 4b to which the IC chip 2 is fixed is entirely flat.

第１セラミック４ａの実装電極７は側面電極７ｂを有して第１セラミック４ａの４角部に設けられる。なお、第１図（ｃ）では便宜的に側面電極７ｂは省略してある。各実装電極７は従来例と同様に気密を確実にするため、ビアホール及び積層面を経た導電路によって各回路端子６中の電源６（Ｖcc）、出力６（Ｖout）、アース６（Ｅ）、自動周波数制御端子６（ＡＦＣ）と電気的に接続する。書込表面端子７（Ｗ1、Ｗ2）は切欠部２１に対応した第２セラミック４ｂの積層面に設けられ、書込端子６（Ｗ1、Ｗ2）に同様にして電気的に接続する。   The mounting electrodes 7 of the first ceramic 4a have side electrodes 7b and are provided at the four corners of the first ceramic 4a. In FIG. 1 (c), the side electrode 7b is omitted for convenience. In order to ensure airtightness as in the conventional example, each mounting electrode 7 has a power supply 6 (Vcc), an output 6 (Vout), an earth 6 (E), a ground 6 (E), and a conductive path through a via hole and a laminated surface. It is electrically connected to the automatic frequency control terminal 6 (AFC). The writing surface terminal 7 (W1, W2) is provided on the laminated surface of the second ceramic 4b corresponding to the notch 21, and is electrically connected to the writing terminal 6 (W1, W2) in the same manner.

このような構成であれば、第１セラミック４ａの両辺の中央部に切欠部２１を有するものの、外周領域であるとともに切欠部２１の面積よりも第１セラミック４ａの面積は大きい。したがって、従来例のように焼成時の収縮力による外力が作用しても、第２セラミック４ｂを湾曲面にするには至らず、平坦度を維持する。これにより、第１実施形態と同様に、バンプ１２を用いた超音波熱圧着による接続を確実にする。 With such a configuration, the first ceramic 4a has the cutout portions 21 at the center of both sides of the first ceramic 4a. However, the area of the first ceramic 4a is larger than the area of the cutout portion 21 as well as the outer peripheral region . Therefore, even if an external force due to contraction force during firing acts as in the conventional example, the second ceramic 4b does not become a curved surface, and the flatness is maintained. Thereby, the connection by the ultrasonic thermocompression bonding which used the bump 12 is ensured similarly to 1st Embodiment.

そして、書込表面端子７(Ｗ1、Ｗ2)はセラミック基板４の外周に設けた切欠部２１に形成したので、セット基板とは接触することなく独立性を維持する。そして、切欠部２１は外周が開放する。したがって、中央部に穴部（凹所）を設けた場合に比較し、書き込み用のプローブを当接しやく作業性を向上できる。   Since the writing surface terminals 7 (W1, W2) are formed in the notches 21 provided on the outer periphery of the ceramic substrate 4, the independence is maintained without contact with the set substrate. The outer periphery of the notch 21 is opened. Therefore, compared with the case where a hole (recess) is provided at the center, the writing probe can be easily brought into contact with the workability.

なお、この実施形態では、、両辺の切欠部２１には温度補償データの書込表面端子７（Ｗ１、Ｗ2）を設けたが、これの代わりに水晶片３の引出電極１４と接続した中継端子１７及び図示しない導電路を経て電気的に接続する水晶検査端子７（Ｑ1、Ｑ2）を設けることもできる。これにより、水晶片３を密閉封入した水晶振動子の電気的特性を独立的に測定できる。また、ＩＣチップ２に書込端子が２個ある場合を示したが、書込端子が１個の場合には、第１セラミックの少なくとも一辺に切欠部があればよいことは勿論である。In this embodiment, the temperature compensation data writing surface terminals 7 (W1, W2) are provided in the cutout portions 21 on both sides. 17 and crystal inspection terminals 7 (Q1, Q2) which are electrically connected via a conductive path (not shown) can also be provided. Thereby, the electrical characteristics of the crystal resonator in which the crystal piece 3 is hermetically sealed can be measured independently. Further, although the case where the IC chip 2 has two write terminals has been described, it is needless to say that when there is one write terminal, it is sufficient that a cutout is provided on at least one side of the first ceramic.

（第３実施形態、特に請求項２〜４に相当）(Third embodiment, particularly equivalent to claims 2 to 4)
第３図は本発明の第３実施形態を説明する図で、同図（ａ）は第１セラミックの平面図、同図（ｂｃ）は表面実装発振器の底面図である。なお、第１及び第２実施形態と同一部分の説明は省略又は簡略する。FIG. 3 is a view for explaining a third embodiment of the present invention, wherein FIG. 3 (a) is a plan view of the first ceramic, and FIG. 3 (bc) is a bottom view of the surface mount oscillator. In addition, description of the same part as 1st and 2nd embodiment is abbreviate | omitted or simplified.

第３実施形態では、前述した第２実施例での実装電極７の形成される第１セラミック４ａは、各辺の中央部に切欠部２１を有する「第３図（ａ）」。そして、各切欠部２１によって露出した第２セラミック４ｂには書込表面端子７（Ｗ1、Ｗ2、Ｗ3、Ｗ4）の計４個を形成する「第３図（ｂ）」。このようにすれば、ＩＣチップ２に４個の書込端子を必要とする場合に適用できる。In 3rd Embodiment, the 1st ceramic 4a in which the mounting electrode 7 in the 2nd Example mentioned above is formed has the notch part 21 in the center part of each side "FIG. 3 (a)." Then, a total of four writing surface terminals 7 (W1, W2, W3, W4) are formed on the second ceramic 4b exposed by the notches 21 (FIG. 3 (b)). In this way, the present invention can be applied when the IC chip 2 requires four write terminals.

また、例えば一組の対向する両辺の切欠部２１には書込表面端子７（Ｗ1、Ｗ2）を、他組の対向する両辺には水晶検査端子７（Ｑ1、Ｑ２）を設けることもできる［第３図（ｃ）］。このようにすれば、書込表面端子７（Ｗ1、Ｗ2）及び水晶検査端子７（Ｑ1、Ｑ２）のいずれも底面に形成できるので、例えば測定治具を統一できて好都合となる。


Further, for example, the writing surface terminals 7 (W1, W2) can be provided in the notches 21 on both sides of one set, and the crystal inspection terminals 7 (Q1, Q2) can be provided on both sides of the other set. FIG. 3 (c)]. In this way, since both the writing surface terminal 7 (W1, W2) and the crystal inspection terminal 7 (Q1, Q2) can be formed on the bottom surface, for example, it is convenient to unify the measuring jig .


これらの場合でも、第１及び第２実施形態と同様に、切欠部２１を第１セラミック４ａの外周領域に設けてＩＣチップ２の搭載される中央領域は平板とするので、焼成時に収縮力が作用しても湾曲することを抑制する。また、いずれの実施例でも中心線に対しても対称とするので、無理な応力が作用しない。Even in these cases, as in the first and second embodiments, the notch 21 is provided in the outer peripheral region of the first ceramic 4a and the central region on which the IC chip 2 is mounted is a flat plate. Even if it acts, curving is suppressed. In any of the embodiments, since it is symmetrical with respect to the center line, excessive stress does not act.

本発明の第１実施形態を説明する図で、同図（ａ）は表面実装発振器の断面図、同図（ｂ）はセラミック基板の平面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure explaining 1st Embodiment of this invention, The figure (a) is sectional drawing of a surface mount oscillator, The figure (b) is a top view of a ceramic substrate. 本発明の第２実施形態を説明する図で、同図（ａ）は表面実装発振器の断面図、同図（ｂ）は第１セラミックの平面図、同図（ｃ）は、表面実装発振器の底面図である。2A and 2B are diagrams illustrating a second embodiment of the present invention, in which FIG. 1A is a cross-sectional view of a surface mount oscillator, FIG. 1B is a plan view of a first ceramic, and FIG. It is a bottom view. 本発明の第３実施形態を説明する図で、同図（ａ）は第１セラミックの平面図、同図（ｂｃ）は表面実装発振器の底面図である。It is a figure explaining 3rd Embodiment of this invention, The figure (a) is a top view of a 1st ceramic, The figure (bc) is a bottom view of a surface mount oscillator. 従来例を説明する表面実装発振器の図で、同図（ａ）は断面図、同図（ｂ）は水晶片３の平面図、同図（ｃ）はＩＣチップの回路機能面（一主面）の図である。FIG. 2A is a cross-sectional view of a surface-mount oscillator for explaining a conventional example, FIG. 2B is a plan view of a crystal piece 3, and FIG. 1C is a circuit function surface (one main surface) of an IC chip. ). 他の従来例を説明する表面実装発振器の断面図である。It is sectional drawing of the surface mount oscillator explaining another prior art example. 従来例の問題点を説明する図で、同図（ａ）シート状のセラミック生地の断面図、同図（ｂ）は同図（ａ）の○囲み部分の一部拡大断面図、同図（ｃ）はＩＣチップを装着した一部断面図ある。It is a figure explaining the problem of a prior art example, The figure (a) Sectional drawing of a sheet-like ceramic cloth, The figure (b) is a partial expanded sectional view of the circled part of the figure (a), c) is a partial cross-sectional view with an IC chip mounted.

符号の説明Explanation of symbols

１ 密閉容器、２ ＩＣチップ、３ 水晶片、４ セラミック基板、５ 金属カバー、６ 回路端子、７ 実装電極、８ ＩＣ端子、９ 金属膜、１０ 水晶保持端子、１１ 金属ロウ、１２ バンプ、１３ 励振電極、１４ 引出電極、１５ 導電性接着剤、１６ 分割溝、１７ 中継端子、１８ 導電路、１９ ビアホール１９、２０ サポータ。 DESCRIPTION OF SYMBOLS 1 Airtight container, 2 IC chip, 3 Crystal piece, 4 Ceramic substrate, 5 Metal cover, 6 Circuit terminal, 7 Mounting electrode, 8 IC terminal, 9 Metal film, 10 Crystal holding terminal, 11 Metal solder, 12 Bump, 13 Excitation Electrode, 14 Lead electrode, 15 Conductive adhesive, 16 Dividing groove, 17 Relay terminal, 18 Conductive path, 19 Via hole 19, 20 Supporter.

Claims (2)

一主面の周回する外周に金属膜を有し、他主面の４角部に実装電極が形成され、少なくとも中央領域に前記両主面を有する平板状のセラミック基板と、前記金属膜に開口端面が固着された凹状の金属カバーとからなる密閉容器とを備え、前記セラミック基板の前記一主面にバンプを用いた超音波熱圧着によって固着されたＩＣチップと、前記セラミック基板の前記一主面で、かつ、前記ＩＣチップの上方で前記ＩＣチップと板面が対向して前記セラミック基板と長さ方向が一致した水晶片を、その一端部両側が金属性のサポータに導電性接着剤によって接続して保持された表面実装用の水晶発振器であって、
前記セラミック基板は、前記実装電極を有する第１セラミックと前記ＩＣチップが固着される第２セラミックとを積層してなり、
前記第２セラミックの主面に前記金属膜を有すると共に、一対の水晶端子、前記ＩＣチップのＩＣ端子と接続する複数の回路端子、前記セラミック基板の長さ方向の一端部両側に設けられて前記一対の水晶端子のそれぞれに電気的に接続する一対の中継端子を有し、
前記水晶片を保持する前記サポータは、両端側が同方向に折曲して一端側の折曲部が前記中継端子に接続し、他端側の折曲部が前記水晶片の前記一端部両側に接続しており、
前記第１セラミックの対向する一組および他組の各両辺の中央部には外周が開放した切欠部を有し、前記切欠部によって露出した前記第２セラミックの積層面の前記一組には一対の温度補償データの書込表面端子が、また、前記他組には一対の水晶振動子の検査端子が、それぞれ水晶発振器の底面に形成されていることを特徴とする表面実装用の水晶発振器。 A flat ceramic substrate having a metal film on the outer periphery of one main surface, mounting electrodes formed on the four corners of the other main surface, and having both the main surfaces at least in the central region, and an opening in the metal film and a sealed container comprising a metal cover of the concave end face is fixed, the IC chip secured by ultrasonic thermo-compression bonding using bumps on the one main surface of the ceramic substrate, wherein the first major of the ceramic substrate in terms, and the crystal element in which the ceramic substrate and the longitudinal direction matches the IC chip and the plate surface above said IC chip is opposed, conductive adhesive supporter one end on both sides of the metal A surface mount crystal oscillator connected and held by
The ceramic substrate is formed by laminating a first ceramic having the mounting electrode and a second ceramic to which the IC chip is fixed,
The main surface of the second ceramic has the metal film, a pair of crystal terminals, a plurality of circuit terminals connected to the IC terminals of the IC chip, provided on both sides of one end of the ceramic substrate in the length direction. A pair of relay terminals electrically connected to each of the pair of crystal terminals;
The supporter holding the crystal piece is bent at both ends in the same direction, the bent portion at one end is connected to the relay terminal, and the bent portion at the other end is on both sides of the one end portion of the crystal piece. Ri you connect,
A pair of opposing sides of the first ceramic and a center portion of each side of the other set have a notch that is open at the outer periphery, and a pair of the pair of laminated surfaces of the second ceramic exposed by the notch is a pair. A surface mount crystal oscillator , wherein the temperature compensation data writing surface terminal and a pair of crystal resonator test terminals of the other set are formed on the bottom surface of the crystal oscillator, respectively . 請求項１において、
前記ＩＣチップのＩＣ端子と接続する複数の回路端子は、電源、出力、アース、自動周波数制御の各回路端子であることを特徴とする表面実装用の水晶発振器。 In claim 1,
A plurality of circuit terminals connected to the IC terminals of the IC chip are power supply, output, ground, and automatic frequency control circuit terminals .
JP2006100025A 2005-11-30 2006-03-31 Crystal oscillator for surface mounting Expired - Fee Related JP4994691B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2006100025A JP4994691B2 (en) 2005-12-06 2006-03-31 Crystal oscillator for surface mounting
US11/606,511 US7602107B2 (en) 2005-11-30 2006-11-30 Surface mount type crystal oscillator
US12/584,155 US7932786B2 (en) 2005-11-30 2009-09-01 Surface mount type crystal oscillator
US12/584,168 US8008980B2 (en) 2005-11-30 2009-09-01 Surface mount type crystal oscillator

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005352687 2005-12-06
JP2005352687 2005-12-06
JP2006100025A JP4994691B2 (en) 2005-12-06 2006-03-31 Crystal oscillator for surface mounting

Publications (2)

Publication Number Publication Date
JP2007184890A JP2007184890A (en) 2007-07-19
JP4994691B2 true JP4994691B2 (en) 2012-08-08

Family

ID=38340568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006100025A Expired - Fee Related JP4994691B2 (en) 2005-11-30 2006-03-31 Crystal oscillator for surface mounting

Country Status (1)

Country Link
JP (1) JP4994691B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5020340B2 (en) * 2010-02-05 2012-09-05 日本電波工業株式会社 Constant temperature crystal oscillator for surface mounting
KR101106550B1 (en) 2010-02-09 2012-01-20 아메스산업(주) Lead sealing device for chips using ultrasonic welding
JP2015039133A (en) * 2013-08-19 2015-02-26 日本特殊陶業株式会社 package
JP6450612B2 (en) * 2015-03-11 2019-01-09 日本特殊陶業株式会社 Electronic component device and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001177055A (en) * 1999-12-17 2001-06-29 Nippon Dempa Kogyo Co Ltd IC surface mount structure, ceramic base and crystal oscillator
JP2005268257A (en) * 2004-03-16 2005-09-29 Kyocera Corp Electronic component storage package and electronic device
JP2006101241A (en) * 2004-09-29 2006-04-13 Kyocera Kinseki Corp Piezoelectric oscillator and manufacturing method thereof

Also Published As

Publication number Publication date
JP2007184890A (en) 2007-07-19

Similar Documents

Publication Publication Date Title
EP1478090B1 (en) Tuning-fork-type piezoelectric resonator element
JP5078512B2 (en) Crystal device
JP2010135890A (en) Crystal device
JP2007158918A (en) Crystal oscillator for surface mounting
CN101199114A (en) Piezoelectric resonator plate and piezoelectric resonator
JP2013106054A (en) Piezoelectric device
JP2010103950A (en) Vibrator and method of manufacturing the same
JP5210106B2 (en) Piezoelectric device
JP4994691B2 (en) Crystal oscillator for surface mounting
JP2007288268A (en) Crystal oscillator for surface mounting
JP2003298000A (en) Oscillator sheet substrate and method for manufacturing crystal oscillator for surface mounting using the same
JP4122512B2 (en) Piezoelectric vibration device
JP2007158419A (en) Surface mount crystal oscillator
JP2007104075A (en) Crystal oscillator for surface mounting
JP3994652B2 (en) Piezoelectric device
JP2010171572A (en) Crystal oscillator for surface mounting
JP5144452B2 (en) Piezoelectric oscillator
JP2009105776A (en) Crystal device for surface mounting
JP6604071B2 (en) Piezoelectric vibration device
JP2008259004A (en) Piezoelectric device and manufacturing method thereof
JP2010135874A (en) Surface mount crystal oscillator
JP5101192B2 (en) Piezoelectric device
JP4373309B2 (en) Package for electronic components
JP2016082548A (en) Electronic apparatus housing package and manufacturing method of piezoelectric oscillator used therefor
JP2007235289A (en) Piezoelectric oscillator

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090324

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110830

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20110930

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111019

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120124

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120417

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120509

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150518

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150518

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees